Integrated circuit with embedded test circuitry

Abstract

An integrated circuit (100) includes a plurality of pins (104, 106, 108) including a signal output pin (108). The integrated circuit also includes a plurality of signal nodes (114N, 116N, 118N). Each of the plurality of signal nodes is operable to store a respective internal data signal. The integrated circuit also includes a plurality of test circuits (120, 122, 124). Each of the plurality of test circuits is configured to sample a respective internal data state and to couple a unique output signal to a same pin (104) of the plurality of pins other than the signal output pin in response to simultaneously coupling the unique output signal to the same pin.

Description

Background Technology

[0001] Examples and embodiments relate to integrated circuits (singular IC, plural ICs), and more specifically, to ICs comprising embedded test circuitry systems and the testing of such ICs.

[0002] Design for Test (DFT) refers to the aspect of IC design that provides testability to the IC once it is in production or manufacturing. A typical DFT circuit system is enabled during testing and deactivated when the IC operates in its nominal non-test environment. During testing, (several) DFT circuits allow additional equipment (such as automated test equipment (ATE)) to provide input test signals to the IC in test mode and observe, capture, and analyze the corresponding output signals generated from the input test signals. Both DFT and ATE testing are common in IC design and production, thereby increasing IC yield and reducing IC failures once the IC is released and implemented in various device applications.

[0003] DFT implementations can be used in ICs with varying pin counts, but are more challenging for ICs with relatively few pins (e.g., six pins or less). Specifically, for ICs with higher pin counts, the design can have the flexibility to include one or more dedicated test pins for input or output signals. In contrast, for ICs with lower pin counts, the design is typically constrained by the number of pins, where one or more pins can be connected to provide different functions at different times. However, in such cases, DFT implementations may require more complex internal structures to support one type of signal communication to a pin (e.g., an IC output pin) during non-test operations, and different types of signal communication to the same pin during test operations.

[0004] Therefore, this document provides example embodiments that can improve upon certain concepts described above, as further detailed below. Summary of the Invention

[0005] An integrated circuit includes a plurality of pins, including signal output pins. The integrated circuit also includes a plurality of signal nodes. Each of the plurality of signal nodes is operable to store a corresponding internal data signal. The integrated circuit also includes a plurality of test circuits. Each of the plurality of test circuits is configured to sample a corresponding internal data state and, in response, simultaneously couple a unique output signal to the same pin among the plurality of pins, excluding the signal output pins.

[0006] It also describes and advocates for other aspects. Attached Figure Description

[0007] Figure 1The illustration includes a schematic diagram of an example embodiment of an embedded test circuit system, IC 100.

[0008] Figure 2 The instructions can be used Figure 1 Block diagram of the test circuit in each of test circuits 120, 122 and 124.

[0009] Figure 3 The instructions can be used Figure 1 A schematic diagram of an example embodiment of a dual-transistor test circuit in any of the test circuits 120, 122, and 124.

[0010] Figure 4 This description is for testing three simultaneously. Figure 1 Example signal diagrams for test circuits 120, 122, and 124.

[0011] Figure 5A This diagram illustrates a test circuit for an NMOS transistor 504 that provides a high-state valid data state response.

[0012] Figure 5B This diagram illustrates a test circuit that is enabled by the high-state active test enable signal T_EN and provides a low-state active data state response from the PMOS transistor 520.

[0013] Figure 5C This diagram illustrates an alternative test circuit that is enabled by the high-state active test enable signal T_EN and provides a low-state active data state response using PMOS transistor 542.

[0014] Figure 6 The illustration includes a schematic diagram of an alternative example embodiment of the embedded test circuit system, IC 600.

[0015] Figure 7 The instructions can be used Figure 6 A schematic diagram of an example embodiment of a three-transistor test circuit (combined with a mirror transistor) of any of the test circuits 604, 606, or 608.

[0016] Figure 8 Instructions for testing Figure 1 IC 100 (or easily modified for testing) Figure 6 A schematic diagram of the test environment for IC 600.

[0017] Figure 9 illustrate Figure 8 A flowchart of an example implementation method 900 for a test environment. Detailed Implementation

[0018] Figure 1The following detailed description illustrates a schematic diagram of an example embodiment IC 100 containing a DFT embedded test circuitry system. IC 100 includes four physical pins (sometimes referred to as pads), shown as pins 102, 104, 106, and 108, and a fifth pin 110 associated with the TEST state. Pin 110 may be an additional physical pin or may have a function enabled as described later. Each physical pin is a conductor that provides a signal interface between IC 100 and external connections. Example embodiment ICs may have any number of pins. However, embodiments with fewer pins (e.g., six or fewer) advantageously facilitate testing IC 100 using a subset of its pins (which may be as few as one pin), where each pin in the subset provides some additional corresponding function during non-test operation. This dual-pin usage eliminates the need for dedicated test pins, as can be implemented in ICs with a greater number of pins. Pin 102 is used to receive a bias voltage VCC, and pin 104 is used to connect to a low reference voltage, such as ground (GND). Pin 106 is used to receive the input signal S_IN, and pin 108 is used to provide the output signal S_OUT. Each of the input and output signals can be of various types, such as voltage, current, or data, depending on the functionality of IC 100. Furthermore, for some ICs, a pin may have a nominal function in one mode but a different function in another. Therefore, for example and illustration, in this document, the nominal function of pin 106 is as an input pin, and the nominal function of pin 108 is as an output pin; however, in other embodiments, one or both pins may provide alternative functions in modes other than the nominal operation. Typically, signal path 112 exists between the S_IN pin 106 and the S_OUT pin 108. Signal path 112 is illustrated as a dashed line because it may not be the same node throughout, but rather represents a general path through blocks that can connect to different devices and other signal paths. As described above, pin 110 represents a physical pin or functional operation, where in either case, the associated TEST signal is asserted. For example, if pin 110 is a dedicated physical test pin, then it can receive an asserted TEST signal. As another example, pin 110 can represent a physical pin that has one function during non-test operation and a different function that enables testing during test operation. In practice, pin 110 can be instantiated by pin 106 to receive S_IN during non-test operation, while during test operation, a signal at pin 110 or a signal to pin 110 (alone or in combination with signaling to one or more other pins) causes the internal circuitry of IC 100 to assert the TEST signal, thereby placing IC 100 in a test state (e.g., test mode). Any of these options enables testing of IC 100, as further detailed below.

[0019] IC 100 comprises N functional blocks, illustrated by example as N=3 functional blocks 114, 116, and 118. N can be selected from a wide range of numbers based on IC implementation, functionality, and test requirements. The example demonstrates a signal path 112 traversing each of functional blocks 114 to 118, and each block contains the corresponding internal data states required for testing. Each of functional blocks 114 to 118 is also biased between VCC and ground. Furthermore, each of functional blocks 114 to 118 can provide the same or different functionality, where these blocks (and potentially other blocks, not shown) collectively provide the overall functionality of IC 100. The example embodiments encompass numerous types of ICs, therefore the layout or number N of functional blocks 114 to 118 is not limited. Instead, each functional block illustrates the circuitry and / or connectivity within IC 100, where nodes of the corresponding functional block provide data states during IC operation, and as described above, these data states are required for testing.

[0020] Each of functional blocks 114, 116, and 118 includes corresponding nodes 114N, 116N, and 118N connected to the inputs of the corresponding test circuits 120, 122, and 124. Each of the test circuits 120, 122, and 124 has the same schematic configuration, although device parameters (e.g., dimensions) may vary depending on the test circuit, as detailed below. For simplicity, Figure 2 Illustrate the block diagram of test circuit 120, further labeling its inputs / outputs (I / O), and in Figure 1 This is applicable to all test circuits 120, 122, and 124. Return to Figure 1 With the help of Figure 2 Additional notes and references Figure 2 The first test circuit in the circuit is externally connected to 200 for, for example Figure 1 As shown in the diagram, VCC is received from the VCC pin 102. Figure 2 The external connection 202 of the second test circuit is Figure 1 The input shown is the Test Enable (T_EN) input connected to pin 110 of the TEST pin. Figure 2 The third test circuit external connection 204 is used to receive the data status (DST) at the internal node. Figure 1 The diagram shows the corresponding connections to nodes 114N, 116N, and 118N. Figure 2 The fourth test circuit in the external connection 206 provides Figure 1The diagram shows the Test Data Output (TDO) connected to the GND pin 104. As detailed below, when IC 100 testing is enabled (via the assertion TEST and the corresponding T_EN), the Test Data Output (TDO) at the GND pin 104 provides a modulated signal output whose magnitude depends on the data inputs to test circuits 120, 122, and 124 and their corresponding outputs. Specifically, in the example embodiment, each of test circuits 120, 122, and 124 outputs an analog current, which is then accumulated at the interconnect node indicated by the GND pin 104. Therefore, TDO effectively contains the total current from all three test circuits 120, 122, and 124. Note that TDO may also contain additional current from other devices that remain connected to the GND pin 104 during both non-test and test modes; this additional current can be easily determined during test operation and subtracted from the measured value of TDO as an offset.

[0021] Figure 3 Instructions for Figure 1 A schematic diagram of one example embodiment of test circuit 300 in all test circuits 120, 122, and 124. Test circuit 300 includes two transistors, which are NMOS transistors 302 and 304 in the illustrated example. When the transistors are enabled, the nominal on-resistance RDSON of each transistor is described by the following Equation 1:

[0022] RDSON = W / L x C Equation 1

[0023] Where W is the transistor structure width, L is the transistor structure length, and C is a constant factor, thus making RDSON proportional to W and L (and C, which is intentionally ignored herein as a constant). In an example embodiment, the RDSON of transistor 302 is equal to the RDSON of transistor 304, which is achieved by constructing each transistor with the same width W and the same length L (and the same constant C). Alternatively, mathematically equivalent RDSON values ​​per transistor can be achieved by having different lengths and widths between each transistor, provided that the W / L ratios of each transistor are equal. However, as a practical implementation problem in constructing transistors, the desired approach is the same W and the same L as described above. In any case, to evaluate the test data output TDO, the total series resistance of the RDSON across the two transistors should be known, as detailed below.

[0024] The connectivity of transistors 302 and 304 is now described. The drain of NMOS transistor 302 is connected to external connection 200, which is used to receive VCC, as shown below. Figure 2 In the example, it is shown at connection 200, and also as for... Figure 1Each of test circuits 120, 122, and 124 is shown. The gate of NMOS transistor 302 is connected to external connection 204, which is used to receive the data state DST. The source of NMOS transistor 302 is connected to the drain of NMOS transistor 304. The gate of NMOS transistor 304 is connected to external connection 202, which is used to receive the test enable T_EN. The source of NMOS transistor 304 is connected to connection 206, from... Figure 1 As previously mentioned, connection 206 provides the test data output TDO and is also connected to the GND pin 104 of IC 100.

[0025] The operation of test circuit 300 will now be described first in relation to any single one of the N=3 test circuits 120, 122, and 124 in IC 100. However, alternatively, embodiments described later may use the cumulative effect of one or more of those test circuits simultaneously providing the cumulative test data output TDO to provide additional functionality. A single test circuit 300 essentially provides a 2-input logic AND operation that gates the current output in response to inputs DST and T_EN. The AND functionality also depends on the assertion state of the inputs (e.g., high or low) and the conduction type of transistors 302 and 304. For example, when transistors 302 and 304 are NMOS, and when both inputs DST and T_EN are high, then when both DST and T_EN are active, a conductive path exists between connection 200 and connection 206, and a total current I_T flows along said path. The total current I_T of circuit 300 can be estimated according to the following Equation 2:

[0026] I_T = VCC / RDSON Equation 2

[0027] Here, RDSON is the total RDSON of transistors 302 and 304.

[0028] Equation 2 confirms that the total current I_T is based on VCC and the combined series resistance of transistors 302 and 304. Therefore, and as detailed later, during the test, via Figure 1Pin 110 (physically or functionally) asserts T_EN, and when the sampled data state DST is simultaneously asserted, the total current I_T provides a measurable signal as TDO, which is sampled at pin 104 of the GND circuit. In other words, when the current at pin 104 of the GND circuit is above a negligible level, this current level indicates that the data DST is asserted, which, when active high, means that the sampled data state is at a logic high level, thus confirming the high-state active data state of DST. Therefore, similarly, when the test is enabled and the data DST is invalid (logic low), the total current I_T is zero or negligible, thus confirming the low-state invalid data state of DST. As stated above, for at least a single corresponding test circuit 120, 122, or 124, the magnitude of TDO indicates the DST state during the test.

[0029] The preceding description describes testing the data state DST of a single test circuit 300 as any of test circuits 120, 122, or 124. However, in alternative embodiments, the corresponding data state DST of each individual test circuit 120, 122, or 124 can be tested simultaneously. This individual test is performed using the same electrical schematic diagram of test circuit 300 for each of test circuits 120, 122, and 124, but by modifying the device (e.g., transistor) parameters in each test circuit so that each circuit provides a measurably different output. For example, the transistor RDSON in each test circuit 120, 122, and 124 is changed to have a different value than in each of the other test circuits. RDSON can be adjusted by changing the width and / or length of the transistors in each test circuit. Thus, in one example, each corresponding RDSON value is adjusted according to different powers of 2, as shown in the following Equation 3:

[0030] Equation 3

[0031] Given Equation 2, different RDSON values ​​in Equation 3 result in correspondingly different total current values ​​through each of test circuits 120, 122, and 124. For example, since RDSON (circuit 120) is twice that of RDSON (circuit 122), and since the two resistors have the same VCC potential across them, the total current through circuit 120 when enabled will be half the total current through circuit 122 when enabled. As another example, since RDSON (circuit 120) is four times that of RDSON (circuit 124), and since the two resistors have the same VCC potential across them, the total current through circuit 120 when enabled will be one-quarter the total current through circuit 124 when enabled.

[0032] Using the example of resistance (RDSON) in Equation 3, Figure 4This section illustrates an example signal diagram for simultaneously testing three IC 100 test circuits: 120, 122, and 124. Figure 4 In the diagram, the horizontal axis represents time and the vertical axis represents TDO. For all times between t0 and t8, T_EN is asserted, thereby enabling the corresponding transistor in each of circuits 120, 122, and 124, with T_EN connected to the gate of that transistor. Again, for the illustrated example, assume VCC = 5 V and RDSON = 100 kOhms. Therefore, given the relative values ​​of RDSON for test circuits 120, 122, and 124 as shown in Equation 3 and the total current from Equation 2, the total current I_T reaching the data output TDO when only one of the circuits is enabled at a time is shown in Table 1 below:

[0033] Table 1

[0034]

[0035] However, Figure 4 This describes some examples of how one or more test circuits can be used simultaneously to represent different data possibilities, as detailed below.

[0036] During the time interval between t0 and t1, TDO is 0 (or some negligible value), indicating that none of the three test circuits 120, 122, and 124 is conducting a non-negligible current. Therefore, the insufficient current measured at TDO confirms that for each of the three test circuits 120, 122, and 124, the corresponding transistor with its gate connected to DST is receiving an enable signal, thus disabling any of the test circuits (e.g., Figure 4 (This is illustrated by the empty symbol for the time period). Therefore, between t0 and t1, the test easily translates insufficient current into data values ​​indicating the presence of the following Table 2:

[0037] Table 2

[0038]

[0039] During the time interval between t1 and t2, TDO (minus any offset from other devices contributing current to TDO in both non-test and test modes) is 50 µA. Recall that TDO is actually the total current I_T from all three test circuits 120, 122, and 124, and the corresponding values ​​of RDSON and I_T cause each test circuit to conduct a different amount of current when enabled. Therefore, in the current time interval (t1 to t2), where TDO = 50 µA, the test samples the TDO value, and it can be translated based on the values ​​in Table 1. That is, the 50 µA TDO value here translates to: during this time interval, test circuit 120 is enabled because it is the test circuit conducting 50 µA, while test circuits 122 and 124 are not enabled. Therefore, between t1 and t2, there are the data values ​​in Table 3 below:

[0040] Table 3

[0041]

[0042] Figure 4 The following two consecutive time periods also illustrate an example of only one test circuit being activated at a time: (i) between time t2 and t3, the value of TDO = 100 µA indicates that during this time period, test circuit 122 is activated because it is a test circuit that conducts 100 µA, while test circuits 120 and 124 are not activated; and (ii) between time t3 and t4, the value of TDO = 200 µA indicates that during this time period, test circuit 124 is activated because it is a test circuit that conducts 200 µA, while test circuits 120 and 122 are not activated.

[0043] During the time interval between t4 and t5, TDO is 150 µA. Therefore, as can also be understood from Table 1, TDO = 150 µA is sampled for testing and translates to an indication that more than one test circuit is activated during this time interval. Conversely, due to the power of the two ratios between the RDSON values ​​of each test circuit, each possible combination of the current values ​​in Table 1 for the two or three conduction test circuits will result in a unique total output. For example, TDO = 150 µA uniquely indicates that test circuits 120 and 122 are activated during this time interval, while test circuit 124 is not activated. Therefore, the data values ​​in Table 4 exist between t4 and t5:

[0044] Table 4

[0045]

[0046] Figure 4The following three consecutive time periods also illustrate an example of enabling multiple test circuits at once: (i) between time t5 and t6, the value of TDO = 350 µA indicates that all test circuits 122, 124, and 126 are enabled during this time period; (ii) between time t6 and t7, the value of TDO = 300 µA indicates that test circuits 122 and 124 are enabled during this time period, while test circuit 120 is not enabled; (iii) between time t7 and t8, the value of TDO = 250 µA indicates that test circuits 120 and 124 are enabled during this time period, while test circuit 122 is not enabled.

[0047] Figure 5A , 5B The 5C specification provides illustrative examples of test circuits 500.1, 500.2, and 500.3, any of which can be used in all test circuits 120, 122, or 124. Therefore, circuits 500.1, 500.2, or 500.3 can replace... Figure 3 Circuit 300, although some connections are similar, and some reference marks and signals from Figure 3 Transfer to Figure 5A , 5B And in 5C. Also as an introduction, with... Figure 3 compared to, Figure 5A , 5B The 5C diagram can be easily identified as an alternative configuration, wherein one or both of the transistor conduction types (NMOS or PMOS) are changed as appropriate, which can be a signal inversion for T_EN. With this change, when T_EN is asserted and the monitored data state DST is active high or active low (depending on the transistor conduction type, as detailed below), the conduction path is again implemented through two transistors.

[0048] exist Figure 5A In this circuit, test circuit 500.1 includes a PMOS transistor 502, whose source is connected to VCC and whose drain is connected to the drain of an NMOS transistor 504. The source of the NMOS transistor 504 is connected to GND / TDO and its gate is connected to DST. The gate of the PMOS transistor 502 is connected to the output of an inverter 506, and the input of the inverter 504 is connected to T_EN. When T_EN is asserted high, the inverter 506 provides a low signal to the PMOS transistor 502, causing it to turn on, while the NMOS transistor 504 only turns on when DST is asserted high. Therefore, test circuit 500.1 outputs a non-negligible current in response to a local AND operation of the high-state active inputs of T_EN and DST.

[0049] exist Figure 5BIn this circuit, test circuit 500.2 includes a PMOS transistor 520, whose gate is connected to DST, source to VCC, and drain to the drain of an NMOS transistor 522. The source of the NMOS transistor 522 is connected to GND / TDO, and its gate is connected to T_EN. When T_EN is asserted high, this provides a high signal to the gate of the NMOS transistor 522, turning it on, while the PMOS transistor 520 only turns on when DST is asserted low. Therefore, test circuit 500.2 outputs a non-negligible current in response to a logic AND operation between a high-state active input of T_EN and a low-state active input of DST.

[0050] exist Figure 5C In this circuit, test circuit 500.3 includes a PMOS transistor 540, whose source is connected to VCC and whose drain is connected to the drain of a PMOS transistor 542. The source of PMOS transistor 542 is connected to GND / TDO and its gate is connected to DST. The gate of PMOS transistor 540 is connected to the output of inverter 544, and the input of inverter 544 is connected to T_EN. When T_EN is asserted high, inverter 544 provides a low signal to the gate of PMOS transistor 540, thereby turning it on, while PMOS transistor 542 only turns on when DST is asserted low. Therefore, test circuit 500.1 outputs a non-negligible current in response to a logic AND operation between a high-state active input of T_EN and a low-state active input of DST.

[0051] Figure 6 A schematic diagram illustrating an alternative embodiment of IC 600. IC 600 and... Figure 1 The IC 100 shares various commonalities, therefore the reference number for common items starts from... Figure 1 Transfer to Figure 6 IC 600 further includes a current reference circuit 602 connected to VCC and outputting a fixed current reference I_REF. The current reference circuit 602 can be constructed in various forms, such as by using a bandgap current reference. A bandgap current reference is typically used to generate a stable and relatively fixed voltage or current, which is made possible by the inherent bandgap voltage of the IC substrate material (e.g., silicon). Despite changes in input voltage and temperature, the bandgap output current I_REF (or voltage) remains stable. Furthermore, in IC 600, the current I_REF is connected as an input to each of test circuits 604, 606, and 608, which will be described in further detail below.

[0052] Figure 7 The instructions can be used Figure 6A schematic diagram of an example embodiment of test circuit 700 in all test circuits 604, 606, and 608. Test circuit 700 includes three transistors with a shared source / drain path, which in the illustrated example are NMOS transistors 702, 704, and 706. Test circuit 700 also includes an additional NMOS transistor 708. The nominal on-resistance RDSON of all four transistors is described by Equation 1 detailed above, and the total series resistance of RDSON across all transistors should also be known to evaluate the test data output TDO.

[0053] The connectivity of the test circuit 700 is now described further to supplement the previous embodiment. The drain of NMOS transistor 702 is connected to external connection 710 for receiving VCC. The gate of NMOS transistor 702 is connected to external connection 712 for receiving data state DST. The source of NMOS transistor 702 is connected to the drain of NMOS transistor 704. The gate of NMOS transistor 704 is connected to external connection 714 for receiving test enable T_EN. The source of NMOS transistor 704 is connected to the drain of NMOS transistor 706. The gate of NMOS transistor 706 is connected to external connection 716 for receiving bandgap output current I_REF. The source of NMOS transistor 706 is connected to connection 718, which provides the total current I_T as test data output TDO and is also connected to the GND pin 104 of IC 600. I_REF is also connected to the drain and gate of NMOS transistor 708, and the source of NMOS transistor 708 is also connected to connection 718.

[0054] The operation of test circuit 700 is now described. Test circuit 700 provides a 2-input logic AND operation that gates the total current I_T output in response to inputs DST and T_EN coupled to an external configuration of current mirrors provided by NMOS transistors 706 and 708. Specifically, given the assertion state of the inputs (e.g., active high or active low) and the NMOS conduction type of transistors 702 and 704, transistors 702 and 704 are turned on when both DST and T_EN are active high, thereby providing a positive voltage to the drain of NMOS transistor 706. In response, NMOS transistors 706 and 708 form a current mirror of I_REF, wherein the total current I_T is further sourced from the two transistors in response to the magnitude of I_REF and further controlled by the W / L ratio between transistors 706 and 708. Therefore, if the available I_REF (e.g., based on a bandgap limit) is limited, then that limitation will necessarily also limit the total current I_T. However, some test equipment is able to sense a decrease in output current between different levels, thereby detecting different data that may occur for various combinations equivalent to those in Table 1, but each individual output is potentially at a value below 50 µA.

[0055] The above operations of the test circuit 700 are individually and generally applicable to... Figure 6 The test circuits are 604, 606, and 608. Specifically, during testing, via... Figure 6 Pin 110 asserts T_EN, and when the sampled data state DST is simultaneously asserted, the total output I_T provides a measurable signal as TDO, which is sampled at pin 104. When the current value at pin 104 is higher than a negligible level, this current level indicates that data DST is asserted, which, when active high, means that the sampled data state is at a logic high level, thus confirming the high-state active data state of DST. Therefore, similarly, when testing is enabled and data DST is invalid (logic low), no non-negligible current I_T is provided, thus confirming the high-state invalid data state of DST. Therefore, the magnitude of TDO indicates the state of DST during testing in each of the corresponding test circuits 604, 606, or 608. Furthermore, as previously demonstrated, RDSON can be adjusted for selected transistors (e.g., either 706 or 708, or further, either or both of 702 and 704) so ​​that each example of test circuit 700 used for test circuits 604, 606, and 608 provides a different output current value when enabled. As previously shown in conjunction with Table 1, when enabled, the different current values ​​provide distinguishable output signals for detecting the corresponding data status DST of each test circuit.

[0056] Figure 8 This diagram illustrates the example test environment 800. Environment 800 is used for testing and therefore also illustrates... Figure 1 IC 100 (or easily modified for testing) Figure 6 (IC 600). In addition to IC 100, the test environment 800 can also be manifested in various forms to complete... Figure 8 Other components, wherein, by way of example, some or all of said components can be implemented in various commercially available or developed general-purpose automated test equipment (ATE) 802. Therefore, in Figure 8In this context, ATE 802 typically refers to various components external to IC 100, and again, some or all of these may be considered as ATE 802. ATE 802 is programmable, or controlled by a separate programmable device (not shown), to sequentially pass through a test procedure that causes signals to be applied to IC 100. Therefore, ATE 802 is shown as including a variable voltage (or other signal) source 804, although typically, ATE devices include a considerable signal generation capability beyond a variable voltage source alone. The positive side of voltage source 804 is connected to provide a signal (e.g., voltage) to S_IN pin 106, and the negative side of voltage source 804 provides ATE ground 806. An input capacitor 808 is connected between S_IN pin 106 and ATE ground 806. A test load is included, which is shown, for example, as including an output capacitor 810 and an output resistor 812 connected between S_OUT pin 108 and ATE ground 806. Input and output capacitors 808 and 810 are examples of test applications, but may be optional for other examples, and are not limited to the implementation and testing of IC 100. The positive terminal of the 0V power supply 814 is connected to the GND pin 104, and the negative terminal of the 0V power supply 814 is connected to the first terminal of the ammeter 816. The second terminal of the ammeter 816 is connected to the ATE ground 806.

[0057] Figure 9 This indicates that it can be used for testing. Figure 8 A flowchart illustrating an example embodiment of method 900 for the execution of an ATE test procedure in environment 800. Method 900 is an example, and the teachings of this document also facilitate the addition, deletion, or reordering of one or more steps in method 900. Furthermore, the flowchart serves as an example regarding the ordering of steps, but other forms (e.g., state diagrams) may also be used to demonstrate the process from which appropriate ATE programming can be provided.

[0058] Method 900 begins at step 902. In step 902, the test of IC 100 is initiated, for example, by an assertion of the TEST (Test Enable) signal. As previously described, the TEST assertion can be directed to a dedicated TEST pin 110, typically indicated by an arrow pointing to the TEST pin 110, as can be accomplished via a signal from ATE 802. Alternatively, the signal can be asserted to one or more pins, which may include pins used for purposes other than testing during non-test operations, where the result is an assertion T_EN. Method 900 then proceeds to step 904.

[0059] In step 904, the variable voltage source 804 outputs a test input signal (e.g., a test voltage) level to the S_IN pin 106, and various circuit systems within IC 100 respond to the test input signal. For example, returning... Figure 1The test input signal has a propagation effect along signal path 112 through functional blocks 114, 116, and 118, and affects the data state in those blocks. Simultaneously, the asserted TEST (or T_EN) signal enables each transistor in each of the test circuits 120, 122, and 124 whose gate is connected. Therefore, and further attributable to the external connection 206 of each of those circuits (see...), the test input signal propagates along signal path 112 through functional blocks 114, 116, and 118, and affects the data state in those blocks. Figure 2 A forced 0V voltage is applied at the GND pin 104 to enable each circuit to output a corresponding current value, which is determined based on the transistor RDSON value and the data state DST in each test circuit. Next, method 900 continues to step 906.

[0060] In step 906, ammeter 816 measures the total current supplied by GND pin 104. The total current may be stored for later evaluation, or it may be substantially translated (e.g., analog-to-digital conversion) during step 906 to inform the data state DST in each test circuit. Specifically, and as described in more detail previously in conjunction with Table 1, given the interconnection of all test circuit outputs with a single node and considering the total number of test circuits, the total output current may be equal to the total output current of zero enabled test circuits, one enabled test circuit, or a combination of the enabled test circuits. Therefore, the total current represents an analog measure of the corresponding data state DST for all test circuits. Next, method 900 continues to step 908.

[0061] Step 908 is a condition check to determine if there is an additional input test signal (e.g., voltage) to be tested. For example, if IC 100 is an analog-to-digital voltage converter, then testing this device may involve sweeping through several different input analog voltage levels, checking the IC output (e.g., S_OUT106) each time to determine if the appropriate digital voltage has been reached. Similarly, for each of the same (or different) input voltages used to test the digital output, the example embodiment allows testing the internal state of this device. As another example, if IC 100 is a voltage regulator, then testing this device may also involve sweeping through several different input analog voltage levels, checking the IC output each time to determine if the IC has properly regulated to the desired (e.g., constant) output voltage. Therefore, again for each test input signal, the test according to the example embodiment may further include testing the internal data state DST value of IC 100. Thus, for these and other examples, several different input test signals may exist to be tested, and step 908 may therefore store conditions, such as the number of required test input signals, or some other control. Therefore, in each example, when further testing is desired at different input signals, step 908 returns control of method 900 to step 904, where a new input test signal is applied, followed by the examples of steps 906 and 908. In contrast, when all different input test signal levels have been tested, step 908 directs control of method 900 to step 910, where the assertion TEST signal is canceled. Therefore, after step 910, IC 100 is available for normal (non-test) operation and functionality.

[0062] As will be appreciated by those skilled in the art from the above, exemplary embodiments include ICs comprising DFT embedded production test circuitry systems and the testing of such ICs. For example, embodiments of apparatus and methods for testing ICs with multiple pins (e.g., IC 100 or IC 600) are described. In exemplary embodiments, IC testing is performed by sampling a signal at one IC pin other than its nominal signal output pin. In exemplary embodiments, such tests sample a signal (e.g., current) from the IC's GND pin. For exemplary embodiments, using the GND pin in this manner relative to another pin is preferred because the GND signal (and VCC) has already been distributed to all functional blocks in the IC design via corresponding signal paths, depending on the nature of the differential bias required for each block. Therefore, there are minimal additional layout considerations for adding test circuitry between each desired functional block and the already planned GND (and VCC) signal paths. In any case, the sampled signal at the desired pin (e.g., GND) responds to several (e.g., one or more) test circuits of the IC, each test circuit outputting a signal based on a corresponding data state of the IC (e.g., at a node within the IC). Furthermore, each test circuit may include a unique parameter (e.g., RDSON) that distinguishes the output signal of the respective test circuit from any other concurrently operating test circuits. Thus, multiple test circuits can output to a single mutual node without requiring additional switching circuitry to that node, and the node can be sampled, allowing identification of multiple data contributions from its signals. Furthermore, different example test circuit configurations have been shown, such as one responsive to an internal bandgap reference signal and another responsive to a test circuit power supply (e.g., VCC). The distinguishable outputs of the respective test circuits can also be combined, for example, where test signal outputs are connected to the current of the same node. Therefore, the example embodiment tests can simultaneously test multiple different data states (or data state nodes) of the IC, where the combined magnitude of all IC test circuits provides a signal from which the corresponding data state of each test circuit can be identified. The signal example embodiment provides additional benefits. For example, tests can be implemented using readily available commercial ATE IC test equipment, where DUT output sampling is performed at various output signal levels (e.g., µA to mA). As another example, the IC can be implemented using this teaching in a package with a relatively low or large pin count. As another example, structures can be added in parallel or series to achieve redundancy. As yet another example, the number of monitored / tested data states can vary. Those skilled in the art will understand or determine these and other contents based on the teachings of this document. Therefore, additional modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An integrated circuit, comprising: Multiple pins, including signal output pins; Multiple signal nodes, each of which is operable to store a corresponding internal data signal; and Multiple test circuits, each of which is configured to sample a corresponding internal data state and, in response to sampling the corresponding internal data state, each of the multiple test circuits is configured to simultaneously couple a unique output signal to the same pin among the multiple pins, excluding the signal output pin.

2. The integrated circuit of claim 1, wherein the unique output signal of each test circuit is provided in response to parameter differences between each of the plurality of test circuits.

3. The integrated circuit of claim 1, wherein the unique output signal of each test circuit is provided in response to the resistance difference between each of the plurality of test circuits.

4. The integrated circuit of claim 1, wherein the unique output signal of each test circuit is provided in response to structural differences between each of the plurality of test circuits.

5. The integrated circuit of claim 1, wherein the unique output signal of each test circuit is provided in response to either a difference in transistor width or a difference in transistor length among the plurality of test circuits.

6. The integrated circuit of claim 1, wherein the same pin includes a ground pin of the integrated circuit used as a test data output.

7. The integrated circuit of claim 1, wherein the unique output signal comprises current.

8. The integrated circuit according to claim 1: The sole output signal mentioned above includes current; and The difference between the current, which is the unique output signal from each of the plurality of test circuits, and the current, which is the unique output signal from each of the other test circuits, is a power of 2.

9. The integrated circuit of claim 1, wherein each of the plurality of test circuits comprises: The first transistor has a gate coupled to receive a test enable signal; The second transistor has a gate coupled to receive the internal data signal from a respective signal node among the plurality of signal nodes; and An output node is configured to output a unique output signal in response to the state of the test enable signal and the state of the internal data signal from the corresponding signal node among the plurality of signal nodes.

10. The integrated circuit of claim 9, wherein each of the first transistor and the second transistor comprises an NMOS transistor.

11. The integrated circuit according to claim 9: The first transistor includes an NMOS transistor; The second transistor includes a PMOS transistor; and The corresponding internal data signal mentioned above is a low-state active signal.

12. The integrated circuit of claim 1, wherein each of the plurality of test circuits comprises: The first transistor has a gate coupled to receive a test enable signal; The second transistor has a gate coupled to receive the internal data signal from a respective signal node among the plurality of signal nodes; The third transistor is configured to mirror the current source; and An output node is configured to output a unique output signal in response to the state of the test enable signal, the state of the internal data signal from the corresponding signal node among the plurality of signal nodes, and the current source.

13. A testing system comprising: Integrated circuits, including: Multiple pins, including signal output pins and signal input pins; Multiple signal nodes, each of which is operable to store a corresponding internal data signal; Multiple test circuits, each of the multiple test circuits being configured to sample a corresponding internal data state, and in response to sampling the corresponding internal data state, each of the multiple test circuits being configured to simultaneously couple a unique output signal to the same pin of the multiple pins other than the signal output pin; A circuit system for applying voltage to the signal input pin; and A circuit system for determining the corresponding internal data state of each test circuit in response to an output at the same pin.

14. The test system of claim 13, further comprising a circuit system for sampling the total current at the same pin.

15. A method for testing the internal data state of an integrated circuit, comprising: Enable the test mode for the integrated circuit; During the test mode, an input signal is applied to the integrated circuit, which includes signal output pins; During the test mode, the output signal at the pins of the integrated circuit, excluding the signal output pin, is measured; and The output signal is translated into multiple internal data states of the integrated circuit.

16. The method of claim 15, wherein the measurement step includes measuring an output signal used as a test data output at a ground pin of the integrated circuit.

17. The method of claim 15, wherein the measurement step includes measuring the current output signal at a pin of the integrated circuit.

18. The method of claim 15, wherein the measurement step comprises measuring a current output signal used as a test data output at a ground pin of the integrated circuit.

19. The method according to claim 15: Each of the plurality of internal data states corresponds to a corresponding test circuit in the plurality of test circuits; and Each of the test circuits is operable to output a corresponding output signal that is different from the output signal from each of the other test circuits in the plurality of test circuits.

20. The method according to claim 15: Each of the plurality of internal data states corresponds to a corresponding test circuit in the plurality of test circuits; and Each of the test circuits is operable to output a corresponding output current signal, the difference between the output current signal and the current output signal from each of the other test circuits in the plurality of test circuits being a power of 2.

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