Skeleton representation of layout for developing photolithography masks

Abstract

A method comprising the steps of: accessing a layout used in a lithography mask development process, for example, the layout may be the layout of the mask itself, or it may be the layout of the resulting printed pattern on a wafer; the layout comprises a plurality of non-intersecting shapes; determining a skeleton representation for at least some of the non-intersecting shapes in the layout; the skeleton representation of the individual shapes has elements of two or more nodes connected by edges; it also includes size parameters for at least some of the elements; the skeleton representation of the shapes is used in the mask development process. A system comprising a processor for executing the method. A non-transitory computer readable medium comprising stored instructions for executing the method.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 977,020, filed on February 14, 2020, “Skeleton Mask Representation,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the development of photolithographic masks, such as for use in the manufacture of integrated circuits. Background Art

[0004] As integrated circuit designs become larger, denser, and more complex, the need for computational lithography solutions to develop masks used in manufacturing continues to increase. Features on masks become smaller and less straight. For example, advanced mask writing tools can produce curved shapes. This makes their simulation more difficult and more computationally intensive. In addition, the number of features on masks continues to increase, further increasing the computational requirements. The lithography process itself has also become more complex. For example, the illumination sources have become more complex. This in turn requires more complex analysis. Therefore, when processing mask layout through mask-related applications such as optical proximity correction (OPC), inverse lithography technology (ILT), and lithography verification, measures need to be taken to reduce processing requirements. Summary of the invention

[0005] In certain embodiments, a method includes the following steps. A layout used in a lithography mask development process is accessed. For example, the layout can be the layout of the mask itself, or it can be the layout of the resulting printed pattern on a wafer. The layout includes a number of non-intersecting shapes. A skeleton representation is determined for at least some of the non-intersecting shapes in the layout. The skeleton representation of the individual shapes has elements of two or more nodes connected by edges. It also includes size parameters for at least some of the elements. The skeleton representation of the shapes is used in the mask development process.

[0006] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other techniques related to any of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of embodiments of the present disclosure. The accompanying drawings are used to provide knowledge and understanding of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0008] Figure 1 A flow chart of a mask development process is depicted in accordance with some embodiments of the present disclosure.

[0009] Figure 2A-2C Depicted are examples of polygonal representations and corresponding skeletal representations of individual shapes in a layout.

[0010] Figure 3A-3B Depicted is the conversion of a polygonal representation to a skeletal representation.

[0011] Figure 3C-Figure 3D Depicted is the conversion of a skeletal representation to a polygonal representation.

[0012] Figure 4A Depicts the perturbation at the tip of the shape.

[0013] Figure 4B Another example of a perturbation of a shape is depicted.

[0014] Figure 5 and Figure 6 Depicted is the use of a skeleton representation for mask rule checking.

[0015] Figure 7 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure.

[0016] Figure 8 An abstract diagram of an example computer system is depicted in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure relate to a skeletal representation of layouts for developing lithography masks. Traditionally, mask layouts are represented by polygons, and more specifically, by rectilinear polygons. However, as lithography becomes more complex and challenging, mask layouts also become more complex. The use of sub-resolution assist features and non-rectangular and even curved shapes makes traditional representations based on rectilinear polygons less than ideal. Representing curved shapes with rectilinear polygons requires a large number of polygons, and the curved edges are still represented by a staircase approximation. Even if non-rectilinear polygons are allowed, the curved edges will still require polygons with a large number of sides to approximate the curve.

[0018] Many processes used in mask development, such as optical proximity correction (OPC), inverse lithography technology (ILT), and lithography verification, require analysis or manipulation of these representations. For example, these mask development processes may introduce subtle changes in the layout to determine whether these changes are beneficial.

[0019] In the method described below, the layout is represented by a skeleton representation, rather than a polygonal representation. The layout can be a layout of the mask itself, a layout of the resulting printed pattern on the wafer, a two-dimensional representation of an aerial image produced by the mask, or other types of two-dimensional images used for mask development. The layout includes a large number of shapes that can traditionally be represented by straight polygons. Here, at least some of the shapes are represented by a skeleton representation as a replacement or supplement for other types of representations. The skeleton representation of an individual shape includes a "skeleton", which corresponds to the axis or centerline of the shape. The elements of the skeleton include two or more nodes connected by edges. The nodes are the "joints" of the skeleton, and the edges are the "bones" of the skeleton. The skeleton representation also includes size parameters for at least some of these elements. These size parameters provide information about the size of the shape at different positions along the skeleton. For example, the size parameters for the edge elements in the skeleton representation can be based on the width of the shape along those edges. The size parameters for the nodes in the skeleton representation can be based on the local radius of the shape at those nodes.

[0020] For certain mask development processes, a skeleton representation can be a more compact and computationally efficient representation of a layout. For example, if the position of a shape needs to be moved or the thickness of a shape needs to be changed, this can be accomplished simply by modifying the corresponding elements (nodes and edges) and / or by changing the various sizing parameters used for those elements. As a result, computation speed is increased and the required computational resources (memory and processor utilization) are reduced.

[0021] Figure 1 A flow chart of a mask development process according to some embodiments of the present disclosure is depicted. The techniques described in the present disclosure can be applied to many types of mask development processes 120. This includes a mask synthesis process (e.g., designing a mask to achieve a desired result) and a mask verification process (e.g., confirming whether the mask design produces the desired result). It also includes a forward propagation process (e.g., predicting an aerial image produced by a mask) and a backward propagation (e.g., based on a desired aerial image, backpropagating to determine a mask that will produce the aerial image). Examples of mask development processes 120 include optical proximity correction (OPC), inverse lithography technology (ILT), and lithography verification (including mask design rule checking).

[0022] The input to the mask development process 120 is a layout 110 of various geometric shapes. For the mask development process 120, the layout 110 may be a layout of a mask for manufacturing an integrated circuit, but the skeleton representation is not limited to this example. In many cases, the shapes in the layout are represented as polygons, such as Figure 1 The polygonal representation 115 is shown.

[0023] The result of the mask development process 120 is generally referred to as a "solution" 190. The solution will depend on the mask development process 120. Table 1 below lists some example applications. The "Layout" column is the input to the mask development process, and the "Solution" column is the output. The "Skeleton Representation" column indicates which quantities the skeleton representation can represent.

[0024] Table 1: Some example mask development processes

[0025]

[0026]

[0027] In one approach, the mask development process 120 is applied to shapes in the layout by using a skeletal representation 125 for at least some of the shapes, such as Figure 1 1. The layout 110 includes a plurality of non-intersecting shapes. A skeleton representation is determined 122 for at least some of the shapes. The skeleton representation of the individual shapes includes elements of two or more nodes connected by edges. The skeleton representation also includes size parameters for at least some of the elements. A mask development process is then applied 124 using the skeleton representation of the shapes.

[0028] Figure 2A-2C Depicted are examples of polygonal representations and corresponding skeleton representations of individual shapes in a layout. In each figure, a polygonal representation with only a skeleton superimposed with dashed lines is shown on the left, and a skeleton representation is shown on the right, where both the skeleton and the edges are defined by size parameters. The polygonal representation 210 is a piecewise linear approximation of the boundary of the shape. In these examples, the polygonal representation 210 is based on boundary segments at 45 degree angles. The skeleton representation 250 includes a skeleton 252 of segmented connections of nodes and edges. In the figure, the nodes are circles, and the edges are thicker lines connecting the circles. The skeleton 252 is a representation of the two-dimensional mask polygon 210, but in a "lower" dimension. It can be based on a morphological erosion of the shape 210.

[0029] The skeleton representation 250 may have additional attributes. Figure 2AIn it, nodes and edges are associated with dimensional parameters. Node N is characterized by a local radius R, and edge E is characterized by a width W. These dimensional parameters represent the local radius R of the curve defined by the node, and the width W of the shape defined by the edge. Node N1 is an end node (i.e., connected to only one other node), so the shape has a tip with a radius of R = R0. Edges E1, E2, and E3 all have a width W = W0 = R0. Node N4 is also an end node with a radius R = R0. Nodes N2 and N3 are internal nodes (connected to two or more other nodes). Their radius R = R0 defines the shape of the local curved shape centered at these nodes. These attributes can be used to reconstruct the original shape 210 from the basic skeleton 252 through dilation or scaling procedures. The scaling procedure uses the dimensional parameters defined at the nodes / edges to appropriately scale the corresponding segments of the basic shape 210. Reducing the mask representation to a lower dimension allows for simpler algorithms to be implemented for various geometric manipulations, and there are many features on the mask, such as auxiliary features, which have a high aspect ratio and can be well represented by a non-branching skeleton, such as as Figure 2A shown in

[0030] The skeleton representation can include additional attributes to represent more complex shapes, including those with branching skeletons. In Figure 2B it, the axis of the shape has multiple branches in an "H" shape, so the skeleton 252 is bifurcated. It includes nodes N1 - N6 and edges E1 - E5. Additionally, the tip of the shape is a rounded corner rather than an arc. To capture this, the end node N1 is characterized by two dimensional parameters: R and r. R defines the width of the end shape, and r defines the local radius of the corner. Thus, r = 0 specifies a square tip, and r = R specifies a circular tip, as Figure 2A shown in Figure 2B it, 0 < r < R and the tip has a rounded corner. Additionally, nodes N2 and N5 can have negative values of r to specify the shape of the internal corners along the crossbar of the "H". Other parameters can also be used to provide more degrees of freedom. For example, the tips and other curves corresponding to the nodes can be elliptical, polygonal, or other shapes. The branches corresponding to the edges can vary in width: linearly increasing or decreasing, varying periodically, or in other ways. Different parameters can be used to capture these and other variations.

[0031] Figure 2C Another example is shown where the skeleton 252 has six nodes N1 - N6, but nodes N1 - N3 are connected as a polygon, and so are nodes N4 - N6. In some cases, the shape can have internal holes.

[0032] Nodes and edges can also have attributes that capture information other than the original shape. One example is the association from a node or edge to a specific polygonal feature. For example, a specific skeleton node N or edge E can be associated with (multiple) specific polygonal segments. This can be used in an OPC solver, where the node N and its parameters (such as radius) are adjusted until the simulation mask (defined by N and other skeleton nodes) prints an image on a target at the polygonal segment or at a point on the segment. Other examples include constraints on the displacement of nodes / edges, constraints on the size of nodes / edges, and other constraints on segments or shapes associated with nodes / edges.

[0033] Different techniques can be used to generate a skeletal representation from polygonal or other representations. Figure 3A-3B An example is shown in FIG. In this example, a polygonal representation 310 of a shape is first converted into a Voronoi diagram 320, such as Figure 3A The Voronoi diagram is the medial axis of the polygon. Figure 3B As shown in , the Voronoi diagram is then trimmed to create a skeleton of nodes and edges 330. The trimming can be a function based on the distance between points on the polygonal boundary that define a particular point on the Voronoi diagram. Alternatively, the trimming can be based on the proximity of the medial axis to the boundary. Additional attributes (such as width and radius and which polygon segments correspond to which skeleton elements) can then be attached to the skeleton.

[0034] In the opposite direction, different techniques can be used to convert the skeletal representation to a complete shape, such as a polygonal representation. Figure 3C-Figure 3D One method is shown in FIG. Figure 3C A skeleton 340 is shown. The nodes and edges of the skeleton are expanded according to their radius and width, as indicated by the light arrows. Alternatively, polygons can be created for the nodes and edges and then merged, with the resulting polygons 350 being Figure 3D In some cases, the skeleton can be simplified before creating polygons.

[0035] There are many use cases where a skeleton representation is more efficient than other representations. In one class of use cases, it is desirable to move a shape or a portion of a shape in a direction perpendicular to the axis of the shape. The skeleton representation naturally allows this to be done. An example of this use case is the use of perturbation tables for OPC. When perturbations are applied to the boundaries of mask M (i.e., when the boundaries of the shape are moved), the perturbation tables allow the tool to quickly calculate the changes in the solution produced by the lithography simulation of mask M. For example, a perturbation table can tabulate the changes in wafer intensity for a given mask perturbation. The use of perturbation tables for skeletons is described below.

[0036] The general mask synthesis problem can be formulated as the optimization of a cost function C(L), which takes as input a lithography signal L (e.g., mask layout) and returns a cost value C. The gradients of C with respect to different perturbations P can be computed. These gradients dC / dP can be used to optimize the layout via a gradient-based optimization scheme.

[0037] like Figure 4A A perturbation of the end 490 of the shape is depicted. In the skeleton representation 450, the end is represented by nodes N1, N2 and edge E1. Nodes N1, N2 have radius R=R0, and edge E1 has width W=W0=R0. If a polygonal representation 410 is used, the tip is represented by seven boundary segments 421-427 that approximate the rounded tip. This is not even a good approximation. A more accurate approximation would use even more boundary segments.

[0038] Perturbing the tip will require moving all affected boundary segments together. As each individual boundary segment is perturbed, the resulting change in the cost function is measured, and a lithography cost gradient dC / dP can be calculated for a given perturbation P. However, if a skeletal representation for the shape is used, the gradient dC / dP can be calculated with respect to the geometric parameters of the skeleton, which can be simpler and more computationally efficient.

[0039] For example, suppose the perturbation of interest is increasing the size of end 490. For the skeleton representation, this is equivalent to increasing the size parameter W=R, with some corresponding movement in the position of node N2. The effect of the perturbation is given by the gradient dC / dW. In the polygonal representation, the seven boundary segments 421-428 move together, and the total gradient is the sum of the individual gradients for each boundary segment.

[0040] Now consider Figure 4B Another example is shown in . In this example, node N1 is the skeleton element to be optimized. In particular, consider the optimization of the position of node N1 along a certain direction v. First assume v = t(N1), i.e. the tangent of the skeleton edge E1 connected to node N1. This takes into account stretching and shrinking the shape along the axis of the shape. If the formula is available, the gradient dC / dN T can be calculated and used for optimization.

[0041] Alternatively, the gradient can be constructed from the collective derivatives of the polygonal boundary segments associated with the node N. Call this set D = {D i}. According to the construction of the polygon from the skeleton, the set D includes boundary segments 423-425. These segments D i Each segment in will have its own cost change dC i , and the normals of these segments {n i} and length {L i} can be used to project the cost change onto t(N) according to equation (1).

[0042]

[0043] where the summation is for polygon segment i (segments 423-425) and "·" is the dot product.

[0044] Now consider the change in radius R of node N1. To calculate the derivative (dC / dR) with respect to the change in radius at node N1, the system can use dC projected onto the outer normal of the corresponding polygon edge 423-425. i sum.

[0045] Now consider the lateral displacement of the shape, which is the movement of edge El in a direction perpendicular to its direction.To calculate the derivative with respect to the lateral displacement of the shape, the system can find the derivative with respect to moving edge El in a direction orthogonal to the edge (dC / dE).

[0046] If this is calculated using a polygonal representation, segment D is projected onto the normal vector n(E1) of edge E1. This is given by equation (2).

[0047]

[0048] where the sum is taken over the affected polygon segment i. Note that the boundary segments D associated with node N1 in equation (2) are a different set than those associated with node N1 in equation (1). Other variations of combinations of these derivatives can be calculated to allow for other skeleton modifications that may be useful depending on the application needs.

[0049] After computing these gradients, a gradient-based optimization scheme can be used to move skeleton elements or modify their parameters to optimize the mask to achieve an improved cost function C.

[0050] The above method for OPC can also be used for ILT and other mask development processes. In ILT, the optimization of skeleton elements uses the ILT cost function and the corresponding gradient field, except for the derivative value dC i The gradient field can be calculated as described above, except that it is calculated from the ILT cost function gradient field that can be sampled at the polygon edges. Subsequent movements by tangential node shifting, modifying the radius, or edge shifting will be similar to those described above. This is because the ILT gradient is calculated with respect to the level set function, whose external normal has magnitude = 1 at the polygon edges.

[0051] Similar to the lithography cost based optimization step, the implementation of MRC (Mask Rule Checking) can also be done by computing appropriate corrections on the mask polygon edges and then applying them in the manner described above to modify the skeleton element positions and / or parameters. Thus, standard MRC checks that can be applied to polygons can be applied, and the violation information can then be used to guide skeleton geometry operations to resolve the MRC violations. Figure 5 , boundary segments 512 and 514 of polygonal representation 510 are the two segments closest to each other. They are too close and a mask rule violation occurs. A polygon-based MRC check identifies these two boundary segments and the rule violation. Segment 512 is associated with node N1 of the top skeleton, and segment 514 is associated with edge E1 of the bottom skeleton. These skeleton elements 550 can then be modified in a way that reduces or eliminates the MRC violation.

[0052] Another way to calculate the estimated MRC result is to calculate the distances between adjacent skeletons and skeleton elements. Figure 6 Two separate skeletons 650 and 655 are shown. Skeleton 655 is for a shape that folds over itself, such as a U-shape. Note that these are the skeletons themselves, not the shapes. The borders of the shapes are omitted for clarity. The double-headed arrows show the locations of possible MRC violations. Given the distance between the two skeletons at these locations and their corresponding size parameters, MRC spacing violations can be evaluated.

[0053] This detection can be accomplished by using an edge-to-edge search algorithm. Alternatively, it can be accomplished by creating additional "MRC" skeletons 670, 675 of mask skeletons 650, 655. In the figure, the MRC skeletons are shown as dotted lines, and these skeletons contain information about which mask skeleton edges are closest to the MRC skeletons and how far they are. This information can be used to calculate the position of the MRC violation. This is a useful technique because the skeleton creation naturally determines which edges of the skeleton 655 can be compared to each other to determine that the MRC spacing violates.

[0054] Figure 7An example set of processes 700 used during the design, verification, and manufacture of an article such as an integrated circuit is illustrated to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term "EDA" represents the term "electronic design automation". These processes begin with creating a product idea 710 using information provided by a designer, which is transformed to produce an article using a set of EDA processes 712. When the design is completed, the design is tape-out 734, which is when the artwork (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing plant to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor die are manufactured 736, and packaging and assembly processes 738 are performed to produce a finished integrated circuit 740.

[0055] The specification of a circuit or electronic structure can range from low-level transistor material layout to high-level description languages. Using a hardware description language ("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera, circuits and systems can be designed using a high level of abstraction. The HDL description can be converted to a logic-level register transfer level ("RTL") description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of abstraction (i.e., less abstract description) adds more useful detail to the design description, for example, more detail for the modules that comprise the description. Lower levels of abstraction (i.e., less abstract descriptions) can be computer-generated, derived from a design library, or created by another design automation process. An example of a specification language for lower levels of abstraction language that specify more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is enabled for use by the corresponding tools for that layer (e.g., formal verification tools). The design process can use Figure 7 The described process is enabled by an EDA product (or tool).

[0056] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction, etc. At this stage, the design may be divided into different types of modules or components.

[0057] During logic design and functional verification 717, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of a circuit can be verified to generate outputs that match the specifications of the designed circuit or system. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components called "simulators" or "prototyping systems" are used to speed up functional verification.

[0058] During synthesis and design for testing 718, the HDL code is converted to a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are manufactured layered products that can be used by the EDA product to verify whether the integrated circuit performs according to the specified design when it is manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify whether the integrated circuit meets the requirements of the specification.

[0059] During netlist verification 720, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 722, the overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0060] During layout or physical implementation 724, physical placement (placement of circuit components (such as transistors or capacitors)) and routing (connection of circuit components through multiple conductors) are performed, and selection of cells from a library to enable specific logic functions may be performed. As used herein, the term "cell" may specify a collection of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flip-flop or latch). As used herein, a circuit "block" may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components and may be enabled as both physical structures and simulations. Parameters such as size are specified for the selected cell (based on a "standard cell") and made accessible in a database for use by EDA products.

[0061] During analysis and extraction 726, circuit functionality is verified at the layout level, which allows improvements to the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints (such as DRC constraints, electrical constraints, lithography constraints) are correct and that the circuit functionality matches the HDL design specifications. During analytical enhancement 730, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0062] During tape-out, data is created for use in producing lithographic masks (after applying lithographic enhancements if appropriate).During mask data preparation 732, the "tape-out" data is used to generate lithographic masks that are used to produce finished integrated circuits.

[0063] Computer systems (such as Figure 8 The storage subsystem of the computer system 800) can be used to store programs or data structures that are used by some or all of the EDA products described herein and by products used to develop units of the library and products used to design physical and logical designs using the library.

[0064] Figure 8 An example machine of a computer system 800 is illustrated in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client computer in a cloud computing infrastructure or environment.

[0065] The machine may be a personal computer (PC), a tablet computer, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specifies actions to be performed by the machine. In addition, while a single machine is illustrated, the term "machine" should also be understood to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0066] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.)), and a data storage device 818, which communicate with each other via a bus 830.

[0067] Processing device 802 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 802 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 802 can be configured to execute instructions 826 to perform the operations and steps described herein.

[0068] The computer system 800 may further include a network interface device 808 to communicate over a network 820. The computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generating device 816 (e.g., a speaker), a graphics processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0069] The data storage device 818 may include a machine-readable storage medium 824 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methods or functions described herein. During execution of the instructions 826 by the computer system 800, the instructions 826 may also reside, in whole or in part, within the main memory 804 and / or within the processing device 802, the main memory 804 and the processing device 802 also constituting machine-readable storage media.

[0070] In some embodiments, the instructions 826 include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding an instruction set that is used to be executed by a machine and causes the machine and processing device 802 to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0071] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the substance of their work to others skilled in the art. An algorithm may be a sequence of operations that result in a desired result. These operations are operations that require physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0072] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise clearly indicated from this disclosure, it should be understood that throughout this description certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0073] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used together with the program according to the teachings herein, or it may prove easy to construct a more specialized device to perform the method. In addition, the present disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0075] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory device, etc.

[0076] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It is apparent that various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and the same elements are marked with the same reference numerals. Therefore, the present disclosure and the accompanying drawings should be considered illustrative rather than restrictive.

Claims

1. A method for representing a layout, comprising: accessing a layout used in a mask development process for a photolithography mask, the layout comprising a plurality of non-intersecting shapes; determining, by a processor, skeletal representations for at least some of the non-intersecting shapes in the layout, wherein the skeletal representations of individual shapes include elements of two or more nodes connected by edges, and include size parameters for at least some of the elements, wherein each edge connects two of the nodes and is within a boundary of the individual shape; and The skeleton representation is used in the mask development process.

2. The method of claim 1 , wherein the individual shapes are polygons, and determining the skeletal representation of the individual shapes comprises: determining a Voronoi diagram for the polygon; as well as Based on the Voronoi diagram, the skeleton representation is determined. 3 . The method of claim 1 , wherein the nodes and the edges of the skeletal representation of the individual shapes are based on morphological erosion of the individual shapes.

4. The method of claim 1, wherein the individual shapes are reconfigurable by morphologically dilating the nodes and the edges of the skeletal representation of the individual shapes according to the size parameters for the nodes and the edges. The method of claim 1 , wherein the size parameters for edges of a skeletal representation are based on the widths of the individual shapes along those edges.

6. The method of claim 1, wherein the size parameters for nodes of a skeletal representation are based on local radii of the individual shapes at those nodes. The method of claim 1 , wherein the edges correspond to axes of the individual shapes.

8. The method of claim 7, wherein the axis is bifurcated.

9. The method of claim 1 , wherein the mask development process is one of optical proximity correction and inverse lithography, and using the skeleton representation in the mask development process comprises: An impact on a cost function of the mask development process resulting from a change in a position of the element of the skeleton representation is determined.

10. The method of claim 1, wherein the mask development process is one of optical proximity correction and inverse lithography, and using the skeleton representation in the mask development process comprises: An impact on a cost function of the mask development process resulting from a change in the dimensional parameter of the skeletal representation is determined.

11. The method of claim 1 , wherein the mask development process is mask rule checking, and using the skeleton representation in the mask development process comprises: A spacing between two shapes is determined based on the spacing between the elements of the skeletal representation for the two shapes in the layout and based on the size parameters of the elements.

12. A system for representing a layout, comprising: a memory storing instructions; as well as a processor coupled to the memory and configured to execute the instructions, which when executed cause the processor to: accessing a layout used in a mask development process for a photolithography mask, the layout comprising a plurality of non-intersecting shapes; determining skeletal representations for at least some of the non-intersecting shapes in the layout, wherein the skeletal representations of individual shapes include elements of two or more nodes connected by edges, and include size parameters for at least some of the elements, wherein each edge connects two of the nodes and is within a boundary of the individual shape; and The skeleton representation is used in the mask development process.

13. The system of claim 12, wherein the layout is a mask layout for a mask developed by the mask development process.

14. The system of claim 12, wherein the layout is one of: an aerial image produced by the photolithography mask and a printed pattern produced by the photolithography mask on a wafer.

15. The system of claim 12, wherein the individual shapes are polygons, and determining the skeletal representations of the individual shapes comprises: determining a Voronoi diagram for the polygon; as well as Based on the Voronoi diagram, the skeleton representation is determined.

16. The system of claim 12, wherein the nodes and the edges of the skeletal representation of the individual shapes are based on morphological erosion of the individual shapes.

17. The system of claim 12, wherein the individual shapes are reconfigurable by morphologically dilating the nodes and the edges of the skeletal representation of the individual shapes according to the size parameters for the nodes and the edges.

18. A non-transitory computer readable medium comprising stored instructions that, when executed by a processor, cause the processor to: accessing a layout used in a mask development process for a photolithography mask, the layout comprising a plurality of non-intersecting shapes; determining skeletal representations of at least some of the non-intersecting shapes in the layout, wherein the skeletal representations of individual shapes include elements of two or more nodes connected by edges, and include size parameters for at least some of the elements, wherein each edge connects two of the nodes and is within a boundary of the individual shape; and A representation of the skeleton is provided for use in the mask development process.

19. The non-transitory computer readable medium of claim 18, wherein the mask development process is one of optical proximity correction and inverse lithography, and using the skeletal representation in the mask development process comprises: An impact on a cost function of the mask development process resulting from a change to the skeletal representation is determined.

20. The non-transitory computer readable medium of claim 18, wherein the mask development process is a mask rule checking, and using the skeleton representation in the mask development process comprises: Based on the skeletal representations for two shapes in the layout, a spacing between the two shapes is determined.

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