Solid-state storage hard disk and control method of solid-state storage hard disk

Abstract

A solid-state storage hard disk and a solid-state storage hard disk control method, wherein the solid-state storage hard disk includes a controller, a selector, and N NAND flash memory chips, N is an integer greater than 1, the N NAND flash memory chips constitute P NAND flash memory chip arrays, P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips respectively; the controller is used to output multiple selection signals to the selector, wherein the multiple selection signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, M is an integer greater than or equal to 1 and less than or equal to N (701); the selector is used to select M NAND flash memory chips for data transmission according to the multiple selection signals (702). The method is conducive to improving the interface rate of the solid-state storage hard disk, and at the same time does not limit the storage capacity of the solid-state storage hard disk, and can simultaneously meet the performance requirements of high interface rate and high storage capacity of the solid-state storage hard disk.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a solid-state storage hard disk and a control method for the solid-state storage hard disk. Background Art

[0002] Since the advent of the internet, the amount of data has exploded exponentially, placing increasingly stringent requirements on the capacity specifications and interface speeds of solid-state storage drives. To achieve these high capacity specifications, solid-state storage drives are equipped with a large number of NAND flash memory chips. These chips are grouped into multiple channels, and the multiple NAND flash memory chips corresponding to each group are connected to the solid-state storage drive's controller via the same input / output bus. However, as the number of NAND flash memory chips connected to the same input / output bus increases, the load rate of the input / output bus also increases. When the load rate of the input / output bus exceeds a certain threshold, the interface speed of the solid-state storage drive decreases, increasing data read and write latency.

[0003] In related technologies, in order to increase the interface speed of solid-state storage hard drives and reduce data read and write delays, it is necessary to reduce the number of NAND flash memory chips connected to the input and output buses and control the load rate of the input and output buses.

[0004] However, controlling the load rate of the input and output bus will result in a reduction in the capacity specifications of the solid-state storage hard drive; failing to control the load rate of the input and output bus will result in the interface rate of the solid-state storage hard drive being unable to be increased, making it difficult to simultaneously achieve both a high interface rate and a high capacity specification of the solid-state storage hard drive. Summary of the Invention

[0005] The embodiments of the present application provide a solid-state storage hard disk and a control method for the solid-state storage hard disk, which are used to solve the technical problem that high interface rate and high capacity specifications are difficult to achieve simultaneously in existing solid-state storage hard disks.

[0006] In a first aspect, the present application provides a solid-state storage hard disk, comprising: a controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips, respectively; the controller is used to output multiple selection signals to the selector, wherein the multiple selection signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is an integer greater than or equal to 1 and less than or equal to N; the selector is used to select the M NAND flash memory chips for data transmission according to the multiple selection signals.

[0007] The controller is used to output a selection signal for indicating part of the NAND flash memory chip, and the selector is used to select the part of the NAND flash memory chip indicated by the selection signal for data transmission, which effectively solves the problem of heavy load on the input and output bus of the solid-state storage hard disk, is beneficial to improving the interface rate of the solid-state storage hard disk, and does not limit the storage capacity of the solid-state storage hard disk. It has wide applicability and can effectively solve the problems of heavy load on the input and output bus and reduced interface rate of large-capacity solid-state storage hard disk.

[0008] In one possible design, the selector includes a bus selector and a chip selector, the controller is connected to the bus selector and the chip selector respectively, the bus selector is connected to the P NAND flash memory chip array through P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips; the bus selector is used to determine a group of input and output buses in the P groups of input and output buses according to each of the selection signals; the chip selector is used to determine each NAND flash memory chip in the M NAND flash memory chips according to each of the selection signals.

[0009] By using the bus selector and chip selector to select some NAND flash memory chips for data transmission according to the selection signal output by the controller, the problem of excessive load on the input and output buses of the solid-state storage hard disk can be effectively solved, which is beneficial to improving the interface rate of the solid-state storage hard disk. The selection process of the NAND flash memory chip does not require software participation, which can avoid increasing software complexity.

[0010] In one possible design, each of the selection signals includes a first signal bit group and a second signal bit; the bus selector is used to receive the first signal bit group in each of the selection signals, and determine a group of input and output buses in the P groups of input and output buses based on the first signal bit group; the chip selector is used to receive the first signal bit group and the second signal bit group in each of the selection signals, and determine each NAND flash memory chip in the M NAND flash memory chips based on the first signal bit group and the second signal bit group.

[0011] The bus selector selects the input and output bus according to the first signal bit group in the selection signal, and the chip selector selects the NAND flash memory chip according to the first signal bit group and the second signal bit group in the selection signal. By switching the input and output bus and selecting the NAND flash memory chip connected to the input and output bus, the problem of excessive load on the input and output bus of the large-capacity solid-state storage hard disk is effectively solved, which is beneficial to improving the interface rate of the large-capacity solid-state storage hard disk and the data reading and writing speed of the large-capacity solid-state storage hard disk.

[0012] In one possible design, the NAND flash memory chip determined by the chip selector according to the first signal bit group and the second signal bit group of any selection signal corresponds to a group of input and output buses determined by the bus selector according to the first signal bit group of the same selection signal.

[0013] The bus selector and chip selector are linked to select the NAND flash memory chip. In addition to effectively improving the interface rate of the solid-state storage hard drive and ensuring the storage capacity of the solid-state storage hard drive, the NAND flash memory chip selection process does not require software participation, has low software complexity, and is simple to implement. It is suitable for various solid-state storage hard drives that use NAND flash memory chips.

[0014] In one possible design, the bus selector includes a data selector MUX, and the chip selector includes a decoder.

[0015] The circuit has a simple implementation method, low hardware cost, and wide applicability, and is applicable to various solid-state storage hard disks using NAND flash memory chips.

[0016] In a possible design, the selector is further used to: receive an enable signal sent by the controller; and control whether the selector is enabled according to the enable signal.

[0017] In a large-capacity solid-state storage hard drive, multiple chip selectors and multiple bus selectors may be provided to cooperate to complete the selection function of the NAND flash memory chip. Controlling whether the selector is enabled by an enable signal is conducive to ensuring the effective selection of the NAND flash memory chip, which can effectively ensure the normal operation of the large-capacity solid-state storage hard drive.

[0018] In a second aspect, the present application provides a controller, which is used for a solid-state storage hard disk, and the solid-state storage hard disk includes a selector and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips respectively; the controller is used to output multiple selection signals to the selector, so that the selector selects M NAND flash memory chips for data transmission according to the multiple selection signals, wherein the multiple selection signals are used to indicate the M NAND flash memory chips among the N NAND flash memory chips, and M is an integer greater than or equal to 1 and less than or equal to N.

[0019] In one possible design, the selector includes a bus selector and a chip selector, and the controller is connected to the bus selector and the chip selector respectively. The bus selector is connected to the P NAND flash memory chip array through P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips; the controller is used to output multiple selection signals to the bus selector, so that the bus selector can determine a group of input and output buses in the P group of input and output buses according to each of the multiple selection signals; the controller is also used to output multiple selection signals to the chip selector, so that the chip selector can determine each NAND flash memory chip in the M NAND flash memory chips according to each of the multiple selection signals.

[0020] In one possible design, each of the selection signals includes a first signal bit group and a second signal bit group; the controller is used to output the first signal bit group of each selection signal in a plurality of selection signals to the bus selector, so that the bus selector can determine a group of input and output buses in the P group of input and output buses according to the first signal bit group of each selection signal; the controller is also used to output the first signal bit group and the second signal bit group of each selection signal in a plurality of selection signals to the chip selector, so that the chip selector can determine each NAND flash memory chip in the M NAND flash memory chips according to the first signal bit group and the second signal bit group of each selection signal.

[0021] In one possible design, the controller is further configured to send an enable signal to the selector and control whether the selector is enabled according to the enable signal.

[0022] In a third aspect, the present application provides a control method for a solid-state storage hard drive, which is applied to a solid-state storage hard drive, wherein the solid-state storage hard drive includes a controller, a selector, and N NAND flash memory chips, where N is a positive integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips; the method includes: the controller outputs multiple selection signals to the selector, wherein the multiple selection signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is a positive integer greater than or equal to 1 and less than or equal to N; the selector selects the M NAND flash memory chips for data transmission according to the multiple selection signals.

[0023] In one possible design, the selector includes a bus selector and a chip selector, the controller is connected to the bus selector and the chip selector respectively, the bus selector is connected to the P NAND flash memory chip array through P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips; P is a positive integer greater than or equal to 1; the method includes: the bus selector determines a group of input and output buses in the P groups of input and output buses according to each of the selection signals; the chip selector determines each NAND flash memory chip in the M NAND flash memory chips according to each of the selection signals.

[0024] In one possible design, each of the selection signals includes a first signal bit group and a second signal bit, and the method includes: the bus selector receives the first signal bit group in each of the selection signals, and determines a group of input and output buses in the P groups of input and output buses based on the first signal bit group; the chip selector receives the first signal bit group and the second signal bit group in each of the selection signals, and determines each NAND flash memory chip in the M NAND flash memory chips based on the first signal bit group and the second signal bit group.

[0025] In one possible design, the NAND flash memory chip determined by the chip selector according to the first signal bit group and the second signal bit group of any selection signal corresponds to a group of input and output buses determined by the bus selector according to the first signal bit group of the same selection signal.

[0026] In one possible design, the bus selector includes a data selector MUX, and the chip selector includes a decoder.

[0027] In one possible design, the method further includes: the selector receiving an enable signal sent by the controller; and controlling whether the selector is enabled based on the enable signal.

[0028] In a fourth aspect, the present application provides a terminal device, wherein the terminal device includes the solid-state storage hard disk described in any one of the first aspects.

[0029] In a fifth aspect, the present application provides a control system, which includes a terminal device and a solid-state storage hard disk as described in any one of the first aspects; or, the control system includes a network device and a solid-state storage hard disk as described in any one of the first aspects.

[0030] In a sixth aspect, the present application provides a computer-readable storage medium comprising instructions, which, when executed on a computer, enables the computer to execute any one of the methods described in the second aspect.

[0031] Other effects of the above optional manner will be described below in conjunction with specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present application.

[0033] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of another application scenario provided by an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of a solid-state storage hard disk provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the structure of another solid-state storage hard disk provided in an embodiment of the present application;

[0037] Figure 5 A schematic structural diagram of another solid-state storage hard disk provided in an embodiment of the present application;

[0038] Figure 6 A control logic diagram of a bus selector and a chip selector provided in an embodiment of the present application;

[0039] Figure 7 A flowchart of a solid-state storage hard disk control method provided in an embodiment of the present application;

[0040] Figure 8 A flowchart of another solid-state storage hard drive control method provided in an embodiment of the present application;

[0041] Figure 9 A schematic diagram of the structure of a control system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The embodiments of the present application are applied to a solid-state storage hard disk, or a terminal device, or a control system, or any system that can execute the embodiments of the present application. The following explains some of the terms in the present application to facilitate understanding by those skilled in the art. It should be noted that when the solution of the embodiment of the present application is applied to a solid-state storage hard disk, or any system that can execute the embodiments of the present application, the names of the solid-state storage hard disk and the NAND flash memory chip may change, but this does not affect the implementation of the solution of the embodiment of the present application.

[0043] It should be understood that the technical solutions of the embodiments of the present application can be used to process solid-state storage hard drives applied to various communication systems, wherein the communication systems include: wireless local area network (WLAN) system, global system of mobile communication (GSM) system, code division multiple access (CDMA) system, wideband code division multiple access (WCDMA) system, general packet radio service (GPRS), long term evolution (LTE) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD), universal mobile telecommunication system (UMTS), worldwide interoperability for microwave access (WiMAX) communication system, and the future fifth generation mobile communication technology (5G) system or other systems that may appear in the future.

[0044] The terms used in the embodiments of this application are only used to explain the specific embodiments of this application and are not intended to limit this application. The following explains some of the terms in this application to facilitate understanding by those skilled in the art.

[0045] 1) Solid state drivers (SSDs) are used to store data. SSDs can be installed on terminals or servers.

[0046] 2) Flash memory: also known as Flash memory, referred to as "Flash", is a type of memory device and a non-volatile memory.

[0047] 3) Nand-Flash memory: It is a type of Flash memory that uses a nonlinear macrocell mode internally. It has the advantages of large capacity and fast rewrite speed, and is suitable for storing large-scale data.

[0048] 4) DRAM: Dynamic Random Access Memory, a type of volatile memory, where data exists when the power is on and is lost when the power is off.

[0049] 5) Interface rate: The nominal value of the total bit rate passing through the interface after all processing is completed.

[0050] 6) "Multiple" refers to two or more, and other quantifiers are similar. "And / or" describes the relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0051] 7) "Correspondence" can refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0052] It should be pointed out that the nouns or terms involved in the embodiments of the present application can refer to each other and will not be repeated here.

[0053] Since the Internet era, the amount of data has shown an exponential explosive growth, which has placed increasingly higher requirements on the capacity specifications and interface speed of solid-state storage hard drives. In order to achieve higher capacity specifications, a large number of NAND flash memory chips are provided in the solid-state storage hard drive. A large number of NAND flash memory chips are grouped according to multiple channels, and the multiple NAND flash memory chips corresponding to each group are connected to the controller of the solid-state storage hard drive through the same input and output bus. However, as the number of NAND flash memory chips connected to the same input and output bus increases, the load rate of the input and output bus is also increasing. When the load rate of the input and output bus exceeds a certain threshold, the interface rate of the solid-state storage hard drive will decrease and the data read and write delay will increase. In the related art, in order to increase the interface rate of the solid-state storage hard drive and reduce the data read and write delay, it is necessary to reduce the number of NAND flash memory chips connected to the input and output bus and control the load rate of the input and output bus.

[0054] When solid-state storage drives are used for large caches and secondary caches, such as PCIe solid-state storage accelerator cards, high-performance accelerator cards, or PCIe flash memory cards, increasing the storage capacity of the solid-state storage drive and ensuring the interface speed of the solid-state storage drive are important factors in improving the overall performance of the solid-state storage drive. When solid-state storage drives are mixed with traditional hard disks to form hierarchical storage, the solid-state storage drive is also required to have large storage capacity, high read and write capabilities, and low data latency. However, controlling the load rate of the input and output buses will result in a reduction in the capacity specifications of the solid-state storage drive. Failure to control the load rate of the input and output buses will result in an inability to increase the interface speed of the solid-state storage drive, making it difficult to simultaneously achieve high interface speed performance and high capacity specifications for solid-state storage drives.

[0055] This application proposes a solution to the above problems. The technical solution of the embodiment of this application will be described below with reference to the accompanying drawings.

[0056] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, this embodiment is applicable to a solid-state storage hard disk SSD.

[0057] Figure 2 Another application scenario diagram provided in the embodiment of the present application is as follows: Figure 2 As shown, this embodiment is applicable to a Nand-Flash memory equipped with a control chip.

[0058] Figure 3 A schematic diagram of the structure of a solid-state storage hard disk provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the solid-state storage hard disk includes: a controller 301, a selector 302 and N NAND flash memory chips 303, where N is an integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; the selector 302 is coupled to the controller 301 and the N NAND flash memory chips 303; the controller 301 is used to output multiple selection signals to the selector 302, wherein the multiple selection signals are used to indicate M NAND flash memory chips 303 among the N NAND flash memory chips 303, where M is an integer greater than or equal to 1 and less than or equal to N; the selector 302 is used to select the M NAND flash memory chips 303 for data transmission according to the multiple selection signals.

[0059] In this embodiment, specifically, to achieve large-capacity storage in a solid-state storage drive, the solid-state storage drive is provided with N NAND flash memory chips 303, where N is an integer greater than 1. The N NAND flash memory chips 303 constitute P NAND flash memory chip arrays. The P NAND flash memory chip arrays are connected to the solid-state storage drive's selector 302 via an input / output bus, and the selector 302 is connected to the solid-state storage drive's controller 301 via an input / output bus. Based on the different input / output buses connected, the N NAND flash memory chips 303 are grouped into channels. Each group corresponds to multiple NAND flash memory chips 303, and the multiple NAND flash memory chips 303 corresponding to each group are connected to the selector 302 via the same input / output bus. Different NAND flash memory chips 303 corresponding to different groups are connected to the selector 302 via parallel input / output buses. In other words, the N NAND flash memory chips 303 are grouped into channels to obtain P NAND flash memory chip arrays. Each NAND flash memory chip array is connected to the selector 302 via the same input / output bus, and different NAND flash memory chip arrays are connected to the selector 302 via parallel input / output buses. As the performance and security level of solid-state storage hard drives continue to improve, the amount of information that data systems interact with solid-state storage hard drives is increasing, and the load rate of the solid-state storage hard drive input and output buses is constantly increasing. The higher the load rate, the more nodes there are on the input and output bus, the greater the distributed capacitance of the input and output bus, the more discharge time it takes for the dominant level to return to the recessive level, and the input and output bus interface rate decreases. To ensure that data transmission delay is within an acceptable range, the utilization rate of the input and output bus does not exceed a certain threshold. The lower the input and output bus load rate, the more the real-time performance of the input and output bus can be guaranteed, but if the load rate of the input and output bus is too low, it is impossible to transmit enough data. Therefore, the controller 301 is used to output multiple selection signals, which are used to indicate M NAND flash memory chips 303 among the N NAND flash memory chips 303 through the multiple selection signals, and then the selector 302 is used to select the indicated M NAND flash memory chips 303 for data transmission.

[0060] Controller 301 is used to select a portion of the multiple NAND flash memory chips 303 in a solid-state storage drive. Specifically, controller 301 outputs multiple selection signals to selector 302. These selection signals are used to select M NAND flash memory chips 303 from the N NAND flash memory chips 303. Selector 302 sequentially selects the M NAND flash memory chips 303 indicated by controller 301 from the N NAND flash memory chips 303 for data transmission based on each of the multiple selection signals. The design of selector 302 enables the selection of a portion of the NAND flash memory chips 303 connected to an input / output bus for data transmission through hardware circuitry. This effectively reduces the load on the input / output bus of the solid-state storage drive, facilitating the maintenance of the solid-state storage drive's interface speed while maintaining the drive's capacity specifications. Furthermore, software selection of NAND flash memory chips 303 is not required, resulting in low software complexity and a simple implementation.

[0061] In this embodiment, a solid-state storage hard drive includes: a controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memory chips form a P NAND flash memory chip array, where P is an integer greater than or equal to 1 and less than or equal to N. The selector is coupled to the controller and the N NAND flash memory chips, respectively. The controller is configured to output a plurality of strobe signals to the selector, wherein the plurality of strobe signals are configured to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is an integer greater than or equal to 1 and less than or equal to N. The controller outputs strobe signals for indicating some of the NAND flash memory chips, and the selector selects the NAND flash memory chips indicated by the controller for data transmission. Since the load rate of the input and output buses of a solid-state storage hard drive is determined by the number of NAND flash memory chips connected to the input and output buses and that are enabled in real time, this solution divides the N NAND flash memory chips of the solid-state storage hard drive into P NAND flash memory chip arrays, and outputs a selection signal through a controller to select some NAND flash memory chips in the P NAND flash memory chip arrays for data transmission, thereby reducing the number of NAND flash memory chips connected to the input and output buses and that are enabled in real time. This effectively solves the problem of heavy load on the input and output buses of large-capacity solid-state storage hard drives and is conducive to effectively improving the interface rate of large-capacity solid-state storage hard drives. Compared with the method of reducing the number of NAND flash memory chips loaded on the input and output buses to ensure the interface rate of large-capacity solid-state storage hard drives, this technical solution can effectively ensure the capacity specifications of the solid-state storage hard drive. The selection of NAND flash memory chips is achieved through hardware circuits, without the need for software to participate in the selection of NAND flash memory chips, thus avoiding increased software complexity and simplifying the circuit implementation.

[0062] Figure 4A structural diagram of another solid-state storage hard disk provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the solid-state storage hard disk includes: a controller 401, a selector, and N NAND flash memory chips 404, where N is an integer greater than 1, and the N NAND flash memory chips 404 constitute P NAND flash memory chip arrays; the selector is coupled to the controller 401 and the N NAND flash memory chips 404 respectively; the controller 401 is used to output multiple selection signals to the selector, wherein the multiple selection signals are used to indicate M NAND flash memory chips 404 among the N NAND flash memory chips 404, where M is an integer greater than or equal to 1 and less than or equal to N; the selector is used to select the M NAND flash memory chips 404 for data transmission according to the multiple selection signals.

[0063] In this embodiment, specifically, the selector includes a bus selector 402 and a chip selector 403. The controller 401 is connected to the bus selector 402 and the chip selector 403 respectively. The bus selector 402 is connected to the P NAND flash memory chip array through the P group input and output buses, and the chip selector 403 is connected to the N NAND flash memory chips 404. P is a positive integer greater than or equal to 1. The bus selector 402 is used to determine a group of input and output buses in the P group input and output buses according to each selection signal; the chip selector 403 is used to determine each NAND flash memory chip 404 in the M NAND flash memory chips 404 according to each selection signal.

[0064] Bus selector 402 is connected to controller 401 via a set of input / output buses and to P NAND flash memory chip arrays via P sets of input / output buses. Each NAND flash memory chip array is connected to bus selector 402 via the same input / output bus, and different NAND flash memory chip arrays are connected to bus selector 402 via parallel input / output buses. Bus selector 402 receives each selection signal from controller 401 via the input / output buses and, based on each selection signal, selects a set of input / output buses from the P sets of input / output buses connected to the P NAND flash memory chip arrays. That is, it selects a NAND flash memory chip array based on each selection signal. Chip selector 403 is connected to controller 401 via a set of input / output buses. Specifically, chip selector 403 and bus selector 402 are connected to controller 401 via the same set of input / output buses and receive the same selection signal from controller 401 via the same set of input / output buses. The chip selector 403 includes multiple output ports, and different output ports of the multiple output ports are respectively connected to different enable pins of N NAND flash memory chips 404. The chip selector 403 receives each selection signal of the controller 401 through the input and output bus, and selects a NAND flash memory chip 404 from the N NAND flash memory chips 404 connected to it according to each selection signal, and finally determines each NAND flash memory chip 404 among the M NAND flash memory chips 404.

[0065] Controller 401 is connected to bus selector 402 and chip selector 403 via input / output buses, respectively. Controller 401 outputs multiple selection signals to bus selector 402 and chip selector 403. Each of the multiple selection signals includes a first signal bit group and a second signal bit group. Bus selector 402 receives the first signal bit group in each selection signal via the input / output bus and, based on the first signal bit group in each selection signal, determines a group of input / output buses among P groups of input / output buses. Chip selector 403 receives the first signal bit group and the second signal bit group in each selection signal via the input / output bus and, based on the first signal bit group and the second signal bit group, determines each NAND flash memory chip 404 among M NAND flash memory chips 404.

[0066] Each selection signal output by the controller 401 via the input / output bus includes a first signal bit group and a second signal bit group, which together constitute the complete selection signal. For example, the first signal bit group is 10, the second signal bit group is 1, and the first signal bit group and the second signal bit group constitute the complete selection signal 101. The bus selector 402 receives the first signal bit group in each selection signal via the input / output bus and, based on the first signal bit group, selects one of the P groups of input / output buses connected to the bus selector 402. The selected group of input / output buses corresponds to a NAND flash memory chip array, which may include multiple NAND flash memory chips 404. The chip selector 403 receives the first signal bit group and the second signal bit group in each selection signal through the input and output bus, and selects one of the N NAND flash memory chips 404 connected to the chip selector 403 based on the first signal bit group and the second signal bit group. The chip selector 403 determines each NAND flash memory chip 404 among the M NAND flash memory chips 404 by receiving multiple selection signals output by the controller 401. Since the bus selector 402 receives a partial signal of any selection signal and the chip selector 403 receives a complete signal of the same selection signal, the NAND flash memory chip 404 determined by the chip selector 403 based on the first signal bit group and the second signal bit group of any selection signal corresponds to a group of input and output buses determined by the bus selector 402 based on the first signal bit group of the same selection signal, that is, the NAND flash memory chip 404 determined by the chip selector 403 based on the complete signal of any selection signal is one of the NAND flash memory chips 404 in the NAND flash memory chip array connected to a group of input and output buses determined by the bus selector 402 based on the partial signal of the same selection signal.

[0067] Specifically, the bus selector 402 in the selector includes a data selector MUX, and the chip selector 403 includes a decoder. The data selector MUX can select any one of the data channels as needed during the multi-channel data transmission process, and is also called a multiplexer or a multi-way switch. Exemplarily, the bus selector 402 in the solid-state storage hard disk is a 1:4 MUX, which is connected to the four NAND flash memory chip arrays through four groups of input and output buses. The 1:4 MUX selects one of the four groups of input and output buses based on the first signal bit group of the selection signal output by the controller 401; the chip selector 403 in the solid-state storage hard disk is a 3-8 decoder, and the eight output ports of the 3-8 decoder are respectively connected to the enable pins of the NAND flash memory chip 404. The 3-8 decoder decodes the first signal bit group and the second signal bit group of the received selection signal, and selects the connected NAND flash memory chip 404 by outputting a low level at a certain output port.

[0068] Optionally, the selector is further configured to receive an enable signal from the controller 401 and control whether the selector is enabled based on the enable signal. The chip selector 403 and bus selector 402 in the selector receive the same enable signal, which controls whether the chip selector 403 and bus selector 402 are enabled. In a large-capacity solid-state storage hard drive, multiple chip selectors 403 and multiple bus selectors 402 may be provided to coordinately select the NAND flash memory chip 404. The enable signal can be used to control which selectors are enabled for operation.

[0069] This embodiment is also applicable to various memory components that use NAND flash memory chips to store programs and various data information, including but not limited to solid-state storage hard drives SSDs, Flash memories, Nand-Flash memories, mobile phones, storage boards, etc.

[0070] In this embodiment, the solid-state storage hard disk includes: a controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips respectively; the controller is configured to output multiple strobe signals to the selector, wherein the multiple strobe signals are configured to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is an integer greater than or equal to 1 and less than or equal to N; the selector is configured to select the M NAND flash memory chips for data transmission based on the multiple strobe signals, and the selector includes a bus selector and a chip selector, the controller is connected to the bus selector and the chip selector respectively, the bus selector is connected to the N NAND flash memory chips via P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips; P is a positive integer greater than or equal to 1; the bus selector is configured to determine a group of input and output buses among the P groups of input and output buses based on each strobe signal; and the chip selector is configured to determine each NAND flash memory chip among the M NAND flash memory chips based on each strobe signal. The bus selector and chip selector are linked to select the NAND flash memory chip. The NAND flash memory chip selection process does not require software participation, which can avoid increasing software complexity. By switching the input and output buses and selecting the NAND flash memory chips connected to the input and output buses, the problem of heavy input and output bus loads of large-capacity solid-state storage hard drives is effectively solved, the interface rate of large-capacity solid-state storage hard drives is effectively improved, and the data reading and writing speed of large-capacity solid-state storage hard drives is effectively improved. There is no limit on the number of NAND flash memory chips in the solid-state storage hard drive, and the storage capacity of the solid-state storage hard drive is not affected. The coupling relationship between the interface rate and storage capacity of the solid-state storage hard drive is well balanced, and the high interface rate and high storage capacity requirements of the solid-state storage hard drive can be met at the same time. The circuit implementation method is simple, the hardware cost is not high, and it is suitable for various solid-state storage hard drives using NAND flash memory chips.

[0071] Figure 5 A schematic diagram of the structure of another solid-state storage hard drive provided in an embodiment of the present application is provided. This solid-state storage hard drive is a hard disk drive that uses NAND Flash semiconductors as its storage medium. Its greatest advantage is that it can provide read and write capabilities hundreds of times faster than mechanical hard disks (HDDs). Its main components include an SSD controller 501, a DRAM buffer, a NAND Flash non-volatile memory device, and a power module. To achieve large-capacity storage in a solid-state storage hard drive (SSD), a large number of NAND Flash non-volatile memory devices are typically used as the NAND flash memory chips 504 of the solid-state storage hard drive (SSD). These NAND flash memory chips 504 are grouped according to multiple channels to form multiple NAND flash memory chip arrays.

[0072] like Figure 5 As shown, the selector in a solid-state storage hard disk (SSD) includes a bus selector and a chip selector. The bus selector is a 1:4 MUX 502, and the chip selector is a 3-8 decoder 503. The SSD controller 501 is connected to the bus selector 1:4 MUX 502 and the chip selector 3-8 decoder 503, respectively. A channel group of the solid-state storage hard disk (SSD) includes eight NAND flash memory chips 504. The enable pins of the eight NAND flash memory chips 504 are CH0_CE0-CH0_CE7, respectively. The eight NAND flash memory chips constitute four NAND flash memory chip arrays. The bus selector 1:4 MUX 502 is connected to the four NAND flash memory chip arrays via four input and output bus groups. The eight output ports of the chip selector 3-8 decoder 503 are connected to the enable pins CH0_CE0-CH0_CE7 of the eight NAND flash memory chips 504, respectively.

[0073] The SSD controller 501 outputs multiple selection signals to the bus selector 1:4 MUX 502 and the chip selector 3-8 decoder 503 via the input / output bus. Each of the multiple selection signals includes a first signal bit group CE0-CE1 and a second signal bit group CE2. The bus selector 1:4 MUX 502 receives the first signal bit group CE0-CE1 in each selection signal as a channel selection signal SEL0-SEL1, where SEL0 is the same as CE0, and SEL1 is the same as CE1. The chip selector 3-8 decoder 503 receives the first signal bit group CE0-CE1 and the second signal bit group CE2 in each selection signal as a channel selection signal.

[0074] In bus selector 1:4 MUX 502, SEL0 and SEL1 are channel select signals. These two-bit binary signals can represent four states, each corresponding to the selection of one of four input and output bus groups. SEL0 and SEL1 select one of these input and output bus groups. The first signal bit of each select signal received by bus selector 1:4 MUX 502 consists of 00, 01, 10, and 11, and it selects one of the four input and output bus groups by outputting 0, 1, 2, and 3.

[0075] In chip selector 3-8 decoder 503, CE0-CE2 are channel selection signals (where CE0 is SEL0 and CE1 is SEL1). These three-bit binary signals can represent eight states, each corresponding to the enable pins for selecting eight NAND flash memory chips 504. Specifically, CE0-CE2 selects one NAND flash memory chip 504. Each selection signal received by chip selector 3-8 decoder 503 has a first signal bit group consisting of 00, 01, 10, and 11, and a second signal bit group consisting of 0 and 1. By outputting a low level at one of its eight output ports, the eight NAND flash memory chips 504 are enabled.

[0076] Figure 6 This is a control logic diagram of a bus selector and chip selector provided in an embodiment of the present application. Because both the bus selector and the chip selector receive the first signal bit group of each selection signal, the selection of the input / output bus is synchronized with the enable selection of the NAND flash memory chip 504. The NAND flash memory chip 504 determined by the chip selector based on the first signal bit group and the second signal bit group of any selection signal corresponds to a group of input / output buses determined by the bus selector based on the first signal bit group of the same selection signal. For example, if the first signal bit group of the selection signal is 01 and the second signal bit group is 1, the bus selector 1:4 MUX 502 receives the first signal bit group 01 of the selection signal and determines input / output bus 1 based on the first signal bit group 01 of the selection signal, thereby selecting the second input / output bus. The chip selector 3-8 decoder 503 receives the first signal bit group 01 and the second signal bit group 1 of the selection signal, and determines that the output port 3 outputs a low level according to the first signal bit group 01 and the second signal bit group 1 of the selection signal, and the enable pin of the corresponding NAND flash memory chip 5043 is a low level, thereby realizing the enable selection of the NAND flash memory chip 5043. The NAND flash memory chip 5043 corresponds to the second input and output bus.

[0077] The SSD controller 501 also controls whether the selector is enabled by outputting an enable signal to the selector. The enable signal MUX_EN# received by the bus selector 1:4MUX502 is the same enable signal as the enable signal CE_EN# received by the chip selector 3-8 decoder 503. The bus selector 1:4MUX502 and the chip selector 3-8 decoder 503 have the same enable state.

[0078] In this embodiment, a solid-state storage hard disk SSD includes: an SSD controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1; the selector is connected to the controller and the N NAND flash memory chips respectively; the controller is used to output multiple selection signals to the selector, wherein the multiple selection signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is an integer greater than or equal to 1 and less than or equal to N; the selector is used to select the M NAND flash memory chips for data transmission according to the multiple selection signals, and the selector includes a bus selector and a chip selector, the controller is connected to the bus selector and the chip selector respectively, the bus selector is connected to the N NAND flash memory chips through P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips; P is a positive integer greater than or equal to 1; the bus selector is used to determine a group of input and output buses among the P groups of input and output buses according to each selection signal; and the chip selector is used to determine each NAND flash memory chip among the M NAND flash memory chips according to each selection signal. The bus selector and chip selector are linked to select the NAND flash memory chip. The selection method of the NAND flash memory chip is convenient and the hardware cost is low. The selection process of the NAND flash memory chip does not require software participation and the software complexity is low. By switching the input and output buses and selecting the NAND flash memory chips connected to the input and output buses, the problem of excessively high input and output bus load rate of the solid-state storage hard disk SSD is effectively solved, the interface rate of the solid-state storage hard disk SSD is effectively improved, and the data reading and writing speed of the solid-state storage hard disk SSD is effectively improved. It can better balance the coupling relationship between the interface rate and storage capacity of the solid-state storage hard disk SSD, and can simultaneously meet the high interface rate and high storage capacity requirements of the solid-state storage hard disk SSD. The circuit implementation method is simple and the hardware cost is not high, which is conducive to controlling the hardware cost of the solid-state storage hard disk SSD.

[0079] Figure 7 A flowchart of a solid-state storage hard drive control method provided in an embodiment of the present application, the method being applied to a solid-state storage hard drive, the solid-state storage hard drive comprising a controller, a selector, and N NAND flash memory chips, where N is a positive integer greater than 1, the N NAND flash memory chips forming a P NAND flash memory chip array, where P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips; Figure 7 As shown, the method includes:

[0080] Step 701: The controller outputs a plurality of strobe signals to the selector, wherein the plurality of strobe signals are used to indicate M NAND flash memory chips among N NAND flash memory chips, where M is a positive integer greater than or equal to 1 and less than or equal to N.

[0081] Step 702: The selector selects M NAND flash memory chips for data transmission according to a plurality of selection signals.

[0082] In this embodiment, the method is applied to a solid-state storage hard disk, which includes a controller, a selector, and N NAND flash memory chips, where N is a positive integer greater than 1, and the N NAND flash memory chips constitute a P NAND flash memory chip array, where P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips; the method includes: the controller outputs multiple selection signals to the selector, where the multiple selection signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is a positive integer greater than or equal to 1 and less than or equal to N; and the selector selects the M NAND flash memory chips for data transmission based on the multiple selection signals. The controller outputs a selection signal for indicating some NAND flash memory chips, and the selector is used to select some NAND flash memory chips indicated by the controller for data transmission, which effectively solves the problem of heavy input and output bus load of large-capacity solid-state storage hard disks and is conducive to effectively improving the interface rate of large-capacity solid-state storage hard disks. Compared with the method of reducing the number of NAND flash memory chips loaded on the input and output buses to ensure the interface rate of large-capacity solid-state storage hard disks, this technical solution can effectively ensure the capacity specifications of solid-state storage hard disks. The selection of NAND flash memory chips is realized by hardware circuit method, and there is no need to use software to participate in NAND flash memory chip selection, which can avoid increasing software complexity and has a simple circuit implementation method.

[0083] Figure 8 A flowchart of another solid-state storage hard drive control method provided in an embodiment of the present application, the method being applied to a solid-state storage hard drive, the solid-state storage hard drive comprising a controller, a selector, and N NAND flash memory chips, where N is a positive integer greater than 1, the N NAND flash memory chips forming a P NAND flash memory chip array, and P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips, the bus selector is connected to the P NAND flash memory chip array via P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips; P is a positive integer greater than or equal to 1; as shown in FIG. Figure 8 As shown, the method includes:

[0084] Step 801: The controller outputs a plurality of strobe signals to the selector, wherein the plurality of strobe signals are used to indicate M NAND flash memory chips among N NAND flash memory chips, where M is a positive integer greater than or equal to 1 and less than or equal to N.

[0085] Step 802: The bus selector determines one of the P groups of input / output buses according to each selection signal; and the chip selector determines each of the M NAND flash memory chips according to each selection signal.

[0086] In this embodiment, specifically, each selection signal includes a first signal bit group and a second signal bit. Optionally, the method further includes: a bus selector receiving the first signal bit group in each selection signal and determining a group of input / output buses among the P groups of input / output buses based on the first signal bit group; and a chip selector receiving the first signal bit group and the second signal bit group in each selection signal and determining each NAND flash memory chip among the M NAND flash memory chips based on the first signal bit group and the second signal bit group. The NAND flash memory chip determined by the chip selector based on the first signal bit group and the second signal bit group of any selection signal corresponds to a group of input / output buses determined by the bus selector based on the first signal bit group of the same selection signal.

[0087] As an optional manner, the bus selector includes a data selector MUX, and the chip selector includes a decoder.

[0088] Optionally, the method further includes: the selector receiving an enable signal sent by the controller; and controlling whether the selector is started according to the enable signal.

[0089] In this embodiment, the method is applied to a solid-state storage hard disk, which includes a controller, a selector, and N NAND flash memory chips, where N is a positive integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips; a bus selector is connected to the P NAND flash memory chip arrays via P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips, where P is a positive integer greater than or equal to 1; the method includes: the controller outputting multiple selection signals to the selector, wherein the multiple selection signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is a positive integer greater than or equal to 1 and less than or equal to N; the bus selector determines a group of input and output buses among the P groups of input and output buses based on each selection signal; and the chip selector determines each NAND flash memory chip among the M NAND flash memory chips based on each selection signal. The bus selector and chip selector are linked to select the NAND flash memory chip. The NAND flash memory chip selection process does not require software participation, which can avoid increasing software complexity. By switching the input and output buses and selecting the NAND flash memory chips connected to the input and output buses, the problem of heavy input and output bus loads of large-capacity solid-state storage hard drives is effectively solved, the interface rate of large-capacity solid-state storage hard drives is effectively improved, and the data reading and writing speed of large-capacity solid-state storage hard drives is effectively improved. There is no limit on the number of NAND flash memory chips of the solid-state storage hard drive, and the storage capacity of the solid-state storage hard drive is not affected. The coupling relationship between the interface rate and storage capacity of the solid-state storage hard drive is well balanced, and the high interface rate and high storage capacity requirements of the solid-state storage hard drive can be met at the same time. The circuit implementation method is simple, the hardware cost is not high, and it is suitable for various solid-state storage hard drives using storage media.

[0090] An embodiment of the present application also provides a controller, which is used for a solid-state storage hard disk. The solid-state storage hard disk includes a selector and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled to the controller and the N NAND flash memory chips, respectively; the controller is used to output multiple selection signals to the selector, so that the selector selects M NAND flash memory chips for data transmission according to the multiple selection signals, wherein the multiple selection signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, and M is an integer greater than or equal to 1 and less than or equal to N.

[0091] As an optional manner, the selector includes a bus selector and a chip selector, the controller is connected to the bus selector and the chip selector respectively, the bus selector is connected to the P NAND flash memory chip arrays via P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips;

[0092] The controller is used to output a plurality of strobe signals to the bus selector, so that the bus selector determines a group of input and output buses in the P groups of input and output buses according to each of the plurality of strobe signals;

[0093] The controller is further configured to output a plurality of strobe signals to the chip selector, so that the chip selector can determine each NAND flash memory chip among the M NAND flash memory chips according to each strobe signal in the plurality of strobe signals.

[0094] As an optional manner, each strobe signal includes a first signal bit group and a second signal bit group;

[0095] The controller is used to output a first signal bit group of each strobe signal in a plurality of strobe signals to the bus selector, so that the bus selector determines a group of input and output buses in the P groups of input and output buses according to the first signal bit group of each strobe signal;

[0096] The controller is also used to output the first signal bit group and the second signal bit group of each selection signal in multiple selection signals to the chip selector, so that the chip selector can determine each NAND flash memory chip in the M NAND flash memory chips according to the first signal bit group and the second signal bit group of each selection signal.

[0097] As an optional manner, the controller is further configured to send an enable signal to the selector, and control whether the selector is enabled according to the enable signal.

[0098] According to an embodiment of the present application, the present application also provides a terminal device, which includes the solid-state storage hard disk described in Example 3 and Example 4.

[0099] Figure 9 A schematic diagram of the structure of a control system provided in an embodiment of the present application is shown in FIG. Figure 9 As shown, the control system includes a network device 901 and a solid-state storage hard disk 902. The solid-state storage hard disk 902 includes the solid-state storage hard disk described in any of the previous embodiments.

[0100] According to an embodiment of the present application, the present application also provides an electronic device and a readable storage medium.

[0101] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data solid-state storage hard disk such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0102] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0103] In the embodiments of the present application, the above embodiments can refer to and learn from each other, and the same or similar steps and nouns will not be repeated one by one.

[0104] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved. This is not a limitation herein.

[0105] The above specific embodiments do not constitute a limitation on the scope of protection of this application. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims

1. A solid-state storage hard disk, characterized in that: include: A controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; The selector is coupled to the controller and the N NAND flash memory chips respectively; The controller is configured to output a plurality of strobe signals to the selector, wherein the plurality of strobe signals are configured to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is an integer greater than or equal to 1 and less than or equal to N; The selector is used to select the M NAND flash memory chips for data transmission according to the multiple selection signals; The selector includes a bus selector and a chip selector. The controller is connected to the bus selector and the chip selector respectively. The bus selector is connected to the P NAND flash memory chip arrays through P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips.

2. The solid-state storage hard disk according to claim 1, wherein: The bus selector is used to determine a group of input and output buses among the P groups of input and output buses according to each of the selection signals; The chip selector is used to determine each NAND flash memory chip among the M NAND flash memory chips according to each of the selection signals.

3. The solid-state storage hard disk according to claim 2, wherein: Each of the strobe signals includes a first signal bit group and a second signal bit group; The bus selector is used to receive a first signal bit group in each of the selection signals, and determine a group of input and output buses in the P groups of input and output buses according to the first signal bit group; The chip selector is used to receive the first signal bit group and the second signal bit group in each of the selection signals, and determine each NAND flash memory chip in the M NAND flash memory chips according to the first signal bit group and the second signal bit group.

4. The solid-state storage hard disk according to claim 3, wherein: The NAND flash memory chip determined by the chip selector according to the first signal bit group and the second signal bit group of any strobe signal corresponds to a group of input and output buses determined by the bus selector according to the first signal bit group of the same strobe signal.

5. The solid-state storage hard disk according to any one of claims 1 to 4, characterized in that: The bus selector includes a data selector MUX, and the chip selector includes a decoder.

6. The solid-state storage hard disk according to any one of claims 1 to 4, wherein: The selector is also used to: receiving an enable signal sent by the controller; According to the enable signal, whether the selector is enabled is controlled.

7. A controller, characterized in that: The controller is used for a solid-state storage hard disk, which includes a selector and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; The selector is coupled to the controller and the N NAND flash memory chips respectively; The controller is configured to output a plurality of strobe signals to the selector, so that the selector selects M NAND flash memory chips for data transmission according to the plurality of strobe signals, wherein the plurality of strobe signals are configured to indicate the M NAND flash memory chips among the N NAND flash memory chips, where M is an integer greater than or equal to 1 and less than or equal to N; The selector includes a bus selector and a chip selector. The controller is connected to the bus selector and the chip selector respectively. The bus selector is connected to the P NAND flash memory chip arrays through P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips.

8. The controller according to claim 7, characterized in that The controller is configured to output a plurality of strobe signals to the bus selector, so that the bus selector determines a group of input / output buses in the P groups of input / output buses according to each of the plurality of strobe signals; The controller is further configured to output a plurality of selection signals to the chip selector, so that the chip selector can determine each NAND flash memory chip among the M NAND flash memory chips according to each of the plurality of selection signals.

9. The controller according to claim 8, characterized in that Each of the strobe signals includes a first signal bit group and a second signal bit group; The controller is configured to output a first signal bit group of each strobe signal among a plurality of strobe signals to the bus selector, so that the bus selector determines a group of input / output buses among the P groups of input / output buses according to the first signal bit group of each strobe signal; The controller is further configured to output a first signal bit group and a second signal bit group of each selection signal in a plurality of selection signals to the chip selector, so that the chip selector can determine each NAND flash memory chip in the M NAND flash memory chips according to the first signal bit group and the second signal bit group of each selection signal.

10. The controller according to any one of claims 7 to 9, characterized in that: The controller is further configured to send an enable signal to the selector and control whether the selector is enabled according to the enable signal.

11. A method for controlling a solid-state storage hard disk, characterized in that: The method is applied to a solid-state storage hard disk, which includes a controller, a selector, and N NAND flash memory chips, where N is a positive integer greater than 1, and the N NAND flash memory chips constitute P NAND flash memory chip arrays, where P is an integer greater than or equal to 1 and less than or equal to N; The selector is coupled to the controller and the N NAND flash memory chips; the method includes: The controller outputs a plurality of strobe signals to the selector, wherein the plurality of strobe signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, where M is a positive integer greater than or equal to 1 and less than or equal to N; The selector selects the M NAND flash memory chips for data transmission according to the multiple selection signals; The selector includes a bus selector and a chip selector. The controller is connected to the bus selector and the chip selector respectively. The bus selector is connected to the P NAND flash memory chip arrays through P groups of input and output buses, and the chip selector is connected to the N NAND flash memory chips.

12. The method according to claim 11, characterized in that The bus selector determines a group of input and output buses among the P groups of input and output buses according to each of the selection signals; The chip selector determines each NAND flash memory chip among the M NAND flash memory chips according to each of the strobe signals.

13. The method according to claim 12, characterized in that Each of the strobe signals includes a first signal bit group and a second signal bit group, and the method includes: The bus selector receives a first signal bit group in each of the selection signals and determines a group of input and output buses in the P groups of input and output buses according to the first signal bit group; The chip selector receives the first signal bit group and the second signal bit group in each of the selection signals, and determines each NAND flash memory chip in the M NAND flash memory chips according to the first signal bit group and the second signal bit group.

14. The method according to claim 13, characterized in that The NAND flash memory chip determined by the chip selector according to the first signal bit group and the second signal bit group of any strobe signal corresponds to a group of input and output buses determined by the bus selector according to the first signal bit group of the same strobe signal.

15. The method according to any one of claims 11 to 14, characterized in that The bus selector includes a data selector MUX, and the chip selector includes a decoder.

16. The method according to any one of claims 11 to 14, characterized in that The method further comprises: The selector receives an enable signal sent by the controller; And according to the enable signal, control is made as to whether the selector is enabled.

17. A terminal device, characterized in that: The terminal device includes the solid-state storage hard disk as described in any one of claims 1-6.

18. A control system, characterized in that: The control system includes a terminal device and a solid-state storage hard disk as described in any one of claims 1-6; or, the control system includes a network device and a solid-state storage hard disk as described in any one of claims 1-6.

19. A computer-readable storage medium, characterized in that The method comprises instructions which, when executed on a computer, cause the computer to execute the method according to any one of claims 11 to 16.

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