Display panel and display device

Abstract

The present invention provides a display panel and a display device. By arranging a plurality of gate drive circuits electrically connected to a plurality of pixel drive circuits in the same pixel row, the number of first gate drive circuits electrically connected to the plurality of pixel drive circuits in the same pixel row is at most two, the number of second gate drive circuits at the same level is at most two, and the number of third gate drive circuits at the same level is at most two, so as to facilitate the display panel to realize a narrow frame design when a dynamic refresh frequency is adopted.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Using dynamic refresh rate to realize display control of display panel can reduce the power consumption of display panel, but flicker problem will occur when display panel uses low refresh rate for display. Therefore, increasing corresponding control signal is often adopted to improve low frequency flicker problem. The increase of control signal will increase the circuits generating control signal, resulting in an increase in the area occupied by control circuit in the frame area, which is not conducive to realizing narrow frame design of display panel. Summary of the invention

[0003] The embodiments of the present invention provide a display panel and a display device, which facilitate the display panel to realize a narrow frame design when a dynamic refresh frequency is adopted by arranging a plurality of gate drive circuits.

[0004] An embodiment of the present invention provides a display panel, which includes: a plurality of gate drive circuits and a plurality of pixel rows. The plurality of gate drive circuits include a plurality of cascaded first gate drive circuits, a plurality of cascaded second gate drive circuits and a plurality of cascaded third gate drive circuits. The plurality of cascaded first gate drive circuits output a plurality of first gate signals in response to a first start signal, the plurality of cascaded second gate drive circuits output a plurality of second gate signals in response to a second start signal, and the plurality of cascaded third gate drive circuits output a plurality of third gate signals in response to a third start signal. In a write frame and a hold frame, the valid pulse of the first start signal and the valid pulse of the second start signal are both within the invalid pulse action time of the third start signal.

[0005] Each of the pixel rows includes a plurality of sub-pixels and a plurality of pixel driving circuits electrically connected to the plurality of sub-pixels, and each of the pixel driving circuits includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The second transistor transmits a data signal in response to the corresponding first selection signal, so that the first transistor generates a driving current for controlling the sub-pixel to emit light according to the data signal, the third transistor compensates the threshold voltage of the first transistor in response to the corresponding second selection signal, the fourth transistor transmits a first reset signal to the gate of the first transistor in response to the corresponding second selection signal, the fifth transistor and the sixth transistor simultaneously respond to the same corresponding third selection signal so that the first transistor provides a driving current to the sub-pixel, and the seventh transistor transmits a second reset signal to the anode of the sub-pixel in response to the corresponding first selection signal.

[0006] Among them, the second transistor and the seventh transistor respond to different levels of the first selection signal, the third transistor and the fourth transistor respond to different levels of the second selection signal, each of the third selection drive circuits is electrically connected to multiple pixel drive circuits in two adjacent pixel rows, the number of the first selection drive circuits of the same level electrically connected to multiple pixel drive circuits located in the same pixel row is at most two, the number of the second selection drive circuits of the same level is at most two, and the number of the third selection drive circuits of the same level is at most two.

[0007] The present invention further provides a display device, comprising any one of the above-mentioned display panels and a timing controller, wherein the timing controller is electrically connected to a plurality of the gate drive circuits.

[0008] The display panel and display device provided by the embodiments of the present invention arrange and arrange multiple enable driving circuits electrically connected to the multiple pixel driving circuits in the same pixel row so that the number of first enable driving circuits of the same level electrically connected to the multiple pixel driving circuits in the same pixel row is at most two, the number of second enable driving circuits of the same level is at most two, and the number of third enable driving circuits of the same level is at most two, so as to facilitate the display panel to achieve a narrow frame design when adopting a dynamic refresh frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0011] Figure 2A to Figure 2B is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0012] Figure 3A is a timing diagram of a first start signal, a second start signal and a third start signal provided by an embodiment of the present invention;

[0013] Figure 3B to Figure 3C is a timing diagram of a first selection signal, a second selection signal and a third selection signal provided by an embodiment of the present invention;

[0014] Figure 4A to Figure 4E It is a schematic diagram of the layout structure of the gate drive circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0016] Specifically, Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention; an embodiment of the present invention provides a display panel, optionally, the display panel includes a self-luminous display panel, a quantum dot display panel, a touch display panel, etc.

[0017] Optionally, the display panel includes a display area 100a and a non-display area 100b. The display area 100a is used to implement a display function. Optionally, the non-display area 100b may be located outside the display area 100a. Optionally, in some embodiments, the display panel further includes a sensing area, which may be surrounded by the display area 100a and / or the non-display area 100b, and the sensing area is used to implement functions such as sensing.

[0018] The display panel includes a plurality of pixel rows PL, a plurality of gate lines, a plurality of data lines and a plurality of gate driving circuits.

[0019] Optionally, a plurality of the pixel rows are located in the display area 100a. Each of the pixel rows PL includes a plurality of sub-pixels PE and a plurality of pixel driving circuits electrically connected to the plurality of sub-pixels PE. Optionally, the sub-pixels PE include light-emitting devices, and the light-emitting devices include organic light-emitting diodes, sub-millimeter light-emitting diodes, micro light-emitting diodes, etc.

[0020] like Figure 2A to Figure 2B : is a structural schematic diagram of a pixel driving circuit provided in an embodiment of the present invention; the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0021] Optionally, the first transistor T1 and the corresponding sub-pixel PE are connected in series between a first voltage terminal VDD and a second voltage terminal VSS, a source and a drain of the second transistor T2 are electrically connected between a corresponding data line DL and one of the source and the drain of the first transistor T1 that is electrically connected to the first voltage terminal VDD, a source and a drain of the third transistor T3 are electrically connected between a gate of the first transistor T1 and one of the source and the drain of the first transistor T1 that is electrically connected to the second voltage terminal VSS, a source and a drain of the fourth transistor T4 are electrically connected between a first reset signal line VI1 and the first transistor T5. 1, the source and drain of the fifth transistor T5 are electrically connected between the first voltage terminal VDD and one of the source and drain of the first transistor T1 that is electrically connected to the second transistor T2, the source and drain of the sixth transistor T6 are electrically connected between the second voltage terminal VSS and one of the source and drain of the first transistor T1 that is electrically connected to the third transistor T3, the source and drain of the seventh transistor T7 are electrically connected between the corresponding sub-pixel PE and the second reset signal line VI2, and the storage capacitor Cst is connected in series between the gate of the first transistor T1 and the first voltage terminal VDD. Optionally, the third transistor T3 and the fourth transistor T4 are both dual-gate transistors; that is, the third transistor T3 includes a transistor T3-1 and a transistor T3-2, and the fourth transistor T4 includes a transistor T4-1 and a transistor T4-2.

[0022] The plurality of gate lines are electrically connected to the plurality of pixel driving circuits. Specifically, the plurality of gate lines include a plurality of first gate lines GL1, a plurality of second gate lines GL2, and a plurality of third gate lines GL3.

[0023] The gates of the second transistors T2 of the plurality of pixel driving circuits of each pixel row PL are electrically connected to the same first selection line GL1, and the gates of the seventh transistors T7 of the plurality of pixel driving circuits of each pixel row PL are electrically connected to the same first selection line GL1; the gates of the second transistors T2 and the seventh transistors T7 of each pixel driving circuit are electrically connected to different first selection lines GL1. The second transistors T2 are used to transmit data signals according to the first selection signal Scan1 transmitted by the corresponding first selection line GL1, so that the first transistors T1 generate driving currents for controlling the sub-pixels PE to emit light according to the data signals. The seventh transistors T7 are used to transmit second reset signals to the anodes of the sub-pixels PE according to the first selection signal Scan1 transmitted by the corresponding first selection line GL1.

[0024] The gates of the third transistors T3 of the plurality of pixel driving circuits of each pixel row PL are electrically connected to the same second selection line GL2, and the gates of the fourth transistors T4 of the plurality of pixel driving circuits of each pixel row PL are electrically connected to the same second selection line GL2; the gates of the third transistors T3 and the gates of the fourth transistors T4 of each pixel driving circuit are electrically connected to different second selection lines GL2. The third transistor T3 is used to compensate the threshold voltage of the first transistor T1 according to the second selection signal SE2 transmitted by the corresponding second selection line GL2, and the fourth transistor T4 is used to transmit a first reset signal to the gate of the first transistor T1 according to the second selection signal SE2 transmitted by the corresponding second selection line GL2.

[0025] The gates of the fifth transistors T5 of the plurality of pixel driving circuits of each pixel row PL are electrically connected to the same third selection line GL3, and the gates of the sixth transistors T6 of the plurality of pixel driving circuits of each pixel row PL are electrically connected to the same third selection line GL3. Optionally, the gates of the fifth transistors T5 and the sixth transistors T6 of each pixel driving circuit are electrically connected to the same third selection line GL3. The fifth transistors T5 and the sixth transistors T6 are used to enable the first transistor T1 to provide a driving current to the sub-pixel PE according to a third selection signal EM transmitted by the third selection line GL3.

[0026] Optionally, the active layers of the first transistor T1 to the seventh transistor T7 all include silicon semiconductor; further, the active layers of the first transistor T1 to the seventh transistor T7 all include low-temperature polysilicon.

[0027] like Figure 4A to Figure 4E 1 is a schematic diagram of the layout structure of the gate drive circuit provided by an embodiment of the present invention. Optionally, multiple gate drive circuits are located in the non-display area 100b. Figure 1 , Figure 2A to Figure 2B and Figure 4A to Figure 4E The plurality of gate drive circuits include a plurality of first gate drive circuits 201 , a plurality of second gate drive circuits 202 and a plurality of third gate drive circuits 203 .

[0028] A plurality of first gate drive circuits 201 are cascaded, and the plurality of cascaded first gate drive circuits 201 output a plurality of first gate signals Scan1 in response to a first start signal STV1. The plurality of cascaded first gate drive circuits 201 are electrically connected to a plurality of first gate lines GL1 to transmit a plurality of first gate signals Scan1 to the plurality of first gate lines GL1. Optionally, the first gate signal Scan1 may also be referred to as a scan signal. Optionally, the gate of the second transistor T2 and the gate of the seventh transistor T7 of each pixel drive circuit are electrically connected to the first gate drive circuits 201 of different stages through different first gate lines GL1. For example, the gate of the second transistor T2 of the pixel driving circuit located in the M+1th pixel row is electrically connected to the first enable driving circuit of the M+1th level, and the gate of the seventh transistor T7 of the pixel driving circuit located in the M+1th pixel row is electrically connected to the first enable driving circuit of the Mth level or the M+2th level; wherein, the first enable driving circuit of the Mth level outputs the first enable signal Scan1(M) of the Mth level, the first enable driving circuit of the M+1th level outputs the first enable signal Scan1(M+1) of the M+1th level, and the first enable driving circuit of the M+2th level outputs the first enable signal Scan1(M+2) of the M+2th level.

[0029] A plurality of the second gate drive circuits 202 are cascaded, and the plurality of cascaded second gate drive circuits 202 output a plurality of second gate signals SE2 in response to the second start signal STV2. The plurality of cascaded second gate drive circuits 202 are electrically connected to a plurality of the second gate lines GL2 to transmit a plurality of the second gate signals SE2 to the plurality of the second gate lines GL2. Optionally, the second gate signal SE2 may also be referred to as a scan signal or an emission control signal.

[0030] Optionally, the circuit structure of the second gate drive circuit 202 is the same as the circuit structure of the first gate drive circuit 201, and the gate of the third transistor T3 and the gate of the fourth transistor T4 of each pixel drive circuit are electrically connected to the second gate drive circuit 202 of different levels through different second gate lines GL2. For example, the gate of the third transistor T3 of the pixel drive circuit located in the M+1 pixel row is electrically connected to the second gate drive circuit of the M+1 level, and the gate of the fourth transistor T4 of the pixel drive circuit located in the M+1 pixel row is electrically connected to the second gate drive circuit of the M level; wherein the second gate drive circuit of the M level outputs the second gate signal SE2(M) of the M level, and the second gate drive circuit of the M+1 level outputs the second gate signal SE2(M+1) of the M+1 level, such as Figure 2A and Figure 4A to Figure 4D shown.

[0031] Optionally, a plurality of the second gate drive circuits 202 can be grouped and cascaded, such as a plurality of the second gate drive circuits 202 electrically connected to the third transistors T3 in a plurality of the pixel drive circuits are cascaded, and a plurality of the second gate drive circuits 202 electrically connected to the fourth transistors T4 in a plurality of the pixel drive circuits are cascaded. Further, the second gate drive circuit 202 and the third gate drive circuit 203 have the same circuit structure, the gate of the third transistor T3 of the pixel drive circuit located in the M+1 pixel row is electrically connected to the second gate drive circuit of the P stage, and the gate of the fourth transistor T4 of the pixel drive circuit located in the M+1 pixel row is electrically connected to the second gate drive circuit of the O stage. Among them, the second gate drive circuit of the P stage outputs a second gate signal SE2_L(P), and the second gate drive circuit of the O stage outputs a second gate signal SE2_R(O), such as Figure 2B and Figure 4E Optionally, when the second gate driving circuit 202 and the third gate driving circuit 203 have the same circuit structure, each second gate driving circuit 202 is electrically connected to a plurality of pixel driving circuits in two adjacent pixel rows PL.

[0032] A plurality of the third gate drive circuits 203 are cascaded, and the plurality of cascaded third gate drive circuits 203 output a plurality of third gate signals EM in response to a third start signal STV3. The plurality of cascaded third gate drive circuits 203 are electrically connected to the plurality of third gate lines GL3 to transmit the plurality of third gate signals EM to the plurality of third gate lines GL3. Optionally, the third gate signal EM may also be referred to as an emission control signal. Optionally, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 of each pixel drive circuit are electrically connected to the same third gate drive circuit 203 through the same third gate line GL3. Optionally, each third gate drive circuit 203 is electrically connected to a plurality of pixel drive circuits in two adjacent pixel rows PL.

[0033] like Figure 3A is a timing diagram of the first start signal, the second start signal and the third start signal provided by an embodiment of the present invention, such as Figure 3B to Figure 3C1 is a timing diagram of the first selection signal, the second selection signal and the third selection signal provided by an embodiment of the present invention. To ensure the normal operation of the pixel driving circuit, in the writing frame WF and the holding frame HF, the valid pulses of the first start signal STV1 and the second start signal STV2 (if T2, T3, T4, T7 are all P-type transistors, then STV1 and STV2 are valid pulses when they are low level) are both located within the invalid pulse action time of the third start signal STV3 (if T5 and T6 are P-type transistors, then STV3 is invalid pulse when it is high level) so that in the writing frame WF and the holding frame HF, the valid pulses of the first selection signal Scan1 and the second selection signal SE2 are both located within the invalid pulse time of the third selection signal EM.

[0034] Optionally, the number of effective pulses of the first start signal STV1 in the write frame WF is single or multiple, and in the hold frame HF, the first start signal STV1 cyclically writes the timing of the frame WF. The write frame WF corresponds to a frame including a data write phase, and the hold frame HF is a frame not including the data write phase. In the data write phase, the second transistor T2 and the third transistor T3 in the pixel drive circuit are turned on, and the data signal transmitted by the data line DL is written into the gate of the first transistor T1 via the second transistor T2 and the third transistor T3.

[0035] Since the first start signal STV1 cyclically writes the timing of the frame WF within the hold frame HF, the sum of the valid pulse numbers of the first start signal STV1 is greater than the sum of the valid pulse numbers of the second start signal STV2 within the period including the write frame WF and the hold frame HF.

[0036] In order to enable the data signal to be written into the gate of the first transistor T1 during the data writing stage, within the writing frame WF, the first valid pulse of the first start signal STV1 and the valid pulse of the second start signal STV2 partially overlap, so that within the writing frame WF, the first valid pulse of the first selection signal Scan1 and the valid pulse of the second selection signal SE2 partially overlap, so that the second transistor T2 and the third transistor T3 can be turned on together for part of the time.

[0037] It can be understood that the plurality of gate drive circuits can be designed using the circuit structure in the prior art, which will not be described in detail herein.

[0038] Please continue reading Figure 1 and Figure 4A to Figure 4E, the number of the first gate drive circuits 201 electrically connected to the plurality of pixel drive circuits of the same pixel row PL is at most two, the number of the second gate drive circuits 202 electrically connected to the plurality of pixel drive circuits of the same pixel row PL is at most two, and the number of the third gate drive circuits 203 electrically connected to the plurality of pixel drive circuits of the same pixel row PL is at most two. By laying out the plurality of gate drive circuits electrically connected to the plurality of pixel drive circuits of the same pixel row PL, the number of the first gate drive circuits 201, the second gate drive circuits 202, and the third gate drive circuits 203 electrically connected to the plurality of pixel drive circuits of the same pixel row PL is controlled to be at most two, respectively, so as to facilitate the narrow frame design of the display panel when a dynamic refresh frequency is adopted.

[0039] Optionally, the non-display area 100b includes a first non-display area 1001b and a second non-display area 1002b located on opposite sides of the display area 100a; wherein, the plurality of the gating drive circuits located in the first non-display area 1001b have a first column number, and the plurality of the gating drive circuits located in the second non-display area 1002b have a second column number, and the first column number is equal to the second column number, so as to facilitate the first non-display area 1001b and the second non-display area 1002b to have the same width and / or length, thereby facilitating the symmetrical setting of the first non-display area 1001b and the second non-display area 1002b.

[0040] The following will be combined Figure 4A to Figure 4E The layout of the plurality of gate drive circuits is described. Figure 4A to Figure 4E CL1, CL2 and CL3 in the figure represent cascade connection lines between the plurality of first gate driving circuits 201, cascade connection lines between the plurality of second gate driving circuits 202, and cascade connection lines between the plurality of third gate driving circuits 203, respectively.

[0041] First, the pixel driving circuit adopts Figure 2A The structure shown in the figure is illustrated, the circuit structure of the second enable driving circuit 202 is the same as the circuit structure of the first enable driving circuit 201, and the first enable driving circuit 201, the second enable driving circuit 202 and the third enable driving circuit 203 electrically connected to the multiple pixel driving circuits of the same pixel row PL can be arranged in the first non-display area 1001b and the second non-display area 1002b in different arrangements.

[0042] Specifically, please continue to refer to 4A. The two first selection drive circuits 201 of the same level electrically connected to the multiple pixel drive circuits of the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b, the two second selection drive circuits 202 of the same level electrically connected to the multiple pixel drive circuits of the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b, and the two third selection drive circuits 203 of the same level electrically connected to the multiple pixel drive circuits of the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b.

[0043] Among them, in the first non-display area 1001b and the second non-display area 1002b, the second enable driving circuit 202 is located between the first enable driving circuit 201 and the third enable driving circuit 203, and the third enable driving circuit 203 is located on the side of the second enable driving circuit 202 away from the display area 100a.

[0044] Further, multiple pixel driving circuits located in the M+1 pixel row PL(M+1) and the M+2 pixel row PL(M+2) are used as an example for description. The gate of the second transistor T2 in the multiple pixel driving circuits located in the M+1 pixel row PL(M+1) is electrically connected to the M+1 first selection driving circuit located in the first non-display area 1001b and the second non-display area 1002b. The gate of the second transistor T2 in the multiple pixel driving circuits located in the M+2 pixel row PL(M+2) is electrically connected to the M+2 first selection driving circuit located in the first non-display area 1001b and the second non-display area 1002b, and the M+2 first selection driving circuit provides the M+2 first selection signal Scan1(M+2).

[0045] The gate of the seventh transistor T7 in the plurality of pixel driving circuits located in the M+1th pixel row PL(M+1) is electrically connected to the Mth-stage first gate driving circuit located in the first non-display area 1001b and the second non-display area 1002b. The gate of the seventh transistor T7 in the plurality of pixel driving circuits located in the M+2th pixel row PL(M+2) is electrically connected to the M+1th-stage first gate driving circuit located in the first non-display area 1001b and the second non-display area 1002b.

[0046] The gates of the third transistors T3 in the plurality of pixel driving circuits in the M+1th pixel row PL(M+1) are electrically connected to the second gate driving circuit of the M+1th level in the first non-display area 1001b and the second non-display area 1002b. The gates of the third transistors T3 in the plurality of pixel driving circuits in the M+2th pixel row PL(M+2) are electrically connected to the second gate driving circuit of the M+2th level in the first non-display area 1001b and the second non-display area 1002b, and the second gate driving circuit of the M+2th level provides the second gate signal SE2(M+2) of the M+2th level.

[0047] The gate of the fourth transistor T4 in the plurality of pixel driving circuits located in the M+1th pixel row PL(M+1) is electrically connected to the second gate driving circuit of the Mth stage located in the first non-display area 1001b and the second non-display area 1002b. The gate of the fourth transistor T4 in the plurality of pixel driving circuits located in the M+2th pixel row PL(M+2) is electrically connected to the second gate driving circuit of the M+1th stage located in the first non-display area 1001b and the second non-display area 1002b.

[0048] The gate of the fifth transistor T5 and the gate of the sixth transistor T6 in the multiple pixel driving circuits located in the M+1 pixel row PL(M+1) are electrically connected to the third selection driving circuit of the Nth level located in the first non-display area 1001b and the second non-display area 1002b, and the third selection driving circuit of the Nth level provides the third selection signal EM(N) of the Nth level. The gate of the fifth transistor T5 and the gate of the sixth transistor T6 in the multiple pixel driving circuits located in the M+2 pixel row PL(M+2) are electrically connected to the third selection driving circuit of the Nth level located in the first non-display area 1001b and the second non-display area 1002b. Wherein, M is greater than or equal to 0, N is greater than or equal to 0, Figure 4A to Figure 4E A is equal to 4, 5, 6, ..., etc., and B is equal to 2, 3, 4, ..., etc.

[0049] Since the third enable driving circuit 203 can be electrically connected to multiple pixel driving circuits of two adjacent pixel rows PL, the third enable driving circuit 203 is arranged on the side of the second enable driving circuit 202 away from the display area 100a, which can reduce the probability of overlap between the first enable line GL1, the second enable line GL2 and the third enable driving circuit 203.

[0050] Optionally, since in the first non-display area 1001b and the second non-display area 1002b, multiple first selection drive circuits 201, multiple second selection drive circuits 202 and multiple third selection drive circuits 203 are all arranged in stages, therefore, in order to reduce the difficulty of wiring and reduce the winding distance, multiple first selection drive circuits 201 are cascaded row by row in the first non-display area 1001b and the second non-display area 1002b, multiple second selection drive circuits 202 are cascaded row by row in the first non-display area 1001b and the second non-display area 1002b, and multiple third selection drive circuits 203 are cascaded row by row in the first non-display area 1001b and the second non-display area 1002b.

[0051] For details, please continue to see Figure 4B The two first selection drive circuits 201 of the same level electrically connected to the multiple pixel drive circuits of the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b; the number of the second selection drive circuits 202 of the same level electrically connected to the multiple pixel drive circuits located in the same pixel row PL is one, and the number of the third selection drive circuits 203 of the same level is one.

[0052] Among them, multiple second-stage enable driving circuits 202 are all located in the second non-display area 1002b, multiple third-stage enable driving circuits 203 are all located in the first non-display area 1001b, and multiple second-stage enable driving circuits 202 and multiple third-stage enable driving circuits 203 are all located on the side of multiple first-stage enable driving circuits 201 away from the display area 100a.

[0053] Optionally, the plurality of first selection drive circuits 201 located in the first non-display area 1001b and the second non-display area 1002b are symmetrically arranged with respect to the display area 100a, so that the first selection signal Scan1 transmitted by the two same-level first selection drive circuits 201 located in the first non-display area 1001b and the second non-display area 1002b has a similar loss when transmitted to the display area 100a via the corresponding first selection line, so that the display panel has better display quality.

[0054] Further, the multiple pixel driving circuits located in the M+1 pixel row PL(M+1) and the M+2 pixel row PL(M+2) are still used as an example for description. Among them, the gate of the second transistor T2, the gate of the seventh transistor T7 and the multiple pixel driving circuits located in the M+1 pixel row PL(M+1) and the M+2 pixel row PL(M+2) are connected to each other. Figure 4AThe connection forms shown are similar and will not be described in detail here.

[0055] The gate of the third transistor T3 in the plurality of pixel driving circuits located in the M+1th pixel row PL(M+1) is electrically connected to the second gate driving circuit of the M+1th level located in the second non-display area 1002b. The gate of the third transistor T3 in the plurality of pixel driving circuits located in the M+2th pixel row PL(M+2) is electrically connected to the second gate driving circuit of the M+2th level located in the second non-display area 1002b.

[0056] The gate of the fourth transistor T4 in the plurality of pixel driving circuits located in the M+1th pixel row PL(M+1) is electrically connected to the second gate driving circuit of the Mth stage located in the second non-display area 1002b. The gate of the fourth transistor T4 in the plurality of pixel driving circuits located in the M+2th pixel row PL(M+2) is electrically connected to the second gate driving circuit of the M+1th stage located in the second non-display area 1002b.

[0057] The gate of the fifth transistor T5 and the gate of the sixth transistor T6 in the multiple pixel driving circuits located in the M+1th pixel row PL(M+1) and the M+2th pixel row PL(M+2) are electrically connected to the third selection driving circuit of the Nth level located in the first non-display area 1001b.

[0058] Optionally, since the first non-display area 1001b and the second non-display area 1002b both include a plurality of the first gate drive circuits 201, and the plurality of the first gate drive circuits 201 are arranged in stages in the first non-display area 1001b and the second non-display area 1002b, the plurality of the first gate drive circuits 201 located in the first non-display area 1001b and the second non-display area 1002b are cascaded row by row. Since the plurality of the second gate drive circuits 202 are all located in the second non-display area 1002b, and the plurality of the second gate drive circuits 202 are arranged in stages, the plurality of the second gate drive circuits 202 can be cascaded row by row. Since the plurality of the third gate drive circuits 203 are all located in the first non-display area 1001b, and the plurality of the third gate drive circuits 203 are arranged in stages, the plurality of the third gate drive circuits 203 can be cascaded row by row.

[0059] Optionally, when writing frame WF and holding frame HF, the number of valid pulses of the first start signal STV1 is single or multiple, since the first non-display area 1001b and the second non-display area 1002b both include multiple first selection drive circuits 201, the multiple first selection signals Scan1 transmitted to the display panel have similar losses, and can also better compensate for the anode voltage and gate voltage of the light-emitting device.

[0060] For details, please continue to see Figure 4C The two second-level selection drive circuits 202 that are electrically connected to the multiple pixel drive circuits in the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b; the number of the first-level selection drive circuits 201 that are electrically connected to the multiple pixel drive circuits located in the same pixel row PL is one, and the number of the third-level selection drive circuits 203 that are located in the same pixel row PL is one.

[0061] Among them, the plurality of first gate drive circuits 201 are all located in the second non-display area 1002b, the plurality of third gate drive circuits 203 are all located in the first non-display area 1001b, and the plurality of first gate drive circuits 201 and the plurality of third gate drive circuits 203 are all located on the side of the plurality of second gate drive circuits 202 away from the display area 100a. The plurality of second gate drive circuits 202 located in the first non-display area 1001b and the second non-display area 1002b are symmetrically arranged with respect to the display area 100a, so that the second gate signal SE2 transmitted by the two same-level second gate drive circuits 202 located in the first non-display area 1001b and the second non-display area 1002b has a similar loss when transmitted to the display area 100a via the corresponding second gate line, so that the display panel has a better display quality.

[0062] Further, the multiple pixel driving circuits located in the M+1 pixel row PL(M+1) and the M+2 pixel row PL(M+2) are still used as an example for description. Among them, the gate of the third transistor T3 and the gate of the fourth transistor T4 in the multiple pixel driving circuits located in the M+1 pixel row PL(M+1) and the M+2 pixel row PL(M+2) are connected to Figure 4A The connection form shown is similar; the gate of the fifth transistor T5 and the gate of the sixth transistor T6 in the plurality of pixel driving circuits located in the M+1th pixel row PL(M+1) and the M+2th pixel row PL(M+2) are connected to Figure 4B The connection forms shown are similar and will not be described in detail here.

[0063] The gates of the second transistors T2 in the plurality of pixel driving circuits in the M+1th pixel row PL(M+1) are electrically connected to the M+1th first gate driving circuit in the second non-display area 1002b. The gates of the second transistors T2 in the plurality of pixel driving circuits in the M+2th pixel row PL(M+2) are electrically connected to the M+2th first gate driving circuit in the second non-display area 1002b.

[0064] The gate of the seventh transistor T7 in the plurality of pixel driving circuits located in the M+1th pixel row PL(M+1) is electrically connected to the Mth-stage first gate driving circuit located in the second non-display area 1002b. The gate of the seventh transistor T7 in the plurality of pixel driving circuits located in the M+2th pixel row PL(M+2) is electrically connected to the M+1th-stage first gate driving circuit located in the second non-display area 1002b.

[0065] Optionally, since the plurality of first gate drive circuits 201 are all located in the second non-display area 1002b, and the plurality of first gate drive circuits 201 are arranged in stages, the plurality of first gate drive circuits 201 can be cascaded row by row. Since the first non-display area 1001b and the second non-display area 1002b both include a plurality of second gate drive circuits 202, and the plurality of second gate drive circuits 202 are arranged in stages in the first non-display area 1001b and the second non-display area 1002b, the plurality of second gate drive circuits 202 located in the first non-display area 1001b and the second non-display area 1002b are cascaded row by row. Since the plurality of third gate drive circuits 203 are all located in the first non-display area 1001b, and the plurality of third gate drive circuits 203 are arranged in stages, the plurality of third gate drive circuits 203 can be cascaded row by row.

[0066] Compared to Figure 4A to Figure 4B The arrangement of Figure 4C In the described arrangement, multiple first selection drive circuits 201 are only located in the second non-display area 1002b. When compensating the anode voltage of the light-emitting device and the gate voltage of the driving transistor in the writing frame WF and the holding frame HF, the number of first selection drive circuits 201 involved is relatively small, which can reduce the power consumption of the display panel.

[0067] See also Figure 4D The two third selection drive circuits 203 of the same level electrically connected to the multiple pixel drive circuits of the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b; the number of the first selection drive circuits 201 of the same level electrically connected to the multiple pixel drive circuits located in the same pixel row PL is one, and the number of the second selection drive circuits 202 of the same level is one.

[0068] Optionally, the plurality of first gate drive circuits 201 are all located in the first non-display area 1001b, and the plurality of second gate drive circuits 202 are all located in the second non-display area 1002b. Optionally, the plurality of first gate drive circuits 201 located in the first non-display area 1001b are cascaded row by row, and the plurality of second gate drive circuits 202 located in the second non-display area 1002b are cascaded row by row.

[0069] Optionally, the plurality of first gate drive circuits 201 and the plurality of second gate drive circuits 202 are alternately arranged in the first non-display area 1001b and the second non-display area 1002b, and the plurality of first gate drive circuits 201 and the plurality of second gate drive circuits 202 are both located on one side of the plurality of third gate drive circuits 203 close to the display area 100a. Figure 4D Optionally, the plurality of first gate drive circuits 201 located in the first non-display area 1001b and the second non-display area 1002b are cascaded in alternate rows, and the plurality of second gate drive circuits 202 located in the first non-display area 1001b and the second non-display area 1002b are cascaded in alternate rows.

[0070] Optionally, a plurality of the third gate driving circuits 203 are cascaded row by row in the first non-display area 1001b and the second non-display area 1002b. Figure 4D The connection form of each transistor in the plurality of pixel driving circuits in the plurality of pixel rows PL can be seen in Figure 4A to Figure 4C The description will not be repeated here.

[0071] The pixel driving circuit adopts Figure 2B The structure shown in the figure is used to illustrate that the circuit structure of the second gate drive circuit 202 is the same as that of the third gate drive circuit 203. The two first gate drive circuits 201 of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b; the second gate drive circuit 202 electrically connected to the gate of the third transistor T3 of the plurality of pixel drive circuits of the same pixel row PL, and the second gate drive circuit 202 electrically connected to the gate of the fourth transistor T4 of the plurality of pixel drive circuits of the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b; the two third gate drive circuits 203 of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row PL are respectively located in the first non-display area 1001b and the second non-display area 1002b.

[0072] Wherein, in the first non-display area 1001b and the second non-display area 1002b, the second gate drive circuit 202 is located between the first gate drive circuit 201 and the third gate drive circuit 203, and the third gate drive circuit 203 is located on the side of the second gate drive circuit 202 away from the display area 100a. Figure 4E As shown. Among them, Figure 4E P in it is greater than or equal to 0, O is greater than or equal to 0; C can be equal to 2, 3, 4, etc.

[0073] Further, a plurality of pixel driving circuits located in the M+1th pixel row PL(M+1) and the M+2th pixel row PL(M+2) are used as an example for description. Among them, the gate of the second transistor T2, the gate of the fifth transistor T5, the gate of the sixth transistor T6, and the gate of the seventh transistor T7 in the plurality of pixel driving circuits located in the M+1th pixel row PL(M+1) and the M+2th pixel row PL(M+2) are connected to Figure 4A The connection forms shown are similar and will not be described in detail here.

[0074] The gates of the third transistors T3 in the multiple pixel driving circuits located in the M+1th pixel row PL(M+1) and the M+2th pixel row PL(M+2) are electrically connected to the Pth level second selection driving circuit located in the first non-display area 1001b.

[0075] The gates of the fourth transistors T4 in the multiple pixel driving circuits located in the M+1th pixel row PL(M+1) and the M+2th pixel row PL(M+2) are electrically connected to the second enable driving circuit of the Oth level located in the second non-display area 1002b.

[0076] Compared to Figure 4A to Figure 4D A second gate driving circuit 20 is shown to be electrically connected to a plurality of pixel driving circuits of a pixel row PL. Figure 4E The second gate driving circuit 202 is electrically connected to the plurality of pixel driving circuits of two adjacent pixel rows PL, so that Figure 4E The refresh rate of the second selection signal SE2 output by the second selection driving circuit 202 is low, which can reduce the power consumption of the display panel.

[0077] Optionally, the multiple first selection drive circuits 201 located in the first non-display area 1001b and the second non-display area 1002b are cascaded row by row, and the multiple second selection drive circuits 202 located in the first non-display area 1001b and the second non-display area 1002b are cascaded row by row; the multiple third selection drive circuits 203 located in the first non-display area 1001b and the second non-display area 1002b are cascaded row by row. Since the multiple second-select drive circuits 202 located in the first non-display area 1001b and the multiple second-select drive circuits 202 located in the second non-display area 1002b are electrically connected to the gates of the third transistor T3 and the fourth transistor T4, respectively, the second start signal corresponding to the multiple second-select drive circuits 202 located in the first non-display area 1001b may be STV21, and the second start signal corresponding to the multiple second-select drive circuits 202 located in the second non-display area 1002b may be STV22, wherein the timing of STV21 and STV22 is different, so that the third transistor T3 can be turned on with the fourth transistor T4 in a time-sharing manner.

[0078] Compared to Figure 4B to Figure 4D The layout shown, Figure 4A The layout shown can reduce the loss of the selection signal transmitted to the display panel and is more suitable for large-size display panels.

[0079] like Figure 4A and Figure 4E In the layout shown, the first number of columns of the plurality of gate drive circuits located in the first non-display area 1001b is 3, and the second number of columns of the plurality of gate drive circuits located in the second non-display area 1002b is 3; Figure 4B to Figure 4D In the layout shown, the first number of columns of the plurality of gate drive circuits located in the first non-display area 1001b is 2, and the second number of columns of the plurality of gate drive circuits located in the second non-display area 1002b is 2. Therefore, compared with Figure 4A and Figure 4E The layout shown, Figure 4B to Figure 4D The layout shown is more conducive to realizing a narrow frame design of the display panel.

[0080] The present invention further provides a display device, the display device comprising any of the above pixel driving circuits or any of the above display panels, and the display device further comprising a timing controller, the timing controller being electrically connected to the plurality of the gate driving circuits.

[0081] The timing controller receives an input image signal, converts the data format of the input image signal into a data format suitable for the interface between the timing controller and the data driving circuit, and generates image data and various control signals. The plurality of strobe driving circuits receive control signals from the timing controller to generate a plurality of strobe signals, and the control signals received by the plurality of strobe driving circuits from the timing controller include a first start signal STV1 to a third start signal STV3 and a clock signal for determining the output timing of the plurality of strobe signals. The data driving circuit receives a data control signal and image data from the timing controller. The data driving circuit converts the image data into a data signal and outputs the data signal to a plurality of data lines; wherein the data signal is an analog voltage corresponding to the grayscale value of the image data.

[0082] It can be understood that the display device includes a movable display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.

[0083] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display panel, characterized in that: include: A plurality of gate drive circuits, including a plurality of cascaded first gate drive circuits, a plurality of cascaded second gate drive circuits and a plurality of cascaded third gate drive circuits; The plurality of cascaded first strobe drive circuits output a plurality of first strobe signals in response to a first start signal, the plurality of cascaded second strobe drive circuits output a plurality of second strobe signals in response to a second start signal, and the plurality of cascaded third strobe drive circuits output a plurality of third strobe signals in response to a third start signal; in a write frame and a hold frame, the valid pulse of the first start signal and the valid pulse of the second start signal are both located within the invalid pulse action time of the third start signal; a plurality of pixel rows, each of the pixel rows comprising a plurality of sub-pixels and a plurality of pixel driving circuits electrically connected to the plurality of sub-pixels, each of the pixel driving circuits comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; the second transistor transmits a data signal in response to the corresponding first selection signal, so that the first transistor generates a driving current for controlling the sub-pixel to emit light according to the data signal, the third transistor compensates for a threshold voltage of the first transistor in response to the corresponding second selection signal, the fourth transistor transmits a first reset signal to a gate of the first transistor in response to the corresponding second selection signal, the fifth transistor and the sixth transistor simultaneously respond to the same corresponding third selection signal so that the first transistor provides a driving current to the sub-pixel, and the seventh transistor transmits a second reset signal to an anode of the sub-pixel in response to the corresponding first selection signal; Among them, the second transistor and the seventh transistor respond to different levels of the first selection signal, and the third transistor and the fourth transistor respond to different levels of the second selection signal; each of the third selection drive circuits is electrically connected to multiple pixel drive circuits in two adjacent pixel rows; the number of the first selection drive circuits of the same level electrically connected to multiple pixel drive circuits located in the same pixel row is at most two, the number of the second selection drive circuits of the same level is at most two, and the number of the third selection drive circuits of the same level is at most two.

2. The display panel according to claim 1, characterized in that: The display panel comprises: A display area, wherein the plurality of pixel rows are located in the display area; and a non-display area, located at the periphery of the display area, wherein the plurality of gate drive circuits are located in the non-display area, and wherein the non-display area includes a first non-display area and a second non-display area located at opposite sides of the display area; The plurality of gate drive circuits located in the first non-display area have a first column number, the plurality of gate drive circuits located in the second non-display area have a second column number, and the first column number is equal to the second column number.

3. The display panel according to claim 2, characterized in that: The circuit structure of the second gate drive circuit is the same as that of the first gate drive circuit, the two first gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area, the two second gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area, and the two third gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area; Among them, in the first non-display area and the second non-display area, the second gate drive circuit is located between the first gate drive circuit and the third gate drive circuit, and the third gate drive circuit is located on a side of the second gate drive circuit away from the display area.

4. The display panel according to claim 2, characterized in that: The circuit structure of the second gate drive circuit is the same as that of the third gate drive circuit; the two first gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area; the second gate drive circuit electrically connected to the third transistors of the plurality of pixel drive circuits of the same pixel row and the second gate drive circuit electrically connected to the fourth transistors of the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area; the two third gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area; Among them, in the first non-display area and the second non-display area, the second gate drive circuit is located between the first gate drive circuit and the third gate drive circuit, and the third gate drive circuit is located on a side of the second gate drive circuit away from the display area.

5. The display panel according to claim 2, characterized in that: The two first gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area; the number of the second gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits located in the same pixel row is one, and the number of the third gate drive circuits of the same level is one; Among them, multiple second-stage enable driving circuits are all located in the second non-display area, multiple third-stage enable driving circuits are all located in the first non-display area, and multiple second-stage enable driving circuits and multiple third-stage enable driving circuits are all located on the side of multiple first-stage enable driving circuits away from the display area.

6. The display panel according to claim 2, characterized in that: The two second gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area; the number of the first gate drive circuit of the same level electrically connected to the plurality of pixel drive circuits located in the same pixel row is one, and the number of the third gate drive circuit of the same level is one; Among them, multiple first enable driving circuits are all located in the second non-display area, multiple third enable driving circuits are all located in the first non-display area, and multiple first enable driving circuits and multiple third enable driving circuits are all located on the side of multiple second enable driving circuits away from the display area.

7. The display panel according to claim 2, characterized in that: The two third gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits of the same pixel row are respectively located in the first non-display area and the second non-display area; the number of the first gate drive circuits of the same level electrically connected to the plurality of pixel drive circuits located in the same pixel row is one, and the number of the second gate drive circuits of the same level is one; Among them, multiple first enable driving circuits and multiple second enable driving circuits are alternately arranged in the first non-display area and the second non-display area, and multiple first enable driving circuits and multiple second enable driving circuits are all located on the side of multiple third enable driving circuits close to the display area.

8. The display panel according to claim 1, characterized in that: In the write frame and the hold frame, the sum of the valid pulse numbers of the first start signal is greater than the sum of the valid pulse numbers of the second start signal.

9. The display panel according to claim 8, characterized in that: In the write frame, the first valid pulse of the first start signal at least partially overlaps with the valid pulse of the second start signal.

10. The display panel according to claim 1, characterized in that: The active layer of the third transistor and the active layer of the fourth transistor both include low temperature polysilicon.

11. A display device, characterized in that: It comprises the display panel as claimed in any one of claims 1 to 10 and a timing controller, wherein the timing controller is electrically connected to the plurality of gate drive circuits.

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