Memristor-based integrated storage and computing timing synchronization computing unit and method

Abstract

The present invention provides a storage-calculation integrated timing synchronization calculation unit and method based on a memristor, comprising: a first MOS transistor, a second MOS transistor, a first and a second memristor, a resistor and a current source; the first and the second memristors input a first and a second control voltage respectively; the gate of the first MOS transistor receives a switching signal, the drain receives an input calculation voltage, and the source is connected to the memristor; the gate of the second MOS transistor is connected to the memristor, the source is connected to the positive electrode of the current source, and the drain outputs a calculation result; one end of the resistor is connected to the gate of the second MOS transistor, and the other end is connected to the negative electrode of the power supply; the negative electrode of the current source is connected to the negative electrode of the power supply; when the calculation voltage and the resistance of the memristor meet preset conditions, the calculation result of the storage-calculation integrated timing synchronization is output through the second MOS transistor M2. The present invention can perform synchronous multiplication and addition calculations through the first memristor and the second memristor, thereby ensuring the parallelism of the calculation process, thereby improving the accuracy of the calculation.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a memristor-based storage and computing integrated timing synchronization computing unit and method. Background Art

[0002] The storage-computing integrated technology aims to transform the traditional computing-centric architecture into a data-centric architecture. It directly uses memory for data processing, thereby integrating data storage and computing into the same chip. It can completely eliminate the bottleneck of the von Neumann computing architecture and is particularly suitable for large-scale parallel application scenarios such as deep learning neural networks with large amounts of data.

[0003] The current mainstream storage and computing integrated circuits are mainly based on memristors. Memristors are non-volatile devices whose resistance can be changed by control signals. High resistance is "1" and low resistance is "0". The change in resistance can represent the stored data.

[0004] As the computing speed of storage and computing becomes faster and faster, the parallelism of the calculation must also be ensured. If some computing units calculate faster and some units calculate slower, it may affect the accuracy and timing of the circuit. Therefore, how to ensure the parallelism of the calculation is a problem that needs to be solved. Summary of the Invention

[0005] The present invention provides a memristor-based integrated storage and computation timing synchronization calculation unit and method, which are used to solve the defect of poor computational parallelism of the existing integrated storage and computation circuit, ensure the parallelism of the calculation process, and thus improve the accuracy of the calculation.

[0006] The present invention provides a memristor-based storage and computing integrated sequential synchronous computing unit, comprising:

[0007] A first MOS transistor M1, a second MOS transistor M2, a first memristor RRAM1 and a second memristor RRAM2 connected to each other, a resistor and a current source;

[0008] When the set clock signal is a falling edge of the clock, the first memristor RRAM1 and the second memristor RRAM2 are respectively input with a first control voltage and a second control voltage to present different resistances;

[0009] The gate of the first MOS transistor M1 receives a switching signal, the drain receives an input calculation voltage, and the source is connected to one end of the first memristor RRAM1;

[0010] When the set clock signal is a rising edge of the clock and the calculated voltage is greater than the threshold voltage of the first MOS transistor M1, the first MOS transistor MI is turned on;

[0011] The gate of the second MOS transistor M2 is connected to one end of the second memristor RRAM2, the source is connected to the positive electrode of the current source, and the drain outputs the calculation result;

[0012] The calculated voltage output by the first MOS transistor M2 is divided to obtain a node voltage. When the node voltage is greater than the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 is turned on.

[0013] One end of the resistor is connected to the gate of the second MOS transistor M2, and the other end is connected to the negative electrode of the power supply; the negative electrode of the current source is connected to the negative electrode of the power supply;

[0014] When the first MOS transistor M1 receives the switch signal, based on the calculation voltage and the resistance of the first memristor RRAM1 and the second memristor RRAM2, the calculation result of the storage-computation integrated timing synchronization is output through the second MOS transistor M2.

[0015] According to a memristor-based storage and computing integrated timing synchronization computing unit provided by the present invention, the first MOS transistor M1 and the second MOS transistor M2 are both NMOS transistors.

[0016] According to a memristor-based storage and computing integrated sequential synchronous computing unit provided by the present invention, the first memristor RRAM1 and the second memristor RRAM2 are connected in parallel or in series.

[0017] According to a memristor-based storage and computing integrated timing synchronous computing unit provided by the present invention, the resistance of the first memristor RRAM1 and the second memristor RRAM2 includes a low resistance state and a high resistance state;

[0018] The low resistance state includes extremely low resistance and low resistance, and the high resistance state includes high resistance and extremely high resistance.

[0019] According to a memristor-based storage and computing integrated timing synchronous computing unit provided by the present invention, the first memristor RRAM1 is connected to a first control voltage, and the second memristor RRAM2 is connected to a second control voltage;

[0020] The first memristor RRAM1 presents a low-resistance state based on a high level of the first control voltage, and presents a high-resistance state based on a low level of the first control voltage;

[0021] The second memristor RRAM2 presents a low-resistance state based on a high level of the second control voltage, and presents a high-resistance state based on a low level of the second control voltage.

[0022] According to the present invention, a memristor-based storage and computing integrated timing synchronization computing unit further includes: a first transistor and a second transistor;

[0023] The first transistor, the second transistor and the second MOS transistor M2 are connected in common gate and common source.

[0024] According to a memristor-based storage and calculation integrated timing synchronous computing unit provided by the present invention, the current source is a bias current source or a current mirror composed of a MOS tube.

[0025] The present invention also provides a memristor-based storage and computing integrated timing synchronous computing method, comprising:

[0026] When the set clock signal is a falling edge of the clock, the resistance is confirmed based on the first control voltage through the first memristor RRAM1, and the resistance is confirmed based on the second control voltage through the second memristor RRAM2;

[0027] When the set clock signal is a clock rising edge, a calculated voltage is input and when the calculated voltage is greater than a threshold voltage of the first MOS transistor M1 , the calculated voltage is output through the drain of the first MOS transistor M1 ;

[0028] The calculated voltage is divided by the first memristor RRAM1, the second memristor RRAM2 and the resistor to obtain a node voltage to control the conduction of the second MOS transistor M2;

[0029] When the node voltage is greater than the conduction threshold voltage of the second MOS transistor M2, the calculation result of the storage-computation integrated timing synchronization is output through the second MOS transistor M2 based on the calculated voltage, resistance, and the resistance of the first memristor RRAM1 and the second memristor RRAM2.

[0030] According to a memristor-based storage and computing timing synchronization calculation method provided by the present invention, when the node voltage is greater than the turn-on threshold voltage of the second MOS transistor M2, based on the calculation voltage, resistance, and the resistivity of the first memristor RRAM1 and the second memristor RRAM2, the calculation result of the storage and computing timing synchronization is output through the second MOS transistor M2, including:

[0031] When the node voltage is greater than the turn-on threshold voltage of the second MOS transistor M2, determining whether the resistance of the first memristor RRAM1 and the second memristor RRAM2 are both low resistance;

[0032] When the resistance of the first memristor RRAM1 and the second memristor RRAM2 are both low, the calculation result of the storage and calculation timing synchronization is output through the second MOS tube M2 in combination with the calculation voltage, resistance, and the resistance values ​​of the first memristor RRAM1 and the second memristor RRAM2.

[0033] According to a memristor-based storage and computing integrated timing synchronization calculation method provided by the present invention, when a set clock signal is a falling clock edge, before confirming the resistance of the first memristor RRAM1 based on the first control voltage and confirming the resistance of the second memristor RRAM2 based on the second control voltage, the method further includes:

[0034] Setting clock signals to control the timing of synchronous computing units;

[0035] The clock signal is a square wave, which switches between a low level and a high level periodically.

[0036] The present invention provides a memristor-based, integrated, and synchronously synchronized computing unit and method. The unit operates by receiving a switching signal. The input computing voltage satisfies the conduction conditions of the first and second MOS transistors M1 and M2, enabling the circuit to conduct. The unit then performs a calculation based on the resistance of the first and second memristors RRAM1 and RRAM2, combined with the input voltage, to obtain a calculation result. The present invention enables synchronous multiplication and addition calculations using the first and second memristors RRAM1 and RRAM2, ensuring parallelism in the computation process and improving computational accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 This is one of the circuit diagrams of the memristor-based integrated timing synchronous computing unit provided by the present invention;

[0039] Figure 2 This is the second circuit diagram of the memristor-based integrated timing synchronous computing unit provided by the present invention;

[0040] Figure 3 This is the third circuit diagram of the memristor-based integrated timing synchronous computing unit provided by the present invention;

[0041] Figure 4 This is an array circuit diagram of a memristor-based integrated storage and computing sequential synchronous computing unit provided by the present invention;

[0042] Figure 5 This is one of the flow charts of the memristor-based storage and computing time-series synchronous calculation method provided by the present invention;

[0043] Figure 6This is the second flow chart of the memristor-based storage and computing time-synchronized calculation method provided by the present invention. DETAILED DESCRIPTION

[0044] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0045] The following combination Figures 1-6 The present invention describes a memristor-based sequential synchronous computing unit and method.

[0046] Reference Figure 1 The present invention provides a memristor-based storage and computing integrated timing synchronization computing unit, comprising: a first MOS transistor M1, a second MOS transistor M2, a first memristor RRAM1 and a second memristor RRAM2 connected to each other, a resistor, and a current source;

[0047] When the set clock signal is a falling edge of the clock, the first memristor RRAM1 and the second memristor RRAM2 are respectively input with a first control voltage and a second control voltage to present different resistances;

[0048] The gate of the first MOS transistor M1 receives a switching signal, the drain receives an input calculation voltage, and the source is connected to one end of the first memristor RRAM1;

[0049] When the set clock signal is a rising edge of the clock and the calculated voltage is greater than the threshold voltage of the first MOS transistor M1, the first MOS transistor MI is turned on;

[0050] The gate of the second MOS transistor M2 is connected to one end of the second memristor RRAM2, the source is connected to the positive electrode of the current source, and the drain outputs the calculation result;

[0051] The calculated voltage output by the first MOS transistor M2 is divided to obtain a node voltage. When the node voltage is greater than the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 is turned on.

[0052] One end of the resistor is connected to the gate of the second MOS transistor M2, and the other end is connected to the negative electrode of the power supply; the negative electrode of the current source is connected to the negative electrode of the power supply;

[0053] When the first MOS transistor M1 receives the switch signal, based on the calculation voltage and the resistance of the first memristor RRAM1 and the second memristor RRAM2, the calculation result of the storage-computation integrated timing synchronization is output through the second MOS transistor M2.

[0054] Specifically, in this embodiment, the first memristor RRAM1 and the second memristor RRAM2 can be regarded as a memristor group, and the memristor group realizes the parallelism of the computing process, wherein the connection relationship between the first memristor RRAM1 and the second memristor RRAM2 can be arbitrarily set to series or parallel.

[0055] The source of the first MOS transistor M1, one end of the first memristor RRAM1, and one end of the second memristor RRAM2 are connected together; the gate of the first MOS transistor M1 is connected to the calculation unit switch signal S11; the drain of the first MOS transistor M1 is connected to the calculation voltage input signal VI; the other end of the first memristor RRAM1, the other end of the second memristor RRAM2, one end of the first resistor, and the gate of the second MOS transistor M2 are connected together; the source of the second MOS transistor M2 is connected to the positive electrode of the current source; the first memristor RRAM1 and the second memristor RRAM2 are connected to the resistance control voltages VSET1 and VSET2, respectively; the drain of the second MOS transistor M2 serves as the output terminal IOUT11 of this synchronous calculation unit, for outputting the calculation result; the other end of the first resistor and the negative electrode of the current source are connected to the negative electrode of the power supply.

[0056] The first memristor RRAM1 and the second memristor RRAM2 exhibit different resistances according to the control voltage. When the preset conditions are met, that is, when the first memristor RRAM1 and the second memristor RRAM2 are both low-resistance, a multiplication and addition calculation is performed based on the input calculation voltage, the resistance value of the first memristor RRAM1, the resistance value of the second memristor RRAM2, and the resistance value of the resistor, and the calculation result is output through the drain of the second MOS transistor M2.

[0057] This embodiment can be understood as a method for calculating the neural network's excitation values ​​and weights by designating the resistance of the first memristor RRAM1 and the second memristor RRAM2 as the input value, i.e., the excitation value; the resistance of the second memristor RRAM2 as the weight, and the convolution calculation using the weight and the excitation value can be considered a multiplication-addition calculation between the first memristor RRAM1 and the second memristor RRAM2.

[0058] It should be noted that the source and drain of the first MOS transistor M1 and the second MOS transistor M2 are interchangeable. The first MOS transistor M1 and the second MOS transistor M2 are both NMOS transistors. The resistor can also be a memristor, which has the same function as a resistor.

[0059] The present invention provides a memristor-based, integrated, and synchronously synchronized computing unit. This unit operates by receiving a switching signal. The input computing voltage satisfies the conduction conditions of the first and second MOS transistors M1 and M2, enabling the circuit to conduct. The unit then performs calculations based on the resistance of the first and second memristors RRAM1 and RRAM2 combined with the input voltage to obtain a result. The present invention enables synchronous multiplication and addition calculations using the first and second memristors RRAM1 and RRAM2, ensuring parallelism in the computation process and improving computational accuracy.

[0060] Based on the above embodiment, the first memristor RRAM1 and the second memristor RRAM2 are connected in parallel or in series.

[0061] Reference Figure 2 In this embodiment, the first memristor RRAM1 and the second memristor RRAM2 are connected in series, and can also realize synchronous multiplication and addition calculations through the first memristor RRAM1 and the second memristor RRAM2, thereby ensuring the parallelism of the calculation process and improving the accuracy of the calculation.

[0062] Based on the above embodiment, the resistance of the first memristor RRAM1 and the second memristor RRAM2 includes a low resistance state and a high resistance state;

[0063] The low resistance state includes extremely low resistance and low resistance, and the high resistance state includes high resistance and extremely high resistance.

[0064] The first memristor RRAM1 presents a low-resistance state based on a high level of the first control voltage, and presents a high-resistance state based on a low level of the first control voltage;

[0065] The second memristor RRAM2 presents a low-resistance state based on a high level of the second control voltage, and presents a high-resistance state based on a low level of the second control voltage.

[0066] Specifically, the resistance of the first memristor RRAM1 and the second memristor RRAM2 can be divided into: low-low resistance (LLRS), low resistance (LRS), high resistance (HRS), and high-high resistance (HHRS).

[0067] By adjusting the control voltage, the first memristor RRAM1 and the second memristor RRAM2 exhibit different resistances, which are specifically shown as follows:

[0068] When the control voltages VSET1 and VSET2 are input at a high level (1), the memristor is written into a low resistance state LRS; when the resistance control voltages VSET1 and VSET2 are input at a low level (0), the memristor is written into a high resistance state HRS.

[0069] Based on the above embodiment, the further comprising: a first transistor and a second transistor;

[0070] The first transistor, the second transistor and the second MOS transistor M2 are connected in common gate and common source.

[0071] Reference Figure 3 In this embodiment, the first transistor M3, the second transistor M4 and the second MOS transistor M2 are connected in common gate and common source, thereby increasing the accuracy of the circuit output.

[0072] According to a memristor-based storage and calculation integrated timing synchronous computing unit provided by the present invention, the current source is a bias current source or a current mirror composed of a MOS tube.

[0073] Specifically, the current source may be a bias current source IBIAS1, or may be various current mirrors composed of MOS transistors to provide a stable 10 A current.

[0074] Reference Figure 4 The memristor-based integrated storage and computing sequential synchronization computing unit provided by the present invention can constitute an array circuit, and the array circuit is expanded by multiple computing units, thereby being able to support larger-scale current multiplication and addition operations.

[0075] It should be noted that the voltages at nodes WL1, WL2, ..., WLK are VSET11, VSET12, ..., VL1K; the voltages at nodes WLB1, WLB2, ..., WLB2K are VSET21, VSET22, ..., VSET2K; and the voltage at node WI is V1. K and N are positive integers.

[0076] In the neural network, weights and excitations are convolved, and the KxN array composed of the memristor-based storage and computing integrated timing synchronization unit in the above embodiment is regarded as a matrix representing KxN weights. Through the input voltage signal (excitation), a current signal is output to represent the result of multiplication and addition.

[0077] In this embodiment, taking the first column as an example, the output currents IOUT11, IOUT21, ..., IOUTK1 of K storage-computation-in-one timing synchronization units are connected together at the node BL1 to obtain the multiplication-addition current I1, which can be expressed as:

[0078] I1=VI*(W11*Vin1+W21*Vin2+···+WK1*VinK)*IO (1)

[0080] Similarly, the values ​​of the multiplied currents I2, I3, ..., IN of the remaining N-1 columns can be obtained.

[0081] The array circuit of this embodiment can synchronize the calculations of the K x N calculation units, preventing the situation where the calculation signals and calculation times are out of sync. The stability of the multiplication and addition current can also be guaranteed through timing control, and the situation where the calculations cannot be completed at the same time will not occur.

[0082] Reference Figure 5 The present invention also provides a memory-computing integrated timing synchronous computing method based on a memristor, comprising the following steps:

[0083] Step 510: When the set clock signal is a falling edge of the clock, the resistance of the first memristor RRAM1 is confirmed based on the first control voltage, and the resistance of the second memristor RRAM2 is confirmed based on the second control voltage;

[0084] Step 520: When the set clock signal is a clock rising edge, input a calculated voltage and output the calculated voltage through the drain of the first MOS transistor M1 when the calculated voltage is greater than the threshold voltage of the first MOS transistor M1;

[0085] Step 530: Dividing the calculated voltage by the first memristor RRAM1, the second memristor RRAM2, and a resistor to obtain a node voltage to control the conduction of the second MOS transistor M2;

[0086] Step 540: When the node voltage is greater than the turn-on threshold voltage of the second MOS transistor M2, based on the calculated voltage, resistance, and the resistance of the first memristor RRAM1 and the second memristor RRAM2, the calculation result of the storage-computation integrated timing synchronization is output through the second MOS transistor M2.

[0087] Specifically, this embodiment performs both write and read operations by using a calculation unit circuit according to a set clock signal. Specific embodiments include:

[0088] When the falling edge of the clock signal CLK arrives, a write operation is performed on the first memristor RRAM1: a resistance value is written into the first memristor RRAM1 through the first control voltage VSET1 inputted by the voltage; the resistance value stored in the first memristor RRAM1 corresponds to the value of the input value Vin.

[0089] When the rising edge of the CLK clock arrives, the multiplication and addition result of the circuit is read: the calculation voltage VI is input to the circuit; when the voltage input terminal S11 is greater than the threshold voltage Vth1 of M1, the first MOS transistor M1 is turned on and the calculation unit operates normally; VI is divided by the first memristor RRAM1, the second memristor RRAM2, and the resistor R3; the node connected by the other end of the first memristor RRAM1, the other end of the second memristor RRAM2, one end of the resistor R3, and the gate of the second MOS transistor M2 is defined as Vp; the node voltage of Vp is connected to the gate of the second MOS transistor M2 to control the conduction of M2. The conduction condition of the second MOS transistor M2 can be expressed by the following expression:

[0090] Vp>Vth2>VI x R3 / ((R1 / / R2)+R3) (2)

[0092] Wherein, R1 and R2 are the resistance values ​​of RRAM1 and RRAM2 respectively; R1 / / R2 represents the parallel connection of the first memristor RRAM1 and the second memristor RRAM2; and Vth is the turn-on voltage of the second MOS transistor M2.

[0093] For example, define low resistance LRS as 10K ohms, high resistance HRS as 100K ohms, and Vth>2 / 3VI.

[0094] For RRAM1, when the resistance control voltage VSET1 is high, R1 becomes LRS; when the resistance control voltage VSET1 is low, R1 becomes HRS. For R2, when the resistance is LRS, the weight W represents 1, and when the resistance is HRS, the weight W represents 0. VSET2 is used to set the value of weight W. The following table shows the truth table of IOUT11 corresponding to VI, R1, R2, and R3.

[0095] Table 1:

[0096]

[0097] From this, we can see that when the VI calculation voltage is applied, the calculation unit outputs 10 A only when the input value Vin represented by R1 and the weight W represented by R2 are both 1, that is, when R1 and R2 are both low resistance LRS. In other cases, the calculation unit outputs 0 A.

[0098] Based on the above embodiment, when the node voltage is greater than the turn-on threshold voltage of the second MOS transistor M2, based on the calculated voltage, resistance, and the resistance of the first memristor RRAM1 and the second memristor RRAM2, the calculation result of the storage-computation integrated timing synchronization is output through the second MOS transistor M2, including:

[0099] When the node voltage is greater than the turn-on threshold voltage of the second MOS transistor M2, determining whether the resistance of the first memristor RRAM1 and the second memristor RRAM2 are both low resistance;

[0100] When the resistance of the first memristor RRAM1 and the second memristor RRAM2 are both low, the calculation result of the storage and calculation timing synchronization is output through the second MOS tube M2 in combination with the calculation voltage, resistance, and the resistance values ​​of the first memristor RRAM1 and the second memristor RRAM2.

[0101] Specifically, this embodiment determines that the second MOS transistor M2 is on by comparing the node voltage after voltage division with the on-state voltage of the second MOS transistor M2. When both the first memristor RRAM1 and the second memristor RRAM2 have low resistance, i.e., their input signals are both "1," the resistance values ​​of the first memristor RRAM1 and the second memristor RRAM2 are used as the stimulus values ​​and weights for the neural network convolution calculation, and a multiplication and addition calculation is performed. The calculation result is obtained by combining the calculated voltage and resistance.

[0102] Based on the above embodiment, when the set clock signal is a falling edge of the clock, before confirming the resistance of the first memristor RRAM1 based on the first control voltage and confirming the resistance of the second memristor RRAM2 based on the second control voltage, the method further includes:

[0103] Setting clock signals to control the timing of synchronous computing units;

[0104] The clock signal is a square wave, which switches between a low level and a high level periodically.

[0105] Reference Figure 6 , Figure 6 The second flow chart of the memristor-based storage and computing time-series synchronous calculation method provided by the present invention includes the following steps:

[0106] Step 610: Wait for the falling edge of the clock to arrive;

[0107] Step 611, VSET1 sets RRAM1;

[0108] Step 612, VSET2 sets RRAM2;

[0109] Step 620: Wait for the rising edge of the clock to arrive (M1 is turned on);

[0110] Step 630 , RRAM1, RRAM2, and R1 are voltage-divided;

[0111] Step 640: Determine whether the voltage of the divided node is greater than M2; if so, execute step 650; if not, return to step 610;

[0112] Step 650: Output IO.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A memristor-based integrated storage and computing time-synchronized computing unit, characterized in that: include: A first MOS transistor M1, a second MOS transistor M2, a first memristor RRAM1 and a second memristor RRAM2 connected to each other, a resistor and a current source; When the set clock signal is a falling edge of the clock, the first memristor RRAM1 and the second memristor RRAM2 are respectively input with a first control voltage and a second control voltage to present different resistances; The gate of the first MOS transistor M1 receives a switching signal, the drain receives an input calculation voltage, and the source is connected to one end of the first memristor RRAM1; When the set clock signal is a rising edge of the clock and the calculated voltage is greater than the threshold voltage of the first MOS transistor M1, the first MOS transistor MI is turned on; The gate of the second MOS transistor M2 is connected to one end of the second memristor RRAM2, the source is connected to the positive electrode of the current source, and the drain outputs the calculation result; The calculated voltage output by the first MOS transistor M2 is divided to obtain a node voltage. When the node voltage is greater than the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 is turned on. One end of the resistor is connected to the gate of the second MOS transistor M2, and the other end is connected to the negative electrode of the power supply; the negative electrode of the current source is connected to the negative electrode of the power supply; When the first MOS transistor M1 receives the switch signal, based on the calculation voltage and the resistance of the first memristor RRAM1 and the second memristor RRAM2, the calculation result of the storage-computation integrated timing synchronization is output through the second MOS transistor M2.

2. The memristor-based integrated storage and computing time-synchronized computing unit according to claim 1, characterized in that: The first MOS transistor M1 and the second MOS transistor M2 are both NMOS transistors.

3. The memristor-based integrated storage and computing time-synchronized computing unit according to claim 1, characterized in that: The first memristor RRAM1 and the second memristor RRAM2 are connected in parallel or in series.

4. The memristor-based integrated storage and computing time-synchronized computing unit according to claim 3, characterized in that: The resistance properties of the first memristor RRAM1 and the second memristor RRAM2 include a low resistance state and a high resistance state; The low resistance state includes extremely low resistance and low resistance, and the high resistance state includes high resistance and extremely high resistance.

5. The memristor-based integrated storage and computing time-synchronized computing unit according to claim 4, characterized in that: The first memristor RRAM1 presents a low-resistance state based on a high level of the first control voltage, and presents a high-resistance state based on a low level of the first control voltage; The second memristor RRAM2 presents a low-resistance state based on a high level of the second control voltage, and presents a high-resistance state based on a low level of the second control voltage.

6. The memristor-based integrated storage and computing time-synchronized computing unit according to claim 1, characterized in that: Also includes: a first transistor and a second transistor; The first transistor, the second transistor and the second MOS transistor M2 are connected in common gate and common source.

7. The memristor-based integrated storage and computing time-synchronized computing unit according to claim 1, characterized in that: The current source is a bias current source or a current mirror composed of a MOS tube.

8. A memristor-based storage-computing integrated sequential synchronous computing method implemented by the memristor-based storage-computing integrated sequential synchronous computing unit according to any one of claims 1 to 7, characterized in that: include: When the set clock signal is a falling edge of the clock, the resistance is confirmed based on the first control voltage through the first memristor RRAM1, and the resistance is confirmed based on the second control voltage through the second memristor RRAM2; When the set clock signal is a clock rising edge, a calculated voltage is input and when the calculated voltage is greater than a threshold voltage of the first MOS transistor M1 , the calculated voltage is output through the drain of the first MOS transistor M1 ; The calculated voltage is divided by the first memristor RRAM1, the second memristor RRAM2 and the resistor to obtain a node voltage to control the conduction of the second MOS transistor M2; When the node voltage is greater than the conduction threshold voltage of the second MOS transistor M2, the calculation result of the storage-computation integrated timing synchronization is output through the second MOS transistor M2 based on the calculated voltage, resistance, and the resistance of the first memristor RRAM1 and the second memristor RRAM2.

9. The memristor-based storage and computing integrated timing synchronous computing method according to claim 8, characterized in that: When the node voltage is greater than the turn-on threshold voltage of the second MOS transistor M2, based on the calculated voltage, the resistance, and the resistance of the first memristor RRAM1 and the second memristor RRAM2, the calculation result of the storage-computation integrated timing synchronization is output through the second MOS transistor M2, including: When the node voltage is greater than the turn-on threshold voltage of the second MOS transistor M2, determining whether the resistance of the first memristor RRAM1 and the second memristor RRAM2 are both low resistance; When the resistance of the first memristor RRAM1 and the second memristor RRAM2 are both low, the calculation result of the storage and calculation timing synchronization is output through the second MOS tube M2 in combination with the calculation voltage, resistance, and the resistance values ​​of the first memristor RRAM1 and the second memristor RRAM2.

10. The memristor-based storage and computing integrated timing synchronous computing method according to claim 8, characterized in that: In the case where the set clock signal is a falling edge of the clock, before confirming the resistance of the first memristor RRAM1 based on the first control voltage and confirming the resistance of the second memristor RRAM2 based on the second control voltage, the method further includes: Setting clock signals to control the timing of synchronous computing units; The clock signal is a square wave, which switches between a low level and a high level periodically.

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