GaN P-channel device and method for manufacturing the same

Abstract

The present invention discloses a GaN-based P-channel device and a manufacturing method thereof. The manufacturing method includes: providing an epitaxial structure, the epitaxial structure including a first semiconductor layer, a second semiconductor layer, and a p-type semiconductor layer; etching a first region on the surface of the p-type semiconductor layer until the region corresponding to the back electrode in the first semiconductor layer is exposed; etching the epitaxial structure with a phosphoric acid solution at least; manufacturing a back electrode, a source electrode, and a drain electrode; etching a groove in the gate region of the p-type semiconductor layer, and repairing the groove with at least a tetramethylammonium hydroxide solution, or sequentially repairing the groove with O plasma and a KOH solution, and then manufacturing a gate that cooperates with the groove. The manufacturing method of a GaN P-channel device based on good P-type ohmic contact provided by the embodiments of the present invention can generate a lot of Ga vacancies after being etched with phosphoric acid, thereby improving the hole current intensity in the ohmic contact region.

Description

Technical Field

[0001] The present invention particularly relates to a GaN P-channel device and a manufacturing method thereof, belonging to the field of semiconductor technology. Background Art

[0002] With the development of technology, the exploration of the characteristics of Si materials has basically reached its limit, and the characteristics of Si-based power electronic devices have approached the theoretical limit that Si materials can achieve. Therefore, the third-generation semiconductors represented by GaN have become the choice for the next-generation semiconductor power device materials; GaN has a large bandgap of 3.39 eV, which means it can withstand high temperatures and high voltages; a high electron mobility of 2000 (2DEG) μ(cm 2 / V·s), indicating that the devices of it have a relatively high operating frequency; good thermal conductivity means that heat dissipation is convenient during device operation; a small dielectric constant ε r = 9, indicating a small parasitic capacitance; at the same time, the third-generation semiconductor materials also have more stable chemical properties and radiation resistance than the first-generation and second-generation materials, and can work in a more severe environment.

[0003] In the manufacturing of such GaN-based semiconductor discrete devices, due to the excellent performance of GaN, the AlGaN / GaN high electron mobility transistor (HEMT) with low RON and fast switching speed capabilities is a competitive candidate. And it plays an important role in the CMOS drive circuit switch. Nowadays, the N-channel devices in GaN CMOS are already relatively mature. However, due to problems such as low hole mobility, easy compensation of defects in GaN, and poor P-type ohmic contact characteristics in P-channel devices, it is difficult to industrialize GaN CMOS integrated circuits. Summary of the Invention

[0004] The main purpose of the present invention is to provide a GaN P-channel device and a manufacturing method thereof. By means of corrosion of defects by chemical solution water bath heating, adjustment of annealing methods, selection of annealing metals and thickness adjustment, adjustment of etching isolation, etc., after forming good ohmic contact on the basis of p-channel devices, an enhanced P-channel device is made, thereby overcoming the deficiencies in the prior art.

[0005] To achieve the foregoing invention purpose, the technical solutions adopted by the present invention include:

[0006] An embodiment of the present invention provides a manufacturing method of a GaN-based P-channel device, including:

[0007] An epitaxial structure is provided. The epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and a p-type semiconductor layer that are stacked in sequence. The first semiconductor layer and the second semiconductor layer cooperate to form a first heterostructure, and a two-dimensional electron gas is formed in the first heterostructure. The second semiconductor layer and the p-type semiconductor layer cooperate to form a second heterostructure, and a two-dimensional hole gas is formed in the second heterostructure.

[0008] Etch a first region on the surface of the p-type semiconductor layer until the region in the first semiconductor layer corresponding to the back electrode is exposed.

[0009] Corrode the epitaxial structure with a phosphoric acid solution at least to extract Ga vacancies.

[0010] Fabricate a back electrode, a source electrode, and a drain electrode. The back electrode is disposed in the region of the first semiconductor layer corresponding to the first region, and then perform rapid annealing in an oxygen-containing atmosphere.

[0011] Etch a groove in the gate region of the p-type semiconductor layer, and repair the groove with at least a tetramethylammonium hydroxide solution, or alternately repair the groove with O plasma and a KOH solution, and then fabricate a gate that cooperates with the groove.

[0012] An embodiment of the present invention also provides a GaN P-channel device obtained by the above manufacturing method.

[0013] Compared with the prior art, the advantages of the present invention include:

[0014] 1) A manufacturing method of a GaN P-channel device based on a good P-type ohmic contact provided by an embodiment of the present invention can generate a large number of Ga vacancies after phosphoric acid corrosion, thereby enhancing the hole current intensity in the ohmic region (i.e., the ohmic contact region).

[0015] 2) A manufacturing method of a GaN P-channel device based on a good P-type ohmic contact provided by an embodiment of the present invention can repair the damage of the etched isolation of the under-gate groove with a tetramethylammonium hydroxide solution (TMAH), reducing the compensation of n-type defects.

[0016] 3) A manufacturing method of a GaN P-channel device based on a good P-type ohmic contact provided by an embodiment of the present invention, the thickness of the metal Au in the ohmic metal for forming the source electrode and the drain electrode is 20 nm, which helps Ni to diffuse outward during annealing to form p-type NiO, and at the same time controlling the thickness of the metal Au therein to 20 nm is also helpful for electrical testing.

[0017] 4) The manufacturing method of a GaN P-channel device based on a good P-type ohmic contact provided by an embodiment of the present invention can overcome the Schottky barrier for realizing the p-type ohmic contact at a momentary high temperature in a way of rapid heating and cooling, and will not cause too much damage to the surface of the GaN device.

[0018] 5) The manufacturing method of a GaN P-channel device based on a good P-type ohmic contact provided by an embodiment of the present invention can adjust the compensation of two-dimensional electron gas to two-dimensional hole gas through the back electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of the manufacturing process of a GaN P-channel device based on a good P-type ohmic contact provided in a typical embodiment of the present invention;

[0020] Figure 2 is the I-V curve of the GaN P-channel device obtained in Example 1 and Comparative Example 1;

[0021] Figure 3 is the I-V curve of the GaN P-channel device obtained in Example 2;

[0022] Figure 4 is the I-V curve of the GaN P-channel device obtained in Comparative Example 2;

[0023] Figure 5a , Figure 5b are respectively the electron microscope images before and after the repair treatment of the groove under the gate without and with the repair treatment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] In view of the deficiencies in the prior art, the inventors of this case have proposed the technical solution of the present invention through long-term research and a large number of practices. The following will further explain the technical solution, its implementation process, principles, etc.

[0025] The embodiment of the present invention provides a manufacturing method of a GaN-based P-channel device, including:

[0026] providing an epitaxial structure, the epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and a p-type semiconductor layer stacked in sequence, the first semiconductor layer and the second semiconductor layer cooperate to form a first heterostructure, a two-dimensional electron gas is formed in the first heterostructure, the second semiconductor layer and the p-type semiconductor layer cooperate to form a second heterostructure, and a two-dimensional hole gas is formed in the second heterostructure;

[0027] etching a first region on the surface of the p-type semiconductor layer until the region corresponding to the back electrode in the first semiconductor layer is exposed;

[0028] Etch the epitaxial structure with a phosphoric acid solution at least to extract Ga vacancies;

[0029] Fabricate a back electrode, a source electrode, and a drain electrode. The back electrode is disposed in the region of the first semiconductor layer corresponding to the first region, and then rapidly annealed in an oxygen-containing atmosphere;

[0030] Etch a groove in the gate region of the p-type semiconductor layer, and repair the groove with at least a tetramethylammonium hydroxide solution, or sequentially repair the groove with O plasma and a KOH solution, and then fabricate a gate that mates with the groove.

[0031] In some specific embodiments, the manufacturing method further includes: etching the first semiconductor layer corresponding to the first region to form a step structure in the first semiconductor layer, and then fabricating the back electrode on the step structure.

[0032] In some specific embodiments, the step structure includes a first step surface and a second step surface sequentially arranged in a direction away from the second semiconductor layer, and the back electrode is disposed on the second step surface.

[0033] In some specific embodiments, the depth of the second step surface is 5 - 10 nm.

[0034] In some specific embodiments, the depth of... is equal to the thickness of the p-type semiconductor layer. (There seems to be a formatting or content error in this line, but translated as is for now.)

[0035] In some specific embodiments, the repair treatment includes: at least contacting the surface of the groove with a tetramethylammonium hydroxide solution at 80°C - 90°C for 5 - 15 min, or first oxidizing the surface of the groove with O plasma and then contacting the groove surface with a KOH solution at 80 - 90°C for 5 - 15 min. The O plasma can oxidize the etching defects of the groove, and at this time the KOH solution removes the oxidized defects together; thereby realizing defect repair of the groove under the gate. It should be noted that if it exceeds 15 min, the sidewall of the groove will bend downward, resulting in deterioration of device performance, while if it is less than 5 min, there will be no obvious improvement effect.

[0036] In some specific embodiments, the concentration of the tetramethylammonium hydroxide solution is 90 - 99%, and the concentration of the KOH solution is 90 - 99%.

[0037] In some specific embodiments, the etching treatment includes: at least contacting the surface of the epitaxial structure with a phosphoric acid solution at 80°C - 90°C for 0.5 h - 3 h.

[0038] In some specific embodiments, the corrosion treatment includes: first irradiating the surface of the epitaxial structure with ultraviolet light for half an hour to form oxidation defects on the surface of the epitaxial structure, and then etching the oxidation defects with the phosphoric acid.

[0039] In some specific embodiments, the concentration of the phosphoric acid solution is 40-60%.

[0040] In some specific embodiments, the manufacturing method includes: sequentially forming a first metal and a second metal arranged in a stacked manner in the source region and the drain region on the surface of the p-type semiconductor layer, and then annealing the first metal and the second metal in a mixed atmosphere containing nitrogen and oxygen at 1000 °C to convert the first metal into a p-type metal oxide, thereby forming a source or a drain.

[0041] In some specific embodiments, the annealing time is 1 s. It should be noted that the pulsed annealing time cannot exceed 1 s. If it exceeds 1 s, GaN will decompose at 1000 °C. When the annealing temperature is lower than 1000 °C, such as 900 °C, the annealing effect is difficult to meet the requirements. When the annealing temperature exceeds 100 °C, such as 1100 °C, the high temperature will cause greater damage to GaN.

[0042] In some specific embodiments, the flow rate ratio of the nitrogen and the oxygen is (8:2)-(2:8) (the total flow rate can be 10 sccm).

[0043] In some specific embodiments, the thickness ratio of the first metal and the second metal is 1:1.

[0044] In some specific embodiments, the thickness of the first metal is 5-25 nm, preferably 20 nm.

[0045] In some specific embodiments, the first metal includes nickel and the second metal includes gold.

[0046] In some specific embodiments, the manufacturing method includes: after the annealing treatment, cooling the temperature of the source or the drain to room temperature at a rate of 5-20 °C / s.

[0047] In some specific embodiments, the depth of the groove is less than the thickness of the p-type semiconductor layer;

[0048] In some specific embodiments, the thickness of the p-type semiconductor layer remaining at the bottom of the groove is 2-3 nm. If it is completely etched, the dielectric will touch the underlying N-type GaN, thereby affecting the device performance.

[0049] In some specific embodiments, the gate is a T-shaped gate.

[0050] In some specific embodiments, the gate includes a stacked Ni layer and Au layer, the Ni layer has a thickness of 50 nm, and the Au layer has a thickness of 150 nm.

[0051] In some specific embodiments, the materials of the first semiconductor layer, the second semiconductor layer, and the p-type semiconductor layer are all selected from III-V group compounds.

[0052] In some specific embodiments, the first semiconductor layer includes an AlGaN layer, the second semiconductor layer includes an unintentionally doped GaN layer, the p-type semiconductor layer includes a p-GaN layer, and the doping concentration of the p-GaN layer is 3×10 19 cm -3 , and the hole concentration after annealing activation is (1 - 3)×10 17 cm -3 .

[0053] In some specific embodiments, the manufacturing method further includes: electrically connecting the back electrode to the source electrode.

[0054] The embodiment of the present invention also provides a GaN P-channel device obtained by the manufacturing method.

[0055] The technical solution, its implementation process, and principles will be further explained below in combination with the drawings and specific implementation cases. Unless otherwise specified, the semiconductor epitaxial manufacturing processes, metal depositions, etching, annealing, testing, and other required equipment and processes used in the embodiments of the present invention can be known to those skilled in the art.

[0056] Example 1

[0057] Please refer to Figure 1 , a manufacturing method of a GaN P-channel device may include the following steps:

[0058] 1) Fabricate an epitaxial structure and perform photolithography marking on the epitaxial structure for subsequent experimental alignment: The epitaxial structure from bottom to top is a 2-μm GaN buffer layer, a 25 - 40-nm Al 0.25 Ga 0.75 N barrier layer (hereinafter simply referred to as the AlGaN layer or the AlGaN barrier layer), an 11 - 30-nm unintentionally doped GaN channel layer, and a 70-nm p-type GaN capping layer. The Al 0.25 Ga 0.75The N-barrier layer and the unintentionally doped GaN channel layer form a first heterostructure, and a two-dimensional electron gas (2DEG) is formed within the first heterostructure. The unintentionally doped GaN channel layer and the p-type GaN capping layer form a second heterostructure, and a two-dimensional hole gas (2DHG) is formed within the second heterostructure. Wherein, the doping concentration of the p-type GaN capping layer is approximately 3×10 19 cm -3 , and the hole concentration after annealing activation is approximately (1 - 3)×10 17 cm -3 ;

[0059] 2) After photolithography, selective etching is performed on the epitaxial structure. The purpose is to achieve etching isolation to cut off the connection between devices. The etching conditions are: ICP etching power is 20w, RF radio frequency power is 100w, and the etching time is 6min. In this way, the etching isolation just reaches the place where the 70nm p-GaN ends, and it cannot be over-etched. Otherwise, when the metal evaporation grows on the sidewall, it will cause the compensation of the two-dimensional electron gas or the n-type impurities in GaN to the holes;

[0060] 3) A mask is set in a device area on the surface of the epitaxial structure, and selective etching is performed on the first area not covered by the mask until 5 - 10nm inside the 40nm AlGaN barrier layer, in order to prepare for making the back electrode. The role of the back electrode is to adjust the two-dimensional electron gas (2DEG) formed by AlGaN / GaN and avoid the compensation of the two-dimensional electron gas to the two-dimensional hole gas (2DHG);

[0061] 4) The epitaxial structure is heated in a water bath with a phosphoric acid solution with a standard composition concentration of 40 - 60% at a temperature of 50 - 90°C for 0.5h - 3h. The purpose is to mainly corrode the p-GaN on the surface layer of the epitaxial structure to extract Ga vacancies. After corrosion, the p-type defects in GaN itself will be improved, which helps hole conduction;

[0062] 5) After photolithography reversal, back electrode, source, and drain metals are grown in the ohmic region (i.e., within the exposed AlGaN barrier layer), source region, and drain region to form the back electrode, source, and drain. The grown back electrode metal is Ti / Al / Ni / Au = 20 / 130 / 50 / 50 nm, and the source and drain metals are Ni / Au (i.e., a stacked Ni layer and Au layer) = 20 / 20 nm. After stripping the metal outside the electrode region, the epitaxial structure is transferred to a rapid annealing furnace. Nitrogen and oxygen are introduced into the rapid annealing furnace. Utilizing the characteristics of the rapid annealing furnace, the temperature of the epitaxial structure is rapidly raised to 1000 °C at a rate of 10 - 30 °C / s, annealed for 1 s, and then immediately cooled at a rate of 5 - 20 °C / s to complete the annealing, thereby converting the metal Ni therein to form p-type NiO. Among them, the flow ratio of N2:O2 is (8:2) - (2:8); the method of rapidly heating and cooling the ohmic contact region of p-type GaN is similar to pulsed annealing, which can overcome the Schottky barrier for realizing p-type ohmic contact at a momentary high temperature and will not cause too much damage to the surface of the GaN device because GaN will decompose above 800 °C without protection;

[0063] 6) The gate region is etched to form a groove until the remaining thickness of p-GaN is 2 - 3 nm, which can better control the two-dimensional hole gas in the channel to form an enhancement-mode device;

[0064] 7) After etching, a 95 - 99% tetramethylammonium hydroxide solution (TMAH) is used to repair the groove under the condition of water bath heating at 50 - 90 °C, and the repair time is 9 - 15 min to repair the damage caused by the etching on the groove surface; because there will be certain damage to the etched area of the p-GaN capping layer after etching, and most of these damages are n-type defects, which will compensate for holes during the conduction process;

[0065] 8) The gate metal is evaporated and grown in the trench of the gate region. The gate metal is Ni / Au = 50 / 150 nm, that is, the gate metal is a stacked Ni layer and Au layer;

[0066] 8) The source and the back electrode are connected with metal to achieve the effect of common ground.

[0067] Comparative Example 1

[0068] The manufacturing method of a GaN P-channel device in Comparative Example 1 is basically the same as that in Example 1, except that:

[0069] In step 4) of Comparative Example 1, the step of water bath heating the epitaxial structure with a phosphoric acid solution at 85 °C is omitted.

[0070] The GaN P-channel devices prepared in Example 1 and Comparative Example 1 were tested, and the test results are as follows Figure 2 shown. It can be seen from Figure 2 that the hole current of the device after phosphoric acid etching treatment has been greatly improved.

[0071] Example 2

[0072] A method for fabricating a GaN P-channel device based on a good P-type ohmic contact may include the following steps:

[0073] 1) Fabricate an epitaxial structure and perform photolithographic marking on the epitaxial structure for subsequent experimental alignment: The epitaxial structure from bottom to top is a 2-μm GaN buffer layer, a 25-40-nm Al 0.25 Ga 0.75 N barrier layer (hereinafter simply referred to as the AlGaN layer or the AlGaN barrier layer), an 11-30-nm unintentionally doped GaN channel layer, a 70-nm p-type GaN cap layer. The Al 0.25 Ga 0.75 N barrier layer and the unintentionally doped GaN channel layer form a first heterostructure, a two-dimensional electron gas (2DEG) is formed in the first heterostructure, the unintentionally doped GaN channel layer and the p-type GaN cap layer form a second heterostructure, and a two-dimensional hole gas (2DHG) is formed in the second heterostructure. Among them, the doping concentration of the p-type GaN cap layer is about 3×10 19 cm -3 , and the hole concentration after annealing activation is about (1-3)×10 17 cm -3 ;

[0074] 2) After photolithography, perform selective etching on the epitaxial structure, aiming to play the role of etching isolation. The etching conditions are: ICP etching power is 20 w, RF radio frequency power is 100 w, and the etching time is 6 min. In this way, the etching isolation just reaches the end of the 70-nm p-GaN, and it cannot be over-etched. Otherwise, when the metal evaporation grows on the sidewall, it will cause the compensation of the two-dimensional electron gas or the n-type impurities in GaN to the holes;

[0075] 3) Set a mask on the surface of the epitaxial structure and perform selective etching until it reaches 5-10 nm inside the 40-nm AlGaN barrier layer, in order to prepare for fabricating the back electrode. The role of the back electrode is to adjust the two-dimensional electron gas (2DEG) formed by AlGaN / GaN and avoid the compensation of the two-dimensional electron gas to the two-dimensional hole gas (2DHG);

[0076] 4) The epitaxial structure is heated in a water bath at 85 °C with a phosphoric acid solution of standard composition. The main purpose is to corrode the p-GaN on the surface layer of the epitaxial structure to a certain extent. After corrosion, the p-type defects in the GaN itself will be improved, which is helpful for hole conduction;

[0077] 5) After lithography reversal, the back electrode, source electrode, and drain electrode metals are grown in the ohmic region (i.e., within the exposed AlGaN barrier layer) to form the back electrode, source electrode, and drain electrode. The grown back electrode metal is Ti / A1 / Ni / Au = 20 / 130 / 50 / 50 nm, and the source and drain electrode metals are Ni / Au (i.e., a stacked Ni layer and Au layer) = 20 / 20 nm. After stripping the metal outside the electrode region, the epitaxial structure is transferred to a rapid annealing furnace. Nitrogen and oxygen are introduced into the rapid annealing furnace. Utilizing the characteristics of the rapid annealing furnace, it is rapidly heated to 550 °C at a rate of 5 °C / s, annealed for 10 min, and then cooled to room temperature at a rate of 5 - 10 °C / s to complete the annealing, thereby converting the metal Ni therein to form p-type NiO. Among them, the ratio of N2:O2 is (8:2) - (2:8); the ohmic contact region of p-type GaN is rapidly heated and cooled, similar to pulsed annealing, which can overcome the Schottky barrier for realizing p-type ohmic contact at a momentary high temperature and will not cause too much damage to the surface of the GaN device because GaN will decompose above 800 °C without protection;

[0078] 6) The gate region is etched to form a groove until the remaining thickness of the p-GaN is 2 - 3 nm, which can better control the two-dimensional hole gas in the channel to form an enhancement-mode device;

[0079] 7) The surface of the groove is repaired by using a tetramethylammonium hydroxide solution (TMAH) under the condition of water bath heating at 85 °C. The repair time is 5 - 15 min to repair the damage caused by the etching on the surface of the groove; because there will be certain damage to the etched area of the p-GaN capping layer after etching, and most of these damages are n-type defects, which will compensate for holes during the conduction process; after that;

[0080] 8) The gate metal is evaporated and grown in the trench of the gate region. The gate metal is Ni / Au = 50 / 150 nm, that is, the gate metal is a stacked Ni layer and Au layer;

[0081] 9) The source electrode and the back electrode are connected with metal to achieve the effect of common ground.

[0082] Comparative Example 2

[0083] The manufacturing method of a GaN P-channel device in Comparative Example 2 is basically the same as that in Example 2, except that:

[0084] The back electrode metal formed in step 5) is Ti / Al / Ni / Au = 20 / 130 / 50 / 50 nm, the source and drain metals are Ni / Au (i.e., a stacked Ni layer and Au layer), and the thickness of the Ni layer therein is 20 nm and the thickness of the Au layer is 100 nm.

[0085] The GaN P-channel devices prepared in Example 1 and Comparative Example 1 were tested. The I-V curve of the GaN P-channel device obtained in Example 2 is as Figure 3 shown, and the I-V curve of the GaN P-channel device obtained in Comparative Example 2 is as Figure 4 shown. From Figure 3 and Figure 4 it can be seen that when the Ni layer of the ohmic metal is too thick, it is not conducive to the formation of p-type NiO, resulting in a decrease in the hole current of the ohmic contact. Figure 3 and Figure 4 show that when the channel lengths between the source and the drain are 2, 4, 8, 12, 16, and 24 μm respectively, the longer the channel conduction length, the smaller the current and the greater the resistance. From Figure 5a and Figure 5b it can be seen that there are many burrs in the groove without repair treatment, while the surface of the groove after repair treatment is very smooth.

[0086] A method for fabricating a GaN P-channel device based on a good p-type ohmic contact provided by an embodiment of the present invention can generate a lot of Ga vacancies after phosphoric acid etching, thereby enhancing the hole current intensity in the ohmic region (i.e., the ohmic contact region); and, the damage of the epitaxial structure etch isolation can be repaired by a tetramethylammonium hydroxide solution (TMAH), reducing the compensation of n-type defects.

[0087] A method for fabricating a GaN P-channel device based on a good p-type ohmic contact provided by an embodiment of the present invention, the thickness of the metal Au in the ohmic metal forming the source and drain is 5 - 25 nm, which helps the Ni to diffuse outward during annealing to form p-type NiO. At the same time, controlling the thickness of the metal Au therein to 5 - 25 nm is also helpful for electrical testing; at the same time, the compensation of two-dimensional electron gas to two-dimensional hole gas can be adjusted through the back electrode.

[0088] A method for fabricating a GaN P-channel device based on a good p-type ohmic contact provided by an embodiment of the present invention adopts a rapid heating and cooling method, similar to pulsed annealing, which can overcome the Schottky barrier for realizing p-type ohmic contact at a momentary high temperature and will not cause too much damage to the surface of the GaN device because GaN will decompose above 800 °C without protection.

[0089] It should be understood that the above embodiments are only used to illustrate the technical concept and features of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. It is not intended to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. A manufacturing method of a GaN-based P-channel device, characterized in that, Comprising: Providing an epitaxial structure, the epitaxial structure including a first semiconductor layer, a second semiconductor layer, and a p-type semiconductor layer stacked in sequence, the p-type semiconductor layer including a p-GaN layer, the first semiconductor layer and the second semiconductor layer cooperating to form a first heterostructure, a two-dimensional electron gas being formed in the first heterostructure, the second semiconductor layer and the p-type semiconductor layer cooperating to form a second heterostructure, a two-dimensional hole gas being formed in the second heterostructure; Etching a first region on the surface of the p-type semiconductor layer until the region corresponding to the back electrode in the first semiconductor layer is exposed; At least bringing the surface of the epitaxial structure into contact with a phosphoric acid solution to perform etching treatment on the epitaxial structure to extract Ga vacancies; Fabricating a back electrode, a source electrode, and a drain electrode, the back electrode being disposed in the region corresponding to the first region in the first semiconductor layer, and then performing rapid annealing in an oxygen-containing atmosphere; Etching a groove in the gate region of the p-type semiconductor layer, and at least performing a repair treatment on the groove with a tetramethylammonium hydroxide solution, or sequentially performing an oxidation treatment on the surface of the groove with O plasma and then a repair treatment on the groove with a KOH solution, and then fabricating a gate cooperating with the groove, and electrically connecting the back electrode and the source electrode.

2. The manufacturing method according to claim 1, characterized in that, Further comprising: Etching the first semiconductor layer corresponding to the first region to form a stepped structure in the first semiconductor layer, and then fabricating the back electrode on the stepped structure.

3. The manufacturing method according to claim 2, wherein: The stepped structure includes a first step surface and a second step surface sequentially arranged in a direction away from the second semiconductor layer, and the back electrode is disposed on the second step surface.

4. The manufacturing method according to claim 3, characterized in that: The depth of the second step surface is 5 - 10 nm.

5. The manufacturing method according to claim 1, characterized in that, The repair treatment includes: at least bringing the surface of the groove into contact with a tetramethylammonium hydroxide solution at 80 - 90 °C for 5 - 15 min, or first performing an oxidation treatment on the surface of the groove with O plasma and then bringing the surface of the groove into contact with a KOH solution at 80 - 90 °C for 5 - 15 min.

6. The manufacturing method according to claim 1 or 5, characterized in that: The concentration of the tetramethylammonium hydroxide solution is 95 - 99%.

7. The manufacturing method according to claim 1, characterized in that, The etching treatment includes: at least bringing the surface of the epitaxial structure into contact with a phosphoric acid solution at 80 - 90 °C for 0.5 h - 3 h.

8. The manufacturing method according to claim 1 or 7, characterized in that: The fabrication method includes: first irradiating the surface of the epitaxial structure with ultraviolet light for half an hour to form oxidation defects on the surface of the epitaxial structure, and then etching the oxidation defects with the phosphoric acid.

9. The manufacturing method according to claim 1 or 7, characterized in that: The concentration of the phosphoric acid solution is 40 - 60%.

10. The manufacturing method according to claim 1, wherein, Comprising: Sequentially forming a first metal and a second metal stacked on the source region and the drain region on the surface of the p-type semiconductor layer respectively, and then performing an annealing treatment on the first metal and the second metal in a mixed atmosphere containing nitrogen and oxygen at 1000 °C to convert the first metal to form a p-type metal oxide, thereby forming a source electrode or a drain electrode.

11. The manufacturing method according to claim 10, characterized in that: The time of the annealing treatment is 1 s.

12. The manufacturing method according to claim 10, characterized in that: The flow ratio of the nitrogen and the oxygen is (8:2) - (2:8).

13. The manufacturing method according to claim 10, wherein: The thickness ratio of the first metal and the second metal is 1:

1.

14. The manufacturing method according to claim 10 or 13, characterized in that: The thickness of the first metal is 5 - 25 nm.

15. The manufacturing method according to claim 10, characterized in that: The first metal includes nickel, and the second metal includes gold.

16. The manufacturing method according to claim 10, characterized in that The manufacturing method described above includes: after annealing treatment, cooling the temperature of the source or drain to room temperature at a rate of 5-20 °C / s.

17. The manufacturing method according to claim 1, wherein: The depth of the groove is less than the thickness of the p-type semiconductor layer.

18. The manufacturing method according to claim 17, characterized in that: The thickness of the remaining p-type semiconductor layer at the bottom of the groove is 2-3 nm.

19. The manufacturing method according to claim 1, wherein: The gate is a T-shaped gate.

20. The manufacturing method according to claim 1 or 19, characterized in that: The gate includes a stacked Ni layer and Au layer, the thickness of the Ni layer is 50 nm, and the thickness of the Au layer is 150 nm.

21. The manufacturing method according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer are selected from III-V group compounds.

22. The manufacturing method according to claim 21, characterized in that: The first semiconductor layer includes an AlGaN layer, the second semiconductor layer includes an unintentionally doped GaN layer, and the doping concentration of the p-GaN layer is 3×10 19 cm -3 , and the hole concentration after annealing activation is (1-3)×10 17 cm -3 .

23. A GaN P-channel device obtained by the manufacturing method according to any one of claims 1-22.

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