Packaging method of stacked chips

Abstract

The application discloses a packaging method of stacked chips, which comprises the following steps: forming a first redistribution layer on a first support plate, fixing a first chip on the first redistribution layer, and forming a first plastic encapsulation layer on the first redistribution layer, wherein the first plastic encapsulation layer covers at least a side surface of the first chip; fixing a second chip on a second support plate, and forming a second plastic encapsulation layer on the second support plate, wherein the second plastic encapsulation layer covers at least a side surface of the second chip, and the first plastic encapsulation layer and the second plastic encapsulation layer are connected through an adhesive layer; forming at least one conductive member which penetrates through the second plastic encapsulation layer, the adhesive layer and the first plastic encapsulation layer and is electrically connected with the first redistribution layer; forming a second redistribution layer on a surface of the second plastic encapsulation layer which is away from the first plastic encapsulation layer, wherein the second redistribution layer is electrically connected with the at least one conductive member and a functional surface of the second chip; and removing the first support plate. In the above manner, the application can reduce warping in the process of stacking chips.

Description

Technical Field

[0001] This application belongs to the field of semiconductor packaging, and in particular relates to a packaging method for stacked chips. Background Technology

[0002] The stacking of chips and their role as a key means of increasing the functionality of electronic devices necessitate fitting more and more chips into increasingly smaller package spaces.

[0003] A key requirement in stacked chips is to reduce chip thickness. At this thickness, the chip has less rigidity, and subsequent operations on the chip (mechanical or other operations) will cause warping. Summary of the Invention

[0004] The purpose of this application is to provide a packaging method for stacked chips that can reduce warpage after packaging.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is as follows: a first redistribution layer is formed on a first support plate, and a first chip is fixed on the first redistribution layer, wherein the functional surface of the first chip faces the first redistribution layer and is electrically connected to the first redistribution layer; a first molding compound layer is formed on the first redistribution layer, at least covering the side surface of the first chip; a second chip is fixed on a second support plate, and a second molding compound layer is formed on the second support plate, at least covering the side surface of the second chip, wherein the functional surface of the second chip faces the second support plate; an adhesive layer is formed on the surface of the first molding compound layer facing away from the first support plate; an integral structure on the second support plate is stacked with an integral structure on the first support plate, and the second molding compound layer is fixedly connected to the first molding compound layer through the adhesive layer; the second support plate is removed, and at least one conductive element is formed that penetrates the second molding compound layer, the adhesive layer, and the first molding compound layer and is electrically connected to the first redistribution layer; a second redistribution layer is formed on the surface of the second molding compound layer facing away from the first molding compound layer, which is simultaneously electrically connected to at least one conductive element and the functional surface of the second chip; the first support plate is removed.

[0006] The beneficial effects are: the chip stacking method proposed in this invention first forms a first redistribution layer on a first support plate, and then fixes the first chip on the first redistribution layer. The redistribution layer is used to fan out the I / O of a single chip, thereby increasing the overall number of I / O.

[0007] Meanwhile, during the chip stacking process, on the one hand, the support plate plays a supporting role in processes such as chip encapsulation, chip bonding, and the fabrication of conductive vias; on the other hand, the second encapsulation layer is fixedly connected to the first encapsulation layer through the adhesive layer, increasing the structural strength during the packaging process, thereby preventing the overall structure from warping during the packaging process and improving the process accuracy. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0009] Figure 1 This is a schematic flowchart of one embodiment of the method for fabricating stacked chips according to this application;

[0010] Figure 2 A schematic diagram of a structure in which a first chip is placed on the surface of a first support plate;

[0011] Figure 3 This is a schematic diagram of the structure after grinding the first molding layer;

[0012] Figure 4 A schematic diagram of a structure for placing a second chip on the surface of a second support plate;

[0013] Figure 5 A schematic diagram of a structure for forming an adhesive layer on the surface of the first molding layer away from the first support plate;

[0014] Figure 6 This is a schematic diagram of the structure after the first and second chips are bonded together.

[0015] Figure 7 A schematic diagram of a structure for forming a conductive component that penetrates the second molding layer, the adhesive layer, and the first molding layer;

[0016] Figure 8 A schematic diagram of the structure forming a redistribution layer for the functional surface of the second chip;

[0017] Figure 9 A schematic diagram of a structure for bonding a third support plate to the upper surface of the second molding compound;

[0018] Figure 10 This is a schematic diagram of a structure that electrically connects the functional surface of the first chip to at least one conductive component.

[0019] Figure 11 This is a schematic flowchart of one embodiment of the method for fabricating stacked chips according to this application;

[0020] Figure 12 A schematic diagram of the structure after the first chip and the second chip are bonded together, showing the formation of a redistribution layer for the functional surface of the first chip;

[0021] Figure 13 A schematic diagram of a structure for forming a conductive component that penetrates the second molding layer, the adhesive layer, and the first molding layer;

[0022] Figure 14 A schematic diagram of the structure forming a redistribution layer for the functional surface of the second chip;

[0023] Figure 15 A schematic diagram of a structure for bonding a third support plate to the upper surface of the second molding compound;

[0024] Figure 16 A schematic diagram of a structure for forming at least one second conductive protrusion electrically connected to the first redistribution layer;

[0025] Figure 17 This is a schematic flowchart of one embodiment of the method for fabricating stacked chips according to this application;

[0026] Figure 18 A schematic diagram of the structure forming the first conductive element;

[0027] Figure 19 A schematic diagram of the structure forming the second conductive element;

[0028] Figure 20 This is a schematic diagram of the structure after the first and second chips are bonded together.

[0029] Figure 21 A schematic diagram of the structure forming a redistribution layer for the functional surface of the second chip;

[0030] Figure 22 A schematic diagram of the structure forming a redistribution layer for the first chip's functional surface;

[0031] Figure 23 A schematic diagram of a structure for stacking a third chip on a first support plate;

[0032] Figure 24 A schematic diagram of a structure for stacking a fourth chip on a first support plate;

[0033] Figure 25 This is a schematic flowchart of one embodiment of the method for fabricating stacked chips according to this application;

[0034] Figure 26 A redistribution layer is formed on the functional surface of the first chip. The first chip and the second chip are bonded together to form a first conductive component and a second conductive component. A redistribution layer is formed on the functional surface of the first chip. The second support plate is removed. Schematic diagram of the structure of the first support plate.

[0035] Figure 27 A schematic diagram of the structure of the third and fourth chips stacked on the first support plate;

[0036] Figure 28 This is a schematic diagram of the structure of one embodiment of the package of this application;

[0037] Figure 29 This is a schematic diagram of another embodiment of the package of this application;

[0038] Figure 30 This is a schematic diagram of another embodiment of the package of this application;

[0039] Figure 31 This is a schematic diagram of another embodiment of the package of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0041] Combination Figure 1 and Figure 2 In the first embodiment of this application, the method for fabricating stacked chips includes:

[0042] S10: Fix the first chip 104 on the first support plate 101, and form a first molding layer 103 on the first support plate 101 that at least covers the side of the first chip 104, wherein the functional surface of the first chip 104 faces the first support plate 101.

[0043] Specifically, the first chip 104 has pins (not shown) on its functional surface, through which signal interaction between the first chip 104 and other components can be realized.

[0044] The first chip 104 can be fixed to the first support plate 101 by adhesive bonding, or a slot can be provided on the first support plate 101, and the first chip 104 can be snapped into the slot, thereby achieving the function of fixing the first chip 104 to the first support plate 101. In summary, this application does not limit the fixing method of the first chip 104.

[0045] In this embodiment, the first support plate 101 includes a base layer 1011 and a photoresist layer 1012, which are stacked together, and the first chip 104 is fixed on the photoresist layer 1012.

[0046] Specifically, the first support plate 101 includes a base layer 1011 and a photoresist layer 1012. Subsequently, the photoresist layer 1012 can be dissolved by laser irradiation, thereby achieving efficient separation of the first chip 104 from the first support plate 101.

[0047] During the preparation process, photoresist can be coated on the substrate layer 1011, and then UV-cured to form a photoresist layer 1012 on the substrate layer 1011.

[0048] It should be noted that this application does not limit the structure of the first support plate 101. For example, the first support plate 101 can also be a glass substrate, a steel plate, or other structures.

[0049] Furthermore, when separating the first chip 104 from the first support plate 101, any other method such as thermal separation or mechanical separation can be used.

[0050] Combination Figure 2 and Figure 3 In this embodiment, the step of forming the first molding compound 103 specifically includes: forming a first molding compound 103 covering the first chip 104 on the first support plate 101; grinding the surface of the first molding compound 103 away from the first support plate 101 until the non-functional surface of the first chip 104 is exposed.

[0051] Specifically, during the preparation process, a first molding compound 103 that completely covers the first chip 104 is first formed on the first support plate 101, and then the first molding compound 103 is ground to expose the non-functional surface of the first chip 104. That is, after grinding, the surface of the first chip 104 is flush with the surface of the first molding compound 103.

[0052] The material of the first molding layer 103 may include epoxy resin, and this application does not limit the material.

[0053] The first molding layer 103 can be ground using the chemical mechanical polishing (CMP) process. Compared with the commonly used mechanical polishing, chemical mechanical polishing can make the ground surface flatter.

[0054] In this embodiment, grinding the first molding layer 103 can reduce the thickness of the final package and expose the first chip 104, thereby making the adhesive properties of the subsequent adhesive layer 110 stronger. The structure of the adhesive layer 110 can be found below.

[0055] It should be noted that in other embodiments, the first molding layer 103 may not be polished, in which case the first molding layer 103 directly covers the first chip 104.

[0056] Alternatively, in other embodiments, during the formation of the first molding compound 103, a removable adhesive film is first applied to the non-functional surface of the first chip 104, then the first chip 104 is molded, and finally the adhesive film is directly removed after molding to expose the non-functional surface of the first chip 104. In summary, this application does not impose specific limitations on the formation process of the first molding compound 103.

[0057] S11: Fix the second chip 204 on the second support plate 201, and form a second molding layer 203 on the second support plate 201 that at least covers the side of the second chip 204, wherein the functional surface of the second chip 204 faces the second support plate 201.

[0058] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure in which the second chip 204 is placed on the surface of the second support plate 201. Step S20 is the same as step S10, and you can refer to the description of step S10 above. It will not be described in detail here.

[0059] The second chip 204 can be selected as a different type of chip than the first chip 104, depending on actual needs, and there is no restriction here.

[0060] S12: An adhesive layer 110 is formed on the surface of the first molding layer 103 that is away from the first support plate 101.

[0061] Combination Figure 5 The adhesive layer 110 covers both the first chip 104 and the first molding layer 103.

[0062] In this embodiment, the step of forming the adhesive layer 110 specifically includes: applying adhesive to the surface of the first molding layer 103 away from the first support plate 101, and forming the adhesive layer 110 after the adhesive has cured.

[0063] The purpose of forming the adhesive layer 110 is twofold: firstly, to bond the first molding layer 103 and the second molding layer 203 together in the future; and secondly, to increase the strength of the structure during the encapsulation process, prevent the overall structure from warping during the encapsulation process, and improve the process accuracy.

[0064] The materials used in the adhesive include, but are not limited to, BCB adhesive (bisphenylcyclobutene), PI adhesive (polyimide), PBO poly-p-phenylene benzobisoxazole fiber, etc., and are not restricted here.

[0065] It should be noted that, in other embodiments, the adhesive layer 110 may also be a pre-prepared film layer, in which the prepared adhesive layer 110 is directly placed on the surface of the first molding layer 103 facing away from the first support plate 101 during the preparation process. In summary, this application does not impose specific limitations on the process of forming the adhesive layer 110 on the surface of the first molding layer 103 facing away from the first support plate 101.

[0066] S13: Stack the overall structure on the second support plate 201 with the overall structure on the first support plate 101, and fix the second molding layer 203 to the first molding layer 103 through the adhesive layer 110.

[0067] Combination Figure 6 After the overall structure on the second support plate 201 is aligned with the overall structure on the first support plate 101, the second molding layer 203 is fixedly connected to the first molding layer 103 through the adhesive layer 110.

[0068] S14: Remove the second support plate 201 and form at least one conductive element 106 that penetrates the second molding layer 203, the adhesive layer 110 and the first molding layer 103.

[0069] The method of removing the second support plate 201 can be the same as the method of removing the first support plate 101 described above, as detailed above, and will not be repeated here.

[0070] Combination Figure 7 In this embodiment, the step of forming at least one conductive element 106 specifically includes: forming at least one conductive through-hole 1061 that penetrates the second molding layer 203, the adhesive layer 110 and the first molding layer 103; forming conductive material in each of the at least one conductive through-hole 1061 to obtain at least one conductive element 106.

[0071] The conductive via 1061 can be fabricated using any of the following methods: laser drilling, mechanical drilling, etching, etc.

[0072] In one application scenario, conductive material is filled into the conductive through-hole 1061 to obtain the conductive component 106; in another application scenario, a layer of conductive material is electroplated on the inner wall of the conductive through-hole 1061 to obtain the conductive component 106. Alternatively, a pre-prepared conductive post can be directly placed inside the conductive through-hole 1061, and this conductive post serves as the conductive component 106.

[0073] The conductive component 106 can be made of any conductive material, including but not limited to copper, gold, aluminum, etc.

[0074] Meanwhile, the number of conductive elements 106 can be one or more, and there is no restriction here.

[0075] In this embodiment, before forming the conductive element 106, a protective film layer 202 is formed to protect the second chip 204 and prevent damage to it. This protective film layer 202 covers the second chip 204 but exposes at least a portion of the second molding compound 203. The protective film layer 202 is removed after the formation of at least one conductive element 106. That is, the second chip 204 is now covered with a protective film layer 202, then at least one conductive element 106 is formed, and then the protective film layer 202 is removed.

[0076] The protective film layer 202 can be any type of film layer, such as a PI (polyimide) film layer. After the conductive element 106 is formed, the protective film layer 202 can be removed by any method such as thermal separation, mechanical separation, or laser separation.

[0077] Of course, in other embodiments, the protective film layer 202 covering the second chip 204 may not be formed before the conductive element 106 is formed, that is, the conductive element 106 is formed directly after the second support plate 201 is removed.

[0078] S15: Electrically connect the functional surface of the second chip 204 to at least one conductive element 106.

[0079] Combination Figure 8 After the functional surface of the second chip 204 is electrically connected to the conductive element 106, signal transmission can be performed between the second chip 204 and the conductive element 106.

[0080] In this embodiment, the method of electrically connecting the second chip 204 to the conductive element 106 includes: forming a first redistribution layer 205 on the side of the second molding layer 203 away from the first molding layer 103, which is simultaneously electrically connected to the functional surface of the second chip 204 and at least one conductive element 106; and forming a plurality of first conductive protrusions 206 electrically connected to the first redistribution layer 205 on the side of the first redistribution layer 205 away from the second molding layer 203.

[0081] The first wiring layer 205 can be formed by sputtering or electroplating, etc., and this embodiment is not limited thereto. The material of the first wiring layer 205 includes, but is not limited to, copper, titanium, etc., and is not limited thereto.

[0082] The first wiring layer 205 serves to fan out the pins of the first chip 104, thereby redistributing the signal pins. The structure and formation of the first wiring layer 205 are existing technologies and will not be detailed here.

[0083] Meanwhile, the first conductive protrusion 206 serves to transmit signals for communication between the final package and the outside world.

[0084] The first conductive protrusion 206 is generally made of tin (Sn) or tin-silver (SnAg).

[0085] S16: Remove the first support plate 101 and electrically connect the functional surface of the first chip 104 to at least one conductive element 106.

[0086] Combination Figure 9 and Figure 10 Before removing the first support plate 101, a third support plate 208 can be used for temporary support. Specifically, before step S70, the method further includes: placing the third support plate 208 on the side of the second molding layer 203 away from the first molding layer 103, and then flipping the overall structure from the third support plate 208 to the first support plate 101 by 180 degrees. The third support plate 208 is removed after the functional surface of the first chip 104 is electrically connected to at least one conductive element 106.

[0087] Specifically, the third support plate 208 can serve as a temporary support to prevent the entire structure from warping after the first support plate 101 is removed.

[0088] The structure of the third support plate 208 can be the same as that of the first support plate 101, and the removal method of the third support plate 208 can also be the same as that of the first support plate 101. For details, please refer to the above-mentioned relevant content, which will not be repeated here.

[0089] It should be noted that in other embodiments, the third support plate 208 may not be provided to provide temporary support, and the first support plate 101 may be removed directly.

[0090] Combination Figure 10 The process of electrically connecting the functional surface of the first chip 104 to at least one conductive element 106 includes: forming a second redistribution layer 105 on the side of the first molding layer 103 away from the second molding layer 203, which is electrically connected to the functional surface of the first chip 104 and at least one conductive element 106; and forming a plurality of second conductive protrusions 107 on the side of the second redistribution layer 105 away from the first molding layer 103, which are electrically connected to the second redistribution layer 105.

[0091] The process of electrically connecting the functional surface of the first chip 104 to at least one conductive element 106 is basically similar to the process of electrically connecting the functional surface of the second chip 204 to at least one conductive element 106 as described above. For details, please refer to the above text, and it will not be repeated here.

[0092] In this embodiment, during the stacking of the first chip 104 and the second chip 204, the adhesive layer 110 is used to achieve a fixed connection between the first molding layer 103 and the second molding layer 203, which can increase the strength of the structure during the packaging process, prevent the overall structure from warping during the packaging process, and improve the process accuracy.

[0093] Combination Figure 11 and Figure 12 In the second embodiment of this application, the method for fabricating stacked chips includes:

[0094] S20: A first super-wiring layer 305 is formed on the first support plate 301, and the first chip 304 is fixed on the first super-wiring layer 305, wherein the functional surface of the first chip 304 faces the first super-wiring layer 305 and is electrically connected to the first super-wiring layer 305.

[0095] Specifically, the function of the first redistribution layer 305 is to fan out the pins of the first chip 304 to redistribute the signal pins.

[0096] The first wiring layer 305 can be formed by sputtering or electroplating, etc., and this embodiment is not limited thereto. The material of the first wiring layer 305 includes, but is not limited to, copper, titanium, etc. The structure and formation method of the first wiring layer 305 are prior art and will not be described in detail in this application.

[0097] Specifically, the first chip 304 has pins (not shown) on its functional surface, through which signal interaction between the first chip 304 and other components can be realized.

[0098] The first chip 304 can be fixed to the first wiring layer 305 by adhesive bonding, or a slot can be provided in the first wiring layer 305, and the first chip 304 can be snapped into the slot, thereby achieving the function of fixing the first chip 304 to the first wiring layer 305. In summary, this application does not limit the fixing method of the first chip 304.

[0099] The structure and material of the first support plate 301 can be the same as the first support plate 101 in step S10, as detailed above, and will not be repeated here. Furthermore, when separating the first redistribution layer 305 from the first support plate 301, any other method such as thermal separation or mechanical separation can be used.

[0100] S21: A first molding compound 303 is formed on the first redistribution layer 305, which at least covers the sides of the first chip 304.

[0101] Combination Figure 12In this embodiment, the step of forming the first molding compound 303 specifically includes: forming a first molding compound 303 covering the first chip 304 on the first redistribution layer 305; and grinding the surface of the first molding compound 303 away from the first support plate 301 until the non-functional surface of the first chip 304 is exposed.

[0102] Specifically, during the fabrication process, a first molding compound 303 that completely covers the first chip 304 is first formed on the first redistribution layer 305, and then the first molding compound 303 is polished to expose the non-functional surface of the first chip 304. That is, after polishing, the surface of the first chip 304 is flush with the surface of the first molding compound 303.

[0103] The grinding process and the formation process of the first molding layer 303 can be the same as the method of forming the first molding layer 103 in step S10, and will not be described again here.

[0104] S22: Fix the second chip 404 on the second support plate 401, and form a second molding layer 403 on the second support plate 401 that at least covers the side of the second chip 404, wherein the functional surface of the second chip 404 faces the second support plate 401.

[0105] Combination Figure 12 Step S22 is the same as step S11, and you can refer to the description of step S11 above, which will not be detailed here.

[0106] S23: An adhesive layer 310 is formed on the surface of the first molding layer 303 that is away from the first support plate 301.

[0107] Combination Figure 12 The adhesive layer 310 simultaneously covers the first chip 304 and the first molding layer 303.

[0108] In this embodiment, the step of forming the adhesive layer 310 specifically includes: applying adhesive to the surface of the first molding layer 303 facing away from the first support plate 301, and forming the adhesive layer 310 after the adhesive has cured.

[0109] Step S23 can be formed in the same way as step S12 to form the first adhesive layer 510, as detailed above, and will not be repeated here.

[0110] S24: Stack the overall structure on the second support plate 401 with the overall structure on the first support plate 301, and fix the second molding layer 403 to the first molding layer 303 through the adhesive layer 310.

[0111] Combination Figure 12After the overall structure on the second support plate 401 is aligned with the overall structure on the first support plate 301, the second molding layer 403 is fixedly connected to the first molding layer 303 through the adhesive layer 310.

[0112] S25: Remove the second support plate 401 and form at least one conductive element 306 that penetrates the second molding layer 403, the adhesive layer 310, the first molding layer 303 and is electrically connected to the first redistribution layer 305.

[0113] The method of removing the second support plate 401 can be the same as the method of removing the first support plate 301 described above, as detailed above, and will not be repeated here.

[0114] Combination Figure 13 In this embodiment, the step of forming at least one conductive element 306 specifically includes: forming at least one conductive via 3061 that penetrates the second molding layer 403, the adhesive layer 310 and the first molding layer 303 and is electrically connected to the first redistribution layer 305; forming conductive material in each of the at least one conductive via 3061 to obtain at least one conductive element 306.

[0115] The conductive element 306 is formed in the same way as the conductive element 106 in step S14. For details, please refer to the above embodiments, and will not be repeated here.

[0116] In this embodiment, before forming the conductive element 306, a protective film layer 402 is formed to protect the second chip 404 and prevent damage to it. This protective film layer 402 covers the second chip 404 but exposes at least a portion of the second molding compound 403. The protective film layer 402 is removed after the formation of at least one conductive element 306. That is, the second chip 404 is now covered with a protective film layer 402, then at least one conductive element 306 is formed, and then the protective film layer 402 is removed.

[0117] The protective film layer 402 can be any type of film layer, such as a PI (polyimide) film layer. After the conductive element 306 is formed, the protective film layer 402 can be removed by any method such as thermal separation, mechanical separation, or laser separation.

[0118] Of course, in other embodiments, the protective film layer 402 covering the second chip 404 may not be formed before the conductive element 306 is formed, that is, the conductive element 306 is formed directly after the second support plate 401 is removed.

[0119] S26: A second redistribution layer 405 is formed on the surface of the second molding layer 403 opposite to the first molding layer 303, which is electrically connected to the functional surface of at least one conductive element 306 and the second chip 404.

[0120] Combination Figure 14 After the functional surface of the second chip 404 is electrically connected to the conductive element 306, signal transmission can be performed between the second chip 404 and the conductive element 306.

[0121] In this embodiment, the method of electrically connecting the second chip 404 to the conductive element 306 includes: forming a second redistribution layer 405 on the side of the second molding layer 403 away from the first molding layer 303, which is simultaneously electrically connected to the functional surface of the second chip 404 and at least one conductive element 306; and forming a plurality of first conductive protrusions 406 electrically connected to the second redistribution layer 405 on the side of the second redistribution layer 405 away from the second molding layer 403.

[0122] Meanwhile, the first conductive protrusion 406 serves to transmit signals for communication between the final package and the outside world.

[0123] The first conductive bump 406 is typically made of tin (Sn) or tin-silver (SnAg). The first conductive bump 406 can be formed on the second redistribution layer 405 using reflow soldering.

[0124] S27: Remove the first support plate 301.

[0125] The removal method of the first support plate 301 can also be the same as the removal method of the second support plate 401. For details, please refer to the relevant content above, which will not be repeated here.

[0126] In this embodiment, before removing the first support plate 301, the following is also included:

[0127] A plurality of first conductive protrusions 406 electrically connected to the second wiring layer 405 are formed on the side of the second wiring layer 405 opposite to the second molding layer 403.

[0128] Combination Figure 15 and Figure 16 After removing the first support plate 301, the method further includes: forming at least one second conductive protrusion 307 electrically connected to the first rewiring layer 305 on the side of the first rewiring layer 305 away from the first molding layer 303.

[0129] After forming at least one first conductive protrusion 406 electrically connected to the second wiring layer 405 on the side of the second encapsulation layer 403 away from the second wiring layer 405, the method further includes: placing a third support plate 408 on the at least one first conductive protrusion 406, using the third support plate 408 to provide temporary support, and then flipping the overall structure from the third support plate 408 to the first support plate 301 by 180 degrees, wherein the third support plate 408 is removed after at least one second conductive protrusion 307 is obtained.

[0130] Specifically, the third support plate 408 can serve as a temporary support to prevent the entire structure from warping after the second support plate 401 is removed.

[0131] The structure of the third support plate 408 can be the same as that of the second support plate 401, and the removal method of the third support plate 408 can also be the same as that of the second support plate 401. For details, please refer to the relevant content above, which will not be repeated here.

[0132] It should be noted that in other embodiments, the third support plate 408 may not be provided to provide temporary support, and the first support plate 301 may be removed directly.

[0133] Combination Figure 16 The process of electrically connecting the functional surface of the first chip 304 to at least one conductive element 306 includes: forming a first redistribution layer 305 on the side of the first molding layer 303 away from the second molding layer 403, which is electrically connected to the functional surface of the first chip 304 and at least one conductive element 306; and forming a plurality of second conductive protrusions 307 on the side of the first redistribution layer 305 away from the first molding layer 303, which are electrically connected to the first redistribution layer 305.

[0134] In this embodiment, during the stacking of the first chip 304 and the second chip 404, the adhesive layer 310 is used to achieve a fixed connection between the first molding layer 303 and the second molding layer 403, which can increase the strength of the structure during the packaging process, prevent the overall structure from warping during the packaging process, and improve the process accuracy.

[0135] The difference between the second embodiment and the first embodiment of this application is that the second embodiment first forms a first redistribution layer 305 on the first support plate 301, and then fixes the first chip 304 on the first redistribution layer 305, while the first embodiment fixes the first chip 104 on the first support plate 101 and then forms the redistribution layer 105.

[0136] Combination Figure 17 and Figure 18 In the third embodiment of this application, the method for fabricating stacked chips includes:

[0137] S30: Fix the first chip 504 on the first support plate 501, and form a first molding layer 503 on the first support plate 501 that at least covers the side of the first chip 504, wherein the functional surface of the first chip 504 faces the first support plate 501.

[0138] The method of fixing the first chip 504 to the first support plate 501 has been described in step S10 and will not be repeated here.

[0139] Combination Figure 18In this embodiment, the step of forming the first molding compound 503 specifically includes: forming a first molding compound 503 covering the first chip 504 on the first support plate 501; and grinding the surface of the first molding compound 503 away from the first support plate 501 until the non-functional surface of the first chip 504 is exposed. The grinding process and the formation process of the first molding compound 503 can be the same as the method for forming the first molding compound 103 in step S10, and will not be described again here.

[0140] The structure and material of the first support plate 501 can be the same as those of the first support plate 101 in step S10, as detailed above, and will not be repeated here.

[0141] Step S30 is similar to step S10 above, and can be found in the relevant content above, so it will not be repeated here.

[0142] S31: Form at least one first conductive element 506 that penetrates the first molding layer 503.

[0143] Please see Figure 18 In this embodiment, the first conductive element 506 includes a first conductive post 5061 that penetrates the first molding layer 503 and a first pad 502 disposed on the side of the first molding layer 503 away from the first support plate 501 and electrically connected to the first conductive post 5061.

[0144] The position of the first conductive post 5061 corresponds to the position of the first pad 502, and the number of the first conductive posts 5061 corresponds to the number of the first pads 502.

[0145] The formation method of the first conductive post 5061 is similar to that of the conductive element 106 in step S14. For details, please refer to the above embodiments, and will not be repeated here.

[0146] It should be noted that in other embodiments, the first conductive element 506 may also be of other structures. For example, the first conductive element 506 may only include a first conductive post 5061 that penetrates the first molding layer 503. In this case, one end of the first conductive post 5061 may protrude from the surface of the first molding layer 503 away from the first support plate 501, or it may be flush with the surface of the first molding layer 503 away from the first support plate 501.

[0147] In summary, this application does not limit the structure of the first conductive element 506, as long as the first conductive element 506 can penetrate the first molding layer 503.

[0148] S32: Fix the second chip 604 on the second support plate 601, and form a second molding layer 603 on the second support plate 601 that at least covers the side of the second chip 604, wherein the functional surface of the second chip 604 faces the second support plate 601.

[0149] The process of step S32 is similar to that of step S30. Please refer to the description of step S30 above, and it will not be described in detail here.

[0150] S33: Form at least one second conductive element 606 that penetrates the second molding layer 603.

[0151] Please see Figure 19 The second conductive element 606 includes a second conductive post 6061 penetrating the second plastic encapsulation layer 603 and a connecting protrusion 602 disposed on the end of the second conductive post 6061.

[0152] The positions of the second conductive posts 6061 correspond to the positions of the connecting protrusions 602, and the number of second conductive posts 6061 corresponds to the number of connecting protrusions 602. The formation method of the second conductive posts 6061 is the same as the formation method of the conductive element 106 in step S14, as detailed in the above-described embodiment, and will not be repeated here.

[0153] It should be noted that in other embodiments, the second conductive element 606 may also have other structures. For example, the second conductive element 606 may only include a second conductive post 6061 that penetrates the second molding layer 603. In this case, one end of the second conductive post 6061 may protrude from the surface of the second molding layer 603 away from the second support plate 601, or it may be flush with the surface of the second molding layer 603 away from the second support plate 601.

[0154] In summary, this application does not limit the structure of the second conductive element 606, as long as the second conductive element 606 can penetrate the second molding layer 603.

[0155] The connecting protrusion 602 can be formed by reflow soldering or wave soldering, and the material of the connecting protrusion 602 includes, but is not limited to, tin (Sn).

[0156] S34: A first adhesive layer 510 is formed on the surface of the first molding layer 503 that is away from the first support plate 501.

[0157] Combination Figure 20 In this embodiment, the step of forming the first adhesive layer 510 specifically includes: applying adhesive to the surface of the first molding layer 503 away from the first support plate 501, and forming the first adhesive layer 510 after the adhesive has cured.

[0158] Step S34 can be performed in the same way as step S12 to form the first adhesive layer 510, as detailed above, and will not be repeated here.

[0159] S35: The overall structure on the second support plate 601 is stacked with the overall structure on the first support plate 501, and at least one second conductive element 606 is electrically connected to at least one first conductive element 506 in the first adhesive layer 510.

[0160] Specifically, after the overall structure on the second support plate 601 is stacked with the overall structure on the first support plate 501, at least one second conductive element 606 is arranged in a one-to-one correspondence with at least one first conductive element 506, and any second conductive element 606 is electrically connected to its corresponding first conductive element 506, and the connection portion of any second conductive element 606 to its corresponding first conductive element 506 is located in the first adhesive layer 510.

[0161] Combination Figure 20 In this embodiment, the step of electrically connecting the second conductive element 606 with the first conductive element 506 specifically includes: the method of electrically connecting the first conductive element 506 and the second conductive element 606 can be, for example, reflow soldering, wave soldering, etc., so that the first pad 502 and the connecting protrusion 602 are soldered in a fusion eutectic manner.

[0162] S36: Remove the second support plate 601 and electrically connect the functional surface of the second chip 604 to at least one second conductive element 606.

[0163] The method of removing the second support plate 601 can be the same as the method of removing the second support plate 201 in step S14, as detailed above, and will not be repeated here.

[0164] Combination Figure 21 In this embodiment, the step of electrically connecting the functional surface of the second chip 604 to at least one second conductive element 606 specifically includes: forming a first redistribution layer 605 on the side of the second molding layer 603 away from the first molding layer 503, which is electrically connected to both the functional surface of the second chip 604 and at least one second conductive element 606; and forming a plurality of first conductive protrusions 607 on the side of the first redistribution layer 605 away from the second molding layer 603, which are electrically connected to the first redistribution layer 605.

[0165] The method of forming the first redistribution layer 605 can be the same as the method of forming the first redistribution layer 205 in step S15 above. For details, please refer to the above text, and it will not be repeated here.

[0166] The method of forming the first conductive protrusion 607 can be the same as the method of forming the first conductive protrusion 206 in step S15 above, as detailed above, and will not be repeated here.

[0167] S37: Remove the first support plate 501 and electrically connect the functional surface of the first chip 504 to at least one first conductive element 506.

[0168] Please see Figure 22 This is a schematic diagram showing the structure of removing the first support plate 501 and electrically connecting the functional surface of the first chip 504 to at least one first conductive element 506. Step S37 can be the same as removing the first support plate 101 and electrically connecting the functional surface of the first chip 104 to at least one conductive element 106 in step S16, as detailed above, and will not be repeated here.

[0169] Please see Figure 23 In this embodiment, before step S37, the method further includes: stacking a third chip 704 on the first support plate 501, which specifically includes:

[0170] (a) A third chip 704 is fixed on a third support plate 701, and a third molding layer 703 is formed on the third support plate 701 to cover at least the side of the third chip 704, wherein the functional surface of the third chip 704 faces the third support plate 701.

[0171] The method of fixing the third chip 704 to the third support plate 701 is the same as that of fixing the first chip 104 to the first support plate 101 in step S10, and will not be described again here.

[0172] (b) Forming at least one third conductive element 706 that penetrates the third molding layer 703.

[0173] The third conductive element 706 includes a third conductive post 7061 that penetrates the third molding layer 703 and a second pad 702 disposed on the side of the third molding layer 703 away from the third support plate 701 and electrically connected to the third conductive post 7061.

[0174] The position of the third conductive post 7061 corresponds to the position of the second pad 702, and the number of the third conductive posts 7061 corresponds to the number of the second pads 702.

[0175] The formation of the third conductive element 706 can be done in the same way as the formation of the first conductive element 506 in step S31 above, as detailed above, and will not be repeated here.

[0176] However, in other embodiments, the third conductive element 706 may also be of other structures. For example, the third conductive element 706 may only include a third conductive post 7061 that penetrates the third molding layer 703. In this case, one end of the third conductive post 7061 may protrude from the surface of the third molding layer 703 away from the third support plate 701, or it may be flush with the surface of the third molding layer 703 away from the third support plate 701.

[0177] In summary, this application does not limit the structure of the third conductive element 706, as long as the third conductive element 706 can penetrate the third molding layer 703.

[0178] (c) A second adhesive layer 710 is formed on the surface of the third molding layer 703 opposite to the third support plate 701.

[0179] The process of forming the second adhesive layer 710 can be the same as that of forming the adhesive layer 110 in step S12, as detailed above, and will not be repeated here.

[0180] (d) The integral structure on the first support plate 501 and the integral structure on the third support plate 701 are stacked and disposed such that at least one first conductive protrusion 607 and at least one third conductive element 706 are electrically connected in the second adhesive layer 710.

[0181] This step is the same as step S35, as detailed above, and will not be repeated here.

[0182] The second adhesive layer 710 here has the same function as the first adhesive layer 510. It can not only bond the second molding layer 603 and the third molding layer 703 together to increase the strength of the structure during the packaging process, avoid the overall structure from warping during the packaging process, and improve the process accuracy, but also suppress the bridging phenomenon between the second pad 702 and the first conductive protrusion 607, thereby improving the yield of electrical performance.

[0183] (e) A schematic diagram of a structure in which the third support plate 701 is removed and the functional surface of the third chip 704 is electrically connected to at least one third conductive element 706.

[0184] This step is the same as step S36, as detailed above, and will not be repeated here.

[0185] In summary, please refer to Figure 24 Similarly, following the above method, after the functional surface of the third chip 704 is electrically connected to at least one third conductive element 706, a fourth chip, a fifth chip, and other chips can be stacked on the third chip 704, and finally step S37 is executed. Figure 24 The Chinese and Israeli companies explained how a fourth chip is stacked on top of a third chip.

[0186] Compared with the first embodiment of this application, where the first chip 104 and the second chip 204 are stacked to form the first conductive element 106, the step-by-step formation of the first conductive element 506 and the second conductive element 606 in this embodiment can result in a higher density of the first conductive element 506 and the second conductive element 606. As a result, the package of the same volume can include more conductive elements for electrically connecting the first chip 504 and the second chip 604, thus ensuring the overall performance of the stacked chips.

[0187] Similar to the first embodiment, in this embodiment, the first adhesive layer 510 can also bond the first molding layer 503 and the second molding layer 603 together, increasing the strength of the structure during the packaging process, preventing the overall structure from warping during the packaging process, and improving the process accuracy.

[0188] In addition, this embodiment also provides the electrical connection portion between the first conductive element 506 and the second conductive element 606 in the first adhesive layer 510, which can suppress bridging during the electrical connection process and improve product yield.

[0189] Combination Figure 25 and Figure 26 In the fourth embodiment of this application, the method for fabricating stacked chips includes:

[0190] S40: A first super-wiring layer 805 is formed on the first support plate 801, and the first chip 804 is fixed on the first super-wiring layer 805, wherein the functional surface of the first chip 804 faces the first super-wiring layer 805 and is electrically connected to the first super-wiring layer 805.

[0191] Step S40 is similar to step S20, as detailed above, and will not be repeated here.

[0192] S41: A first molding compound 803 is formed on the first redistribution layer 805, which at least covers the sides of the first chip 804.

[0193] The specific steps for forming the first molding compound 803 include: forming a first molding compound 803 covering the first chip 804 on the first redistribution layer 805; and grinding the surface of the first molding compound 803 away from the first support plate 801 until the non-functional surface of the first chip 804 is exposed.

[0194] Step S41 is similar to the formation of the first molding layer 303 in step S21 above, as detailed above, and will not be repeated here.

[0195] S42: Form a first conductive element 806 that penetrates the first molding layer 803 and is electrically connected to the first redistribution layer 805.

[0196] Please see Figure 26 The first conductive element 806 includes a first conductive post 8061 that penetrates the first molding layer 803 and a first pad 802 disposed on the side of the first molding layer 803 away from the first support plate 801 and electrically connected to the first conductive post 8061.

[0197] The step of forming the first conductive element 806 specifically includes: forming at least one first conductive through hole 8062 penetrating the first molding compound 803; filling the first conductive through hole 8062 with conductive material to obtain at least one first conductive post 8061; and forming at least one first pad 802 electrically connected to each first conductive post 8061 on the side of the first molding compound 803 away from the first support plate 801.

[0198] The first conductive through hole 8062 is perpendicular to the first support plate 801.

[0199] The first conductive post 8061 is formed in the same way as the conductive element 106 in step S14. For details, please refer to the above embodiments, and will not be repeated here.

[0200] It should be noted that in other embodiments, the first conductive element 806 may also be of other structures. For example, the first conductive element 806 may only include a first conductive post 8061 that penetrates the first molding layer 803. In this case, one end of the first conductive post 8061 may protrude from the surface of the first molding layer 803 away from the first support plate 801, or it may be flush with the surface of the first molding layer 803 away from the first support plate 801.

[0201] In summary, this application does not limit the structure of the first conductive element 806, as long as the first conductive element 806 can penetrate the first molding layer 803.

[0202] In this embodiment, before forming the conductive element 806, in order to protect the first chip 804 and prevent damage to the first chip 804, a protective film layer (not shown) is formed that covers the first chip 804 but exposes at least a portion of the first molding compound 803. The protective film layer is removed after at least one first conductive element 806 is formed.

[0203] The formation and removal of the protective film can be done in the same way as the formation and removal of the protective film 202 in step S14, as detailed above, and will not be repeated here.

[0204] S43: Fix the second chip 904 on the second support plate 901, and form a second molding layer 903 on the second support plate 901 that at least covers the side of the second chip 904, wherein the functional surface of the second chip 904 faces the second support plate 901.

[0205] The specific steps for forming the second molding compound 903 include: forming a second molding compound 903 covering the second chip 904 on the second support plate 901; and grinding the surface of the second molding compound 903 away from the second support plate 901 until the non-functional surface of the second chip 904 is exposed.

[0206] Step S43 is similar to step S22 above, as detailed above, and will not be repeated here.

[0207] S44: Forming a second conductive element 906 that penetrates the second molding layer 903.

[0208] The second conductive element 906 includes a second conductive post 9061 penetrating the second plastic encapsulation layer 903 and a connecting protrusion 902 disposed on the end of the second conductive post 9061.

[0209] Step S44 is similar to step S33 above, and can be found above for details, so it will not be repeated here.

[0210] S45: A first adhesive layer 810 is formed on the surface of the first molding layer 803 opposite to the first support plate 801.

[0211] The specific steps for forming the first adhesive layer 810 include: applying adhesive to the surface of the first molding layer 803 away from the first support plate 801, and forming the first adhesive layer 810 after the adhesive has cured.

[0212] Step S45 can be formed in the same way as step S12 to form the first adhesive layer 510, as detailed above, and will not be repeated here.

[0213] S46: The overall structure on the second support plate 901 is stacked with the overall structure on the first support plate 801, and at least one second conductive element 906 is electrically connected to at least one first conductive element 806 in the first adhesive layer 810.

[0214] Step S46 is similar to step S35 above, and can be found above for details, so it will not be repeated here.

[0215] S47: Remove the second support plate 901 and form a second redistribution layer 905 on the surface of the second molding layer 903 opposite to the first molding layer, which is electrically connected to the functional surface of at least one second conductive element 906 and the second chip 904.

[0216] The method of forming the second routing layer 905 is the same as that of forming the second routing layer 405 in step S26, as detailed above, and will not be repeated here.

[0217] S48: Remove the first support plate 801.

[0218] Step S48 can be similar to removing the first support plate 301 in step S27. For details, please refer to the relevant content above, and it will not be repeated here.

[0219] Please see Figure 26 In this embodiment, before removing the first support plate 801, the following is also included:

[0220] A plurality of first conductive protrusions 906 electrically connected to the second wiring layer 905 are formed on the side of the second wiring layer 905 opposite to the second molding layer 903.

[0221] The first conductive protrusion 906 can be formed by sputtering or electroplating, and the material of the first conductive protrusion 906 is generally tin (Sn) or tin silver (SnAg), etc., but this embodiment does not limit it.

[0222] After removing the first support plate 801, the method further includes: forming a plurality of second conductive protrusions 807 electrically connected to the first rewiring layer 805 on the side of the first rewiring layer 805 away from the first molding layer 803.

[0223] The second conductive protrusion 807 can be formed in the same way as the first conductive protrusion 906, as detailed above, and will not be repeated here.

[0224] Please see Figure 27 In this embodiment, before step S47, the method further includes: stacking a third chip 1004 on the first support plate 801, which specifically includes:

[0225] (a) A third chip 1004 is fixed on a third support plate 1001, and a third molding layer 1003 is formed on the third support plate 1001 to cover at least the side of the third chip 1004, wherein the functional surface of the third chip 1004 faces the third support plate 1001.

[0226] (b) Forming at least one third conductive element 1006 that penetrates the third molding layer 1003;

[0227] (c) A second adhesive layer 1010 is formed on the surface of the third molding layer 1003 opposite to the third support plate 1001;

[0228] (d) The integral structure on the first support plate 801 and the integral structure on the third support plate 1001 are stacked and arranged so that at least one first conductive protrusion 906 and at least one third conductive element 1006 are electrically connected in the second adhesive layer 1010.

[0229] (e) Remove the third support plate 1001 and electrically connect the functional surface of the third chip 1004 to at least one third conductive element 1006.

[0230] The stacking of the third chip 1004 is similar to the stacking of the third chip 704 in step S37. For details, please refer to the relevant content above, and it will not be repeated here.

[0231] The third conductive element 1006 includes a third conductive post 10061 that penetrates the third molding layer 1003 and a second pad 1002 disposed on the side of the third molding layer 1003 away from the third support plate 1001 and electrically connected to the third conductive post 1006.

[0232] However, in other embodiments, the third conductive element 1006 may also have other structures. For example, the third conductive element 1006 may only include a third conductive post 10061 that penetrates the third molding layer 1003. In this case, one end of the third conductive post 10061 may protrude from the surface of the third molding layer 1003 away from the third support plate 1001, or it may be flush with the surface of the third molding layer 1003 away from the third support plate 1001.

[0233] In summary, this application does not limit the structure of the third conductive element 1006, as long as the third conductive element 1006 can penetrate the third molding layer 1003.

[0234] In summary, please refer to Figure 27 Similarly, following the above method, after the functional surface of the third chip 1004 is electrically connected to at least one third conductive element 1006, a fourth chip, a fifth chip, and other chips can be stacked on the third chip 1004, and finally step S48 is executed. The figure illustrates the stacking of a fourth chip on the third chip.

[0235] Similar to the aforementioned embodiments, this embodiment utilizes the first adhesive layer 810 to achieve a fixed connection between the first molding layer 803 and the second molding layer 903, which can increase the strength of the structure during the packaging process, prevent the overall structure from warping during the packaging process, and improve the process accuracy.

[0236] The difference between the fourth and third embodiments of this application is that the first redistribution layer 805 is first formed on the first support plate 801, and then the first chip 804 is fixed on the first redistribution layer 805, while the third embodiment fixes the first chip 504 on the first support plate 501 and then forms the redistribution layer 505.

[0237] Combination Figure 28 In the fifth embodiment of this application, the structure of the package 100 includes: a first chip 1104, a first molding compound 1103, a second chip 1204, a second molding compound 1203, and a first adhesive layer 1110.

[0238] The first molding compound 1103 at least covers the sides of the first chip 1104, providing molding protection for the first chip 1104. The material of the first molding compound 1103 includes, but is not limited to, epoxy resin.

[0239] In an application scenario, such as Figure 28As shown, the two surfaces of the first molding layer 1103 are flush with the two surfaces of the first chip 1104, which facilitates the subsequent bonding of the first molding layer 1103 and the second molding layer 1203 together.

[0240] In another application scenario, the first molding layer 1103 may not be polished, in which case one surface of the first molding layer 1103 is flush with one surface of the first chip 1104.

[0241] The second chip 1204 is located on the non-functional side of the first chip 1104, and the non-functional side of the second chip 1204 faces the first chip 1104, which facilitates the subsequent formation of the second redistribution layer 1205.

[0242] The second molding layer 1203 covers at least the side of the second chip 1204.

[0243] In an application scenario, such as Figure 28 As shown, the two surfaces of the second molding layer 1203 are flush with the two surfaces of the second chip 1204.

[0244] In other application scenarios, the second molding layer 1203 may not need to be polished. In this case, one surface of the second molding layer 1203 is flush with one surface of the second chip 1204.

[0245] The first adhesive layer 1110 is disposed between the first molding layer 1103 and the second molding layer 1203 and is fixedly connected to the first molding layer 1103 and the second molding layer 1203. This facilitates the subsequent bonding of the first molding layer 1103 and the second molding layer 1203 together. On the other hand, it increases the strength of the structure during the packaging process, avoids warping of the overall structure during the packaging process, and improves the process accuracy.

[0246] The functional surfaces of the first chip 1104 and the second chip 1204 are electrically connected through at least one first conductive element 1106 that penetrates the second molding layer 1203, the first adhesive layer 1110 and the first molding layer 1103, that is, the first chip 1104 and the second chip 1204 realize the transmission of electrical signals through the first conductive element 1106.

[0247] For further reference Figure 28 The first conductive element 1106 includes a conductive post 11061 that penetrates the second molding layer 1203, the first adhesive layer 1110, and the first molding layer 1103.

[0248] In this embodiment, the step of forming at least one conductive element 1106 specifically includes: forming at least one conductive through-hole that penetrates the second molding layer 1203, the adhesive layer 1110, and the first molding layer 1103; the conductive pillar 11061 may be formed with conductive material inside the conductive through-hole, or a layer of conductive material may be electroplated on the inner wall of the conductive through-hole, or a pre-prepared conductive pillar may be placed inside the conductive through-hole, and the conductive pillar 11061 is the conductive element 1106.

[0249] The number of first conductive elements 1106 can be one or more, and there is no restriction here.

[0250] Continue reading Figure 28 The package 100 further includes a second rewiring layer 1205, a second conductive bump 1207, a first rewiring layer 1105, and a first conductive bump 1107. The second rewiring layer 1205 is disposed on the side of the second molding compound 1203 opposite to the first molding compound 1103, and is electrically connected to the functional surface of the second chip 1204 and at least one first conductive element 1106. The function of the second rewiring layer 1205 is to fan out the pins of the second chip 1204, thereby redistributing the signal pins. The material of the second rewiring layer 1205 includes, but is not limited to, copper, titanium, etc., and is not restricted herein.

[0251] At least one second conductive bump 1207 is disposed on the side of the second rewiring layer 1205 opposite to the second molding layer 1203 and is electrically connected to the second rewiring layer 1205. The function of the second conductive bump 1207 is to transmit signals for communication between the final package and the outside world. The material of the second conductive bump 1207 is generally tin (Sn) or tin-silver (SnAg).

[0252] The first redistribution layer 1105 is disposed on the side of the first molding layer 1103 away from the second molding layer 1203, and is electrically connected to the functional surface of the first chip 1104 and at least one first conductive element 1106.

[0253] At least one first conductive protrusion 1107 is disposed on the side of the first rewiring layer 1105 away from the first molding layer 1103 and is electrically connected to the first rewiring layer 1105.

[0254] The structure and function of the first wiring layer 1105 and the first conductive bump 1107 are the same as those of the second wiring layer 1205 and the second conductive bump 1207.

[0255] In this embodiment, the package 100 is prepared using the packaging methods described in Embodiments 1 and 2 above. For detailed methods, please refer to the above embodiments, which will not be repeated here.

[0256] Combination Figure 29In the sixth embodiment of this application, the structure of the package 200 includes: a first chip 1304, a first molding compound 1303, a second chip 1404, a second molding compound 1403, and a first adhesive layer 1310.

[0257] The first molding compound 1103 covers at least the sides of the first chip 1304, providing molding protection for the first chip 1304. The material of the first molding compound 1103 includes, but is not limited to, epoxy resin.

[0258] In an application scenario, such as Figure 29 As shown, the two surfaces of the first molding layer 1303 are flush with the two surfaces of the first chip 1304, which facilitates the subsequent bonding of the first molding layer 1303 and the second molding layer 1403 together.

[0259] In another application scenario, the first molding layer 1303 may not be polished, in which case one surface of the first molding layer 1303 is flush with one surface of the second chip 1404.

[0260] The second chip 1404 is located on the non-functional side of the first chip 1304, and the non-functional side of the second chip 1404 faces the first chip 1304, which facilitates the subsequent formation of the second redistribution layer 1405.

[0261] In an application scenario, such as Figure 29 As shown, the two surfaces of the second molding layer 1403 are flush with the two surfaces of the second chip 1404.

[0262] In other application scenarios, the second molding layer 1403 may not need to be polished. In this case, one surface of the second molding layer 1403 is flush with one surface of the second chip 1404.

[0263] The first adhesive layer 1310 is disposed between the first molding layer 1303 and the second molding layer 1403 and is fixedly connected to the first molding layer 1303 and the second molding layer 1403. This facilitates the subsequent bonding of the first molding layer 1303 and the second molding layer 1403 together. On the other hand, it increases the strength of the structure during the packaging process, avoids warping of the overall structure during the packaging process, and improves the process accuracy.

[0264] The first conductive element 1308 includes a first sub-conductive element 1306 penetrating the first molding compound 1303 and a second sub-conductive element 1406 penetrating the second molding compound 1403. The first sub-conductive element 1306 and the second sub-conductive element 1406 are electrically connected in the first adhesive layer 1310. This embodiment, by forming the first sub-conductive element 1306 and the second sub-conductive element 1406 in stages, allows for a higher density of the first sub-conductive element 1306 and the second sub-conductive element 1406. This results in a package of the same volume containing more conductive elements for electrically connecting the first chip 1304 and the second chip 1404, ensuring the overall performance of the stacked chips.

[0265] The first sub-conductive component 1306 includes a first conductive post 13061 penetrating the first molding layer 1303 and a first pad 1302 electrically connected to the first conductive post 13061.

[0266] The second sub-conductive component 1406 includes a second conductive post 14061 penetrating the second molding layer 1403 and a connecting protrusion 1402 electrically connected to the second conductive post 14061.

[0267] The connecting protrusion 1402 and the first pad 1302 are electrically connected in the first adhesive layer 1310, which can not only increase the strength of the structure during the packaging process and avoid the overall structure from warping during the packaging process, thus improving the process accuracy, but also suppress the bridging phenomenon during the electrical connection process and improve the product yield.

[0268] The number of first conductive elements 1308 can be one or more, and there is no restriction here.

[0269] Continue reading Figure 29 The package further includes a second rewiring layer 1405, a second conductive bump 1407, a first rewiring layer 1305, and a first conductive bump 1307.

[0270] The first redistribution layer 1305 is disposed on the side of the first molding compound 1303 opposite to the second molding compound 1403, and is electrically connected to the functional surface of the first chip 1304 and at least one first sub-conductive component 1306. The function of the first redistribution layer 1305 is to fan out the pins of the first chip 1304, thereby redistributing the signal pins. The material of the first redistribution layer 1305 includes, but is not limited to, copper, titanium, etc., and is not restricted herein.

[0271] At least one first conductive bump 1307 is disposed on the side of the first rewiring layer 1305 opposite to the first molding layer 1303 and is electrically connected to the first rewiring layer 1305. The function of the first conductive bump 1307 is to transmit signals for communication between the final package and the outside world. The material of the first conductive bump 1307 is generally tin (Sn) or tin-silver (SnAg).

[0272] The second redistribution layer 1405 is disposed on the side of the second molding layer 1403 away from the first molding layer 1303, and is electrically connected to the functional surface of the second chip 1404 and at least one second sub-conductive component 1406.

[0273] At least one second conductive protrusion 1407 is disposed on the side of the second rewiring layer 1405 away from the second molding layer 1403 and is electrically connected to the second rewiring layer 1405.

[0274] The structure and function of the second rewiring layer 1405 and the second conductive protrusion 1407 are the same as those of the first rewiring layer 1305 and the second conductive protrusion 1307.

[0275] In this embodiment, the package 200 is prepared using the packaging methods described in embodiments three and four above. For detailed methods, please refer to the above embodiments, which will not be repeated here.

[0276] Combination Figure 30 In the seventh embodiment of this application, the structure of the package 300 includes: a first chip 1304, a first molding compound 1303, a second chip 1404, a second molding compound 1403, a first adhesive layer 1310, a third chip 1504, a third molding compound 1503, and a second adhesive layer 1510.

[0277] Compared to package 200, package 300 adds a third chip 1504, a third molding layer 1503, and a second adhesive layer 1510.

[0278] The third chip 1504 is located on the functional side of the second chip 1404, and the non-functional side of the third chip 1504 faces the second chip 1404, which facilitates the subsequent formation of the third wiring layer 1505.

[0279] The third molding layer 1503 at least covers the sides of the third chip 1504, providing molding protection for the third chip 1504. The material of the third molding layer 1503 includes, but is not limited to, epoxy resin.

[0280] In an application scenario, such as Figure 30 As shown, the two surfaces of the third molding layer 1503 are flush with the two surfaces of the third chip 1504, which facilitates the subsequent bonding of the third molding layer 1503 and the second molding layer 1403 together.

[0281] In another application scenario, the third molding layer 1503 may not be polished. In this case, one surface of the third molding layer 1503 is flush with one surface of the third chip 1504.

[0282] The second adhesive layer 1510 is disposed between the third molding layer 1503 and the second redistribution layer 1405 to fix the third molding layer 1503 and the second redistribution layer 1405, thereby increasing the strength of the structure during the packaging process, preventing the overall structure from warping during the packaging process, and improving the process accuracy.

[0283] The functional surface of the third chip 1504 is connected to at least one second conductive protrusion 1407 through at least one second conductive element 1506 penetrating the third molding layer 1503.

[0284] The second conductive element 1506 includes a third conductive post 15061 that penetrates the third molding layer 1503 and a second pad 1502 that is electrically connected to the third conductive post 15061.

[0285] See Figure 30 The package 300 further includes a third wiring layer 1505 and a third conductive protrusion 1507.

[0286] The third wiring layer 1505 is disposed on the side of the third molding layer 1503 opposite to the third chip 1504, and is electrically connected to the functional surface of the third chip 1504 and at least one second conductive element 1506. The function of the third wiring layer 1505 is to fan out the pins of the third chip 1504, thereby redistributing the signal pins. The material of the third wiring layer 1505 includes, but is not limited to, copper, titanium, etc.

[0287] At least one third conductive bump 1507 is disposed on the side of the third wiring layer 1505 opposite to the third molding layer 1503 and is electrically connected to the third wiring layer 1505. The function of the third conductive bump 1507 is to transmit signals for communication between the final package and the outside world. The material of the third conductive bump 1507 is generally tin (Sn) or tin-silver (SnAg).

[0288] Please see Figure 31 After the functional surface of the third chip 1504 is electrically connected to at least one second conductive element 1506, more chips such as the fourth chip and the fifth chip can be stacked on the third chip 1504.

[0289] In this embodiment, the package 300 is prepared using the packaging methods described in embodiments three and four above. For detailed methods, please refer to the above embodiments, which will not be repeated here.

[0290] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method of packaging stacked chips, comprising: The method comprises: forming a first redistribution layer on a first support plate and fixing a first chip on the first redistribution layer, wherein a functional surface of the first chip faces the first redistribution layer and is electrically connected to the first redistribution layer; forming a first encapsulation layer on the first redistribution layer, the first encapsulation layer covering at least a side surface of the first chip; fixing a second chip on a second support plate and forming a second encapsulation layer on the second support plate, the second encapsulation layer covering at least a side surface of the second chip, wherein a functional surface of the second chip faces the second support plate; forming an adhesive layer on a surface of the first encapsulation layer away from the first support plate; stacking the structure on the second support plate and the structure on the first support plate, and fixing the second encapsulation layer to the first encapsulation layer through the adhesive layer; removing the second support plate, and forming at least one conductive member penetrating through the second encapsulation layer, the adhesive layer, the first encapsulation layer and electrically connected to the first redistribution layer; forming a second redistribution layer on a surface of the second encapsulation layer away from the first encapsulation layer, the second redistribution layer being electrically connected to at least one of the conductive member and the functional surface of the second chip; removing the first support plate.

2. The method of claim 1, wherein, Before the removing of the first support plate, the method further comprises: forming at least one first conductive bump on a side of the second redistribution layer away from the second encapsulation layer, the first conductive bump being electrically connected to the second redistribution layer. After the removing of the first support plate, the method further comprises: forming at least one second conductive bump on a side of the first redistribution layer away from the first encapsulation layer, the second conductive bump being electrically connected to the first redistribution layer.

3. The method of claim 2, wherein, After the forming of at least one first conductive bump on a side of the second redistribution layer away from the second encapsulation layer, the first conductive bump being electrically connected to the second redistribution layer, the method further comprises: placing a third support plate on the at least one first conductive bump, and then turning over the structure from the third support plate to the first support plate by 180 degrees, wherein the third support plate is removed after the forming of at least one second conductive bump.

4. The method of claim 1, wherein, The forming of an adhesive layer on a surface of the first encapsulation layer away from the first support plate comprises: applying glue on the surface of the first encapsulation layer away from the first support plate, and forming the adhesive layer after the glue is cured.

5. The method of claim 1, wherein, The forming of a first encapsulation layer on the first redistribution layer, the first encapsulation layer covering at least a side surface of the first chip comprises: forming the first encapsulation layer covering the first chip on the first redistribution layer; polishing a surface of the first encapsulation layer away from the first support plate until a non-functional surface of the first chip is exposed.

6. The method of claim 1, wherein, The forming of a second encapsulation layer on the second support plate, the second encapsulation layer covering at least a side surface of the second chip comprises: forming the second encapsulation layer covering the second chip on the second support plate; polishing a surface of the second encapsulation layer away from the second support plate until a non-functional surface of the second chip is exposed.

7. The method of claim 1, wherein, Before the forming of at least one conductive member penetrating through the second encapsulation layer, the adhesive layer and the first encapsulation layer and electrically connected to the first redistribution layer, the method further comprises: forming a protective film layer covering the second chip but exposing at least part of the second encapsulation layer, wherein the protective film layer is removed after forming the at least one conductive member.

8. The method of claim 7, wherein, The protective film is a polyimide film.

9. The method of claim 1, wherein, The step of forming the at least one conductive member penetrating through the second encapsulation layer, the adhesive layer and the first encapsulation layer to be electrically connected with the first redistribution layer includes: forming at least one conductive via penetrating through the second encapsulation layer, the adhesive layer and the first encapsulation layer; forming conductive material in the at least one conductive via respectively to obtain the at least one conductive member.

10. The method of claim 1, wherein, The first support plate includes: a base layer; a photoresist layer stacked with the base layer, wherein the first chip is fixed on the photoresist layer.

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