Semiconductor device structure and method of forming the same

Abstract

The semiconductor device structure includes a nanostructure formed over a substrate. The structure also includes a gate structure formed over and around the nanostructure. The structure further includes a spacer layer formed over the sidewalls of the gate structure above the nanostructure. The structure also includes source / drain epitaxial structures formed adjacent to the spacer layer. The structure also includes contact structures formed over the source / drain epitaxial structures, and air spacers formed between the spacer layer and the contact structures. Embodiments of this application also relate to methods for forming the semiconductor device structure.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor device structures and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or ILD structure, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements. Many integrated circuits are typically fabricated on a single semiconductor wafer, and the individual dies on the wafer are cut between the integrated circuits by sawing along scribe lines. The individual dies are typically packaged individually, for example, in multi-chip modules or other types of packages.

[0003] Recently, in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE), multi-gate devices have been introduced. One such multi-gate device is the gate-all-around transistor (GAA). GAA devices are named for their gate structure, which extends around the channel region, allowing access to the channel from two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes.

[0004] GAA devices are not immune to parasitic capacitances that can affect device performance. While existing GAA structures and fabrication methods are satisfactory in many respects, further improvements are still needed. Summary of the Invention

[0005] Some embodiments of this application provide a semiconductor device structure, including: a nanostructure formed over a substrate; a gate structure formed over and around the nanostructure; a spacer layer formed over the sidewall of the gate structure over the nanostructure; a source / drain epitaxial structure formed adjacent to the spacer layer; a contact structure formed over the source / drain epitaxial structure; and an air spacer disposed between the spacer layer and the contact structure.

[0006] Some other embodiments of this application provide a semiconductor device structure, including: a fin structure formed above a substrate; a nanostructure formed above the fin structure; a gate structure enclosing the nanostructure; a spacer layer formed above the nanostructure on the opposite side of the gate structure; a source / drain epitaxial structure formed above the opposite side of the nanostructure; a contact structure formed above the source / drain epitaxial structure; a protective layer formed above the sidewall of the contact structure; and an air spacer disposed between the spacer layer and the protective layer.

[0007] Some embodiments of this application provide a method for forming a semiconductor device structure, comprising: forming a nanostructure over a substrate; forming a gate structure around and over the nanostructure; forming a spacer layer over the opposite side of the gate structure above the nanostructure; forming a dummy layer over the sidewalls of the spacer layer; forming a contact structure next to the gate structure; removing the dummy layer to form an air spacer between the spacer layer and the contact structure; and depositing a sealing gasket layer over the gate structure, the contact structure, and the air spacer. Attached Figure Description

[0008] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0009] Figure 1 This is a perspective view of a semiconductor device structure according to some embodiments of the present disclosure.

[0010] Figures 2A-2J These are cross-sectional views of various stages in forming a semiconductor device structure according to some embodiments of the present disclosure.

[0011] Figures 3A-3C These are cross-sectional views of various stages in forming a semiconductor device structure according to some embodiments of the present disclosure.

[0012] Figures 4A-4B These are cross-sectional views of various stages in forming a semiconductor device structure according to some embodiments of the present disclosure.

[0013] Figures 5A-5C These are cross-sectional views of various stages in forming a semiconductor device structure according to some embodiments of the present disclosure.

[0014] Figure 6 This is a cross-sectional view of a semiconductor device structure according to some embodiments of the present disclosure.

[0015] Figures 7A-7F These are cross-sectional views of various stages in forming a semiconductor device structure according to some embodiments of the present disclosure. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range that takes into account variations inherent in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics related to the value, a numerical value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer with a thickness of "about 5 nm" can encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposited material layer are known by those skilled in the art to be + / - 15%. Furthermore, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Some variations of the embodiments are described. Throughout the various views and exemplary embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0020] The various components in the Gate All-Around (GAA) transistor structure described below can be patterned using any suitable method. For example, the active region and gate structure of the GAA transistor can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the active region or gate structure of the GAA transistor.

[0021] Embodiments for forming semiconductor device structures are provided. Methods for forming semiconductor device structures may include forming an air spacer between a spacer layer and a contact structure. The air spacer may be formed using a sealing gasket layer. Using an air spacer can reduce parasitic capacitance.

[0022] Figure 1 It is according to some embodiments of this disclosure for use Figure 2J The diagram shows a three-dimensional view of the semiconductor device structure 10a. The semiconductor device structure 10a is a gate-all-around (GAA) transistor structure. Figures 2A-2J These are cross-sectional views of various stages of forming a semiconductor device structure 10a according to some embodiments of the present disclosure. Figures 2A-2J It shows along Figure 1 The cross-sectional view taken from line 2-2 in the diagram.

[0023] According to some embodiments, such as Figure 1 and Figure 2AAs shown, a substrate 102 is provided. Substrate 102 can be a semiconductor wafer, such as a silicon wafer. Substrate 102 can also include other elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. Substrate 102 may include an epitaxial layer. For example, substrate 102 may be an epitaxial layer located on a bulk semiconductor. Furthermore, substrate 102 may also be a semiconductor-on-insulator (SOI). SOI substrates can be fabricated using wafer bonding processes, silicon film transfer processes, oxygen implantation isolation (SIMOX) processes, other applicable methods, or combinations thereof. Substrate 102 can be an N-type substrate. Substrate 102 can be a P-type substrate.

[0024] Next, according to some embodiments, such as Figure 1 As shown, a first semiconductor layer 104 and a second semiconductor layer 106 are alternately stacked over a substrate 102. The first semiconductor layer 104 and the second semiconductor layer 106 may comprise Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. The first semiconductor layer 104 and the second semiconductor layer 106 may be made of different materials with different etch rates. In some embodiments, the first semiconductor layer 104 comprises SiGe and the second semiconductor layer 106 comprises Si.

[0025] The first semiconductor layer 104 and the second semiconductor layer 106 may be formed by low-pressure chemical vapor deposition (LPCVD), epitaxial growth, other suitable methods, or combinations thereof. Epitaxial growth processes may include molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0026] It should be noted that, although Figure 1 The diagram shows a three-layer first semiconductor layer 104 and a three-layer second semiconductor layer 106, but the workpiece may include fewer or more first semiconductor layers 104 and second semiconductor layers 106, depending on the design of the semiconductor device structure 10a and the process of forming the structure.

[0027] Next, a hard mask layer can be formed and patterned over the first semiconductor layer 104 and the second semiconductor layer 106 (not shown). The patterned hard mask layer can be used as a mask layer to pattern the first semiconductor layer 104 and the second semiconductor layer 106 to form the fin structure 108. The patterning process can include photolithography and etching processes. The photolithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process can include dry etching or wet etching.

[0028] According to some embodiments, such as Figure 1 As shown, after forming the fin structures 108, a pad layer 110 is formed in the trenches between the fin structures 108. The pad layer 110 may be conformally formed over the substrate 102, the fin structures 108, and the hard mask layer covering the fin structures. The pad layer 110 serves to protect the fin structures 108 from damage in subsequent processes, such as annealing or etching. The pad layer 110 may be made of silicon nitride. The pad layer 110 may be formed using CVD processes, atomic layer deposition (ALD) processes, LPCVD processes, plasma-enhanced CVD (PECVD) processes, HDPCVD processes, other applicable processes, or combinations thereof.

[0029] Next, an isolation structure material 112 can be deposited over the padding layer 110 in the trenches between the fin structures 108. The isolation structure 112 can be made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-k dielectric materials. The isolation structure 112 can be deposited by a deposition process such as chemical vapor deposition (CVD), spin-coating glass, or other suitable processes.

[0030] Next, an etching process can be performed on the isolation structure 112 and the pad layer 110. The etching process can be used to remove the top of the pad layer 110 and the top of the isolation structure 112. As a result, the first semiconductor layer 104 and the second semiconductor layer 106 can be exposed, and the remaining isolation structure 112 and the pad layer 110 can surround the base of the fin structure 108. The remaining isolation structure 112 can be a shallow trench isolation (STI) structure surrounding the base of the fin structure 108. The isolation structure 112 can be configured to prevent electrical interference or crosstalk. Therefore, trenches can be formed between the fin structures 108.

[0031] Next, according to some embodiments, such as Figure 1 As shown, a dummy gate structure 114 is formed above and across the fin structure 108. The dummy gate structure 114 may include a dummy gate dielectric layer 116 and a dummy gate electrode layer 118. The dummy gate dielectric layer 116 and the dummy gate electrode layer 118 can be constructed using, for example... Figure 2A The steps shown in the diagram, namely the high-k dielectric layer and the metal gate electrode layer 140, are replaced to form a real gate structure.

[0032] The dummy gate dielectric layer 116 may include silicon oxide. Silicon oxide may be formed by an oxidation process (e.g., dry oxidation or wet oxidation), a chemical vapor deposition process, other suitable processes, or combinations thereof. Optionally, the gate dielectric layer 116 may include a high-k dielectric layer (e.g., a dielectric constant greater than 3.9), such as hafnium oxide (HfO2). Optionally, the high-k dielectric layer may include other high-k dielectrics, such as LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba,Sr)TiO3, Al2O3, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric layers can be formed using chemical vapor deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD) or metal-organic chemical vapor deposition (MOCVD)), atomic layer deposition (ALD) processes (e.g., plasma-enhanced atomic layer deposition (PEALD)), physical vapor deposition (PVD) processes (e.g., vacuum evaporation or sputtering), other applicable processes, or combinations thereof.

[0033] The dummy gate electrode layer 118 may comprise polysilicon (poly-Si), polysilicon germanium (poly-SiGe), other suitable materials, or combinations thereof. The dummy gate electrode layer 118 may be formed by chemical vapor deposition (e.g., low-pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition), physical vapor deposition (e.g., vacuum evaporation, or sputtering), other suitable processes, or combinations thereof.

[0034] Subsequently, an etching process can be performed on the dummy gate dielectric layer 116 and the dummy gate electrode layer 118 using a patterned photoresist layer as a mask (not shown) to form the dummy gate structure 114. The etching process can be a dry etching process. The dummy gate dielectric layer 116 and the dummy gate electrode layer 118 can be etched using a dry etching process. Dry etching processes may include using fluorine-based etchant gases, such as SF6, C... x F y (where x and y can be positive integers), NF3, or a combination thereof. After the etching process, the first semiconductor layer 104 and the second semiconductor layer 106 can be exposed on opposite sides of the dummy gate structure 114.

[0035] Next, according to some embodiments, such as Figure 1 and Figure 2AAs shown, a pair of spacer layers 120 are formed on opposite sidewalls of the dummy gate structure 114. The spacer layers 120 may be made of silicon oxide, silicon nitride, silicon oxynitride, and / or dielectric materials. The spacer layers 120 may be formed by chemical vapor deposition (CVD), ALD, or other suitable processes.

[0036] In such Figure 2A In some embodiments shown, each spacer layer 120 includes an inner portion 120a and an outer portion 120b. The inner portion 120a of the spacer layer 120 covers the sidewalls of the dummy gate structure 114 and the top surface of the stack of the second semiconductor layer 106 and the first semiconductor layer 104. The outer portion 120b of the spacer layer 120 is formed over the sidewalls and top surface of the inner portion 120a of the spacer layer 120. The inner portion 120a of the spacer layer 120 may include more carbon and nitrogen to avoid consumption in subsequent etching processes. The outer portion 120b of the spacer layer 120 may include more oxygen to reduce the k-value.

[0037] Subsequently, according to some embodiments, such as Figure 1 As shown, the first semiconductor layer 104 and the second semiconductor layer 106 of the fin structure 108 not covered by the dummy gate structure 114 can be removed during the etching process to form the source / drain opening 122. The etching process can be a dry etching process. Dry etching processes can include the use of fluorine-based etchant gases, such as SF6, C x F y (where x and y can be positive integers), NF3, or combinations thereof.

[0038] Next, according to some embodiments, such as Figure 1 As shown, the first semiconductor layer 104 is laterally etched from the source / drain opening 122 to form a recess 124. The outer portions of the first semiconductor layer 104 can be removed, while the inner portions of the first semiconductor layer 104 located below the dummy gate structure 114 or the spacer layer 120 can be retained. The lateral etching of the first semiconductor layer 104 can be a dry etching process, a wet etching process, or a combination thereof. After lateral etching, the sidewalls of the etched first semiconductor layer 104 may not be aligned with the sidewalls of the second semiconductor layer 106.

[0039] Next, according to some embodiments, such as Figure 2AAs shown, an internal spacer 126 is formed in the recess 124. The internal spacer 126 can provide a barrier between the subsequently formed source / drain epitaxial structure and the gate structure. The internal spacer 126 can be made of silicon oxide, silicon nitride, silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), or a combination thereof. The internal spacer 126 can be formed by a deposition process and an etch-back process. The deposition process can include CVD processes (such as LPCVD, PECVD, SACVD, or FCVD), ALD processes, another suitable method, or a combination thereof. The etch-back process can include a dry etching process or a wet etching process.

[0040] Next, according to some embodiments, such as Figure 2A As shown, a source / drain epitaxial structure 128 is formed in the source / drain opening 122. Figure 2A As shown, the source / drain epitaxial structure 128 is formed above the opposite side of the fin structure 108.

[0041] A strained material can be grown in the source / drain opening 122 using an epitaxial (epi) process to form a source / drain epitaxial structure 128. Furthermore, the lattice constant of the strained material can differ from the lattice constant of the substrate 102. The source / drain epitaxial structure 128 can include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, SiC, SiP, other suitable materials, or combinations thereof. The source / drain epitaxial structure 128 can be formed by epitaxial growth steps, such as molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), or any other suitable method. The source / drain epitaxial structure 128 can be doped with one or more dopants. For example, when the semiconductor device structure 10a is p-type, the source / drain epitaxial structure 128 may be silicon germanium (SiGe) doped with boron (B) or other suitable dopants; and when the semiconductor device structure 10a is n-type, the source / drain epitaxial structure 128 may include silicon (Si) doped with phosphorus (P) or other suitable dopants.

[0042] In such Figure 2A In some embodiments shown, the source / drain epitaxial structure 128 includes a bottom portion 128a, an edge portion 128b, and a center portion 128c. The bottom portion 128a may be formed at the bottom of the source / drain opening 122. The edge portion 128b may be formed above the bottom portion 128a in the source / drain opening 122 and above the sidewall of the second semiconductor layer 106. The center portion 128c may fill the source / drain opening 122.

[0043] The strain and dopant concentration in the bottom portion 128a, edge portion 128b, and center portion 128c of the source / drain epitaxial structure 128 can be different. For example, the strain in the bottom portion 128a can be less than the strain in the edge portion 128b, and the strain in the edge portion 128b can be less than the strain in the center portion 128. Furthermore, the dopant concentration in the bottom portion 128a can be less than the dopant concentration in the edge portion 128b, and the dopant concentration in the edge portion 128b can be less than the dopant concentration in the center portion 128.

[0044] The bottom portion 128a of the source / drain epitaxial structure 128, with its lower strain and dopant concentration, can help reduce lattice defects. The edge portion 128b of the source / drain epitaxial structure 128 can help grow the central portion 128c of the source / drain epitaxial structure 128. The central portion 128c of the source / drain epitaxial structure 128 can dominate the strain and resistance of the source / drain epitaxial structure 128.

[0045] Next, according to some embodiments, such as Figure 2A As shown, a first contact etch stop layer 130 is formed above the sidewall of the spacer layer 120. The first contact etch stop layer 130 can define an implantation region in a subsequent implantation process and also defines the size of the subsequently formed contact structure. The first contact etch stop layer 130 may include silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon carbonitride (SiOCN), other suitable materials, or combinations thereof. The first contact etch stop layer 130 can be formed by chemical vapor deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) processes (e.g., plasma-enhanced atomic layer deposition (PEALD)), physical vapor deposition (PVD) processes (e.g., vacuum evaporation or sputtering), other suitable processes, or combinations thereof.

[0046] An interlayer dielectric (ILD) structure (not shown) is formed above the first contact etch stop layer 130. The ILD structure may include multiple layers made of various dielectric materials, such as silicon oxide (SiO2). x (where x can be a positive integer), silicon dioxide (SiCO) y (where y can be a positive integer), silicon dioxide (SiNCO) z(where z can be a positive integer), silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. The ILD structure can be formed by chemical vapor deposition (CVD), spin coating, or other suitable processes.

[0047] Subsequently, a planarization process is performed on the ILD structure until the top surface (not shown) of the dummy gate structure 114 is exposed. After the planarization process, the top surface of the dummy gate structure 114 may be substantially flush with the top surface of the spacer layer 120, the first contact etch stop layer 130, and the ILD structure. The planarization process may include a polishing process, a chemical mechanical polishing (CMP) process, an etching process, other applicable processes, or a combination thereof.

[0048] Next, the dummy gate structure 114 (not shown), including the dummy gate dielectric layer 116 and the dummy gate electrode layer 118, is removed. Therefore, a gate trench is formed between the spacer layers 120 above the fin structure 108, and the second semiconductor layer 106 is exposed from the trench. The dummy gate structure 114 can be removed by a dry etching process or a wet etching process.

[0049] After forming the gate trench, the first semiconductor layer 104 is removed to form a gap (not shown) between adjacent second conductor layers 106. The removal process may include a selective etching process. According to some embodiments, the selective etching process may remove the first semiconductor layer 104 to release the second semiconductor layer 106 as a nanostructure 106 (as a channel region of the semiconductor device structure 10a).

[0050] The selective etching process for removing the first semiconductor layer 104 may include a wet etching process, a dry etching process, or a combination thereof. The selective etching process may be a plasma-free dry chemical etching process. The etchant in a dry chemical etching process may include free radicals, such as HF, NF3, NH3, H2, or a combination thereof.

[0051] According to some embodiments, such as Figure 2A As shown, after forming the gap, a gate structure 132 is formed around and above the nanostructure 106. The gate structure 132 can be a multilayer structure. Each gate structure 132 may include an interface layer 134, a high-k dielectric layer 136, a work function layer 138, and a gate electrode layer 140. The gate structure 132 surrounds the nanostructure 106, which can enhance gate control capability. The nanostructure 106 can be surrounded by and in direct contact with the interface layer 134, and the interface layer 134 can be surrounded by the high-k dielectric layer 136. In addition, the high-k dielectric layer 136 can be surrounded by the work function layer 138.

[0052] Interface layer 134 may be made of silicon oxide, and interface layer 134 may be formed by thermal oxidation. High-k dielectric layer 136 may include dielectric materials such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric layer 136 may be formed using CVD, ALD, other suitable methods, or combinations thereof.

[0053] The work function layer 138 can be made of a metallic material, and the metallic material can include N-work function metals or P-work function metals. N-work function metals can include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium-aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), silicon tantalum nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. P-work function metals can include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. The work function layer 138 can be formed using CVD, ALD, other suitable methods, or combinations thereof.

[0054] It should be noted that Figure 2A The number of power function layers 138 shown is merely an example and is not limited to this, depending on the required target power function value.

[0055] Next, the high-k dielectric layer 136, the power function layer 138, and the spacer layer 120 are recessed to form a groove (not shown) over the gate structure 132. The recessing process may include one or more etching processes, such as dry etching and / or wet etching. After the recessing process, the top surface of the spacer layer 120 is higher than the top surfaces of the high-k dielectric layer 136 and the power function layer 138.

[0056] Next, according to some embodiments, such as Figure 2A As shown, the gate electrode layer 140 is formed in a recess above the high-k dielectric layer 136 and the power function layer 138. The gate electrode layer 140 can be formed to fill the recess between the power function layers 138. The gate electrode layer 140 can also be formed to cover the top surface of the high-k dielectric layer 136 and the power function layer 138 between the spacer layers 120 for a larger bonding area of ​​the subsequently formed contact structure.

[0057] The gate electrode layer 140 may be made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. The gate electrode layer 140 may be formed using CVD, ALD, electroplating, other applicable methods, or combinations thereof.

[0058] Next, according to some embodiments, such as Figure 2A As shown, a hard mask layer 142 is formed in a recess above the gate structure 132 and the spacer 120. The hard mask layer 142 can provide isolation for subsequently formed contact structures and nearby conductive elements. The hard mask layer 142 can be made of a material that has etch selectivity relative to the subsequently formed protective layer and contact structure. More specifically, the hard mask layer 142 can have etch selectivity relative to SiN and metals. For example, the hard mask layer 142 can include semiconductor oxides, metal oxides, Si, Ge, SiGe, TiN, LaO, AlO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, LaO, ZrN, ZrAlO, TiO, TaO, ZrO, HfO, SiN, HfSi, AlON, SiO, SiC, ZnO, other suitable materials, or combinations thereof. In one embodiment, the hard mask layer 142 can be formed of a semiconductor material such as Si, Ge, or SiGe. The hard mask layer 142 can be deposited in the trench by CVD (such as HDP-CVD, PECVD, or HARP), ALD, other suitable methods, and / or combinations thereof. After depositing the hard mask layer 142, a planarization process (e.g., chemical mechanical polishing or etch-back process) can optionally be performed to remove excess dielectric material.

[0059] After depositing the hard mask layer 142, a planarization process (e.g., chemical mechanical polishing or etch-back process) may be optionally performed to remove excess dielectric material.

[0060] Next, according to some embodiments, such as Figure 2A As shown, the ILD structure above the source / drain epitaxial structure 128 can be removed, and a contact opening 144 can be formed above the source / drain epitaxial structure 128 between the gate structures 132. The contact opening 144 can be formed by an etching process such as a dry etching process or a wet etching process. Figure 2A As shown, the contact opening 144 is defined between the first contact etch stop layers 130.

[0061] Subsequently, according to some embodiments, such as Figure 2BAs shown, an implantation process 146 is performed over the source / drain epitaxial structure 128. The implantation process 146 can be a pre-amorphous implantation process, and an amorphous layer can be formed on top of the source / drain epitaxial structure 128. The subsequently formed first metal-semiconductor compound layer can be confined within the amorphous region. The implantation used in the implantation process 146 can include Si, Ge, C, Xe, other suitable implants, or combinations thereof. The implantation energy or source can be modified to achieve the desired implantation depth.

[0062] Next, according to some embodiments, such as Figure 2C As shown, the first contact etch stop layer 130 is removed, exposing the sidewalls of the spacer layer 120 and the hard mask layer 142. The first contact etch stop layer 130 can be removed by an etching process such as a dry etching process or a wet etching process.

[0063] According to some embodiments, such as Figure 2D As shown, after the first contact etch stop layer 130 is removed, a dummy layer 148 is formed over the sidewalls of the spacer layer 120 and the hard mask layer 142. The dummy layer 148 may be made of a material that has etch selectivity relative to the subsequently formed protective layer and contact structure. More specifically, the dummy layer 148 may have etch selectivity for SiN and metals. The dummy layer 148 may include semiconductor oxides, metal oxides, Si, Ge, SiGe, TiN, LaO, AlO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, LaO, ZrN, ZrAlO, TiO, TaO, ZrO, HfO, SiN, HfSi, AlON, SiO, SiC, ZnO, other suitable materials, or combinations thereof. In some embodiments, the dummy layer 148 and the hard mask 142 are made of the same material. In one embodiment, the dummy layer 148 may have the same composition as the hard mask layer 142 and may include semiconductor materials such as Si, Ge, or SiGe. The dummy layer 148 can be conformally deposited in the contact opening 144 and above the hard mask layer 142 using ALD, CVD (such as HDP-CVD, PECVD, or HARP), other suitable methods, and / or combinations thereof. Subsequently, the dummy layer 148 above the hard mask 142 and the top surface of the source / drain epitaxial structure 128 can be etched away, exposing the top surface of the hard mask 142 and the source / drain epitaxial structure 128. The dummy layer 148 can be etched using an isotropic etching process, such as a dry etching process. In some embodiments, the thickness of the dummy layer 148 is less than 10 nm, constrained by the space between the gate structures 132.

[0064] Subsequently, according to some embodiments, such as Figure 2EAs shown, a protective layer 150 is formed above the sidewalls of the dummy layer 148. The protective layer 150 can be made of semiconductor nitrides, semiconductor oxides, metal oxides, metal nitrides, other suitable materials, or combinations thereof. For example, the protective layer 150 may include silicon oxide, silicon nitride, TiN, LaO, AlO, YO, TaCN, SiOCN, SiOC, SiCN, LaO, ZrN, ZrAlO, TiO, TaO, ZrO, HfO, SiN, HfSi, AlON, SiO, SiC, or ZnO. In subsequent annealing processes, the protective layer 150 will not react with the subsequently formed metal layer. The protective layer 150 can maintain the etching process during subsequent processes to remove the dummy layer 148 and the hard mask layer 142, which might otherwise affect the gap used to reduce parasitic capacitance. In one embodiment, while the dummy layer 148 and the hard mask layer 142 are formed of semiconductor materials such as Si, Ge, or SiGe, the protective layer 150 is formed of silicon nitride, silicon oxynitride, or silicon oxide.

[0065] The protective layer 150 can be conformally deposited in the contact opening 144 and above the hard mask layer 142 using ALD, CVD (such as HDP-CVD, PECVD, or HARP), other suitable methods, and / or combinations thereof. Subsequently, the protective layer 150 above the hard mask 142 and the top surface of the source / drain epitaxial structure 128 can be etched away, exposing the hard mask 142 and the top surface of the source / drain epitaxial structure 128. The protective layer 150 can be etched using an anisotropic etching process, such as a dry etching process. In some embodiments, the total thickness of the dummy layer 148 and the protective layer 150 is related to the thickness of the contact opening 144 and the hard mask layer 142. Figure 2A The thickness of the first contact etch stop layer 130 formed in the middle is basically the same.

[0066] Next, according to some embodiments, such as Figure 2F As shown, a first silicide layer 152a can be formed over the source / drain epitaxial structure 128. The first silicide layer 152a can reduce the contact resistance between the source / drain epitaxial structure 128 and the contact structure subsequently formed over the source / drain epitaxial structure 128. The first silicide layer 152a can be made of titanium silicide (TiSi2), nickel silicide (NiSi), cobalt silicide (CoSi), or other suitable low-resistance materials. The first silicide layer 152a can also be a first metal-semiconductor compound layer 152a. The first silicide layer 152a can be formed over the source / drain epitaxial structure 128 by first forming a metal layer over it. The metal layer can react with the source / drain epitaxial structure 128 in an annealing process to produce the first silicide layer 152a. Subsequently, the unreacted metal layer can be removed in an etching process, leaving the first silicide layer 152a.

[0067] Next, according to some embodiments, such as Figure 2F As shown, the barrier layer 154 can be conformally formed above the bottom surface and sidewalls of the contact opening 144. The barrier layer 154 can be formed before the conductive material is filled into the contact opening 144 to prevent the conductive material from diffusing out. The barrier layer 154 can also be used as an adhesive or glue layer. The barrier layer 154 can also serve as a seed layer for forming the conductive material in the contact opening 144. The material of the barrier layer 154 can be TiN, Ti, TaN, Ta, other suitable materials, or combinations thereof. The barrier layer 154 can be formed by depositing the material of the barrier layer 154 using physical vapor deposition (PVD) processes (e.g., evaporation or sputtering), atomic layer deposition (ALD) processes, electroplating processes, other suitable processes, or combinations thereof.

[0068] Subsequently, according to some embodiments, such as Figure 2F As shown, a conductive material is formed in the contact opening 144 and a contact structure 156 is formed over the source / drain epitaxial structure 128. The contact structure 156 may include a barrier layer 154 and conductive material filling the contact opening 144. The conductive material may be made of metallic materials (e.g., Co, Ni, W, Ti, Ta, Cu, Al, Ru, Mo, TiN, TaN and / or combinations thereof), metal alloys, other suitable conductive materials, or combinations thereof. The conductive material may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) (e.g., evaporation or sputtering), atomic layer deposition (ALD), electroplating, other suitable processes, or combinations thereof.

[0069] Then, according to some embodiments, such as Figure 2G As shown, a planarization process, such as chemical mechanical polishing (CMP) or etching back, can be optionally performed to remove excess conductive material. The top surface of the hard mask 142 can be exposed after the planarization process. After the planarization process, the top surface of the contact structure 156 can be flush with the top surfaces of the hard mask layer 142, the dummy layer 148, and the protective layer 150.

[0070] Next, according to some embodiments, such as Figure 2HAs shown, the hard mask layer 142 and dummy layer 148 are removed, and a trench 158 is formed between the spacer layer 120 and the protective layer 150. In some embodiments, the sidewalls of the spacer layer 120 and the protective layer 150, as well as a portion of the top surface of the source / drain epitaxial structure 128, are exposed from the trench 158. Because the materials of the hard mask layer 142 and the dummy layer 148 are etch-selective relative to the materials of the contact structure 156 and the protective layer 150, the contact structure 156 and the protective layer 150 can be substantially retained after the removal of the hard mask layer 142 and the dummy layer 148. The hard mask layer 142 and the dummy layer 148 can be removed by an etching process such as a dry etching process or a wet etching process. In some embodiments, there is a height difference between the bottom surface of the trench 158 and the top surface of the gate structure 132 and the spacer layer 120.

[0071] Next, according to some embodiments, such as Figure 2I As shown, a sealing gasket layer 160 is formed over the gate structure 132 and the contact structure 156. In some embodiments, a trench 158 between the spacer layer 120 and the protective layer 150 is sealed by the sealing gasket layer 160, and an air spacer 162 is formed below the sealing gasket layer 160. In some embodiments, the sealing gasket layer 160 is conformally formed over the gate structure 132 and the contact structure 156. In some embodiments, the sealing gasket layer 160 is deposited over the air spacer 162. In some embodiments, the air spacer 162 is formed between the spacer layer 120 and the contact structure 156. In some embodiments, the air spacer 162 is formed between the protective layer 150 and the gate structure 132. In some embodiments, the top surface of the air spacer 162 is lower than the top surface of the contact structure 156. In some embodiments, the top surface of the air spacer 162 is lower than the top surface of the spacer layer 120.

[0072] The sealing liner 160 may have a low k-value and can be retained in subsequent etching processes. In some embodiments, the sealing liner 160 and the protective layer 150 are made of different materials. The air spacer 162 can help reduce parasitic capacitance. In some embodiments, the sealing liner 160 may be made of SiOCN. The silicon content in the sealing liner 160 ranges from about 30% to about 40%. The oxygen content in the sealing liner 160 ranges from about 30% to about 60%. A higher oxygen content may help reduce the k-value. However, if the oxygen content is too high, it may be difficult to retain the sealing liner 160 during subsequent etching processes. The carbon content in the sealing liner 160 ranges from about 1% to about 30%. A higher carbon content may help reduce the k-value. However, if the carbon content is too high, it may be difficult to retain the sealing liner 160 during subsequent etching processes. The nitrogen content in the sealing liner 160 ranges from about 5% to about 30%. A higher nitrogen content in the sealing gasket 160 can help retain the sealing gasket 160 in subsequent etching processes. However, if the nitrogen content is too high, the k value may be too high.

[0073] In some embodiments, the sealing gasket layer 160 and the protective layer 150 are made of the same material. Therefore, the interface between the sealing gasket layer 160 and the protective layer 150 may be difficult to observe or even unobservable.

[0074] The sealing gasket layer 160 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (e.g., evaporation or sputtering), electroplating, other suitable methods, or combinations thereof. In some embodiments, the sealing gasket layer 160 is formed by an ALD-like deposition process.

[0075] Next, according to some embodiments, such as Figure 2IAs shown, a filler film 164 is formed over a sealing gasket layer 160. The filler film 164 may be deposited over a gate structure 132 between adjacent contact structures 156. The filler film 164 may have a low k value to reduce parasitic capacitance. The filler film 164 may be made of silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxynitride, undoped silicate glass, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), low-k metal oxide, or other suitable materials, or combinations thereof. Exemplary low-k metal oxides may include porous metal oxide materials such as aluminum oxide, magnesium oxide, zinc oxide, indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). The filler film 164 may be formed by physical vapor deposition (PVD) processes (e.g., evaporation or sputtering), chemical vapor deposition (CVD), flowable CVD (FCVD) processes, spin coating processes, other suitable processes, or combinations thereof. In some embodiments, the filler film 164 is formed by a PVD-like deposition process.

[0076] Next, according to some embodiments, such as Figure 2J As shown, a planarization process is performed over the filler film 164 until the top surface of the sealing gasket layer 160 is exposed. The planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, other applicable processes, or a combination thereof.

[0077] Next, according to some embodiments, such as Figure 2J As shown, a second contact etch stop layer 166 is formed over the filler film 164 and the sealing gasket layer 160. The second contact etch stop layer 166 may have the same composition as the first contact etch stop layer 130. In some alternative embodiments, the second contact etch stop layer 166 may comprise SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, SiO, or undoped silicon. The second contact etch stop layer 166 may be formed using CVD (such as LPCVD, PECVD, HDP-CVD, HARP, and FCVD), ALD, other suitable methods, or combinations thereof.

[0078] When the hard mask layer 142 above the dummy layer 148 and the gate structure 132 is formed of the same material, a trench 158 can be formed between the protective layer 150 and the spacer layer 120 after the dummy layer 148 and the hard mask layer 142 are removed. A sealing gasket layer 160 is deposited over the trench 158, and an air spacer 162 can be formed therein. As described herein, the air spacer 162 is a sealing gap that may be filled with gaseous material present in the gap before it is sealed by the sealing gasket layer 160. In some cases where the processing chamber is under vacuum, the sealing gap (i.e., the air spacer 162) may include little or no gaseous material. By forming the air spacer 162 between the spacer layer 120 and the contact structure 156, parasitic capacitance can be reduced. Figure 2J In the illustrated embodiments, the air spacer 162 may have a width between about 1 nm and about 10 nm and a height between about 10 nm and about 30 nm. In these embodiments, the air spacer 162 may have an aspect ratio between about 3 and about 10.

[0079] Many variations and / or modifications can be made to the embodiments of this disclosure. Figures 3A-3C The semiconductor device structure 10b is formed according to some embodiments of the present disclosure. Figure 3C Cross-sectional views of each stage (shown). Some processes or devices are the same as or similar to those described in the above embodiments, and therefore will not be repeated here. In conjunction with the above... Figures 2A to 2J Compared to the described embodiments, a significant difference is that, as Figure 3A As shown, the spacer layer 120 extends higher.

[0080] In some embodiments, after the hard mask layer 142 is formed over the gate structure 132, the remaining spacer layer 120 extends further. In some embodiments, the top surface of the spacer layer 120 is substantially flush with the top surface of the hard mask layer 142.

[0081] In some embodiments, the carbon content of the spacer layer 120 in the semiconductor device structure 10b can be higher. Therefore, after a recess is formed above the gate structure 132, the material of the spacer layer 120 can be etched more slowly, and the spacer layer 120 can be higher. In these embodiments, the spacer layer 120 can be made of SiCN, SiC, other suitable materials, or combinations thereof. The carbon content of the spacer layer 120 can be increased by using a carbon-containing gas or carbon doping.

[0082] According to some embodiments, such as Figure 3B As shown, due to the higher spacer layer 120, the trench 158 is deeper after removing the hard mask layer 142 and the dummy layer 148. In other words, the trench 158 can have a greater depth than... Figure 2HThe groove 158 has a larger aspect ratio. In some embodiments, the top surface of the spacer layer 120 is substantially flush with the top surface of the contact structure 156.

[0083] Next, according to some embodiments, such as Figure 3C As shown, an air spacer 162 is formed after the sealing gasket layer 160 is formed. Because the trench 158 is deeper, the air spacer 162 can be higher. Parasitic capacitance can be further reduced with a higher air spacer 162. In some embodiments, the air spacer 162 is higher than the gate structure 132. In some embodiments, the air spacer 162 is substantially the same height as the contact plug 156. If the air spacer 162 is higher than the contact plug 156, the air spacer 162 may not be sealed during subsequent etching processes.

[0084] It should be noted that, although air spacer 162 and Figure 3C The contact plugs 156 shown are substantially the same height, but the height of the air spacer 162 is not limited to this and can be larger or smaller depending on the design of the semiconductor device structure 10b. Figure 3C In the illustrated embodiments, the air spacer 162 may have a width between about 1 nm and about 10 nm and a height between about 30 nm and about 50 nm. In these embodiments, the aspect ratio of the air spacer 162 may be between about 5 and about 30. The carbon composition of the spacer layer 120 may be modified to meet the target height of the air spacer 162.

[0085] When the hard mask layer 142 above the dummy layer 148 and the gate structure 132 is formed of the same material, a trench 158 can be formed between the protective layer 150 and the spacer layer 120 after removing the dummy layer 148 and the hard mask layer 142. A sealing gasket layer 160 is deposited above the trench 158, and an air spacer 162 can be formed therein. By forming the air spacer 162 between the spacer layer 120 and the contact structure 156, parasitic capacitance can be reduced. The height and parasitic capacitance of the air spacer 162 can be changed by altering the material hardness of the spacer layer 120.

[0086] Many variations and / or modifications can be made to the embodiments of this disclosure. Figures 4A-4B These are cross-sectional views of various stages in forming a semiconductor device structure 10c according to some embodiments of this disclosure. Some processes or devices are the same as or similar to those described in the above embodiments, and therefore these processes and devices will not be described again here. In conjunction with the above Figures 2A to 2J Compared to the described embodiments, a significant difference is that, as Figure 4A As shown, the trench 158 extends further into the source / drain epitaxial structure 128.

[0087] In some embodiments, the source / drain epitaxial structure 128 is further etched during the formation of trench 158. In some embodiments, the edge portion 128b of the source / drain epitaxial structure 128 is etched. In some embodiments, the etching process includes a dry etching process using an etchant gas based on Ar or Cl. In some embodiments, the etching process provides etch selectivity between the source / drain epitaxial structure 128 and the first silicide layer 152a. This is particularly true because both the dummy layer 148 and the hard mask layer 142 can be formed from semiconductor materials, such as the source / drain epitaxial structure 128. Therefore, the first silicide layer 152a may not be damaged, and the resistance may not increase. Furthermore, the second semiconductor layer 106 near trench 158 is also retained after the etching process.

[0088] Subsequently, an air spacer 162 is formed extending into the source / drain epitaxial structure 128. Because the total height of the air spacer 162 is greater, parasitic capacitance can be reduced. In some embodiments, the bottom surface of the air spacer 162 is shallower or has the same depth as the bottom surface of the first silicide layer 152a. If the air spacer 162 extends further into the source / drain epitaxial structure 128 than the bottom surface of the first silicide layer 152a, the parasitic capacitance may not be further reduced. Figure 4B In the illustrated embodiments, the air spacer 162 may have a width between about 1 nm and about 10 nm and a height between about 15 nm and about 35 nm. In these embodiments, the air spacer 162 may have an aspect ratio between about 3.5 and about 15.

[0089] When the dummy layer 148 and the hard mask layer 142 above the gate structure 132 are formed using the same material, a trench 158 can be formed between the protective layer 150 and the spacer layer 120 after the dummy layer 148 and the hard mask layer 142 are removed. A sealing gasket layer 160 is deposited above the trench 158, and an air spacer 162 can be formed. By forming the air spacer 162 between the spacer layer 120 and the contact structure 156, parasitic capacitance can be reduced. While allowing the air spacer 162 to extend further into the source / drain epitaxial structure 128 could further reduce parasitic capacitance, such an excessively downward extension of the air spacer 162 could disable the topmost channel region 206.

[0090] Many variations and / or modifications can be made to the embodiments of this disclosure. Figures 5A-5C The semiconductor device structure 10d is formed according to some embodiments of the present disclosure. Figure 5C Cross-sectional views of each stage (shown). Some processes or devices are the same as or similar to those described in the above embodiments, and therefore will not be repeated here. In conjunction with the above... Figures 2A to 2JCompared to the described embodiments, a significant difference is that, as Figure 5A and Figure 5B As shown, the top surface of the air spacer 162 is higher and the air spacer 162 extends further into the source / drain epitaxial structure 128. Figure 5C In the illustrated embodiments, the air spacer 162 may have a width between about 1 nm and about 10 nm and a height between about 35 nm and about 55 nm. In these embodiments, the air spacer 162 may have an aspect ratio between about 5.5 and about 3.5.

[0091] According to some embodiments, such as Figure 5A As shown, the spacer layer 120 can be made of a harder material (i.e., a slower-etching material), and the spacer layer 120 is higher when the hard mask layer 142 is formed. Subsequently, according to some embodiments, such as Figure 5B As shown, trench 158 is further etched into source / drain epitaxial structure 128. Therefore, in some embodiments, air spacer 162 is higher than gate structure 132. In some embodiments, the top surface of air spacer 162 is higher than the top surface of gate structure 132, and the bottom surface of air spacer 162 is lower than the bottom surface of gate structure 132.

[0092] According to some embodiments, such as Figure 5A As shown, by combining Figures 3A-3C and Figures 4A-4B The embodiment shown features a higher air spacer 162. Therefore, parasitic capacitance can be further reduced.

[0093] When the hard mask layer 142 above the dummy layer 148 and the gate structure 132 is formed of the same material, a trench 158 can be formed between the protective layer 150 and the spacer layer 120 after removing the dummy layer 148 and the hard mask layer 142. A sealing gasket layer 160 is deposited over the trench 158, and an air spacer 162 can be formed. By forming the air spacer 162 between the spacer layer 120 and the contact structure 156, parasitic capacitance can be reduced. Since the spacer layer 120 is made of a harder material and the source / drain epitaxial structure 128 is further etched through the trench 158, the air spacer 162 can be higher, and parasitic capacitance can be further reduced.

[0094] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 6 This is a cross-sectional view of a semiconductor device structure 10e according to some embodiments of the present disclosure. Some processes or devices are the same as or similar to those described in the above embodiments, and therefore these processes and devices will not be described again here. In conjunction with the above Figures 2A to 2J Compared to the described embodiments, a significant difference is that, as Figure 6As shown, voids 168 are formed in the filling membrane 164.

[0095] In some embodiments, the filler film 164 may be formed using a PVD-like deposition process with limited pore-filling capability, which could cause the filler film 164 to coalesce prematurely, leaving voids 168 within the filler film 164. Exemplary PVD-like deposition processes may include PVD or CVD processes. To form voids 168, the filler film 164 may be formed without using a deposition technique with good pore-filling capability, such as ALD, FCVD, spin coating, or PECVD. Voids 168 are formed over the gate structure 132 between adjacent contact structures 156. Therefore, the parasitic capacitance between adjacent contact structures 156 can be reduced by the voids 168 in the filler film 164. In some embodiments, voids 168 are formed during the formation of the filler film 164.

[0096] In some embodiments, since the void 168 is formed by the overhang of the filling membrane 164, the bottom of the void 168 is wider than the top of the void 168.

[0097] When the hard mask layer 142 above the dummy layer 148 and the gate structure 132 is formed of the same material, a trench 158 can be formed between the protective layer 150 and the spacer layer 120 after removing the dummy layer 148 and the hard mask layer 142. A sealing gasket layer 160 is deposited above the trench 158, and an air spacer 162 can be formed. By forming the air spacer 162 between the spacer layer 120 and the contact structure 156, parasitic capacitance can be reduced. A void 168 can be formed in the fill layer 164, and the parasitic capacitance between adjacent contact structures 156 can be reduced.

[0098] Many variations and / or modifications can be made to the embodiments of this disclosure. Figures 7A-7F The semiconductor device structure 10f is formed according to some embodiments of the present disclosure. Figure 7F Cross-sectional views of each stage (shown). Some processes or devices are the same as or similar to those described in the above embodiments, and therefore will not be repeated here. In conjunction with the above... Figures 2A to 2J Compared to the described embodiments, a significant difference is that, as Figure 7A As shown, the dummy layer 148 is relatively thick, and the protective layer 150 is not formed above the sidewall of the dummy layer 148.

[0099] Next, according to some embodiments, such as Figure 7BAs shown, during the silicide process, while a first silicide layer 152a is formed over the source / drain epitaxial structure 128 via an annealing step, a second silicide layer 152b is formed over the sidewalls of the dummy layer 148 when the dummy layer 148 is formed of a semiconductor material (such as Si, Ge, or SiGe). The second silicide layer 152b may be a second metal semiconductor layer 152b and may have a composition similar to or different from the first silicon layer 152a. When the dummy layer 148 and the source / drain component 128 have the same composition, the first silicide layer 152a and the second silicide layer 152b may have the same composition. When the dummy layer 148 and the source / drain component 128 have different compositions, the first silicide layer 152a and the second silicide layer 152b may have different compositions. In some embodiments, the second silicide layer 152b is formed only over the surface of the dummy layer 148 near the contact structure 156. In some embodiments, a second silicide layer 152b is formed along the sidewall of the dummy layer 148 and contacts the contact structure 156. In some embodiments, the dummy layer 148 is retained near the gate structure 132.

[0100] In some embodiments, when forming the first silicide layer 152a and the second silicide layer 152b, the annealing temperature of the annealing step in the silicide process is in the range of about 400°C to about 800°C. In some embodiments, the annealing duration of the annealing step in the silicide process for forming the first silicide layer 152a and the second silicide layer 152b is in the range of about 30 seconds to about 10 minutes.

[0101] Next, according to some embodiments, such as Figure 7C As shown, after the planarization process, a contact structure 156 is formed next to the second silicide layer 152b. The top surface of the hard mask 142 can be exposed after the planarization process. After the planarization process, the top surface of the contact structure 156 can be flush with the top surfaces of the hard mask layer 142, the dummy layer 148, and the second silicide layer 152b. The planarization process can be the same as or similar to the planarization process in the foregoing embodiments. For the sake of brevity, these processes will not be described again here.

[0102] Next, according to some embodiments, such as Figure 7D As shown, the hard mask layer 142 and the dummy layer 148 are removed, and a trench 158 is formed between the spacer layer 120 and the second silicide layer 152b. In some embodiments, the sidewalls of the spacer layer 120 and the second silicide layer 152b, as well as a portion of the top surface of the source / drain epitaxial structure 128, are exposed from the trench 158. The removal process can be the same as or similar to the removal process in the foregoing embodiments. For the sake of brevity, these processes will not be described again here.

[0103] Next, according to some embodiments, such as Figure 7EAs shown, a sealing gasket layer 160 is formed over the gate structure 132 and the contact structure 156. In some embodiments, the trench 158 is sealed, and an air spacer 162 is formed beneath the sealing gasket layer 160 between the spacer layer 120 and the second silicide layer 152b, according to some embodiments, such as Figure 7E As shown. The process for forming the sealing gasket layer 160 can be the same as or similar to the process for forming the sealing gasket layer 160 in the foregoing embodiments. For the sake of brevity, these processes will not be described again here.

[0104] Subsequently, according to some embodiments, such as Figure 7E As shown, the filler film 164 fills the spacer layer 160. Subsequently, according to some embodiments, such as... Figure 7F As shown, a planarization process is performed over the filler film 164 until the top surface of the sealing gasket layer 160 is exposed. Next, according to some embodiments, such as... Figure 7F As shown, a second contact etch stop layer 166 is formed over the filler film 164 and the sealing gasket layer 160. The process for forming the filler film 164 and the second contact etch stop layer 166 can be the same as or similar to the process for forming the filler film 164 and the second contact etch stop layer 166 in the foregoing embodiments. For the sake of brevity, these processes will not be described again here.

[0105] When the hard mask layer 142 above the dummy layer 148 and the gate structure 132 is formed of the same material, a trench 158 can be formed between the protective layer 150 and the spacer layer 120 after removing the dummy layer 148 and the hard mask layer 142. A sealing gasket layer 160 is deposited above the trench 158, and an air spacer 162 can be formed. By forming an air spacer 162 between the spacer layer 120 and the contact structure 156, parasitic capacitance can be reduced. A thicker dummy layer 148 may react during the silicide process, and a second silicide layer 152b can be formed in the dummy layer 148 close to the contact structure 156. The second silicide layer 152b can replace the protective layer 150. Therefore, the process of forming the protective layer 150 can be skipped, and production time and cost can be reduced.

[0106] As previously mentioned, forming an air spacer 162 between the spacer layer 120 and the contact structure 156 can reduce parasitic capacitance. When the dummy layer 148 adjacent to the spacer layer 120 and the hard mask layer 142 above the gate structure 132 are formed of the same material, the dummy layer 148 and the hard mask layer 142 can be removed in the same process, and the height difference between the dummy layer 148 and the hard mask layer 142 can facilitate the formation of the air spacer 162 when the sealing liner layer 160 is deposited. Figure 3CIn some embodiments shown, the height of the air spacer 162 is increased by enhancing the etch resistance of the spacer layer 120. The higher the air spacer 162, the lower the parasitic capacitance. In... Figure 4B In some embodiments shown, the air spacer 162 extends into the source / drain epitaxial structure 128, and the height of the air spacer 162 is increased. In such embodiments... Figure 5C In some embodiments shown, the etch resistance of the spacer layer 120 is increased, and the source / drain epitaxial structure 128 is further etched, resulting in a further increase in the total height of the air spacer 162. In such embodiments... Figure 6 In some embodiments shown, voids 168 are formed in the filler film 164. The parasitic capacitance between the contact structures 156 is reduced through the voids 168. Figure 7A In some embodiments shown, an air spacer is formed between spacer layer 120 and second silicide layer 152b, the second silicide layer 152b being formed along the sidewall of dummy layer 148 near contact structure 156.

[0107] Embodiments of semiconductor device structures and methods for forming the same are provided. The method for forming the semiconductor device structure may include depositing a sealing liner layer over a gate structure and a contact structure, and forming an air spacer between a spacer layer and a protective layer. Using the air spacer can reduce parasitic capacitance.

[0108] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a nanostructure formed over a substrate. The semiconductor device structure also includes a gate structure formed over and around the nanostructure. The semiconductor device structure further includes a spacer layer formed over the sidewalls of the gate structure above the nanostructure. The semiconductor device structure also includes a source / drain epitaxial structure formed adjacent to the spacer layer. The semiconductor device structure also includes a contact structure formed over the source / drain epitaxial structure, and an air spacer formed between the spacer layer and the contact structure.

[0109] In some embodiments, the semiconductor device structure further includes a protective layer formed above the sidewall of the contact structure, wherein the air spacer is disposed between the protective layer and the gate structure. In some embodiments, the semiconductor device structure further includes a sealing liner layer deposited above the gate structure and the contact structure, wherein the sealing liner layer is deposited above the air spacer. In some embodiments, the air spacer is higher than the gate structure. In some embodiments, the air spacer extends into the source / drain epitaxial structure. In some embodiments, the top surface of the air spacer is higher than the top surface of the gate structure, and the bottom surface of the air spacer is lower than the bottom surface of the gate structure. In some embodiments, the top surface of the air spacer is lower than the top surface of the contact structure.

[0110] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate. The semiconductor device structure also includes a nanostructure formed over the fin structure. The semiconductor device structure further includes a gate structure enclosing the nanostructure. The semiconductor device structure also includes a spacer layer formed over opposite sides of the gate structure above the nanostructure. The semiconductor device structure also includes source / drain epitaxial structures formed over opposite sides of the nanostructure. The semiconductor device structure also includes a contact structure formed over the source / drain epitaxial structures. The semiconductor device structure also includes a protective layer formed over the sidewalls of the contact structure, and an air spacer formed between the spacer layer and the protective layer.

[0111] In some embodiments, the semiconductor device structure further includes: a sealing gasket layer covering the gate structure and the contact structure, wherein the sealing gasket layer and the protective layer are made of different materials. In some embodiments, the top surface of the air spacer is lower than the top surface of the spacer layer. In some embodiments, the semiconductor device structure further includes: a first silicide layer formed above the source / drain epitaxial structure; a second silicide layer formed above the sidewall of the contact structure, wherein the air spacer is located between the second silicide layer and the spacer layer. In some embodiments, the semiconductor device structure further includes: a filler film formed above the gate structure between the contact structures. In some embodiments, the semiconductor device structure further includes: a void disposed in the filler film.

[0112] In some embodiments, a method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure further includes forming a nanostructure over a substrate. The method for forming a semiconductor device structure further includes forming a gate structure around and over the nanostructure. The method for forming a semiconductor device structure further includes forming a spacer layer over the opposite side of the gate structure over the nanostructure. The method for forming a semiconductor device structure further includes forming a dummy layer over the sidewalls of the spacer layer. The method for forming a semiconductor device structure further includes forming a contact structure next to the gate structure. The method for forming a semiconductor device structure further includes removing the dummy layer to form an air spacer between the spacer layer and the contact structure. The method for forming a semiconductor device structure further includes depositing a sealing gasket layer over the gate structure, the contact structure, and the air spacer.

[0113] In some embodiments, the method of forming a semiconductor device structure further includes: forming a protective layer above the sidewalls of the dummy layer before forming the contact structure, wherein the air spacer is formed between the spacer layer and the protective layer. In some embodiments, the method of forming a semiconductor device structure further includes: annealing the dummy layer to form a second silicide layer in the portion of the dummy layer that contacts the contact structure, wherein the air spacer is formed between the spacer layer and the second silicide layer. In some embodiments, the method of forming a semiconductor device structure further includes: forming a filler film above the sealing gasket layer; and depositing a contact etch stop layer above the filler film. In some embodiments, the method of forming a semiconductor device structure further includes: forming a void in the filler film above the gate structure while forming the filler film. In some embodiments, the method of forming a semiconductor device structure further includes: forming a source / drain epitaxial structure next to the nanostructure, wherein forming the dummy layer includes forming a dummy layer on the source / drain epitaxial structure, and removing the dummy layer includes etching the portion of the source / drain epitaxial structure located below the dummy layer. In some embodiments, the method for forming a semiconductor device structure further includes: forming a hard mask layer over the gate structure before forming the dummy layer; and removing the hard mask layer when removing the dummy layer.

[0114] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device structure, comprising: Nanostructures are formed on the substrate; A gate structure is formed above and around the nanostructure; A spacer layer is formed above the sidewall of the gate structure above the nanostructure; A source / drain epitaxial structure is formed adjacent to the spacer layer and includes an edge portion that intersects with the sidewall of the nanostructure and a central portion located above the edge portion, wherein the edge portion and the central portion are doped differently; A contact structure is formed above the source / drain epitaxial structure; as well as An air spacer is disposed between the spacer layer and the contact structure. The air spacer extends into the source / drain epitaxial structure, such that portions of the edge portion and the center portion are exposed in the air spacer.

2. The semiconductor device structure according to claim 1, further comprising: A protective layer is formed above the sidewall of the contact structure. The air spacer is disposed between the protective layer and the gate structure.

3. The semiconductor device structure according to claim 1, further comprising: A sealing liner layer is deposited over the gate structure and the contact structure. The sealing gasket layer is deposited above the air gap.

4. The semiconductor device structure according to claim 1, wherein, The air spacer is higher than the gate structure.

5. The semiconductor device structure according to claim 1, wherein, The doping concentration of the edge portion is less than that of the center portion.

6. The semiconductor device structure according to claim 1, wherein, The top surface of the air spacer is higher than the top surface of the gate structure, and the bottom surface of the air spacer is lower than the bottom surface of the gate structure.

7. The semiconductor device structure according to claim 1, wherein, The top surface of the air gap is lower than the top surface of the contact structure.

8. A semiconductor device structure, comprising: Fin structures are formed above the substrate; Nanostructures are formed above the fin structure; A gate structure encapsulates the nanostructure. A spacer layer is formed above the gate structure on the nanostructure; A source / drain epitaxial structure is formed above opposite sides of the nanostructure and includes an edge portion that intersects with the sidewall of the nanostructure and a central portion located above the edge portion, wherein the edge portion and the central portion are doped differently; A contact structure is formed above the source / drain epitaxial structure; A protective layer is formed above the sidewall of the contact structure; as well as An air spacer is disposed between the spacer layer and the protective layer. The air spacer extends into the source / drain epitaxial structure, such that portions of the edge portion and the center portion are exposed in the air spacer.

9. The semiconductor device structure according to claim 8, further comprising: A sealing gasket layer covers the gate structure and the contact structure. The sealing gasket layer and the protective layer are made of different materials.

10. The semiconductor device structure according to claim 8, wherein, The top surface of the air spacer is lower than the top surface of the spacer layer.

11. The semiconductor device structure according to claim 8, further comprising: A first silicide layer is formed above the source / drain epitaxial structure.

12. The semiconductor device structure according to claim 8, further comprising: A filler film is formed above the gate structure between the contact structures.

13. The semiconductor device structure according to claim 12, further comprising: The voids are provided in the filling membrane.

14. A method for forming a semiconductor device structure, comprising: Nanostructures are formed on the substrate; A source / drain epitaxial structure is formed next to the nanostructure. The source / drain epitaxial structure includes an edge portion that intersects with the sidewall of the nanostructure and a central portion located above the edge portion. The edge portion and the central portion are doped differently. A gate structure is formed around and above the nanostructure; A spacer layer is formed above the gate structure on the opposite side of the nanostructure; A pseudo-layer is formed above the sidewall of the spacer layer; A contact structure is formed next to the gate structure; Remove the dummy layer to form an air spacer between the spacer layer and the contact structure; as well as A sealing liner layer is deposited over the gate structure, the contact structure, and the air spacer. The air spacer extends into the source / drain epitaxial structure, such that portions of the edge portion and the center portion are exposed in the air spacer.

15. The method for forming a semiconductor device structure according to claim 14, further comprising: Before forming the contact structure, a protective layer is formed above the sidewalls of the dummy layer. The air spacer is formed between the spacer layer and the protective layer.

16. The method for forming a semiconductor device structure according to claim 14, further comprising: The dummy layer is annealed to form a second silicide layer in the portion of the dummy layer that contacts the contact structure. The air spacer is formed between the spacer layer and the second silicide layer.

17. The method for forming a semiconductor device structure according to claim 14, further comprising: A filling film is formed over the sealing gasket layer; as well as A contact etch stop layer is deposited over the filler film.

18. The method for forming a semiconductor device structure according to claim 17, further comprising: A void is formed in the filling film above the gate structure while the filling film is being formed.

19. The method for forming a semiconductor device structure according to claim 14, wherein, Forming the pseudo-layer includes forming a pseudo-layer on the source / drain epitaxial structure. Removing the dummy layer includes etching the portion of the source / drain epitaxial structure located below the dummy layer.

20. The method for forming a semiconductor device structure according to claim 14, further comprising: A hard mask layer is formed over the gate structure before the dummy layer is formed; as well as The hard mask layer is removed when the pseudo layer is removed.

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