Semiconductor device and method of forming the same

Abstract

A method of forming a semiconductor device includes: forming a fin structure extending along a first direction on a substrate, the fin structure having a height along a second direction transverse to the first direction, and including a stacked portion and a hard mask portion located above the stacked portion, the stacked portion including alternating channel semiconductor portions and sacrificial material portions. The sacrificial material portions include a first sacrificial material portion in contact with the hard mask portion and a second sacrificial material portion located below the first sacrificial material portion. Next, the first and second sacrificial material portions are laterally recessed, wherein the first sacrificial material portion is etched to a greater extent than the second sacrificial material portion. After removing the recessed first and sacrificial material portions to form a plurality of channel nanostructures, gate stacks are formed to surround the channel nanostructures. Embodiments of this application also disclose a semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each smaller and more complex than the last. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This shrinkage process generally provides benefits through increased production efficiency and reduced associated costs. However, this shrinkage also increases the complexity of handling and manufacturing ICs. Summary of the Invention

[0003] According to one aspect of the present application, a method of forming a semiconductor device is provided, comprising: forming a fin structure extending along a first direction over a substrate, the fin structure having a height along a second direction transverse to the first direction, and including a stacked portion and a hard mask portion located above the stacked portion, the stacked portion including alternating channel semiconductor portions and sacrificial material portions, wherein the sacrificial material portions include a first sacrificial material portion in contact with the hard mask portion and a second sacrificial material portion located below the first sacrificial material portion; laterally recessing the first sacrificial material portion and the second sacrificial material portion, wherein the first sacrificial material portion is etched to a greater extent than the second sacrificial material portion; removing the recessed first sacrificial material portion and the recessed second sacrificial material portion to form a plurality of channel nanostructures from the channel semiconductor portion; and forming a gate stack around the channel nanostructures.

[0004] According to another aspect of the embodiments of this application, a method of forming a semiconductor device is provided, comprising: forming a fin structure extending along a first direction above a substrate, the fin structure having a height along a second direction transverse to the first direction, and including a stacked portion and a hard mask portion located above the stacked portion, the stacked portion including alternating channel semiconductor portions and sacrificial semiconductor portions, wherein the sacrificial semiconductor portions include a first sacrificial semiconductor portion in contact with the hard mask portion and a second sacrificial semiconductor portion located below the first sacrificial semiconductor portion, the first sacrificial semiconductor portion having a first etch rate to an etchant, and the second sacrificial semiconductor portion having a second etch rate to an etchant lower than the first etch rate; laterally recessing the first sacrificial semiconductor portion and the second sacrificial semiconductor portion; and replacing the recessed first sacrificial semiconductor portion and the recessed second sacrificial semiconductor portion with a gate stack to surround the channel semiconductor portion.

[0005] According to another aspect of the present application, a semiconductor device is provided, comprising: a plurality of nanostructures located above a substrate and extending along a length direction; a gate stack surrounding each of the plurality of nanostructures; and source / drain components adjacent to the gate stack, wherein the gate stack includes a first portion located on the top surface of the topmost nanostructure of the plurality of nanostructures and a second portion located between adjacent nanostructures of the plurality of nanostructures, the first portion having a first dimension in the length direction, and the second portions each having a second dimension in the length direction greater than the first dimension. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a flowchart of a method for manufacturing a gate-all-around (GAA) device according to some embodiments of the present disclosure.

[0008] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A ,and Figure 18B GAA devices according to some embodiments of this disclosure are based on... Figure 1 Cross-sectional view of the manufacturing process of the method.

[0009] Figure 19This is a flowchart of a method for forming a GAA device according to an alternative embodiment of the present disclosure.

[0010] Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A ,and Figure 26B GAA devices according to some embodiments of this disclosure are based on... Figure 19 Cross-sectional view of the manufacturing process of the method. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0013] Compared to fin field-effect transistors, non-planar transistor architectures, such as nanosheet field-effect transistors (FETs), utilize semiconductor nanosheet channels with gate-all-around (GAA) technology to improve device density, power efficiency, and performance. In a GAA configuration, a nanosheet FET includes a source component, a drain component, and a nanosheet channel vertically stacked and spaced between the source and drain components. The gate surrounds the nanosheet channel and modulates the electron flow through the nanosheet channel between the source and drain components. GAA nanosheet FETs are fabricated by forming alternating layers of channel nanosheets and sacrificial nanosheets. The sacrificial nanosheets are released from the channel nanosheets before the FET device is completed.

[0014] In stacked nanosheet GAA-FETs, the nanosheets used to form the channel typically have a uniform thickness. However, the top nanosheet usually experiences a greater junction push than the bottom nanosheet because it receives more dopant during source / drain implantation to form epitaxial source / drain components. This higher dopant concentration causes the junction to further invade the gate, increasing the effective capacitance (Ceff) between the source / drain components and the gate. The increased Ceff can degrade device performance by increasing parasitic coupling and reducing switching speed.

[0015] The embodiments of this disclosure effectively reduce Ceff by implementing a topmost sacrificial semiconductor portion that is thicker than the underlying sacrificial semiconductor portion. These sacrificial semiconductor portions are then removed to free the channel nanostructure and replaced with a metal gate stack. The increased thickness of the topmost sacrificial portion results in a smaller critical dimension (CD) of the metal gate at the top of the channel nanostructure and a thicker internal spacer, both of which contribute to reducing Ceff between the source / drain components and the metal gate stack. As a result, the performance of the GAA-FET can be improved.

[0016] The GAA transistor structure described below can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0017] Figure 1 This is a flowchart of a method 100 for forming a GAA device 200 according to some embodiments of the present disclosure. Figure 2-Figure 18BThese are various views of the GAA device 200 according to some embodiments at various stages of method 100. The following refers to the GAA device 200 in conjunction with... Figure 2-Figure 18B Some embodiments of method 100 are described. Method 100 is merely an example and is not intended to limit this disclosure beyond the scope expressly referenced in the claims. Additional operations may be provided before, during, and after method 100, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of the method.

[0018] Reference Figure 1 and Figure 2 Method 100 includes operation 102, wherein an initial structure of GAA device 200 is provided. The initial structure includes a substrate 202, a stack 204 of alternating epitaxial semiconductor layers on the substrate 202, and a hard mask layer 209 on the stack 204. Figure 2 This is a cross-sectional view of a GAA device 200 after a stack of alternating epitaxial semiconductor layers 204 is formed on a substrate 202, and a hard mask layer 209 is formed on the stack 204.

[0019] Substrate 202 can be any suitable substrate and can be processed with various features. In some embodiments, substrate 202 can be a semiconductor substrate, such as a silicon substrate. In some embodiments, substrate 202 can include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 can include various doping configurations. For example, different doping profiles (e.g., n-wells, p-wells) can be formed on substrate 202 in regions designed for different device types (e.g., n-type FETs, p-type FETs). Suitable doping can include ion implantation and / or diffusion processes of dopants. Substrate 202 typically has isolation features (e.g., shallow trench isolation (STI) features) that are inserted to provide regions for different device types. Substrate 202 can include other semiconductors, such as germanium or diamond. Alternatively, substrate 202 can include compound semiconductors such as silicon carbide (SiC), gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, and / or other suitable materials. In addition, the substrate 202 may optionally include an epitaxial layer, may be strained to improve performance, may include a silicon-on-insulator structure, and / or may have other suitable enhancement features.

[0020] A stack 204 of alternating epitaxial semiconductor layers is blanket-deposited on a substrate 202. The stack 204 includes alternating sacrificial semiconductor layers 206 and channel semiconductor layers 208, with the sacrificial semiconductor layer 208 being the top layer. In some embodiments, the sacrificial semiconductor layer 206 comprises a first semiconductor material, and the channel semiconductor layer 208 comprises a second semiconductor material different from the first semiconductor material. The materials of the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 can be selected based on providing different etch selectivity. For example, in some embodiments, the first semiconductor material may comprise germanium (Ge) or silicon germanium (SiGe), while the second semiconductor material may comprise silicon (Si). In some alternative embodiments, the first semiconductor material comprises SiGe with a first Ge content, and the second semiconductor material comprises SiGe with a second Ge content lower than the first Ge content. In some embodiments, the topmost sacrificial semiconductor layer (represented as layer 206TL) is formed to have a higher etch rate than the underlying sacrificial semiconductor layer 206. For example, when the sacrificial semiconductor layer 206 is composed of SiGe, the top layer 206TL may include a higher Ge content than the underlying layers to improve the etch rate of the top layer 206TL. In various embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are substantially dopant-free (i.e., have a dopant content of less than about 1 × 10⁻⁶). 17 cm -3 (concentration of exogenous dopant).

[0021] The channel semiconductor layers 208 define the channel nanostructure for subsequently formed multi-gate devices (e.g., GAA device 200), and their thickness is selected based on device performance considerations. In some embodiments, the thickness of the channel semiconductor layers 208 ranges from about 3 nm to about 10 nm. The thickness of the channel semiconductor layers 208 can be substantially uniform.

[0022] The sacrificial semiconductor layer 206 defines a gap between adjacent channel nanostructures, within which a metal gate stack for subsequent multi-gate formation is formed. Therefore, the thickness of the sacrificial semiconductor layer 206 can be used to control the dimensions of the metal gate stack. In some embodiments, each sacrificial semiconductor layer 206 has the same thickness. In other embodiments, the thickness T1 of the topmost sacrificial semiconductor layer 206TL is greater than the thickness T2 of the lower sacrificial semiconductor layer 206. The thickness of the lower sacrificial semiconductor layer 206 can be substantially uniform. In some embodiments, the thickness T1 of the topmost sacrificial semiconductor layer 206TL is about 0.5 nm to about 2 nm greater than the thickness T2 of the lower sacrificial semiconductor layer 206. In some embodiments, the topmost sacrificial semiconductor layer 206TL can have a thickness of about 6.5 nm to 17 nm, while the lower sacrificial semiconductor layer 206 can have a thickness of about 6 nm to 15 nm.

[0023] The number of sacrificial semiconductor layer 206 and channel semiconductor layer 208 depends on the required number of channel nanostructures in the GAA device 200 (e.g., Figure 14A and Figure 14B (208C). In some embodiments, the number of channel semiconductor layers 208 is, for example, 2 to 10, to form a stack of 2 to 10 vertically separated channel nanostructures. In some embodiments, such as Figure 2 As shown, the stack 204 includes four (4) sacrificial semiconductor layers 206 and three (3) channel semiconductor layers 208.

[0024] The sacrificial semiconductor layer 206 and the channel semiconductor layer 208 can be epitaxially grown layer by layer from the top surface of the substrate 202. In some embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD (MOCVD)), or other suitable epitaxial growth processes. Epitaxial growth results in the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 having the same crystal orientation as the substrate 202. In some embodiments, when the substrate 202 has a (100) surface crystal orientation, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 also exhibit a (100) surface crystal orientation.

[0025] A hard mask layer 209 is formed on the topmost sacrificial semiconductor layer 206TL. In some embodiments, the hard mask layer 209 may include silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbide (SiOC), silicon carbonitride oxynitride (SiOCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), or other suitable dielectric layers. In some embodiments, the hard mask layer 209 may be formed by CVD, plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, the hard mask layer 209 may have a bilayer structure, including a pad oxide layer and a pad nitride layer formed on the pad oxide layer. In some embodiments, the pad oxide layer comprises SiO2, which may be formed by thermal oxidation, and the pad nitride layer comprises SiN, which may be formed by CVD, PECVD, PVD, ALD, or other suitable deposition processes. The hard mask layer 209 serves as a gate protection layer and is configured to reduce damage to the underlying substrate 202 and stack 204 during manufacturing.

[0026] Reference Figure 1 and Figures 3A-3B According to some embodiments, method 100 continues to operation 104, wherein fin structure 210 is formed by stack 204. Figure 3A and Figure 3B This is a cross-sectional view of the GAA device 200 after the fin structure 210 has been formed. It should be noted that, although... Figure 3B Two fin structures 210 are shown, but any number of fin structures 210 can be formed.

[0027] In some embodiments, portions of the hard mask layer 209, the stack 204, and the substrate 202 are patterned to form fin structures 210. Each fin structure 210 extends perpendicularly from the substrate 202 along the Z direction and has a length dimension along the X direction and a width dimension along the Y direction. The width of each fin structure 210 can range from about 10 nm to about 90 nm. Each fin structure 210 includes a base portion 210B, a stack portion 210S, and a hard mask portion 209P. The base portion 210B is formed by the substrate 202, the stack portion 210S is formed by the stack 204 and includes a portion of a sacrificial semiconductor layer 206 (hereinafter referred to as sacrificial semiconductor portion 206P, the topmost sacrificial semiconductor portion is denoted as 206TP) and a portion of a channel semiconductor layer 208 (hereinafter referred to as channel semiconductor portion 208P), while the hard mask portion 209P is formed by the hard mask layer 209.

[0028] In some embodiments, the fin structure 210 can be formed using photolithography and etching processes. During the photolithography process, a photoresist layer is first applied to the hard mask layer 209, for example, by spin coating. The photoresist layer is then exposed according to a patterned mask and developed to form a pattern in the photoresist layer. The patterned photoresist layer can be used as an etching mask to pattern other layers. In some embodiments, the photoresist layer is patterned using extreme ultraviolet (EUV) lithography. The patterned photoresist layer is then used to protect areas of the substrate 202 and the sacrificial semiconductor layer 206 and channel semiconductor layer 208 formed thereon, while the etching process forms the fin structure 210. In some embodiments, the etching process can be a dry etching process, such as plasma etching or reactive ion etching (RIE), a wet etching process, or a combination thereof.

[0029] In various other embodiments, the fin structure 210 can be formed using suitable processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A mandrel is formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining mandrel is used as an etch mask to pattern the hard mask layer 209, the stack 204, and the substrate 202, thereby providing the fin structure 210.

[0030] Subsequently, isolation components 214 can be formed on the substrate 202 and on the opposite sides of the fin structure 210. In some embodiments, the isolation components 214 may include silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride fluorine-doped silicate glass (FSG), low-k dielectric, and / or other suitable dielectric materials. In an example process, the isolation components 214 can be formed by first depositing a dielectric layer on the substrate 202 to fill the trenches between the fin structures 210. In various examples, the dielectric layer can be deposited using CVD processes, negative pressure CVD (SACVD) processes, flowable CVD processes, atomic layer deposition (ALD) processes, physical vapor deposition (PVD) processes, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized, for example by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed using a suitable anisotropic etching process to expose the stacked portions 210S of the fin structures 210. In some embodiments, the anisotropic etching process is a dry etching process, a wet etching process, and / or a combination thereof. In some embodiments, such as Figure 3B As shown, the top surface of the isolation component 214 is lower than the bottom surface of the bottommost sacrificial semiconductor portion 206P, causing the stacked portion 210S to rise above the isolation component 214.

[0031] Because the hard mask portion 209P is formed of a dielectric material with high etch selectivity relative to the isolation component 214, the hard mask portion 209P is retained in the structure after the isolation component 214 is formed.

[0032] refer to Figure 1 and Figures 4A-4B According to some embodiments, method 100 continues to operation 106, wherein a sacrificial gate structure 220 is formed on the fin structure 210 and the isolation member 214. Figure 4A and Figure 4B This is a cross-sectional view of the GAA device 200 after the sacrificial gate structure 220 is formed.

[0033] The sacrificial gate structures 220 extend longitudinally in parallel and are spaced apart, for example, by a distance of about 10 nm to 25 nm. In some embodiments, such as Figure 4A As shown, each sacrificial gate structure 220 surrounds the fin structure 210, covering the top and sidewall surfaces of the hard mask portion 209P, as well as the sidewall surfaces of the sacrificial semiconductor portion and the channel semiconductor portions 206P and 208P. The sacrificial gate structure 220 serves as a placeholder and will be replaced by the metal gate structure later.

[0034] In some embodiments, each sacrificial gate structure 220 may include a sacrificial gate stack (222, 224) and a gate spacer 226 located on the sidewall of the sacrificial gate stack. In some embodiments, the sacrificial gate stack (222, 224) includes a sacrificial gate dielectric 222 and a sacrificial gate electrode 224 from bottom to top. In some embodiments, the sacrificial gate dielectric 222 may include silicon oxide, silicon nitride, or silicon oxynitride. The sacrificial gate electrode 224 may include silicon, such as polycrystalline silicon or amorphous silicon.

[0035] In some embodiments, the sacrificial gate stack (222, 224) can be formed by first conformally depositing a sacrificial gate dielectric layer on the fin structure 210 and the isolation member 214. The sacrificial gate dielectric layer can be deposited using CVD, PECVD, ALD, or other suitable conformal deposition processes. In some embodiments, the thickness of the sacrificial gate dielectric layer can be in the range of about 1 nm to about 5 nm. Then, a sacrificial gate electrode layer is deposited on the sacrificial gate dielectric layer in a blanket manner, such that the fin structure 210 is completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer can be deposited using CVD, PECVD, PVD, ALD, or other suitable deposition processes. In some embodiments, the thickness of the sacrificial gate electrode layer can be in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation after deposition. Subsequently, the sacrificial gate electrode layer and the sacrificial gate dielectric layer are patterned using photolithography and etching processes. For example, a photoresist layer (not shown) is applied to the sacrificial gate electrode layer and photolithographically patterned by photolithographic exposure and development. The pattern in the photoresist layer is sequentially transferred to the sacrificial gate electrode layer and the sacrificial gate dielectric layer using at least one anisotropic etching process, thereby forming a sacrificial gate stack (222, 224) including the remaining portions of the sacrificial gate electrode and the sacrificial gate dielectric layer. The anisotropic etching process can be a dry etching process, such as RIE, a wet etching process, or a combination thereof. If the remaining photoresist layer after forming the sacrificial gate stack (222, 224) is not completely consumed, the remaining photoresist layer is removed by, for example, ashing.

[0036] Next, a gate spacer layer is deposited on the exposed surface of the GAA device 200 using a conformal deposition process, such as ALD or CVD. The gate spacer layer may include a dielectric material, such as an oxide, a nitride, an oxide oxynitride, or a combination thereof. In some embodiments, the gate spacer layer is made of silicon nitride. In some embodiments, an anisotropic etching process may be performed after deposition to remove the horizontal portions of the gate spacer layer. The remaining portions of the gate spacer layer on the sidewalls of the sacrificial gate stacks (222, 224) constitute gate spacer 226.

[0037] Reference Figure 1 and Figures 5A-5BAccording to some embodiments, method 100 continues to operation 108, wherein a source / drain trench 228 is formed in fin structure 210. Figure 5A and Figure 5B This is a cross-sectional view of the GAA device 200 after the source / drain trench 228 is formed.

[0038] The source / drain trench 228 may extend through the hard mask portion 209P and the underlying stack portion 210S. In some embodiments, the hard mask portion 209P, the sacrificial semiconductor portion 206P, and the channel semiconductor portion 208P in the source / drain region or in areas not covered by the sacrificial gate structure 200 are etched using the sacrificial gate structure 220 as an etch mask to form the source / drain trench 228. Etching may be performed by anisotropic dry etching processes, such as plasma etching or RIE. Example dry etching processes may be implemented using oxygen-containing gases, hydrogen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. Alternatively, etching can be performed using anisotropic wet etching processes that employ etchants such as a mixture of ammonium hydroxide, hydrogen peroxide, and water (APM), tetramethylammonium hydroxide (TMAH), or ammonium hydroxide (NH4OH). Figure 5A As shown, the sidewalls of the hard mask portion 209P, the sacrificial semiconductor portion 206P, and the channel semiconductor portion 208P are exposed in the source / drain trench 228. In some embodiments, the substrate portion 210B may also be partially etched, such that the source / drain trench 228 extends into the substrate portion 210B. Therefore, the bottom surface of the source / drain trench 228 may be flush with or below the top surface of the substrate portion 210B. In some embodiments, portions of the hard mask portion 209P and the stack portion 210S of each fin structure 210 between the sacrificial gate structures 220 are completely removed, exposing the substrate portion 210B of each fin structure 220.

[0039] Reference Figure 1 and Figures 6A-6B According to some embodiments, method 100 continues to operation 110, wherein the sacrificial semiconductor portion 206P is removed. Figure 6A and Figure 6B This is a cross-sectional view of the GAA device 200 after removing the sacrificial semiconductor portion 206P.

[0040] Selectively removing the sacrificial semiconductor portion 206P releases the channel semiconductor portion 208P, thereby forming a gap 230 within the structure. In each fin structure 210, the gap 230 includes a first gap 230T, which is the topmost gap located between the hard mask portion 209P and the topmost channel semiconductor portion 208P. The gap 230 also includes a plurality of second gaps 230U, which are located below the first gaps 230T and between adjacent channel semiconductor portions 208P, and between the bottommost channel semiconductor portion 208P and the substrate portion 210B of the fin structure 210. The first gap 230T is created by removing the topmost sacrificial semiconductor layer 206TL, while the second gaps 230U are created by removing the underlying sacrificial semiconductor layer 206. As a result, the height H1 of the first gap 230T is greater than the height H2 of the second gaps 230U.

[0041] In some embodiments, the sacrificial semiconductor portion 206P can be removed by a selective etching process using an etchant selective for the material of the sacrificial semiconductor portion 206P, thereby removing the sacrificial semiconductor portion 206P without substantially damaging the channel semiconductor portion 208P. In some embodiments, the etching process is an isotropic etching process, which can be a dry etching process or a wet etching process. In some embodiments, the selective etching process may include oxidizing the sacrificial semiconductor portion 206P using a suitable oxidant (such as ozone). Thereafter, the oxidized sacrificial semiconductor portion 206P can be selectively removed. In some embodiments, when the channel semiconductor portion 208P comprises Si and the sacrificial semiconductor portion 206P comprises SiGe, the sacrificial semiconductor portion 206P can be selectively removed by applying HCl gas or a gas mixture of CF4, SF6, and CHF3 at a temperature of about 500°C to about 700°C.

[0042] refer to Figure 1 and Figures 7A-7B According to some embodiments, method 100 continues to operation 112, wherein a sacrificial dielectric layer 232 is formed on the exposed surfaces of the source / drain trench 228 and the sacrificial gate structure 220 and within the gap 230. Figure 7A and Figure 7B This is a cross-sectional view of the GAA device 200 after the formation of the sacrificial dielectric layer 232.

[0043] A sacrificial dielectric layer 232 is conformally deposited on the channel semiconductor portion 208P, the substrate portion 210B, and the hard mask portion 209P to fill the gap 230. In some embodiments, the sacrificial dielectric layer 232 may comprise a dielectric oxide, such as silicon dioxide or silicon-rich oxide nitride. The sacrificial dielectric layer 232 can be formed by a conformal deposition process such as CVD or ALD. In some embodiments, the thickness of the sacrificial dielectric layer 232 is controlled such that the sacrificial dielectric layer is inserted into the first and second gaps 230T and 230U. In some embodiments, the sacrificial dielectric layer completely fills the first gap 230T and the second gap 230U. In other embodiments, such as Figure 7A As shown, the sacrificial dielectric layer 232 completely fills the second gap 230U, such that the sidewall surface of a portion of the sacrificial dielectric layer 232 within the second gap 230U extends laterally beyond the sidewall surface of the channel semiconductor portion 208P. However, since the height H1 of the first gap 230T is greater than the height H2 of the second gap 230U, the sacrificial dielectric layer 232 only partially fills the first gap 230T. As a result, the sidewall surface of a portion of the sacrificial dielectric layer 232 within the first gap 230T is recessed relative to the sidewall surface of the channel semiconductor portion 208P and does not extend laterally beyond the sidewall surface of the channel semiconductor portion 208P.

[0044] Reference Figure 1 and Figures 8A-8B According to some embodiments, method 100 continues to operation 114, wherein the sacrificial dielectric layer 232 is recessed to form a first sacrificial dielectric portion 232T within a first gap 230T and a second sacrificial dielectric portion 232U within a second gap 230U. Figure 8A and Figure 8B This is a cross-sectional view of the GAA device 200 after the sacrificial dielectric layer 232 has been recessed into a first sacrificial dielectric portion 232T and a second sacrificial dielectric portion 232U.

[0045] An etching process, such as an isotropic etching process, can be performed on the recessed portion of the sacrificial dielectric layer 232 exposed by the source / drain trench 228 to form a first sacrificial dielectric portion 232T within the first gap 230T and a second sacrificial dielectric portion 232U within the second gap 230U. Within each fin structure 210, the first sacrificial dielectric portion 232T is the topmost portion located above the second sacrificial dielectric portion 232U.

[0046] In embodiments of this disclosure, the height H1 of the first gap 230T is greater than the height H2 of the second gap 230U, resulting in a portion of the sacrificial dielectric layer 232 within the first gap 230T being thicker than the portion within the second gap 230U. Therefore, the portion of the sacrificial dielectric layer 232 in the first gap 230T is recessed to a greater extent than the portion in the corresponding second gap 230U. As a result, the width W1 of the first sacrificial dielectric portion 232T is smaller than the width W2 of the second sacrificial dielectric portion 232U. In some embodiments, the etching process is controlled such that the sidewalls of the second sacrificial dielectric portion 232U are aligned with the inner sidewalls of the gate spacer 226, while the sidewalls of the first sacrificial dielectric portion 232T are recessed inward from the inner sidewalls of the gate spacer 226. In some embodiments, the second sacrificial dielectric portions 232U have substantially the same width.

[0047] The etching process selectively removes the material of the sacrificial dielectric layer 232 without substantially etching the semiconductor material forming the channel semiconductor portion 208P and the substrate 202, or the dielectric material forming the gate spacer 226. In some embodiments, isotropic etching may be an isotropic dry etching process using an etching gas composition comprising a halogen-containing compound, ammonia (NH3), and an amine. In some embodiments, the halogen-containing compound is a fluorine-containing compound. In some embodiments, the fluorine-containing compound may include, but is not limited to, hydrogen fluoride (HF), carbon tetrafluoride (CF4), trifluoromethane (CHF3), sulfur hexafluoride difluoromethane (CH2F2), and hexafluoroethane (C2F6). In some embodiments, the amine may include, but is not limited to, methylamine, dimethylamine, trimethylamine, ethylamine, diethylamine, triethylamine, methylethylamine, N,N-diethylmethylamine, N,N-dimethylethylamine, isopropylamine, N-ethyldiisopropylamine, and tert-butylamine. In some embodiments, the etching gas composition comprises hydrogen fluoride, ammonia, and trimethylamine.

[0048] Reference Figure 1 and Figures 9A-9B According to some embodiments, method 100 continues to operation 116, wherein a first internal spacer 234T is formed in a first gap 230T and a second internal spacer 234U is formed in a second gap 230U. Figure 9A and Figure 9B This is a cross-sectional view of the GAA device 200 after the formation of the first internal spacer 234T and the second internal spacer 234U.

[0049] In each fin structure 210, the first inner spacer 234T is the topmost inner spacer located above the second inner spacer 234U. The first inner spacer 234T laterally surrounds the first sacrificial dielectric portion 232T, while each second inner spacer 234 laterally surrounds the corresponding second sacrificial dielectric portion 232U. The sidewalls of the first and second inner spacers 234T, 234U are aligned with the outer sidewall of the gate spacer 226.

[0050] In some embodiments, such as Figure 9A As shown, the width W3 of the first internal spacer 234T, formed in the first gap 230T and contacting the sidewall of the first sacrificial dielectric portion 232T, can be greater than the width of the gate spacer 226. In contrast, the width W4 of the second internal spacer 234U, formed in the second gap 230U and contacting the sidewall of the second sacrificial dielectric portion 232U, can be the same as the width of the gate spacer 226. Therefore, the width W3 is greater than the width W4. In some embodiments, the width W3 is approximately 0.25 nm to approximately 2.5 nm larger than the width W4.

[0051] To form the internal spacers 234T, 234U, an internal spacer material layer is structurally deposited, including within the first and second gaps 230T, 230U. The internal spacer material layer may comprise a dielectric nitride, such as silicon nitride, silicon carbonitride, or any suitable dielectric material having an etch selectivity different from that of the dielectric oxide forming the first and second sacrificial dielectric portions 232T, 232U. The internal spacer material layer may be formed by CVD, ALD, or any other suitable conformal deposition process. In some embodiments, the internal spacer material layer may be formed to a thickness such that the remaining volume in the first and second gaps 230T, 230U not occupied by the first and second sacrificial dielectric portions 232T, 232U is filled by the internal spacer material layer.

[0052] An etching process, such as an anisotropic etching process, is then performed to remove a portion of the internal spacer material layer disposed outside the first and second gaps 230T, 230U. The remaining portion of the internal spacer material layer (i.e., the portion disposed within the first and second gaps 230T, 230U) forms the internal spacers 234T and 234U. In some embodiments, the anisotropic etching process may be a wet etching process, which includes using an etchant such as buffered hydrofluoric acid (BHF), hydrofluoric acid (HF), hydrofluoric acid diluted with nitric acid (HNA), phosphoric acid, HF diluted with ethylene glycol (HFEG), hydrochloric acid (HCl), or any combination thereof. In some embodiments, the anisotropic etching process can be a dry etching process, which includes the use of oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas (e.g., CF3I), other suitable gases and / or plasma and / or combinations thereof.

[0053] Reference Figure 1 and Figures 10A-10B According to some embodiments, method 100 continues to operation 118, wherein an epitaxial semiconductor component 240 is formed in a source / drain trench 228. Figure 10A and Figure 10B This is a cross-sectional view of the GAA device 200 after the epitaxial semiconductor component 240 is formed in the source / drain trench 228.

[0054] The epitaxial semiconductor component 240 is disposed on the opposite side of the sacrificial gate structure 220 and is in contact with the channel semiconductor portion 208P and the first and second internal spacers 234T and 234U.

[0055] The epitaxial semiconductor component 240 is epitaxially grown from the semiconductor surfaces exposed by the source / drain trench 228 (including the sidewall surfaces of the channel semiconductor portion 208P, the sidewalls of the substrate 202, and the bottom surface), but not from dielectric surfaces (such as the surfaces of the first and second internal spacers 234T, 234U, and the gate spacer 226). Therefore, the epitaxial semiconductor component 240 can be grown vertically and horizontally to form facets that can correspond to the crystal planes of the substrate 202. The epitaxial semiconductor component 240 can be formed by, for example, vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), molecular beam epitaxy (MBE), or other suitable selective epitaxial growth processes. The formed epitaxial semiconductor component 240 may have a top surface above the top surface of the topmost channel semiconductor portion 208P. In some embodiments, the top surface of the epitaxial semiconductor component 240 may be coplanar with or below the bottom surface of the hard mask portion 209P.

[0056] The epitaxial semiconductor component 240 may include any suitable material for an n-type or p-type FET device. For example, when forming an n-type FET device, the epitaxial semiconductor component 240 may include a material for applying tensile strain in the channel region, such as Si, SiC, SiCP, SiP, etc. Similarly, when forming a p-type FET device, the epitaxial semiconductor component 240 may include a material for applying compressive strain in the channel region, such as Si, SiGe, SiGeB, Ge, GeSn.

[0057] Reference Figure 1 and Figures 11A-11B According to some embodiments, method 100 continues to operation 120, wherein a dopant is implanted into epitaxial semiconductor component 240 to form source / drain component 242. Figure 10A and Figure 10B This is a cross-sectional view of the GAA device 200 after the source / drain components 242 are formed.

[0058] An implantation process can be performed to introduce a dopant into the epitaxial semiconductor component 240, thereby forming a source / drain component 242 as a doped epitaxial semiconductor region. In some embodiments, the dopant can be a p-type dopant, such as boron (B), aluminum (Al), gallium (Ga), or indium (In). For example, the source / drain component 242 of a p-type FET device may include boron-doped SiGe. In some embodiments, the dopant can be an n-type dopant, such as phosphorus (P) or arsenic (As). For example, the source / drain component 242 of an n-type FET device may include phosphorus-doped Si. The concentration range of the p-type or n-type dopant can be from about 1 × 10⁻⁶. 19 atoms / cm 3 Up to approximately 1×1021 atoms / cm 3 For example, approximately 5 × 10 20 atoms / cm 3 In some embodiments, implantation is performed vertically. In some embodiments, the source / drain components 242 have a gradient doping distribution, with the dopant concentration gradually decreasing from the top to the bottom of the source / drain components 242. After implantation, annealing can be performed to repair implantation damage and activate the dopant.

[0059] In some embodiments, the epitaxial semiconductor component 240 can be doped in situ during the growth process, in which case operation 120 can be omitted.

[0060] refer to Figure 1 and Figures 12A-12B According to some embodiments, method 100 continues to operation 122, wherein a contact etch stop layer (CESL) 250 is formed on the source / drain component 242, and then an interlayer dielectric (ILD) layer 252 is formed on the contact etch stop layer 250. Figure 12A and Figure 12B This is a cross-sectional view of the GAA device 200 after the formation of the contact etch stop layer 250 and the ILD layer 252.

[0061] In some embodiments, the contact etch stop layer 250 is conformally deposited on the source / drain portion 242, the first internal spacer 234T, the hard mask portion 209P, the gate spacer 226, and the sacrificial gate electrode 224. The contact etch stop layer 250 may include a dielectric material such as silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, or a combination thereof. The contact etch stop layer 250 may be formed using a conformal deposition process such as ALD or CVD.

[0062] ILD layer 252 is disposed on contact etch stop layer 250 and has a different etch rate than contact etch stop layer 250. In some embodiments, ILD layer 252 may include a low-k dielectric material having a dielectric constant lower than that of silicon dioxide (approximately 3.9). Low-k dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), spin-coated glass (SOG), or combinations thereof. ILD layer 252 may be deposited by CVD, flowable CVD (FCVD), PECVD, spin coating, or other suitable deposition processes.

[0063] After depositing the ILD layer 252, a planarization process, such as a CMP process, can be performed to remove portions of the ILD layer 252 and the contact etch stop layer 250 from the top surface of the sacrificial gate structure 220. This exposes the top surface of the sacrificial gate structure 220. In some embodiments, the top surfaces of the ILD layer 252 and the contact etch stop layer 250 are coplanar with the top surface of the sacrificial gate structure 220 (i.e., the top surfaces of the gate spacer 226 and the sacrificial gate electrode 224).

[0064] Reference Figure 1 and Figures 13A-13B According to some embodiments, method 100 continues to operation 124, in which the sacrificial gate stack (222, 224) is removed. Figure 13A and Figure 13B This is a cross-sectional view of the GAA device 200 after removing the sacrificial gate stack (222, 224).

[0065] One or more etching processes can be performed to selectively remove multiple components of each sacrificial gate stack (222, 224), including the sacrificial gate dielectric 222 and the sacrificial gate electrode 224. Removal of each sacrificial gate stack (222, 224) forms a gate trench 260 that exposes a hard mask portion 209P, a channel semiconductor portion 208P, and sacrificial dielectric portions 232T, 232U in the channel region of each fin structure 210. An ILD layer 252 and a contact etch stop layer 250 protect the source / drain components 242 during the etching process. The etching process can be a dry etching process, a wet etching process, or a combination thereof. The etching process can be adjusted so that the sacrificial gate dielectric 222 and the sacrificial gate electrode 224 are removed without (or with minimal) etching of other components in the GAA device 200, including the ILD layer 252, the contact etch stop layer 250, the source / drain components 242, the gate spacer 226, and the hard mask portion 209P. For example, in the case where the sacrificial gate electrode 224 is made of polysilicon and the ILD layer 252 is made of silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode 224. Subsequently, plasma dry etching and / or wet etching are used to remove the sacrificial gate dielectric 222.

[0066] Reference Figure 1 and Figures 14A-14B According to some embodiments, method 100 continues to operation 126, wherein the sacrificial dielectric portions 232T and 232U are removed. Figure 14A and Figure 14B This is a cross-sectional view of the GAA device 200 after removing the sacrificial dielectric portions 232T and 232U.

[0067] Selective removal of sacrificial dielectric portions 232T and 232U releases channel semiconductor portion 208P to form channel nanostructure 208C. In some embodiments, channel nanostructure 208C is a nanosheet. In some embodiments, the sacrificial dielectric portions 232T and 232U can be removed by a selective etching process using an etchant selective to the material of the sacrificial dielectric portions 232T and 232U, such that the sacrificial dielectric portions 232T and 232U are removed without substantially damaging the channel semiconductor portion 208P, gate spacer 226, inner spacers 234T and 234U, ILD layer 252, and contact etch stop layer 250. In some embodiments, the etching process is an isotropic etching process, which can be a dry etching process or a wet etching process. The inner spacers 234T and 234U serve as etch stop layers to protect the source / drain components 242 during the removal of the sacrificial dielectric portions 232T and 232U.

[0068] In some embodiments, after exposing the channel nanostructure 208C by removing the sacrificial dielectric portions 232T and 232U, a trimming operation can be performed to reduce the thickness of the channel nanomaterial 208C, thereby improving the gate fill window. The trimming operation can utilize any suitable etching process, such as dry etching, wet etching, or a combination of both. The resulting channel nanostructure 208C can range in thickness from 3 nm to 8 nm.

[0069] like Figure 14A As shown, as a result of removing the sacrificial dielectric portions 232T and 232U and trimming the nanosheets, a first gate gap 262T is formed within each fin structure 210 between the topmost channel nanostructure 208C and the hard mask portion 209P, while a second gate gap 262U is formed between adjacent channel nanostructures 208C and between the bottommost channel nanostructure 208C and the substrate portion 210B. The second gate gap 262U defines the spacing between adjacent channel nanostructures 208C. In some embodiments, the spacing between adjacent channel nanostructures 208C (also referred to as inter-chip spacing) can be in the range of about 8 nm to about 15 nm. The first gate gap 262T, located above the second gate gap 262U, defines the spacing between the hard mask portion 209P and the topmost channel nanostructure 208C. Compared to the second gate gap 262U, the first gate gap 262T has a larger height but a smaller width. In some embodiments, the height of the first gate gap 262T is about 0.5 nm to about 2 nm greater than the height of the second gate gap 262U, and the width of the first gate gap 262T is about 0.5 nm to about 5 nm smaller than the width of the second gate gap 262U.

[0070] Reference Figure 1 and Figures 15A-15BAccording to some embodiments, method 100 continues to operation 128, wherein an interface layer 272, a gate dielectric layer 274, and a gate electrode layer 276 for replacing the gate are formed. Figure 15A and Figure 15B This is a cross-sectional view of the GAA device 200 after the formation of the interface layer 272, the gate dielectric layer 274, and the gate electrode layer 276.

[0071] An interface layer 272 is formed on the exposed surfaces of the channel nanostructure 208C and the substrate portion 210B, such as on the top, sidewalls, and bottom surfaces of the channel nanostructure 208C, and on the top and sidewalls of the substrate portion 210B. The interface layer 272 can facilitate the adhesion of the gate dielectric layer 274 to the channel nanostructure 208C. In some embodiments, the interface layer 272 may include a dielectric material, such as silicon oxide. In some embodiments, the interface layer 272 can be formed by chemically oxidizing or thermally oxidizing surface portions of the channel nanostructure 208C and the substrate portion 210B. For example, in some embodiments, ozonated deionized water containing ozone is used to form the interface layer 272. The thickness of the interface layer 272 ranges from about 0.5 nm to about 1.5 nm. In some embodiments, the thickness of the interface layer 272 is about 1 nm, which is achieved by oxidizing about 1 nm of the channel nanostructure 208C.

[0072] Subsequently, a gate dielectric layer 274 is conformally deposited in the gate trench 260 and gate gaps 262T and 262U. The gate dielectric layer 274 surrounds the channel nanostructure 208C and the hard mask portion 209P, such that the gate dielectric layer 274 is disposed on the top, sidewalls, and bottom surfaces of the interface layer 272, the sidewalls and top surface of the gate trench 260, and the top surface of the gate spacer 226, the contact etch stop layer 250, and the ILD layer 252. In some embodiments, the gate dielectric layer 274 may comprise a high-k dielectric material with a dielectric constant greater than that of silicon dioxide. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfSrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and hafnium oxide-aluminum oxide (HfO2-Al2O3) alloys. The gate dielectric layer 274 can be formed by CVD, ALD, or other suitable conformal deposition methods. In some embodiments, the gate dielectric layer 274 can be formed using a conformal deposition process such as ALD to ensure that the high-k gate dielectric layer 274 has a uniform thickness around each channel nanostructure 208C. The gate dielectric layer 274 can be formed to have a thickness ranging from about 1 nm to about 2.5 nm. In some embodiments, the gate dielectric layer 274 can be formed to have a thickness of about 1.5 nm.

[0073] Gate electrode layers 276 are deposited on gate dielectric layers 274 and fill the remaining volume of gate trenches 260 and gate gaps 262T and 262U. Gate electrode layers 276 may comprise metal-containing materials, such as aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum tantalum carbide (TaAlC), aluminum tantalum silicide (TaSiAl), silicon tantalum carbide (TaSiC), tantalum silicide (TaSi), hafnium carbide (HfC), tungsten nitride (WN), tungsten nitride carbon (WCN), silicon tantalum nitride (TaSiN), titanium nitride (TaN), cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although... Figure 15A , Figure 15B The diagram shows a single-layer gate electrode layer 276, but the gate electrode layer 176 may include any number of work function tuning layers and filler materials. The gate electrode layer 276 may be formed by a conformal deposition process (e.g., ALD or CVD).

[0074] Reference Figure 1 and Figures 16A-16B According to some embodiments, method 100 continues to operation 130, wherein gate stack 280 is formed in gate trench 260 and gate gaps 262T, 262U. Figure 16A and Figure 16B This is a cross-sectional view of the GAA device 200 after the gate stack 280 is formed.

[0075] Each gate stack 280 is formed as a channel nanostructure 208C surrounding the fin structure 210. In some embodiments, the gate stack 280 includes an interface layer 272 on the top, bottom, and sidewall surfaces of the channel nanostructure 208C and on the top and sidewall surfaces of the substrate portion 210B; a gate dielectric layer 274 on the interface layer 272 and on the sidewall and bottom surfaces of the hard mask portion 209P; and a gate electrode layer 276 on the gate dielectric layer 274 to fill the remaining volume of the gate trench 260 and gate gaps 262T, 262U. In some embodiments, as Figure 16B As shown, the top surface of each gate stack 280 is coplanar with the top surface of the hard mask portion 209P.

[0076] To form the gate stack 280, after depositing the gate electrode layer 276, a planarization process such as CMP can be performed to remove portions of the gate electrode layer 276 and the gate dielectric layer 274 from above the hard mask portion 209P, thereby exposing the top surface of the hard mask portion 209P. The interface layer 272, together with the remaining portions of the gate dielectric layer 274 and the gate electrode layer 276, constitutes the replacement gate of the resulting nanosheet FET. The planarization process also flushes the gate spacer 226, the contact etch stop layer 250, and the ILD layer 252 with the hard mask portion 209P, such that the top surfaces of the remaining portions of the gate spacer 226, the contact etch stop layer 250, and the ILD layer 252 are coplanar with the top surface of the hard mask portion 209P.

[0077] Figure 17A and Figure 17B A GAA device 200 according to a second exemplary embodiment is shown, wherein a planarization process is performed to completely remove the hard mask portion 209P from the structure. As a result, as Figure 17A and Figure 17B As shown, the gate dielectric layer 274 on the top surface of the topmost channel nanostructure 208C is exposed after planarization. In some embodiments, the planarization process also completely removes the ILD layer 252 covering the source / drain components 242. In some embodiments, the planarization process removes a portion of the gate dielectric layer 274 on the top surface of the topmost channel nanostructure 208C. As a result, the thickness of the portion of the gate dielectric layer 274 on the top surface of the topmost channel nanostructure 208C is less than the thickness of the portions of the gate dielectric layer 274 on the sidewalls and bottom surface of the topmost channel nanostructure 208C.

[0078] Figure 18A and Figure 18B A GAA device 200 according to a third exemplary embodiment is shown, wherein a planarization process is performed to partially remove the hard mask portion 209P from the structure. As a result, as Figure 18A and Figure 18B As shown, the gate stack 280 is still protected by the hard mask portion 209P, although... Figure 16A and Figure 16B The thickness of the hard mask portion 209P shown is reduced compared to the previous version.

[0079] like Figures 16A-18BAs shown, within the fin structure 210, each gate stack 280 thus formed includes a first portion located in a first gate gap 262T (i.e., the topmost gate gap) and a second portion located in a second gate gap 262U below the first gate gap 262T. The first portion has a smaller width but a larger height compared to the second portion. In some embodiments, the width W5 of the first portion is about 0.5 nm to about 5 nm smaller than the width W6 of the second portion, while the height of the first portion is about 0.5 nm to about 2 nm greater than the height of the second portion. Figure 16A , Figure 17A and Figure 18A As further shown, the first part is separated from the source / drain component 242 by a first internal spacer 234T with a width of W3, while the second part is separated from the source / drain component 242U by a corresponding second internal spacer 234U with a width of W4, which is smaller than W3. Therefore, the first part is further away from the source / drain component 242 than the second part.

[0080] In embodiments of this disclosure, the effective capacitance (Ceff) can be reduced by employing a thicker top sacrificial layer to form a metal gate stack, the top width of which is smaller than the bottom width and is further spaced from the source / drain components.

[0081] Additional processes can be performed to complete the fabrication of the GAA device 200. For example, gate contacts and source / drain contacts (not shown for simplicity) can be formed to be electrically coupled to the gate stack 280 and the source / drain component 242, respectively. Interconnect structures can then be formed on the source / drain contacts and the gate contacts. The interconnect structures may include multiple dielectric layers surrounding metal components (including conductive traces and conductive vias) that provide electrical connections between devices (such as the GAA device 200) formed on the substrate 202.

[0082] Figure 19 This is a flowchart of a method 300 for forming a GAA device 200 according to an alternative embodiment of the present disclosure. Figures 20A-26B This is a cross-sectional view of an intermediate stage in the formation process of the GAA device 200 corresponding to method 300. Unless otherwise stated, the materials and formation methods of the components in these embodiments are the same as those in... Figure 2-Figure 18B In the illustrated embodiments, similar components represented by the same reference numerals are substantially identical. Therefore, in Figure 2-Figure 18B In the discussion of the illustrated embodiments, one can find information about Figures 20A-26B Details of the component's formation process and materials are shown.

[0083] Unlike method 100, which performs operations to replace the sacrificial semiconductor portion with the sacrificial dielectric portion, in method 300, these operations are omitted, thereby forming the channel nanostructure by removing the sacrificial semiconductor portion from the structure.

[0084] The initial operations of method 300 are the same as operations 102-108 of method 100. (See reference) Figure 19 In operation 302, method 300 forms an initial structure of GAA device 200, which includes a substrate 202, a stack 204 of alternating epitaxial semiconductor layers on the substrate 202, and a hard mask layer 209 on the stack 204, as previously referenced. Figure 2 As described above. In operation 304, method 300 forms a fin structure 210 formed by portions of the stack 204 and the substrate 202, as previously referred to. Figure 3A and Figure 3B As described above. In operation 306, method 300 forms a sacrificial gate structure 220 on the fin structure 210, as previously referred to. Figure 4A and Figure 4B As described above. In operation 308, method 300 forms a source / drain trench 228 in the fin structure 210, as previously referred to. Figure 5A and Figure 5B As stated above.

[0085] Reference Figure 19 and Figures 20A-20B According to some embodiments, the method proceeds to operation 310, in which the sacrificial semiconductor portion 206P is recessed. Figure 20A and Figure 20B This is a cross-sectional view of the GAA device 200 after the recessed sacrificial semiconductor portion 206P.

[0086] An etching process, such as an isotropic etching process, can be performed on the recessed portion of the sacrificial semiconductor portion 206P exposed by the source / drain trench 228 to form a first recessed sacrificial semiconductor portion 206T within a first gap 230T and a second recessed sacrificial semiconductor portion 206U within a second gap 230U. Within each fin structure 210, the first recessed sacrificial semiconductor portion 206T is the topmost portion located above the second recessed sacrificial semiconductor portion 206U. In embodiments of this disclosure, the topmost sacrificial semiconductor portion 206TP is etched faster than the lower sacrificial semiconductor portion 206P because the topmost sacrificial semiconductor portion 206TP is formed of a material with a higher etch rate, or is formed at a greater thickness, or both. Figure 20AAs shown, the width W1 of the first recessed sacrificial semiconductor portion 206T is smaller than the width W2 of the second recessed sacrificial semiconductor portion 206U. In some embodiments, the etching process is controlled such that the sidewall of the second recessed sacrificial semiconductor portion 206U is aligned with the inner sidewall of the gate spacer 226, while the sidewall of the first recessed sacrificial semiconductor portion 206T is recessed inward from the inner sidewall of the gate spacer 226. In some embodiments, the second recessed sacrificial semiconductor portion 206U has substantially the same width.

[0087] The etching process selectively removes material from the sacrificial semiconductor portion 206P while substantially leaving the channel semiconductor portion 208P and substrate 202 unetched. In some embodiments, when the channel semiconductor portion 208P comprises Si and the sacrificial semiconductor portion 206P comprises SiGe, the sacrificial semiconductor portion 206P can be recessed by applying HCl gas at a temperature of about 500°C to about 700°C, or by applying a gas mixture of CF4, SF6, and CHF3. In some other embodiments, the etching process may include oxidizing portions of the sacrificial semiconductor portion 206P using a suitable oxidant, such as ozone. Thereafter, the oxidized portions of the sacrificial semiconductor portion 206P can be selectively removed.

[0088] Reference Figure 19 and Figures 21A-21B According to some embodiments, method 300 continues to operation 312, wherein a first internal spacer 234T is formed in a first gap 230T and a second internal spacer 234U is formed in a second gap 230U. Figure 21A and Figure 21B This is a cross-sectional view of the GAA device 200 after the formation of the first internal spacer 234T and the second internal spacer 234U. The first internal spacer 234T contacts the sidewall of the first recessed sacrificial semiconductor portion 206T, and the second internal spacer 234U contacts the sidewall of the second recessed sacrificial semiconductor portion 206U. (The above is an explanation of the process.) Figure 9A and Figure 9B The process described is used to form the first internal spacer 234T and the second internal spacer 234U.

[0089] Reference Figure 19 and Figures 22A-22B According to some embodiments, method 300 continues to operation 314, wherein epitaxial semiconductor component 240 is formed in source / drain trench 228. Figure 22A and Figure 22B This is a cross-sectional view of the GAA device 200 after the epitaxial semiconductor component 240 is formed in the source / drain trench 228. (The above is related to...) Figure 10A and Figure 10BThe process described is used to form an epitaxial semiconductor component 240 in a source / drain trench 228.

[0090] Reference Figure 19 and Figures 23A-23B According to some embodiments, method 300 continues to operation 316, wherein a dopant is implanted into epitaxial semiconductor component 240 to form source / drain component 242. Figure 23A and Figure 23B This is a cross-sectional view of the GAA device 200 after the source / drain components 242 are formed. (The above is related to...) Figure 11A and Figure 11B The described process is used to form source / drain components 242.

[0091] refer to Figure 19 and Figures 24A-24B According to some embodiments, method 300 continues to operation 318, wherein a contact etch stop layer (CESL) 250 is formed on the source / drain component 242, and then an interlayer dielectric (ILD) layer 252 is formed on the contact etch stop layer 250. Figure 24A and Figure 24B This is a cross-sectional view of the GAA device 200 after the formation of the contact etch stop layer 250 and the ILD layer 252. (The above is related to...) Figure 12A and Figure 12B The process described is used to form a contact etch stop layer 250 and an ILD layer 252.

[0092] Reference Figure 19 and Figures 25A-25B According to some embodiments, method 300 continues to operation 320, wherein the sacrificial gate stack (222, 224) is removed to form gate trench 260. Figure 25A and Figure 25B This is a cross-sectional view of the GAA device 200 after the sacrificial gate stack (222, 224) has been removed to form the gate trench 260. (The above refers to...) Figure 13A and Figure 13B The process described is to remove the sacrificial gate stack (222, 224).

[0093] Reference Figure 19 and Figures 26A-26B According to some embodiments, method 300 proceeds to operation 322, in which the recessed sacrificial semiconductor portions 206T, 206U are removed. Figure 26A and Figure 26B This is a cross-sectional view of the GAA device 200 after the recessed sacrificial semiconductor portions 206T and 206U have been removed.

[0094] The recessed sacrificial semiconductor portions 206T and 206U are selectively removed to release the channel semiconductor portion 208P, thereby forming the channel nanostructure 208C. In some embodiments, the recessed sacrificial semiconductor portions 206T and 206U can be removed by a selective etching process using an etchant that is selective to the material of the recessed sacrificial semiconductor portions 206T and 206U, thereby removing the recessed sacrificial semiconductor portions 206T and 206U without substantially damaging the channel semiconductor portion 208P. In some embodiments, the etching process is an isotropic etching process, which can be a dry etching process or a wet etching process. In some embodiments, the selective etching process may include oxidizing the recessed sacrificial semiconductor portions 206T and 206U using a suitable oxidant (such as ozone). Thereafter, the oxidized recessed sacrificial semiconductor portions 206T and 206U can be selectively removed. In some embodiments, when the channel semiconductor portion 208P comprises Si and the recessed sacrificial semiconductor portions 206T and 206U comprise SiGe, the recessed sacrificial semiconductor portions 206T and 206U can be selectively removed by applying HCl gas or a mixture of gases CF4, SF6 and CHF3 at a temperature of about 500°C to about 700°C.

[0095] Reference Figure 19 According to some embodiments, method 300 proceeds to operation 324, wherein an interface layer 272, a gate dielectric layer 274, and a gate electrode layer 276 for replacing the gate are formed. The above-mentioned... Figure 15A and Figure 15B The described process forms an interface layer 272, a gate dielectric layer 274, and a gate electrode layer 276.

[0096] Reference Figure 19 According to some embodiments, method 300 continues to operation 326, wherein gate stack 280 is formed in gate trench 260 and gate gaps 262T, 262U. The above-mentioned... Figure 16A and Figure 16B The process described is used to form gate stack 280.

[0097] One aspect of this specification relates to a method of forming a semiconductor device. The method includes: forming a fin structure extending along a first direction over a substrate, the fin structure having a height along a second direction transverse to the first direction, and including a stacked portion and a hard mask portion located above the stacked portion, the stacked portion including alternating channel semiconductor portions and sacrificial material portions. The sacrificial material portions include a first sacrificial material portion in contact with the hard mask portion and a second sacrificial material portion located below the first sacrificial material portion. Next, the first and second sacrificial material portions are laterally recessed. The first sacrificial material portion is etched to a greater extent than the second sacrificial material portion. After removing the recessed first and second sacrificial material portions to form a plurality of channel nanostructures from the channel semiconductor portions, a gate stack surrounding the channel nanostructures is formed.

[0098] In some embodiments, the channel semiconductor portion includes a first semiconductor material, and the sacrificial material portion includes a second semiconductor material different from the first semiconductor material.

[0099] In some embodiments, the first sacrificial material portion and the second sacrificial material portion are semiconductor portions of different compositions, wherein the first sacrificial material portion has a first etch rate to the etchant, and the second sacrificial material portion has a second etch rate to the etchant that is less than the first etch rate.

[0100] In some embodiments, the first sacrificial material portion and the second sacrificial material portion are semiconductor portions having the same composition.

[0101] In some embodiments, the sacrificial material portion includes a dielectric material, and the channel semiconductor portion includes a semiconductor material.

[0102] In some embodiments, in the second direction, the first sacrificial material portion has a first thickness, and each of the second sacrificial material portions has a second thickness less than the first thickness.

[0103] In some embodiments, in a first direction, the recessed first sacrificial material portion has a first width, and the recessed second sacrificial material portion each has a second width greater than the first width.

[0104] In some embodiments, forming a fin structure includes: forming a stack of alternating sacrificial semiconductor layers and channel semiconductor layers over a substrate, wherein the top layer is a sacrificial semiconductor layer; forming a hard mask layer over the stack; and patterning portions of the hard mask layer, the stack, and the substrate.

[0105] In some embodiments, the method further includes forming a sacrificial gate structure over the fin structure, the sacrificial gate structure including a sacrificial gate electrode and a gate spacer located on the sidewall of the sacrificial gate electrode.

[0106] In some embodiments, the method further includes forming source / drain trenches in the fin structure on opposite sides of the sacrificial gate structure.

[0107] In some embodiments, the patterned stack forms alternating sacrificial semiconductor portions and channel semiconductor portions, wherein the sacrificial semiconductor portions constitute sacrificial material portions.

[0108] In some embodiments, the patterned stack forms alternating sacrificial semiconductor portions and channel semiconductor portions, and the method further includes replacing the sacrificial semiconductor portions with sacrificial dielectric portions to form sacrificial material portions composed of dielectric material.

[0109] In some embodiments, the method further includes forming internal spacers that laterally surround the recessed first sacrificial material portion and the recessed second sacrificial material portion.

[0110] Another aspect of this specification relates to a method of forming a semiconductor device. The method includes: forming a fin structure extending along a first direction on a substrate. The fin structure has a height along a second direction transverse to the first direction and includes a stacked portion and a hard mask portion located above the stacked portion. The stacked portion includes alternating channel semiconductor portions and sacrificial semiconductor portions. The sacrificial semiconductor portions include a first sacrificial semiconductor portion in contact with the hard mask portion and a second sacrificial semiconductor portion located below the first sacrificial semiconductor portion. The first sacrificial semiconductor portion has a first etch rate to an etchant, and the second sacrificial semiconductor portion has a second etch rate to an etchant lower than the first etch rate. The first and second sacrificial semiconductor portions are laterally recessed. Next, the recessed first and second sacrificial semiconductor portions are replaced with gate stacks to surround the channel semiconductor portion.

[0111] The first semiconductor portion has a first etching rate to the etchant, and the second semiconductor portion has a second etching rate to the etchant that is lower than the first etching rate.

[0112] In some embodiments, in a first direction, the recessed first sacrificial semiconductor portion has a first width, and the recessed second sacrificial semiconductor portion each has a second width greater than the first width.

[0113] In some embodiments, in the second direction, the first sacrificial semiconductor portion has a first thickness, and each of the second sacrificial semiconductor portions has a second thickness less than the first thickness.

[0114] In some embodiments, the first sacrificial semiconductor portion comprises SiGe having a first Ge content, and the second sacrificial semiconductor portion comprises SiGe having a second Ge content lower than the first Ge content.

[0115] In some embodiments, replacing the recessed first sacrificial semiconductor portion and the recessed second sacrificial semiconductor portion with a gate stack includes: forming an internal spacer that contacts the sidewalls of the recessed first sacrificial semiconductor portion and the recessed second sacrificial semiconductor portion; removing the recessed first sacrificial semiconductor portion and the recessed second sacrificial semiconductor portion to form a gap between the channel semiconductor portions and between the topmost channel semiconductor portion and the hard mask portion; and forming a gate stack in the gap.

[0116] Another aspect of this specification relates to a semiconductor device. The semiconductor device includes a plurality of nanostructures situated above a substrate and extending along a length direction, a gate stack surrounding each of the plurality of nanostructures, and source / drain components adjacent to the gate stack. The gate stack includes a first portion situated on the top surface of the topmost nanostructure of the plurality of nanostructures and a second portion situated between adjacent nanostructures of the plurality of nanostructures. The first portion has a first dimension in the length direction, and each of the second portions has a second dimension in the length direction greater than the first dimension.

[0117] In some embodiments, a first portion of the gate stack includes an interface layer above the top surface of the topmost nanostructure, a gate dielectric above the interface layer, and a gate electrode surrounding the gate dielectric above the interface layer, wherein the thickness of the portion of the gate dielectric above the top surface of the topmost nanostructure is less than the thickness of the portions of the gate dielectric on the sidewalls and bottom surface of the topmost nanostructure.

[0118] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A method for forming a semiconductor device, comprising: A fin structure extending in a first direction is formed above a substrate. The fin structure has a height in a second direction transverse to the first direction and includes a stacked portion and a hard mask portion located above the stacked portion. The stacked portion includes alternating channel semiconductor portions and sacrificial material portions, wherein the sacrificial material portions include a first sacrificial material portion in contact with the hard mask portion and a second sacrificial material portion located below the first sacrificial material portion. The first sacrificial material portion and the second sacrificial material portion are laterally recessed, wherein the first sacrificial material portion is etched to a greater extent than the second sacrificial material portion; The recessed first sacrificial material portion and the recessed second sacrificial material portion are removed to form a plurality of channel nanostructures from the channel semiconductor portion; and A gate stack is formed around the channel nanostructure.

2. The method according to claim 1, wherein, The channel semiconductor portion includes a first semiconductor material, and the sacrificial material portion includes a second semiconductor material that is different from the first semiconductor material.

3. The method according to claim 1, wherein, The first sacrificial material portion and the second sacrificial material portion are semiconductor portions of different compositions, wherein the first sacrificial material portion has a first etching rate to the etchant, and the second sacrificial material portion has a second etching rate to the etchant that is less than the first etching rate.

4. The method according to claim 1, wherein, In the second direction, the first sacrificial material portion has a first thickness, and each of the second sacrificial material portions has a second thickness less than the first thickness.

5. The method according to claim 1, wherein, In the first direction, the recessed first sacrificial material portion has a first width, and the recessed second sacrificial material portion each has a second width greater than the first width.

6. The method according to claim 1, wherein, The formation of the fin structure includes: A stack of alternating sacrificial semiconductor layers and channel semiconductor layers is formed above a substrate, wherein the top layer is the sacrificial semiconductor layer; A hard mask layer is formed over the stack; and Pattern portions of the hard mask layer, the stack, and the substrate.

7. The method according to claim 6, wherein, The method further includes patterning the stacked components to form alternating sacrificial semiconductor portions and channel semiconductor portions, and replacing the sacrificial semiconductor portions with sacrificial dielectric portions to form sacrificial material portions composed of dielectric material.

8. A method of forming a semiconductor device, comprising: A fin structure extending in a first direction is formed above a substrate. The fin structure has a height in a second direction transverse to the first direction and includes a stacked portion and a hard mask portion located above the stacked portion. The stacked portion includes alternating channel semiconductor portions and sacrificial semiconductor portions. The sacrificial semiconductor portions include a first sacrificial semiconductor portion in contact with the hard mask portion and a second sacrificial semiconductor portion located below the first sacrificial semiconductor portion. The first sacrificial semiconductor portion has a first etch rate to an etchant, and the second sacrificial semiconductor portion has a second etch rate to the etchant that is lower than the first etch rate. Laterally recessed first sacrificial semiconductor portion and second sacrificial semiconductor portion; and The recessed first sacrificial semiconductor portion and the recessed second sacrificial semiconductor portion are replaced with gate stacks to surround the channel semiconductor portion.

9. The method according to claim 8, wherein, Replacing the recessed first sacrificial semiconductor portion and the recessed second sacrificial semiconductor portion with a gate stack includes: An internal spacer is formed that contacts the sidewalls of the recessed first sacrificial semiconductor portion and the recessed second sacrificial semiconductor portion; Remove the recessed first sacrificial semiconductor portion and the recessed second sacrificial semiconductor portion to form a gap between the channel semiconductor portions and between the topmost channel semiconductor portion and the hard mask portion; and The gate stack is formed in the gap.

10. A semiconductor device, comprising: Multiple nanostructures are located above the substrate and extend along the length direction; Gate stacks surrounding each of the plurality of nanostructures; as well as The source / drain components are adjacent to the gate stack. The gate stack includes a first portion located on the top surface of the topmost nanostructure of the plurality of nanostructures and a second portion located between adjacent nanostructures of the plurality of nanostructures. The first portion has a first dimension in the length direction, and the second portion has a second dimension in the length direction that is greater than the first dimension.

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