Capacitor, storage element and method

Abstract

The device comprises: a substrate (110); a first nanostructure (22) above the substrate (110) comprising a semiconductor having a first resistance; a second nanostructure (26) above the substrate (110), offset laterally from the first nanostructure (22) at approximately the same height above the substrate (110) as the first nanostructure (22), comprising a conductor having a second resistance lower than the first resistance; a first gate structure (200A) above and surrounding the first nanostructure (22); and a second gate structure (200D) above and surrounding the second nanostructure (26), wherein the ratio of the first resistance to the second resistance is at least approximately 100.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US patent application No. 63 / 049,525 entitled “A GAA CAPACITANCE DEVICE STRUCTURE IN INTEGRATED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME”, filed on July 8, 2020, which is incorporated by reference into the present application. STATE OF THE ART

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be produced using a manufacturing process) has decreased. This downscaling process generally provides benefits by increasing manufacturing efficiency and reducing associated costs. However, this downscaling has also increased the complexity of IC fabrication and manufacturing. List of characters

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1A-1E are diagrammatic cross-sectional side views of sections of IC devices manufactured according to embodiments of the present disclosure. Fig. Figures 2A-10D are views of different embodiments of an IC component at different manufacturing stages according to different aspects of the present disclosure. Fig. Figure 11 is a flowchart illustrating a process for manufacturing a semiconductor device according to various aspects of the present disclosure. Fig. Figures 12A-15C are views of different embodiments of an IC device at different manufacturing stages according to different aspects of the present disclosure. Fig. Figure 16 is a flowchart illustrating a manufacturing process of a semiconductor device according to various aspects of the present disclosure. Fig. Figures 17-19 are views of different embodiments of an IC component at different manufacturing stages according to different aspects of the present disclosure. Fig. Figures 20-25 are diagrams of a system and process for manufacturing a semiconductor device layer according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "underlying," "below," "under," "overlying," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0006] This disclosure relates generally to semiconductor devices and, in particular, to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-conductor FETs (FinFETs), or gate-all-around (GAA) devices. Downscaling is becoming increasingly difficult in advanced technology nodes. Three-dimensional device structures, such as FinFETs and / or GAA devices, are promising for increasing device density by overcoming certain problems associated with downscaling. It is desirable to integrate not only transistor devices but also passive devices, such as capacitors, into advanced technology nodes. The techniques and structures described herein provide 3D GAA capacitor devices and fabrication methods for them, thereby increasing device density.

[0007] The 3D GAA capacitive device can be formed through various processes. A semiconductor lattice containing two semiconductor layer types, such as silicon and SiGe, is formed and structured to create active multilayer fins. The active fins are separated by isolation regions formed between them and recessed below the height of the active fins. In one configuration, the active fins are heavily doped by solid-state diffusion (SPD) or implantation. In another configuration, channels of the active fins are replaced with a conductor, such as a metal nitride. Dummy gate structures, internal spacers, and source / drain regions are formed. The dummy gate structures are replaced with active gate structures that include boundary layer(s), high-k-gate dielectric layer(s), and output work and other metal layers.Mid-end-of-line (MEOL) structures and back-end-of-line (BEOL) structures are formed over the 3D-GAA capacitance devices to provide metal conduction for electrical connection between the 3D-GAA capacitance devices and other circuit elements of an IC (Integrated Circuit).

[0008] Fig. Figure 1A illustrates a diagrammatic cross-sectional side view of a section of an IC device 10, manufactured according to embodiments of the present disclosure, wherein the IC device 10 comprises gate-all-around (GAA) devices 20N, 20C. The GAA devices 20N, 20C may, in some embodiments, comprise at least one NFET or one PFET. For example, the GAA device 20N is an NFET in some embodiments. The GAA device 20C is a GAA capacitor, which is an integrated capacitor, in accordance with some embodiments, and may alternatively be referred to throughout as "GAA capacitor 20C".

[0009] The cross-sectional view of the IC component 10 in Fig. 1A is taken along an XZ plane, where the X direction is the horizontal direction and the Z direction is the vertical direction. The GAA device 20N and the GAA capacitor 20C are similar in many respects, with one difference being that the GAA device 20N has channels 22A-22C (alternatively referred to as "nanostructures") over a fin structure 32, and the GAA capacitor 20C has doped channels 26A-26C (alternatively referred to as "doped nanostructures") over a doped fin structure 37.

[0010] In some embodiments, the doped channels 26A-26C and the doped fin structure 37 contain dopants such as boron, although other suitable dopants such as aluminum, gallium, indium, or the like may also be included. In some embodiments, the concentration of the dopants in the doped channels 26A-26C and the doped fin structure 37 ranges from approximately 1 × 10¹⁶ atoms / cm³ to approximately 1 × 10²⁹ atoms / cm³.3 For the sake of simplicity, channels 22A-22C and the doped channels 26A-26C may be referred to collectively as "channels 22A-22C, 26A-26C" in the following. In some embodiments, channels 22A-22C are lightly doped or undoped. In some embodiments, channels 22A-22C are doped with the same dopant(s) as the doped channels 26A-26C, but at a lower doping concentration. In some embodiments, the ratio of doping concentration (e.g., average doping concentration) in the doped channels 26A-26C to doping concentration (e.g., average doping concentration) in channels 22A-22C is greater than 100.

[0011] Channels 22A-22C and 26A-26C are laterally delimited by source / drain features 82 and covered and surrounded by gate structures 200A and 200D. Gate structure 200A controls the flow of electric current through channels 22A-22C based on voltages applied to gate structure 200A and source / drain features 82. Gate structure 200D acts as a first plate, or first electrode, of the GAA capacitor 20C. The doped channels 26A-26C and the doped fin structure 37 act as a second plate, or second electrode, of the GAA capacitor 20C.

[0012] In some embodiments, the doped channels 26A-26C are conductive, exhibiting a lower resistance than the first resistance of the semiconducting channels 22A-22C. In some embodiments, the ratio of the first resistance to the second resistance is greater than approximately 100. In some embodiments, both the first and second resistances are film resistors. In some embodiments, the second resistance is less than approximately 100 ohms squared. A second resistance greater than approximately 100 ohms squared can lead to unacceptable signal loss and signal delay. In some embodiments, the first resistance is measured when the gate structure 200A is biased at a voltage below the threshold voltage of the GAA device 20N. In some embodiments, the voltage is ground or floating.

[0013] In some embodiments, the fin structure 32 and the doped fin structure 37 contain silicon. In some embodiments, the GAA device 20N is an NFET and its source / drain features 82 contain silicon phosphorus (SiP). In some embodiments, the GAA device 20N is a PFET and its source / drain features 82 contain SiGe. In some embodiments, the GAA device 20C can be considered a P-type device and its source / drain features 82 contain SiGe.

[0014] Channels 22A-22C and 26A-26C each contain a semiconducting material, for example, silicon or a silicon compound such as silicon germanium or the like. Channels 22A-22C and 26A-26C are nanostructures (e.g., having sizes on the order of a few nanometers) and may each have an elongated shape extending in the X direction. In some embodiments, channels 22A-22C and 26A-26C each have a nanowire shape (NW shape), a nanosheet shape (NS shape), a nanotube shape (NT shape), or another suitable nanoscale shape. The cross-sectional profile of channels 22A-22C and 26A-26C may be rectangular, round, square, circular, elliptical, hexagonal, or combinations thereof.

[0015] In some embodiments, the lengths (e.g., measured in the X-direction) of channels 22A-22C and 26A-26C may differ, for example, due to tapering during a fin etching process. In some embodiments, the length of channel 22A may be shorter than the length of channel 22B, which in turn may be shorter than the length of channel 22C. Similarly, the length of doped channel 26A may be shorter than the length of doped channel 26B, which in turn may be shorter than the length of doped channel 26C. Channels 22A-22C and 26A-26C may not have a uniform thickness, for example, due to a channel trimming process used to widen the spacing (e.g., measured in the Z-direction) between channels 22A-22C and 26A-26C to extend the gate structure fabrication process window. For example, a middle section of each of the channels 22A-22C, 26A-26C can be thinner than the two ends of each of the channels 22A-22C, 26A-26C.Such a shape can collectively be described as a "dog bone" shape.

[0016] In some embodiments, the distance between channels 22A-22C, 26A-26C (e.g., between channel 22B and channel 22A or channel 22C) is in a range between approximately 8 nanometers (nm) and approximately 12 nm. In some embodiments, the thickness (e.g., measured in the Z-direction) of each of channels 22A-22C, 26A-26C is in a range between approximately 5 nm and approximately 8 nm. In some embodiments, the width (e.g., measured in the Y-direction, not in Fig. 1A shown, orthogonal to the XZ plane) each of the channels 22A-22C, 26A-26C at least about 8 nm.

[0017] Gate structures 200A and 200D are located above and between channels 22A-22C and 26A-26C, respectively. IC components such as IC component 10 often contain transistors with different threshold voltages based on their function within the IC. For example, input / output transistors (IO transistors) typically have the highest threshold voltages due to the high current handling required by IO transistors. Core logic transistors typically have the lowest threshold voltages to achieve higher switching speeds at lower power consumption. A third threshold voltage, between that of the 10 transistors and that of the core logic transistors, may also be used for certain other functional transistors, such as static random-access memory (SRAM) transistors.Some circuit blocks within the IC component 10 can include two or more NFETs and / or PFEs with two or more different threshold voltages. Thoughtful design of the gate structure 200A can provide threshold voltage tuning for the GAA component 20N.

[0018] In some embodiments, threshold voltage tuning is achieved by driving at least one specific dopant into one or more gate dielectric layers 600 of the gate structures 200A. In some embodiments, threshold voltage tuning is alternatively or further achieved by incorporating one or more barrier layers 700 (also referred to as "outflow barrier layers", see Fig. 13A-14C) are added between the gate dielectric layers 600 and the metal filler layer 290.

[0019] A first boundary layer (IL) 210, which may be an oxide of the material of channels 22A-22C, 26A-26C, is formed on exposed areas of channels 22A-22C, 26A-26C and the top surface of fin 32. The first IL 210 promotes adhesion of the gate dielectric layers 600 to channels 22A-22C, 26A-26C. In some embodiments, the first IL 210 has a thickness of about 5 angstroms (Å) to about 50 angstroms (Å). In some embodiments, the first IL 210 has a thickness of about 10 Å. If the first IL 210 has a thickness that is too thin, it may exhibit gaps or insufficient adhesion properties. If the first IL 210 is too thick, it consumes the gate fill window, which affects threshold voltage tuning and resistance. In some embodiments, the thickness of the first IL 210 in the 200A gate structure can be essentially the same as the thickness of the first IL 210 in the 200D gate structure.In some embodiments, the thicknesses of the first ILs 210 of the gate structures 200A, 200D differ by at least approximately 2 angstroms or by at least approximately 20%. In some embodiments, the thickness of the first IL 210 over channels 22A, 26A is greater than the thickness over channels 22B, 26B, which in turn is greater than the thickness over channels 22C, 26C, which is greater than the thickness over fin 32 or the doped fin structure 37.

[0020] In some embodiments, the gate dielectric layers 600 contain a high-k dielectric material, which may refer to dielectric materials exhibiting a high dielectric constant greater than that of silicon dioxide (k ≈ 3.9). Exemplary high-k dielectric materials include HfO₂, HfSiO₂, HfSiON₂, HfTaO₂, HfTiO₂, HfZrO₂, ZrO₂, Ta₂O₅, or combinations thereof. In some embodiments, the dielectric layers 600 in gate structure 200A have a different material composition than the gate dielectric layers 600 in gate structure 200D. In some embodiments, the gate dielectric layers 600 have a total thickness of about 10 Å to about 100 Å, which may be similar to, or slightly thicker than, the first IL 210.In some embodiments, the thickness of the dielectric layers 600 over the channels 22A, 26A is greater than over the channels 22B, 26B, which is greater than over the channels 22C, 26C, which is greater than over the fin 32 or the doped fin structure 37.

[0021] In some embodiments, at least one of the gate dielectric layers 600 may contain further dopants, such as metal ions driven into the high-k gate dielectric by La₂O₃, MgO, Y₂O₃, TiO₂, Al₂O₃, Nb₂O₅, or the like, or boron ions driven in by B₂O₃, at a concentration to achieve threshold voltage tuning, while other gate dielectric layers 600 are essentially free of the dopants. As an example, for N-type transistors, lanthanum ions at a higher concentration reduce the threshold voltage relative to layers with a lower concentration or free of lanthanum ions, while the opposite is true for P-type devices.

[0022] The gate structures 200A and 200D further comprise one or more exit metal layers, collectively represented as exit metal layers 900. In the GAA device 20N, which in most embodiments is an NFET, the exit metal layers 900 may comprise at least one N exit metal layer, an in-situ termination layer, and an oxygen blocking layer. In some embodiments, the exit metal layers 900 comprise more or fewer layers than described. In the GAA capacitor 20C, which in most embodiments is P, the exit metal layers 900 are essentially the same as in the GAA device 20N.

[0023] The gate structures 200A and 200D also feature a metal filler layer 290. The metal filler layer 290 can contain a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. Between channels 22A-22C and 26A-26C, the metal filler layer 290 is surrounded (in cross-sectional view) by one or more exit work metal layers 900, which are then surrounded by the gate dielectric layers 600. In the section of the gate structures 200A and 200D formed above channel 22A and 26A most distal to fin 32 and 37, the metal filler layer 290 is formed above one or more exit work metal layers 900. The one or more exit work metal layers 900 are wound around the metal filler layer 290. The gate dielectric layers 600 are also wound around the one or more exit work metal layers 900.The gate structures 200A, 200D can also have an adhesive layer formed between the one or more exit working layers 900 and the metal filler layer 290 to increase adhesion. For simplicity, the adhesive layer is shown in . Fig. 1A is not particularly illustrated, but it will be in Fig. 15A-15C shown.

[0024] The GAA devices 20N, 20C also feature gate spacers 41 and internal spacers 74 arranged on the side walls of the first gate dielectric layers 222, 220. The internal spacers 74 are also arranged between channels 22A-22C, 26A-26C. The gate spacers 41 and the internal spacers 74 can contain a dielectric material, for example, a low-k material such as SiOCN, SiON, SiN, or SiOC.

[0025] The GAA devices 20N, 20C further feature source / drain contacts 120 formed over the source / drain features 82. The source / drain contacts 120 may contain a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. The source / drain contacts 120 may be surrounded by barrier layers (not shown), such as SiN or TiN, which help to prevent or reduce diffusion of materials to and from the source / drain contacts 120. A silicide layer 118 may also be formed between the source / drain features 82 and the source / drain contacts 120 to reduce the source / drain contact resistance. The silicide layer 118 may contain a metal silicide material, such as cobalt silicide in some embodiments, or TiSi in some other embodiments.

[0026] The GAA devices 20N, 20C further feature an interlayer dielectric (ILD) 130. The ILD 130 provides electrical insulation between the various components of the GAA devices 20N, 20C discussed above, for example between the gate structures 200A, 200D and the source / drain contacts 120.

[0027] Figure iB illustrates the GAA component 20N and a GAA component 20D in accordance with various embodiments. The GAA components 20N, 20D, which are shown in Fig. The components shown in Figure 1B are in many respects similar to the GAA components 20N and 20C, which are shown in Figure 1B. Fig. 1A are shown, and similar reference symbols refer to similar components. In the GAA component 20D of Fig. In 1B, the heavily doped channels 26A-26C are replaced by channels 28A-28C. In some embodiments, the channels 28A-28C are or contain conductive material, such as a metal nitride (e.g., TiN, TaN) or another suitable material. In some embodiments, the channels 28A-28C have a third resistance, and the ratio of the first resistance of the channels 22A-22C to the third resistance is at least approximately 100. In some embodiments, the source / drain features 82 are further replaced by conductive features 84. In some embodiments, the conductive features 84 are or contain a metal nitride, such as TiN or another suitable material. In some embodiments, the material of the channels 28A-28C is the same as the material of the conductive features 84 or different from it. In some embodiments, the doped fin structure 37 is replaced by a conductive fin structure 33.In some embodiments, the conductive fin structure 33 is a metal nitride or contains one, such as TiN, TaN, or another suitable material. In some embodiments, a buffer layer 34 is further incorporated in the GAA devices 20A, 20D. In some embodiments, the buffer layer 34 is silicon nitride, SiC, SiCN, SiOCN, SiON, or the like, or contains one.

[0028] Continue to Fig. 1B, by forming the channels 28A-28C, the conductive features 84, and the conductive fin structure 33 in an exchange process, the doping process used to form the doped channels 26A-26C can be omitted, thus simplifying the manufacturing process. A description of the exchange process can be given in relation to Fig. 17-19 can be found.

[0029] Fig. Figures 1C-1E illustrate the stacking of a first wafer 100A onto a second wafer 100B in various configurations.

[0030] In Fig. 1C, the first wafer 100A has at least two of the in Fig. Wafer 1B illustrates the GAA device 20N. The second wafer 100B has at least one of both the GAA device 20N and the GAA device 20C, which are shown in Fig. Figure 1A illustrates this. In some embodiments, the first wafer 100A is free of the GAA capacitors 20C, 20D. In some embodiments, the GAA component 20N and the GAA capacitor 20C of the second wafer 100B are directly adjacent to each other, with no intervening active components. Both the first wafer 100A and the second wafer 100B have a front-side interconnect structure 121. The first wafer 100A further has a back-side interconnect structure 129, which is physically and electrically coupled to the front-side interconnect structure 121 of the second wafer 100B, for example, by front-to-back hybrid bonds. In some embodiments, the second wafer 100B does not have the back-side interconnect structure 129, as shown in Figure 1A. Fig. 1C shown. While the first wafer 100A and the second wafer 100B are described as “wafers” in the preceding description, it should be understood that in some embodiments the first wafer 100A and the second wafer 100B are individual dies 100A, 100B, which are separated from either a single semiconductor wafer or two different semiconductor wafers.

[0031] The front-side interconnect structure 121 has conductive features 122-123 in insulating layers 125, 126 in the first wafer 100A, and conductive features 122, 124 in the second wafer 100B. In some embodiments, the conductive features 122-124 are metallization features, such as vias, wires, traces, or the like, and the insulating layers 125-126 are interlayer dielectric (ILD) layers. Only the uppermost two insulating layers 125-126 of the interconnect structure 121 are in Fig. Figure 1C shows that in some embodiments, each of the interconnect structures 121 has more than two insulating layers 125-126 and more than two conductive features 122-123 or 122, 124 stacked vertically above the source / drain contacts 120 of each of the first and second wafers 100A and 100B, respectively. In some embodiments, the conductive features 122, 123, 124 form an electrical connection with one of the source / drain contacts 120.

[0032] In some embodiments, the conductive features 123, 124 can be formed before or after singulation. The uppermost dielectric layer, e.g., the insulating layer 126 of the interconnect structure 121, can be structured to expose sections of the underlying metallization structures. In some embodiments, underbump metallurgies (UBMs) can be formed in the openings. The conductive features 123, 124 are then formed on the UBMs. The conductive features 123, 124 can be solder balls, metal pillars, ball-grid array (BGA) connectors, flip-chip bumps (C4 bumps), microbumps, bumps formed by the electroless nickel-electroless palladium gold plating (ENEPIG) technique, or the like. The conductive features 123, 124 can be formed from a metal or metal alloy, such as solder, copper, aluminium, gold, nickel, silver, palladium, tin, the like or a combination thereof.In some embodiments, the conductive features 123, 124 are formed by initially creating a layer of solder using conventional methods such as evaporation, electroplating, printing, solder transfer, bead placement, or the like. Once a layer of solder has formed on the structure, melting can be performed to shape the material into the desired bump forms. In another embodiment, the conductive features 123, 124 are metal columns (such as a copper column) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns can be solder-free and have substantially vertical sidewalls. The conductive features 123, 124 are electrically coupled to the metallization structures of the interconnect structure 121.

[0033] The backside interconnect structure 129 has a conductive feature 127 in the insulating layer 128 of the first wafer 100A. The conductive feature 127 is electrically connected to a backside via 125 formed on one of the source / drain features 82. In some embodiments, the backside via 125 is formed on the same source / drain feature 82 that is also electrically connected to the conductive features 122, 123 or 122, 124. Only the insulating bottom layer 128 of the interconnect structure 129 and the conductive feature 127 are in Fig. 1C shown. In some embodiments, each of the interconnect structures 129 has more than one insulating layer 128 and more than one conductive feature 127 stacked vertically across the backside via 125.

[0034] The first wafer 100A and the second wafer 100B are bonded directly in a back-to-front manner, e.g., by hybrid bonding, such that the back sides of the GAA devices 20N of the first wafer 100A are electrically connected to the front sides of the GAA devices 20C, 20N of the second wafer 100B. Specifically, the insulating layer 128 of the first wafer 100A is bonded to the insulating layer 126 of the second wafer 100B by dielectric-to-dielectric bonding without the use of an adhesive material (e.g., die adhesive film), and the conductive features 127 of the first wafer 100A are bonded to the conductive features 124 of the second wafer 100B by metal-to-metal bonding without the use of any eutectic material (e.g., solder).As described in terms of hybrid bonding, the first wafer 100A and the second wafer 100B can be bonded by aligning solder bumps or other meltable conductive materials of the conductive features 127, 124 and melting the conductive features 127, 124 so that the conductive features 127, 124 form solder joints, establishing the physical and electrical connection between the first and second wafer 100A, 100B.

[0035] After bonding, a first component 150A and a second component 150B are formed in the first and second wafers 100A and 100B, respectively. In some embodiments, the first component 150A is a dynamic random-access memory (DRAM) component comprising the GAA component 20N of the first wafer 100A and the GAA capacitor 20C of the second wafer 100B in a one-transistor-one-capacitor configuration (1T1C configuration). In some embodiments, the second component 150B is a two-transistor circuit component (2T circuit component), such as a buffer, converter, amplifier, or other component, which can be determined by connecting the gate, source, and drain terminals of the GAA components 20N of the second component 150B. The use of the GAA capacitor 20C increases component density as well as design flexibility for wafer-level or component-level packages.

[0036] In Fig. In 1D, the first wafer 100A is stacked with a third wafer 100C, which is similar in many respects to the second wafer 100B. In some embodiments, the entirety, a die region, a functional region, or other part of the third wafer 100C comprises an array of GAA capacitors 20C free of GAA devices 20N. In some embodiments, the entirety, a die region, a functional region, or other part of the first wafer 100A comprises a corresponding array of GAA devices 20N free of GAA capacitors 20C. While the number of channels 22, 26, which in Fig. As illustrated in Figure 1D, where the GAA devices 20N and the GAA capacitors 20C are the same, in some embodiments each of the GAA capacitors 20C has at least one more channel 26 than the channels 22 in the GAA device 20N. By having a larger number of channels 26 in the GAA capacitors 20C, the capacitance of the GAA capacitors 20C can be increased, which is advantageous for forming the GAA capacitors 20C in the third wafer 100C, which is free of GAA devices 20N. By aligning the arrays of GAA capacitors 20C and GAA devices 20N and bonding the first wafer 100A to the third wafer 100C, similar to what was done previously with respect to Fig. As described in 1C, a first component 150A1 and a second component 150B1 are formed. In some embodiments, the first and second components 150A1, 150B1 are both DRAM components in the 1T1C configuration. Therefore, a large array (having many cells) of DRAM components with high component density can be formed by bonding the first wafer 100A to the third wafer 100C, as shown.

[0037] In Fig. 1E is a fifth wafer 100E stacked with a fourth wafer 100D. The fifth wafer 100E is similar to the first wafer 100A in many respects, except that the substrate of the fifth wafer 100E is not removed and no backside via or other backside interconnect structure is formed on the fifth wafer 100E. The fourth wafer 100D is similar to the second wafer 100B in many respects, but instead of having the GAA devices 20C, the fourth wafer 100D has the GAA devices 20D. In some embodiments, the entirety, a die region, a functional region, or other part of the fourth wafer 100D has an array of the GAA capacitors 20D, which are free of the GAA devices 20N. In some embodiments, the entirety, a die area, a functional area or other of the fifth wafer 100E includes a corresponding array of the GAA devices 20N, which are free of the GAA capacitors 20C, 20D.While the number of channels is 22 and channels are 28, which are in . Fig. As illustrated in Figure 1E, where the GAA devices 20N and the GAA capacitors 20D are the same, in some embodiments each of the GAA capacitors 20D has at least one more channel 28 than the channels 22 in the GAA device 20N. By having a larger number of channels 28 in the GAA capacitors 20D, the capacitance of the GAA capacitors 20D can be increased, which is advantageous for forming the GAA capacitors 20D in the fourth wafer 100D, which is free of GAA devices 20N. By aligning the arrays of GAA capacitors 20D and GAA devices 20N and aligning the fifth wafer 100E with the fourth wafer 100D similarly to the previous one with respect to Fig. As described in the 1C configuration, bonding creates a first component 150C1 and a second component 150C2. In some embodiments, the first and second components 150C1 and 150C2 are both DRAM components in the 1T1C configuration. Therefore, a large array (having many cells) of high-density DRAM components can be formed by bonding the fifth wafer 100E to the fourth wafer 100D, as shown.

[0038] Additional details relating to the manufacture of GAA devices are disclosed in US Patent No. 10,164,012, entitled “Semiconductor Device and Manufacturing Method Thereof”, published on December 25, 2018, as well as in US Patent No. 10,361,278, “Method of Manufacturing a Semiconductor Device and a Semiconductor Device”, published on July 23, 2019, which is incorporated by reference into the present application.

[0039] Fig. Figure 11 illustrates a flowchart illustrating a method 100 for forming an IC device, or a portion thereof, from a workpiece according to one or more aspects of the present disclosure. Method 1000 is merely an example and is not intended to limit the present disclosure to what is expressly illustrated in method 1000. Additional actions may be provided before, during, and after method 1000, and some of the described actions may be substituted, eliminated, or deferred for additional embodiments of the methods. For simplicity, not all actions are described herein in detail. Method 1000 is shown below in conjunction with partial cross-sectional views of a workpiece (in Figure 11). Fig. (2A-10D shown) at different manufacturing stages according to embodiments of Method 1000. To avoid any doubt, throughout the figures the X-direction is perpendicular to the Y-direction and the Z-direction is perpendicular to both the X-direction and the Y-direction. It is noted that because the workpiece can be manufactured to form a semiconductor device, the workpiece may be referred to as the semiconductor device, as the context requires.

[0040] Fig. 2A to Fig. 10D are perspective views and cross-sectional views of intermediate stages in the fabrication of nano-FETs in accordance with some embodiments. Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A and Fig. 10A illustrates perspective views. Fig. 2B, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B and Fig. Figure 10B illustrates reference cross-section BB' (gate section), which is shown in Fig. 2A, Fig. 3A and Fig. 4A is illustrated. Fig. 4C, Fig. 5C, Fig. 6C, Fig. 7C, Fig. 8C, Fig. 9C and Fig. Figure 10C illustrates reference cross-section DD' (doped channel / fin section), which is in Fig. 4A is illustrated.

[0041] In Fig. 2A and Fig. 2B provides a substrate 110. The substrate 110 can be a semiconductor substrate, such as a bulk semiconductor, or the like, which may be doped (e.g., with p- or n-type dopants) or undoped. The semiconductor material of the substrate 110 can be silicon; germanium; a compound semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor containing silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as single-layer, multi-layer, or graded substrates, may be used.

[0042] Continue in Fig. 2A and Fig. In some embodiments, a buffer layer 140 is formed over the substrate 110. The buffer layer 140 can be a nitride layer, such as a SiN layer, or another suitable material layer. In some embodiments, the buffer layer 140 is not formed. The buffer layer 140 can be used in subsequent operations to form backside contacts and interconnects for the GAA device 20N, the GAA device 20C, and / or the GAA device 20D. Following the formation of the buffer layer 140, a semiconductor layer 31 can be formed on the buffer layer 140. In some embodiments, the semiconductor layer 31 comprises the same material as the substrate 110, e.g., silicon.

[0043] Following the formation of the semiconductor layer 31, a multilayer stack 25 or “lattice” of alternating layers of first semiconductor layers 21A-21C (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23A-23C (collectively referred to as second semiconductor layers 23) is formed over the substrate 110, the buffer layer 140, and the semiconductor layer 31. In some embodiments, the first semiconductor layers 21 can be formed from a first semiconductor material suitable for n-nanoFETs, such as silicon, silicon carbide, or the like, and the second semiconductor layers 23 can be formed from a second semiconductor material suitable for p-nanoFETs, such as silicon germanium or the like. In some embodiments, the first semiconductor layers 21 are formed from the second semiconductor material, and the second semiconductor layers 23 are formed from the first semiconductor material.Each layer of the multilayer stack 25 can be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor deposition (VDE), molecular beam epitaxy (MBE), or the like. In some embodiments, when the buffer layer 140 and the semiconductor layer 31 are not formed, the multilayer stack 25 can be formed to contact the substrate 110.

[0044] Three layers of both the first semiconductor layers 21 and the second semiconductor layers 23 are illustrated. In some embodiments, the multilayer stack 25 can have one, two, four, or more of the first semiconductor layers 21 and the second semiconductor layers 23. Although the multilayer stack 25 is illustrated to have a second semiconductor layer 23C as the bottom layer, in some embodiments the bottom layer of the multilayer stack 25 can be a first semiconductor layer 21.

[0045] Due to high etch selectivity between the first and second semiconductor materials, the second semiconductor layers 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layers 12 of the first semiconductor material, thus allowing the first semiconductor layers 21 to be structured to form channel regions of nanoFETs. In some embodiments, the first semiconductor layers 21 are removed and the second semiconductor layers 23 are structured to form channel regions. The high etch selectivity allows the first semiconductor layers 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layers 23 of the second semiconductor material, thus allowing the second semiconductor layers 23 to be structured to form channel regions of nanoFETs.

[0046] In Fig. 3A and Fig. 3B fins 32 are formed in the semiconductor layer 31 and nanostructures 22, 24 are formed in the multilayer stack 25, according to action 1100 of Fig. 11. In some embodiments, the nanostructures 22, 24 and the fins 32 can be formed by etching trenches in the multilayer stack 25 and the semiconductor layer 31. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. First nanostructures 22A-22C (hereinafter also referred to as "channels") are formed from the first semiconductor layers 21, and second nanostructures 24A-24C are formed from the second semiconductor layers 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 can be from about 18 nm to about 100 nm.

[0047] The fins 32 and the nanostructures 22, 24 can be structured by any suitable method. For example, one or more photolithography processes, including dual-structuring or multi-structuring processes, can be used to form the fins 32 and the nanostructures 22, 24. In general, dual-structuring or multi-structuring processes combine photolithography and self-aligning processes, allowing for smaller spacings than would otherwise be obtainable using a single direct photolithography process. As an example of a multi-structuring process, a sacrificial layer can be formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can be used to structure the fins 32.

[0048] Fig. Figures 3A-3D illustrate the fins 32, which have tapered sidewalls such that the width of each of the fins 32 and / or the nanostructures 22, 24 increases continuously in one direction towards the substrate 110. In such embodiments, each of the nanostructures 22, 24 can have a different width and be trapezoidal. In other embodiments, the sidewalls are essentially vertical (not tapered), so that the width of the fins 32 and the nanostructures 22, 24 is essentially similar, and each of the nanostructures 22, 24 is rectangular.

[0049] In Fig. 3A-3D are isolation regions 36, which can be trench isolation regions (STI regions), formed adjacent to the fins 32. The isolation regions 36 can be formed by depositing an insulating material over the substrate 110, the buffer layer 140, the fins 32, and nanostructures 22, 24, and between adjacent fins 32 and nanostructures 22, 24. The insulating material can be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FVCD), the like, or a combination thereof. In some embodiments, a lining (not shown separately) can first be formed along the surfaces of the buffer layer 140, the fins 32, and the nanostructures 22, 24. Subsequently, a filler material, such as those discussed previously, can be formed over the lining.

[0050] The insulating material undergoes a removal process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, to remove excess insulating material from the nanostructures 22, 24. The top surfaces of the nanostructures 22, 24 can be exposed and be flush with the insulating material after the removal process is complete.

[0051] The insulating material is then deepened to form the insulating regions 36. After deepening, the nanostructures 22, 24 and upper portions of the fins 32 can project between adjacent insulating regions 36. The insulating regions 36 can have top surfaces that are flat, as illustrated, convex, concave, or a combination thereof. In some embodiments, the insulating regions 36 are deepened by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective for the insulating material and leaves the fins 32 and the nanostructures 22, 24 essentially unchanged.

[0052] Fig. 2A to Fig. Figure 3B illustrates one embodiment (e.g., etch-last) for forming the fins 66 and the nanostructures 55. In some embodiments, the fins 32 and / or the nanostructures 22, 24 are epitaxially grown in trenches in a dielectric layer (e.g., etch-first). The epitaxial structures can contain the previously discussed alternating semiconductor materials, such as the first semiconductor materials and the second semiconductor materials.

[0053] Further information can be found in Fig. 3A and Fig. 3B Appropriate wells (not illustrated separately) are formed in the fins 32, the nanostructures 22, 24, and / or the isolation regions 36. Using masks, an n-impurity implantation can be performed in p-regions of the substrate 110, and a p-impurity implantation can be performed in n-regions of the substrate 110. Exemplary n-impurities may include phosphorus, arsenic, antimony, or the like. Exemplary p-impurities may include boron, boron fluoride, indium, or the like. Annealing can be performed after the implantations to repair implantation damage and activate the p- and / or n-impurities. In some embodiments, in-situ doping during epitaxial growth of the fins 32 and the nanostructures 22, 24 can avoid separate implantations, although in-situ and implantation doping can be used together.

[0054] In Fig. 3C-3D are the doped channels 26 and the doped fin structure 37 formed by a process 800 by which dopants are introduced into the nanostructures 22, according to action 1200 of Fig. 11. As in Fig. As shown in Figure 3C, one or more of the stacks of nanostructures 22, 24 can be masked during process 800. In some embodiments, process 800 is a solid-phase diffusion (SPD) process performed to dope the exposed nanostructures 22 to form the doped channels 26. In other embodiments, process 800 to form the doped channels 26 is an ion implantation process performed on the exposed nanostructures 22. The resulting structure is shown in Fig. shown in 3D. Fig. The 3D-shown structure can be used to configure the second wafer 100B. Fig. 1C. If no stacks of the nanostructures 22, 24 are masked during process 800, all of the nanostructures 22 will be the doped channels 26, which can correspond to the configuration of the third wafer 100C, which is in Fig. It is shown in 1D.

[0055] In some embodiments, the dopants contain boron, although other suitable dopants such as aluminum, gallium, indium, or the like may also be included. In some embodiments, the concentration of the dopants in the doped channels 26A-26C and the doped fin structure 37 is in a range of approximately 1 × 10¹⁶ atoms / cm². 3 up to about 1E21 atoms / cm² 3Therefore, the doped channels 26 and the doped fin structure 37 can be described as "heavily doped". In some embodiments, doping of the doped channels 26 and the doped fin structure 37 does not result in doping of the entire fin 32, so that a lower region 39 of the fins 32 is essentially free of dopants or only lightly doped, exhibiting a doping concentration of less than about 1 × 10¹³ atoms / cm². 3 In some embodiments, there is no sharp interface between the doped fin structure 37 and the lower region 29, and the doping concentration decreases stepwise from the heavily doped, doped fin structure 37 to the undoped or lightly doped lower region 39.

[0056] In Fig. 4A-4D are dummy gate structures 40 formed over the fin 32, the doped fin 37, the doped channels 26 and / or the nanostructures 22, 24, according to action 1300 of Fig. 11. A dummy gate layer 45 is formed over the fin 32, the doped fin 37, the doped channels 26, and / or the nanostructures 22, 24. The dummy gate layer 45 can be made of materials exhibiting high etch selectivity towards the isolation regions 36. The dummy gate layer 45 can be a conductive, semiconducting, or nonconducting material and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer 45 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing the selected material. A mask layer 47 is formed over the dummy gate layer 45 and can contain, for example, silicon nitride, silicon oxynitride or the like.In some embodiments, a gate dielectric layer (not illustrated for simplicity) is formed before the dummy gate layer 45 is formed between the dummy gate layer 45 and the fin 32, the doped fin 37, the doped channels 26 and / or the nanostructures 22, 24.

[0057] A spacer layer 41 is formed over the sidewalls of the mask layer 47 and the dummy gate layer 45. The spacer layer 41 is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and may have a single-layer structure or a multi-layer structure comprising a plurality of dielectric layers, according to some embodiments. The spacer layer 41 can be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. Sections of the spacer material layer between dummy gate structures 40 are removed using an anisotropic etching process, according to some embodiments.

[0058] In Fig. In 5A-5D, an etching process is performed to etch the portions of the protruding fin 32, doped fin structure 37, lower region 39, doped channels 26, and / or nanostructures 22, 24 that are not covered by dummy gate structures 40, resulting in the structure shown. The recession can be anisotropic, so that the portions of the fin 32, doped fin structure 37, lower region 39, doped channels 26, and / or nanostructures 22, 24 that lie directly beneath dummy gate structures 40 and the spacer layer 41 are protected and not etched. According to some embodiments, the top surfaces of the recessed fin 32 and doped fin structure 37 can be substantially coplanar with the top surfaces of the isolation regions 36, as shown.The upper surfaces of the recessed fin 32 and the doped fin structure 37 can be lower than the upper surfaces of the insulation areas 36 in accordance with some other embodiments.

[0059] Fig. 6A-6D and Fig. 7A-7D illustrate the formation of internal spacers 74 according to action 1400 of Fig. 11. A selective etching process is performed to deepen end sections of the nanostructures 24 that are exposed by openings in the spacer layer 41, without substantially attacking the nanostructures 22 and / or the doped channels 26. After the selective etching process, depressions 64 are formed in the nanostructures 24 at the locations where the removed end sections were. The resulting structure is in Fig. 6A-6C shown.

[0060] Next, an internal spacer layer is formed to fill the wells 64 in the nanostructures 24 created by the previous selective etching process. The internal spacer layer can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like, formed by a suitable deposition process, such as PVD, CVD, ALD, or the like. An etching process, such as an anisotropic etching process, is performed to remove sections of the internal spacer layer that are located outside the wells in the nanostructures 24. The remaining sections of the internal spacer layer (e.g., sections located inside the wells 64 in the nanostructures 24) form the internal spacers 74. The resulting structure is described in Fig. 7A-7D shown.

[0061] Fig. Figures 8A-8D illustrate the formation of source / drain systems. Figure 82 corresponds to action 1500 of Fig. 11. In the illustrated embodiment, the source / drain regions 82 are epitaxially grown from epitaxial (epitaxial) material(s). In some embodiments, the source / drain regions 82 exert voltage in the respective channels 22A-22C and / or the doped channels 26A-26C, thereby improving performance. The source / drain regions 82 are formed such that each dummy gate structure 40 is located between respective adjacent pairs of source / drain regions 82. In some embodiments, the spacer layer 41 separates the source / drain regions 82 from the dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to downstream gates of the resulting device.

[0062] The source / drain regions 82 may contain any acceptable material, as is appropriate for n- or p-type devices. For n-type devices, the source / drain regions 82 contain materials that exert tensile force in the channel regions, such as silicon, SiC, SiCP, SiP, or the like, in some embodiments. When p-type devices are formed, the source / drain regions 82 contain materials that exert compressive deformation in the channel regions, such as SiGe, SiGeB, Ge, GeSn, or the like, according to certain embodiments. The source / drain regions 82 may have surfaces that are raised from the respective surfaces of the fins and may have facets. Adjacent source / drain regions 82 can converge in some embodiments to form a single source / drain region 82 that borders two adjacent fins 32 or two adjacent doped fin structures 37.

[0063] The source / drain regions 82 can be implanted with dopants, followed by annealing. The source / drain regions can accommodate an impurity concentration of approximately 10 19 cm -3 and about 10 21 cm -3 The nitrogen and / or p-impurities for source / drain regions 82 can be any of the impurities discussed previously. In some embodiments, the source / drain regions 82 are doped in situ during growth. A contact etch stop layer (CESL) and an interlayer dielectric (ILD), not illustrated for simplicity, can then be formed covering the dummy gate structures 40 and the source / drain regions 82.

[0064] Fig. 9A, Fig. 9B and Fig. Figure 9C illustrates the release of fin channels 22A-22C and doped channels 26A-26C by removing the nanostructures 24A-24C, the mask layer 47 and the dummy gate layer 45, which is action 1600 of Fig. 11 corresponds. A planarization process, such as a CMP, is performed to flatten the top surfaces of the dummy gate layer 45 and gate spacer layer 41. The planarization process can also flatten the mask layer 47 (see Fig. 8A) on the dummy gate layer 45 and remove sections of the gate spacer 41 along the side walls of the mask layer 47. Accordingly, the top surfaces of the dummy gate layer 45 are exposed.

[0065] Next, the dummy gate layer 45 is removed in an etching process, forming depressions 92. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may involve a dry etching process using reactive gas(es) that selectively etches the dummy gate layer 45 without etching the spacer layer 41. The dummy gate dielectric, if present, can be used as an etch stop layer when the dummy gate layer 45 is etched. The dummy gate dielectric can then be removed after the dummy gate layer 45 has been removed.

[0066] The nanostructures 24 are removed to expose the nanostructures 22 and the doped channels 26. After the nanostructures 24 are removed, the nanostructures 22 form a multitude of nanosheets extending horizontally (e.g., parallel to an upper main surface of the substrate 110), and the doped channels 26 similarly form a multitude of nanosheets also extending horizontally. The nanosheets can be collectively referred to as the channels 22 and the doped channels 26 of the GAA devices 20N, 20C.

[0067] In some embodiments, the nanostructures 24 are removed by a selective etching process using an etchant that is selective for the material of the nanostructures 24, such that the nanostructures 24 are removed without substantially attacking the nanostructures 22 and / or the doped channels 26. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, where the etching gas comprises F2 and HF and the carrier gas can be an inert gas such as Ar, He, N2, combinations thereof, or the like.

[0068] In some embodiments, the nanosheets 22 and the doped channels 26 of the GAA devices 20N, 20C are reshaped (e.g., thinned) by a further etching process to improve a gate fill window. The reshaping can be performed by an isotropic etching process that is selective for the nanosheets 22 and the doped channels 26. After reshaping, the nanosheets 22 and the doped channels 26 can exhibit a dogbone shape, in which the central sections of the nanosheets 22 and the doped channels 26 are thinner than the circumferential sections of the nanosheets 22 and the doped channels 26 along the X-direction.

[0069] Next, in Fig. 10A-10C, replacement gates 200, like gate structures 200A, 200D, are formed, according to action 1700 of Fig. 11. Each replacement gate 200 generally has a first IL 210, a first gate dielectric layer 220-222, a second gate dielectric layer 230, a second IL layer 240, exit work metal layers 900 and a gate filler layer 290 (see Fig. 15A-15C). In some embodiments, the replacement gates 200 further feature a second exit working layer 700 (see Fig. 15C). Cross-sections of the formation of gate structures 200A, 200D, as well as another gate structure 200B, are shown in relation to Fig. 12A to Fig. 15C provided. A flowchart of a procedure for forming the gate structures 200A, 200B, 200D is in Fig. 16 illustrated.

[0070] Additional processing can be carried out to complete the fabrication of the GAA device 20N and / or the GAA device 20C. For example, gate contacts (not illustrated for simplicity) and the source / drain contacts 120 can be formed to couple electrically with the gate structures 200 and the source / drain regions 82, respectively, according to action 1800 of Fig. 11. An interconnect structure can then be formed via the source / drain contacts 120 and the gate contacts, according to action 1800 of Fig. 11. The interconnect structure can have a variety of dielectric layers surrounding metallic features, conductive traces and conductive vias that form electrical connections between components on the substrate 110, such as the GAA components 20N, 20C, as well as to IC components outside the IC component 10.

[0071] In some embodiments, the gate structures 200 can be formed on the same wafer and / or be parts of the same IC device. Therefore, at least some of the manufacturing processes discussed below can be performed on all the gate structures 200 simultaneously.

[0072] Fig. Figures 12A-12C illustrate gate structures 200A, 200B, 200D at an intermediate manufacturing stage, in which each gate structure 200A, 200B, 200D carries the first IL 210 over channels 22A-22C of Fig. 1A formed, according to action 2100 of Fig. 16. For simplicity, only a section of channel 22A is shown as an example in Fig. 2A-19F illustrates this. In some embodiments, the first IL 210 contains an oxide of the semiconductor material of the substrate 110, e.g., silicon oxide. In other embodiments, the first IL 210 may contain another suitable type of dielectric material. The first IL 210 has a thickness 215 (in the Z direction of Fig. (measured at 12A). In some embodiments, the thickness 215 is in a range between approximately 5 angstroms and approximately 50 angstroms. In some embodiments, the thickness 215 is approximately 10 angstroms.

[0073] Still in relation to Fig. 12A-12C is the first gate dielectric layer 220 formed over the first IL 210, according to action 2200 of Fig. 16. In some embodiments, an atomic layer deposition (ALD) process is used to form the first gate dielectric layer 220, in order to precisely control the thickness of the deposited first gate dielectric layer 220. In some embodiments, the ALD process is carried out using about 20 to 40 deposition cycles at a temperature range of about 200 degrees Celsius to about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and / or H2O as precursors. Such an ALD process can form the first gate dielectric layer 220 to have a thickness 225 that can be in a range between about 5 angstroms and about 50 angstroms. In some embodiments, the thickness 225 is about 9 angstroms.

[0074] In some embodiments, and as previously mentioned in relation to Fig. As described in Figure 1A, the first gate dielectric layer 220 contains a high-k dielectric material, which can refer to dielectric materials that have a high dielectric constant greater than that of silicon dioxide (k ≈ 3.9). Examples of high-k dielectric materials include HfO₂, HfSiO₂, HfSiON₄, HfTaO₂, HfTiO₂, HfZrO₂, ZrO₂, Ta₂O₅, or combinations thereof. In other embodiments, the first gate dielectric layer 220 can contain a non-high-k dielectric material, such as silicon dioxide.

[0075] In some embodiments, dielectric tuning layers (not particularly illustrated) are formed on the first gate dielectric layers 220 of the gate structures 200A, 200B, 200D, according to action 2300 of Fig. 16. The dielectric tuning layers allow for threshold voltage tuning in the gate structures 200A, 200B, and 200D. More precisely, a first dielectric tuning layer can be deposited directly on the first gate dielectric layer 220 in the gate structures 200A, 200B, and 200D. In some embodiments, the first dielectric tuning layer can contain a dipole material suitable for N-type devices (also referred to as an N-dipole material), which may contain a metal oxide material such as lanthanum oxide (La₂O₃), magnesium oxide (MgO), yttrium oxide (Y₂O₃), titanium oxide (TiO₂), or combinations thereof, as non-limiting examples. For N-type transistor devices, the N-dipole material can decrease the threshold voltage Vt. For P-type transistor devices, the N-dipole material can increase the threshold voltage Vt.In alternative embodiments where a P-dipole material is used to implement the first dielectric tuning layer, the threshold voltage Vt is increased for NFET devices and decreased for PFET devices. Exemplary P-dipole materials include Al₂O₃, Nb₂O₅, or B₂O₃.

[0076] Following the deposition of the first dielectric tuning layer, the first dielectric tuning layer can be removed from gate structures 200B and 200D, leaving the first dielectric tuning layer on gate structure 200A. An additional dielectric tuning layer can then be formed on gate structures 200A, 200B, and 200D, and then removed from gate structure 200D, resulting in two dielectric tuning layers over gate structure 200A, one dielectric tuning layer over gate structure 200B, and no dielectric tuning layer over gate structure 200D. Therefore, the first gate dielectric layer 220 will experience the strongest doping effect for gate structure 200A during a thermal insertion process. The first gate dielectric layer 220 may experience a weaker doping effect in gate structure 200B.In the gate structure 200D there is no dielectric tuning layer, so the first gate dielectric layer 220 in the gate structure 200 can experience the weakest (or essentially no) doping effect.

[0077] A thermal insertion process is performed on the gate structures 200A, 200B, and 200D, which may include an annealing process. In some embodiments, the annealing process can be carried out at an annealing temperature of approximately 600°C to approximately 800°C using nitrogen gas. The annealing temperature causes the metal ions in the dielectric tuning layers to penetrate (or react with) the first gate dielectric layer 220. This change in the composition of the first gate dielectric layer 220 is represented in the figures by the first gate dielectric layer 221 and the first gate dielectric layer 222. As previously described, the doping concentration is highest in the first gate dielectric layer 222 and lowest or zero in the first gate dielectric layer 220.The dopant concentration in the first gate dielectric layer 221 is lower than in the first gate dielectric layer 222 and higher than in the first gate dielectric layer 220. It is understood that within each of the first gate dielectric layers 222, 221, 220, the concentration of the dopant material (e.g., the metal ions) at a surface of the first gate dielectric layers 222, 221, 220 can be highest at their apex and then gradually decreases as the distance to the surface increases (e.g., closer to channels 22A-22C).

[0078] Now, regarding Fig. 13A-13C, after removal of the dielectric tuning layers, the second gate dielectric layer 230 is deposited on the first gate dielectric layers 222, 221, 220, according to action 2500 of Fig. 16. In some embodiments, the removal process includes an etching process, such as a wet etching process, a dry etching process, or a combination thereof. In some embodiments, an etchant used in such an etching process may contain hydrochloric acid (HCl), alkali (NH4), oxidant, or another suitable etchant. Removing the dielectric tuning layers 300, 400 improves the gate fill window, while the advantage of varying levels of dopant concentration has already been conferred on the first gate dielectric layers 222, 221, 220, corresponding to varying threshold voltages of the gate structures 200A, 200B, 200D. The second gate dielectric layer 230 can reduce gate loss.In some embodiments, an atomic layer deposition (ALD) process similar to that used to form the first gate dielectric layer 220 is used to form the second gate dielectric layer 230 with a precisely controlled thickness. The second gate dielectric layer 230 has a thickness 235, which can range from about 5 angstroms to about 50 angstroms. In some embodiments, the thickness 235 is about 6 angstroms. In some embodiments, fewer ALD deposition cycles are used to deposit the second gate dielectric layer 230 than are used to deposit the first gate dielectric layer 220, so that the second gate dielectric layer 230 is generally thinner than the first gate dielectric layer 220. The material of the second gate dielectric layer 230 can, in some embodiments, be essentially the same as that of the first gate dielectric layer 220.In other embodiments, the material of the second gate dielectric layer 230 differs from the material of the first gate dielectric layer 220. In some embodiments, the second gate dielectric layer 230 is crystallized and exhibits a higher crystallization rate than the first gate dielectric layers 220-222.

[0079] Continue in Fig. In embodiments 13A-13C, the second IL 240 is formed on the second gate dielectric layer 230, and the exit-work barrier layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion to the second gate dielectric layer 230. In many embodiments, the second IL 240 provides further improved thermal stability for the gate structures 200A, 200B, 200D and serves to limit the diffusion of metallic impurities from the exit-work metal layers 900 and / or the exit-work barrier layer 700 into the first gate dielectric layer 222, 221, 220 and the second gate dielectric layer 230. In some embodiments, the formation of the second IL 240 is accomplished by first depositing a high-k cover layer (not illustrated for simplicity) on the second gate dielectric layer 230.The high-k cover layer contains one or more of the following: HfSiON, HfTaO, HfTiO, HfAlON, HZrO, or other suitable materials in various embodiments. In one specific embodiment, the high-k cover layer contains titanium silicon nitride (TiSiN). In some embodiments, the high-k cover layer is deposited by an ALD using approximately 40 to approximately 100 cycles at a temperature of approximately 400°C to approximately 450°C. Thermal annealing is then performed to form the second IL 240, which in some embodiments may be or contain TiSiN. Following the formation of the second IL 240 by thermal annealing, artificial intelligence (AI)-controlled atomic layer etching (ALE) is performed in cycles to remove the high-k cover layer, while the second IL 240 is essentially retained.Each cycle can include an initial pulse of WCl5, followed by an Ar flush, followed by a second pulse of O2, followed by another Ar flush. AI control is based on... Fig. Discussed in more detail on pages 20-26. The high-k cover layer is removed to increase the gate fill window for further multiple threshold voltage tuning by metal gate structuring.

[0080] Continue in Fig. 13A-13C, after formation of the second IL 240 and removal of the high-k cover layer, the exit working barrier layer 700 is optionally formed on the gate structures 200A, 200B, 200D in accordance with some embodiments, which is action 2700 of Fig. 16 corresponds to the exit-load barrier layer 700. The exit-load barrier layer 700 is or contains a metal nitride, such as TiN, WN, MoN, TaN, or the like. In a specific embodiment, the exit-load barrier layer 700 is TiN. The exit-load barrier layer 700 can have a thickness 705 ranging from about 5 Å to about 20 Å. Inclusion of the exit-load barrier layer 700 provides additional threshold voltage tuning flexibility. In general, the exit-load barrier layer 700 increases the threshold voltage for NFET transistor devices and decreases the threshold voltage (magnitude) for PFET transistor devices. As in Fig. As shown in Figures 13A-13C, after the formation of the exit working barrier layer 700, a mask 710 is formed over the gate structure 200D, while the gate structures 200A and 200B are exposed. The formation of the mask 710 can include at least one photoresist deposition process, followed by an exposure and removal process. The mask 710 is used when removing the exit working barrier layer 700 from gate structures exposed by the mask 710, such as gate structures 200A-200B, as shown in Figure 13A-13C. Fig. Figures 13A-13C are shown. In some embodiments, the deposition and structuring of the exit-work barrier layer 700 can be repeated to form varying numbers of exit-work barrier layers 700 on the gate structures 200A, 200B, 200D to achieve variable threshold voltage tuning among the gate structures 200A, 200B, 200D. In some embodiments, each of the gate structures 200A, 200B, 200D can have as few as zero exit-work barrier layers 700 to three or more. Fewer exit-work barrier layers 700 allow a larger gate fill window, whereas a larger number of exit-work barrier layers 700 allows improved threshold voltage tuning.

[0081] Fig. Figures 14A-14C illustrate the gate structures 200A, 200B, and 200D with the exit work barrier layers 700 in position for gate structure 200D and removed for gate structures 200A-200B. Further shown are the formation of the N exit work metal layer 250, the in-situ cover layer 260, and the oxygen blocking layer 270 (corresponding to action 2800 of Fig. 16) illustrated, which may be collectively referred to as the exit work metal layer 900. In some embodiments, the N exit work metal layer 250 is or contains a metallic material, such as TiAlC, TiAl, TaAlC, TaAl, or the like. The N exit work metal layer 250 may be formed by one or more deposition processes, such as CVD, PVD, ALD, plating, and / or other suitable processes, and has a thickness 255 between about 10 Å and 20 Å.

[0082] The in-situ cover layer 260 is formed on the N exit metal layer 250. In some embodiments, the in-situ cover layer 260 is or contains TiN, TiSiN, TaN, or other suitable material and has a thickness 265 of between about 10 Å and 20 Å. The oxygen-blocking layer 270 is formed on the in-situ cover layer 260 to prevent oxygen diffusion into the N exit metal layer 250, which would cause an undesirable shift in the threshold voltage. The oxygen-blocking layer 270 is formed of a dielectric material that can prevent oxygen from penetrating to the N exit metal layer 250 and can protect the N exit metal layer 250 from further oxidation. The oxygen-blocking layer 270 may contain an oxide of silicon, germanium, SiGe, or another suitable material.In some embodiments, the oxygen blocking layer 270 is formed using ALD and has a thickness 275 between about 10 Å and about 20 Å.

[0083] Fig. Figures 15A-15C illustrate the gate structures 200A, 200B, 200D after formation of an adhesive layer 280 and the metal filler layer 290, according to action 2900 of Fig. 16. In some embodiments, the adhesive layer 280 is formed on the oxygen-blocking layer 270 of the exit working metal layer 900. The adhesive layer 280 can promote and / or improve the adhesion between the metal filler layer 290 and the exit working metal layer 900. In some embodiments, the adhesive layer 280 can be formed from a metal nitride, such as TiN, TaN, MoN, WN, or another suitable material, using ALD. In some embodiments, the thickness 285 of the adhesive layer 280 is between about 10 Å and about 25 Å.

[0084] The metal filler layer 290 is formed on the adhesive layer 280 and can contain a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. In some embodiments, the metal filler layer 290 can be deposited using processes such as CVD, PVD, plating, and / or other suitable processes. As shown in Fig. As shown in Figures 15A-15C, the metal filler layers 290 can have a thickness 295N in the gate structures 200A, 200B as a result of the inclusion of the exit work barrier layer(s) 700 in the gate structure 200D, which is thicker than the thickness 295D of the metal filler layer 290 in the gate structure 200D.

[0085] Fig. Figures 17-19 illustrate cross-sectional views of intermediate stages in the manufacture of the GAA component 20D, in accordance with some embodiments.

[0086] In relation to Fig. 10A-10D and Fig. Following the process described in 15A-15C, in Fig. 17 The conductive features 84, the channels 28A-28C, and the conductive fin structure 33 are formed by one or more replacement processes. In some embodiments, one or more openings are etched in the ILD 130 to expose the source / drain features 82. An etching process can create an opening by removing the source / drain features 82 using a first etchant, such as a dry or wet etchant. In some embodiments, the source / drain features 82 are or contain SiGe, and the nanostructures 22 and the fin structure 32 are or contain silicon. Following removal of the source / drain features 82, a second etching process can be performed using a second etchant to enlarge the opening by removing the nanostructures 22 and the fin structure 32.In some embodiments, the second etchant is a different etchant from the first etchant used to remove the source / drain features 82.

[0087] Following the removal of the source / drain features 82, the nanostructures 22, and the fin structure 32, the conductive features 84, the channels 28, and the conductive fin structure 33 are formed by one or more deposition processes. In some embodiments, the deposition process comprises PVD, CVD, PECVD, ALD, or another suitable process. In some embodiments, the deposition process deposits a metal nitride, such as TiN, TaN, or the like, to essentially fill the opening between the ILD 130, the isolation regions 36, the buffer layer 140, the gate structure 200, the spacers 41, and the internal spacers 74. In some embodiments, there is no discernible interface between the conductive features 84, the channels 28, and the conductive fin structure 33, essentially because they are formed in a single, continuous process.

[0088] Following the deposition of the conductive features 84, the channels 28, and the conductive fin structure 33, excess deposited material above the ILD 130, the spacers 41, and the gate structure 200 is removed by a removal process such as CMP, etching, or another suitable process. In some embodiments, the deposited material in the opening of the ILD 130 above the conductive features 84 is recessed to a level equal to or just below the upper surfaces of the conductive features 84 in order to reopen the opening in the ILD 130. The opening in the ILD 130 can then be refilled with a dielectric material, which is generally the same material as the ILD 130.In some embodiments, due to the refilling process, a discernible vertical interface is present in the ILD 130 above the upper surface of the conductive feature 84 and / or is substantially aligned with an outer wall of the conductive feature 84 that adjoins the ILD 130 and the insulating region 36. In some embodiments, when a contact 120 is to be formed above and electrically connected to the conductive feature 84, the opening in the ILD 130 is not refilled with the dielectric material, as shown in [reference]. Fig. 18 shown.

[0089] In Fig. Contacts 120 are formed over the conductive features 84. The contacts 120 can contain a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. A silicide layer 118 can be formed between the source / drain features 82 and the contacts 120 to reduce contact resistance. The silicide layer 118 can contain a metal silicide material, such as cobalt silicide in some embodiments, or TiSi in some other embodiments.

[0090] Continue in Fig. Following the formation of the contacts 120, the interconnect structure 121 is formed and electrically connected to at least one of the contacts 120. A single conductive via 122 and a single conductive track 123 are in Fig. Figure 18 is shown for the sake of clarity. In general, the interconnect structure 121 comprises a stack of several dielectric layers, such as the insulating layers 125, 126, and many conductive features embedded therein, similar to the conductive via 122 and the conductive track 123. The conductive features in the dielectric layers of the interconnect structure 121 can be formed from conductive materials such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. The conductive features can be formed by a suitable process, including PVD or electroplating, in a single-damascus or double-damascus scheme.

[0091] By electrically connecting the conductive via 122 and the conductive track 123 to the conductive features 84 via the contact 120, electrical signals can be applied to the conductive features 84, the channels 28, and the conductive fin structure 33, which together form a second plate of the GAA capacitor 20D. Further electrical signals can be applied to the gate structure 200, which is a first plate of the GAA capacitor 20D.

[0092] In Fig. Following the formation of the interconnect structure 121, a backside via 125 and a backside interconnect structure 129 are formed on the back side of the GAA capacitor 20D. In some embodiments, the substrate 110 and the buffer layer 140 are removed by a removal process, such as grinding, CMP, etching, or another suitable process, to expose the back sides of the conductive features 84. In some embodiments, following the removal process, the buffer layer 34 is, as in Fig. Figure 19 shows a remaining section of buffer layer 140 and is not removed.

[0093] In some embodiments, the backside via 125 is formed by first turning the GAA capacitor 20D and countersinking the conductive feature 84. The countersinking can be any suitable process, generally involving a dry or wet etching process that attacks the conductive feature 84 but is not selective for the adjacent insulating region 36 and the buffer layer 34, leaving an opening above the conductive feature 84. Following the countersinking of the conductive feature 84, a conductive material is filled into the opening by any suitable process, such as a deposition or electroplating process. The conductive material can be tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof.In some embodiments, a barrier or seed layer is formed before the conductive material is filled to promote better adhesion to the underlying metal nitride material of the conductive feature 84. Excess conductive material present on the back side of the GAA device 20D can then be removed, for example, by a CMP or etching process, after which the bottom surfaces of the isolation regions 36, the backside via 125, the buffer layer 34, and the conductive feature 84 can be substantially coplanar.

[0094] Continue to Fig. Following the formation of the backside via 125, the backside interconnect structure 129 is formed over the bottom surfaces of the insulation areas 36, the backside via 125, the buffer layer 34, and the conductive feature 84. While the backside interconnect structure 129 is in Fig. Figure 19 shows, for the simplicity of illustration, only a single bottom insulating layer 128 and the conductive feature 127 embedded therein; the backside interconnect structure 129 generally has a stack of multiple insulating layers and conductive features embedded therein.

[0095] In some embodiments, the bottom insulating layer 128 is first formed over the insulating areas 36, the backside via 125, the buffer layer 34, and the conductive feature 84. The bottom insulating layer 128 is then structured to form an opening that exposes the backside via 125. The opening over the backside via 125 can then be filled with a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof, by a suitable process, such as deposition or electroplating, to form the conductive feature 127. In some embodiments, a barrier or seed layer is formed prior to filling with the conductive material, such as a copper seed layer if the conductive material is copper.In some embodiments, the conductive feature 127 is located above the barrier layer 34 and / or the insulation region 36 on opposite sides of the backside via 125.

[0096] Fig. Figure 20 is an illustration of a semiconductor process system 3200 according to one embodiment. The semiconductor process system 3200 can be used to perform the controlled ALE processes used to form the GAA devices 20N, 20C, 20D, as described in Figure 20. Fig. Described in 1A-19, the semiconductor process system 3200 has a process chamber 3202, which has an internal volume 3203. A support 3206 is positioned within the internal volume 3203 and configured to support a substrate 3204 during a thin-film etching process. The semiconductor process system 3200 is configured to etch a thin film onto the substrate 3204, such as the high-k cover layer used to form the second IL 240 or the exit-work barrier layer 700. The semiconductor process system 3200 has a control system 3224 that dynamically adjusts thin-film etching parameters. Details of the control system 3224 are provided after the description of the operation of the semiconductor process system 3200.

[0097] In one embodiment, the semiconductor process system 3200 comprises a first fluid source 3208 and a second fluid source 3210. The first fluid source 3208 supplies a first fluid to the internal volume 3203. The second fluid source 3210 supplies a second fluid to the internal volume 3203. Both the first and the second fluids contribute to etching a thin film onto the substrate 3204. Fig. As illustrated in Figure 20, fluid sources 3208 and 3210 can contain or supply materials other than fluids in practice. For example, fluid sources 3208 and 3210 can have material sources that provide all the materials for the etching processes.

[0098] In one embodiment, the semiconductor process system 3200 is an atomic layer etching (ALE) system that performs ALE processes. The ALE system performs etching processes in cycles. Each cycle includes flowing a first etching fluid from fluid source 3208, followed by purging the first etching fluid from the etching chamber by purging gas from one or both of purge sources 3212 and 3224, followed by flowing a second etching fluid from fluid source 3210, followed by purging the second etching fluid from the etching chamber by purging gas from one or both of purge sources 3212 and 3224. This corresponds to a single ALE cycle. Each cycle etches one atomic or molecular layer from the thin film being etched. A specific example of the ALE cycle is shown in Fig. 22 illustrated.

[0099] The parameters of a thin film produced by the 3200 semiconductor process system can be affected by a large number of process conditions. The process conditions may include, but are not limited to, the quantity of fluid or material remaining in the fluid sources 3208, 3210, the flow rate of fluid or material from the fluid sources 3208, 3210, the pressure of fluids supplied by the fluid sources 3208 and 3210, the length of tubes or conduits conveying fluid or material into the process chamber 3203, the age of an ampoule defining or present in the process chamber 3203, the temperature in the process chamber 3202, the humidity in the process chamber 3202, the pressure within the process chamber 3202, light absorption and reflection within the process chamber 3202, surface features of the semiconductor wafer 3204, and the composition of materials supplied by the fluid sources 3208 and 3210.the phase of materials supplied by fluid sources 3208 and 3210, the duration of the etching process, the duration of individual phases of the etching process, and various other factors, including those relating to , Fig. 20 are described, or factors not specifically listed above.

[0100] The combination of different process conditions during the etching process determines the remaining thickness of a thin film etched by the ALE process. It is possible that process conditions may result in thin films with a remaining thickness that does not fall within the target parameters. If this occurs, ICs formed from the 3204 semiconductor wafer may not function properly. The quality of batches of semiconductor wafers may be compromised. In some cases, some semiconductor wafers may have to be discarded.

[0101] The 3200 semiconductor processing system uses the 3224 control system to dynamically adjust process conditions to ensure that etching processes result in thin films with parameters or properties that fall within the target parameters or properties. The 3224 control system is connected to processing equipment linked to the 3200 semiconductor processing system. The processing equipment may include components that are in Fig. Figure 2A shows that the control system 3224 can control the flow rate of material from fluid sources 3208 and 3210, the temperature of materials supplied by fluid sources 3208 and 3210, the pressure of fluids supplied by fluid sources 3208 and 3210, the flow rate of material from purge sources 3212 and 3214, the duration of flow of materials from fluid sources 3208 and 3210 and purge sources 3212 and 3214, the temperature inside process chamber 3202, the pressure inside process chamber 3202, the humidity inside process chamber 3203, and other aspects of the thin-film etching process. The 3224 control system manages these process parameters so that the thin-film etching process results in a thin film that exhibits target parameters such as a remaining target thickness, a target composition, a target crystal orientation, etc. Further details regarding the control system are available in relation to Fig. Provided on 22-23.

[0102] In one embodiment, the control system 224 is communicatively coupled to the first and second fluid sources 3208, 3210 via one or more communication channels 3225. The control system 3224 can send signals to the first fluid source 3208 and the second fluid source 3210 via the communication channels 3225. The control system 3224 can control the functionality of the first and second fluid sources 3208, 3210, in part, in response to sensor signals from a by-product sensor 3222.

[0103] In one embodiment, the semiconductor process system 3200 may include one or more valves, pumps, or other flow control mechanisms for controlling the flow rate of the first fluid from the first fluid source 3208. These flow control mechanisms may be part of the fluid source 3208 or may be separate from the fluid source 3208. The control system 3224 may be communicatively coupled to these flow control mechanisms or to systems that control these flow control mechanisms. The control system 3224 may control the flow rate of the first fluid by controlling these mechanisms. The control system 3200 may include valves, pumps, or other flow control mechanisms that control the flow of the second fluid from the second fluid source 3210 in the same manner as previously described with respect to the first fluid and the first fluid source 3208.

[0104] In one embodiment, the semiconductor process system 3200 comprises a collecting mixer 3216 and a fluid distributor 3218. The collecting mixer 3216 receives the first and second fluids, either together or separately, from the first fluid source 3208 and the second fluid source 3210. The collecting mixer 3216 supplies either the first fluid, the second fluid, or a mixture of the first and second fluids to the fluid distributor 3218. The fluid distributor 3218 receives one or more fluids from the collecting mixer 3216 and distributes the one or more fluids into the internal volume 3203 of the process chamber 3202.

[0105] In one embodiment, the first fluid source 3208 is coupled to the mixing unit 3216 by a first fluid channel 3230. The first fluid channel 3230 conveys the first fluid from the fluid source 3208 to the mixing unit 3216. The first fluid channel 3230 can be a pipe, hose, or other suitable channel for conveying the first fluid from the first fluid source 3208 to the mixing unit 3216. The second fluid source 3210 is coupled to the mixing unit 3216 by a second fluid channel 3232. The second fluid channel 3232 conveys the second fluid from the second fluid source 3210 to the mixing unit 3216.

[0106] In one embodiment, the collecting mixer 3216 is coupled to the fluid distributor 3218 by a third fluid line 3234. The third fluid line 3234 conveys fluid from the collecting mixer 3216 to the fluid distributor 3218. The third fluid line 3234 can convey the first fluid, the second fluid, a mixture of the first and second fluids, or other fluids, as described in more detail below.

[0107] The first and second fluid sources 3208 and 3210 can have fluid reservoirs. The fluid reservoirs can store the first and second fluids. The fluid reservoirs can selectively dispense the first and second fluids.

[0108] In one embodiment, the semiconductor process system 3200 has a first purge source 3212 and a second purge source 3214. The first purge source is coupled to the first fluid line 3230 by first purge line 3236. The second purge source is coupled to the fluid line 3232 by second purge line 3238. In practice, the first and second purge sources can be a single purge source.

[0109] In one embodiment, the first and second purge sources 3212, 3214 supply a purge gas to the internal volume 3203 of the process chamber 3202. The purge fluid is selected to flush or transport the first fluid, the second fluid, byproducts of the first or second fluid, or other fluids from the internal volume 3203 of the process chamber 3202. The purge fluid is selected to be inert and not react with the substrate 3204, the gate metal layer on the substrate 3204, the first and second fluids, or byproducts of these first or second fluids. Accordingly, the purge fluid can be an inert gas comprising, but not limited to, Ar or N₂.

[0110] While Fig. Figure 20 illustrates a first fluid source 3208 and a second fluid source 3210. In practice, the semiconductor process system 3200 may have other numbers of fluid sources. For example, the semiconductor process system 3200 may have only a single fluid source or more than two fluid sources. Accordingly, the semiconductor process system 3200 may have a different number than two fluid sources without deviating from the scope of this disclosure.

[0111] Fig. Figure 21 is a graph illustrating a cycle of an ALE process according to an embodiment, performed by the 3200 semiconductor processing system. At time T1, the first etching fluid begins to flow. In the example of Fig. 2B is the first etching fluid, WCl5. The first etching fluid flows from fluid source 3208 into internal volume 3203. In internal volume 3203, the first etching fluid reacts with the uppermost exposed layer of the high-k cover layer (e.g., TiSiN) or the exit work barrier layer 700 (e.g., TiN). At time T2, the first etching fluid, WCl5, stops flowing. In this example, the time elapsed between T1 and T2 is between 1 s and 10 s.

[0112] At time T3, the purge gas begins to flow. The purge gas flows from one or both of the purge sources 3212 and 3224. In one example, the purge gas is argon, N2, or another inert gas that can purge the first etching fluid WCl5 without reacting with the high-k cover layer (e.g., TiSiN) or the exit work barrier layer 700 (e.g., TiN). At time T4, the purge gas stops flowing. In one example, the time elapsed between T3 and T4 is between 2 s and 15 s.

[0113] At time T5, the second etching fluid flows into the internal volume 3203. The second etching fluid flows from fluid source 3210 into the internal volume 3203. In one example, the second etching fluid is O2. The O2 reacts with the outermost atomic or molecular layer of the titanium nitride layer 124 and completes the etching of the outermost atomic or molecular layer of the titanium nitride layer 124. At time T6, the second etching fluid stops flowing. In one example, the time elapsed between T5 and T6 is between 1 s and 10 s.

[0114] At time T7, the purge gas flows again and flushes the second etching fluid from the internal volume 3203. At time T8, the purge gas stops flowing. The time between T1 and T8 corresponds to a single ALE cycle.

[0115] In practice, an ALE process can comprise between 5 and 50 cycles, depending on the initial thickness of the high-k cover layer (e.g., TiSiN) or the exit-work barrier layer 700 (e.g., TiN) and the desired final thickness of the high-k cover layer (e.g., TiSiN) or the exit-work barrier layer 700 (e.g., TiN). Each cycle removes one atomic or molecular layer of the high-k cover layer (e.g., TiSiN) or the exit-work barrier layer 700 (e.g., TiN). Other materials, processes, and past times can be used without deviating from the scope of this disclosure.

[0116] Fig. 22 is a block diagram of the 3224 control system by Fig. 2A, according to one embodiment. The control system 3224 of Fig. 22 is configured to control the operation of the semiconductor processing system 3200 when performing ALE processes to manufacture the GAA devices 20N, 20C, 20D. Fig. 1A-1B according to one embodiment. The control system 3224 uses machine learning to adjust parameters of the semiconductor process system 3200. The control system 3224 can adjust parameters of the semiconductor process system 3200 between ALE passes or even between ALE cycles to ensure that a thin film layer formed by the ALE process meets selected specifications.

[0117] In one embodiment, the control system 3224 comprises an analysis model 3302 and a training module 3304. The training module 3304 trains the analysis model 3302 using a machine learning process. The machine learning process trains the analysis model 3302 to select parameters for an ALE process that will result in a thin film exhibiting selected properties. Although the training module 3304 is shown to be separate from the analysis model 3302, in practice the training module 3304 can be part of the analysis model 3302.

[0118] The control system 3224 has or stores training set data 3306. The training set data 3306 includes historical thin-film data 3308 and historical process condition data 3310. The historical thin-film data 3308 contains data relating to thin films resulting from ALE processes. The historical process condition data 3310 contains data relating to process conditions during the ALE processes that produced the thin films. As explained in more detail below, the training module 3304 uses the historical thin-film data 3308 and the historical process condition data 3310 to train the analysis model 3302 using a machine learning process.

[0119] In one embodiment, the historical thin-film data 3308 contains data regarding the remaining thickness of previously etched thin films. For example, during the operation of a semiconductor manufacturing facility, thousands or millions of semiconductor wafers may be processed over the course of several months or years. Each of the semiconductor wafers may have thin films that are etched by ALE processes. After each ALE process, the thicknesses of the thin films are measured as part of a quality control process. The historical thin-film data 3308 contains the remaining thicknesses of each of the thin films that are etched by ALE processes. Accordingly, the historical thin-film data 3308 can contain thickness data for a large number of thin films that are etched by ALE processes.

[0120] In one embodiment, the historical thin-film data 3308 may also include data regarding the thickness of thin films at intermediate stages of the thin-film etching processes. For example, an ALE process may involve a large number of etching cycles during which individual layers of the thin film are etched. The historical thin-film data 3308 may include thickness data for thin films after individual etching cycles or groups of etching cycles. Therefore, the historical thin-film data 3308 not only includes data regarding the overall thickness of a thin film after completion of an ALE process, but may also include data regarding the thickness of the thin film at various stages of the ALE process.

[0121] In one embodiment, the historical thin-film data 3308 includes data relating to the composition of the remaining thin films etched by ALE processes. After a thin film is etched, measurements can be taken to determine the elemental or molecular composition of the thin films. Successful etching of the thin films results in a thin film with specified remaining thicknesses. Unsuccessful etching processes may result in a thin film that does not have the specified proportions of elements or compounds. The historical thin-film data 3308 may include data from measurements indicating the elements or compounds that constitute the different thin films.

[0122] In one embodiment, the historical process conditions 3310 include various process conditions or parameters during ALE processes that etch the thin films, which are associated with the historical thin-film data 3308. Accordingly, for each thin film that has data in the historical thin-film data 3308, the historical process condition data 3310 may include the process conditions or parameters that were present during the etching of the thin film. For example, the historical process condition data 3310 may include data regarding the pressure, temperature, and fluid flow rates within the process chamber during ALE processes.

[0123] The historical process condition data 3310 may contain data regarding remaining quantities of pre-product material in the fluid sources during ALE processes. The historical process condition data 3310 may contain data regarding the age of process chamber 3202, the number of etching processes performed in process chamber 3202, the number of etching processes performed in process chamber 3202 since the last cleaning cycle of process chamber 3202, or other data regarding process chamber 3202. The historical process condition data 3310 may contain data regarding compounds or fluids introduced into process chamber 3202 during the etching process. The compound data may include compound types, phases of compounds (solid, gaseous, or liquid), compound mixtures, or other aspects regarding compounds or fluids introduced into process chamber 3202.The historical process condition data 3310 may contain data regarding humidity within process chamber 3202 during ALE processes. The historical process condition data 3310 may contain data regarding light absorption, light adsorption, and light reflection within process chamber 3202. The historical process condition data 3326 may contain data regarding the length of pipes, hoses, or lines that transport compounds or fluids into process chamber 3202 during ALE processes. The historical process condition data 3310 may contain data regarding the conditions for carrier gases that transport compounds or fluids into process chamber 3202 during ALE processes.

[0124] In one embodiment, historical process condition data can contain 3310 process conditions for each of a multitude of individual cycles of a single ALE process. Accordingly, the historical process condition data can contain 3310 process condition data for a very large number of ALE cycles.

[0125] In one embodiment, the training set data 3306 links the historical thin-film data 3308 to the historical process condition data 3310. In other words, the thin-film thickness, material composition, or crystal structure associated with a thin film in the historical thin-film data 3308 is linked (e.g., by tagging) to the process condition data associated with that etching process. As detailed below, the tagged training set data can be used in a machine learning process to train the analysis model 3302 to predict semiconductor process conditions that will result in neatly formed thin films.

[0126] In one embodiment, the control system 3324 comprises processing resources 3312, memory resources 3314, and communication resources 3316. The processing resources 3312 may comprise one or more controllers or processors. The processing resources 3312 are configured to execute software instructions, process data, make thin-film etching control decisions, perform signal processing, read data from memory, write data to memory, and perform other processing operations. The processing resources 3312 may comprise physical processing resources 3312 located at a site or facility of the semiconductor process system 3200. The processing resources may comprise virtual processing resources 3312 located remotely from the site of the semiconductor process system 3200 or a facility where the semiconductor process system 3200 is located.The processing resources 3312 can include cloud-based processing resources that include processors and servers accessed through one or more cloud computing platforms.

[0127] In one embodiment, the memory resources 3314 can comprise one or more computer-readable memories. The memory resources 3314 are configured to store software instructions associated with the function of the control system and its components, including, but not limited to, the analysis model 3302. The memory resources 3314 can store data associated with the function of the control system 3224 and its components. The data can include the training set data 3306, current process condition data, and any other data associated with the operation of the control system 3224 or any of its components. The memory resources 3314 can comprise physical memory resources located at the site or facility of the semiconductor process system 3200. The memory resources can comprise virtual memory resources located remotely from the site or facility of the semiconductor process system 3200.The storage resources 3314 can include cloud-based storage resources that are accessed via one or more cloud computing platforms.

[0128] In one embodiment, the communication resources may include resources that enable the control system 3224 to communicate with equipment associated with the semiconductor process system 3200. For example, the communication resources 3316 may include wired and wireless communication resources that enable the control system 3224 to receive sensor data associated with the semiconductor process system 3200 and to control equipment of the semiconductor process system 3200. The communication resources 3316 may enable the control system 3224 to control the flow of fluid or other material from the fluid sources 3308 and 3310 and from the purge sources 3312 and 3314. The communication resources 3316 may enable the control system 3224 to control heating elements, voltage sources, valves, exhaust ducts, wafer transfer equipment, and any other equipment associated with the semiconductor process system 3200.The communication resources 3316 enable the control system 3224 to communicate with remote systems. The communication resources 3316 can include, or facilitate, communication over one or more networks, such as wired networks, wireless networks, the Internet, or an intranet. The communication resources 3316 enable components of the control system 3224 to communicate with each other.

[0129] In one embodiment, the analysis model 3302 is implemented via the processing resources 3312, the storage resources 3314, and the communication resources 3316. The control system 3224 can be a distributed control system with components and resources located remotely from each other and from the semiconductor process system 3200.

[0130] Fig. Figure 23 is a block diagram illustrating operational and training aspects of the analysis model 3302 by Fig. Figure 22 illustrates one embodiment. The analysis model 3302 can be used to select parameters for ALE processes from the semiconductor process system 3200. Fig. 2A is performed to replace the GAA components 20N, 20C, 20D of Fig. to form 1A-1B. As previously described, the training set data 3306 contains data relating to a multitude of previously performed thin-film etching processes. Each previously performed thin-film etching process took place under specific process conditions and resulted in a thin film exhibiting a particular property. The process conditions for each previously performed thin-film etching process are formatted into a respective process condition vector 3352. The process condition vector contains a multitude of data fields 3354. Each data field 3354 corresponds to a specific process condition.

[0131] The example of Fig. Figure 23 illustrates a single process condition vector 3352 that is passed to the analysis model 3302 during the training process. In the example of Fig. In Figure 23, the process condition vector 3352 has nine data fields 3354. The first data field 3354 corresponds to the temperature during the previously performed thin-film etching process. The second data field 3356 corresponds to the pressure during the previously performed thin-film etching process. The third data field 3354 corresponds to the humidity during the previously performed thin-film etching process. The fourth data field 3354 corresponds to the flow rate of etching materials during the previously performed thin-film etching process. The fifth data field 3354 corresponds to the phase (liquid, solid, or gaseous) of etching materials during the previously performed thin-film etching process. The sixth data field 3354 corresponds to the age of the ampoule used in the previously performed thin-film etching process. The seventh data field 3354 corresponds to the size of an etched area on a wafer during the previously performed thin-film etching process.The eighth data field 3354 corresponds to the density of surface features of the wafer used during the previously performed thin-film etching process. The ninth data field corresponds to the angle of sidewalls of surface features during the previously performed thin-film etching process. In practice, each process condition vector 3352 may have more or fewer data fields than shown. Fig. 23 are shown, without deviating from the scope of the present disclosure. Each process condition vector 3352 can have different process condition types, without deviating from the scope of the present disclosure. The specific process conditions shown in Fig. The 23 illustrated examples are merely provided by way of illustration. Each process condition is represented by a numerical value in the corresponding data field 3354. For condition types that are not inherently represented by numbers, such as material phase, a number can be assigned to each possible phase.

[0132] The analysis model 3302 has a plurality of neural layers 3356a-e. Each neural layer has a plurality of nodes 3358. Each node 3358 can also be called a neuron. Each node 3358 of the first neural layer 3356a receives the data values ​​for each data field from the process condition vector 3352. Accordingly, in the example of Fig. 23, each node 3358 receives nine data values ​​from the first neural layer 3356a because the process condition vector 3352 has nine data fields. Each neuron 3358 has a respective internal mathematical function, which is described in Fig. 23 is labeled with F(x). Each node 3358 of the first neural layer 3356a generates a scalar value by applying the internal mathematical function F(x) to the data values ​​from the data fields 3354 of the process condition vector 3352. Further details regarding the internal mathematical functions F(x) are provided below.

[0133] Each node 3358 of the second neural layer 3356b receives the scalar values ​​generated by each node 3358 of the first neural layer 3356a. Accordingly, in the example of Fig. 23 Each node of the second neural layer 3356b has four scalar values ​​because there are four nodes 3358 in the first neural layer 3356a. Each node 3358 of the second neural layer 3356b generates a scalar value by applying the respective internal mathematical function F(x) to the scalar values ​​from the first neural layer 3356a.

[0134] Each node 3358 of the third neural layer 3356c receives the scalar values ​​generated by each node 3358 of the second neural layer 3356b. Accordingly, in the example of Fig. 23 Each node of the third neural layer 3356c has five scalar values ​​because there are five nodes 3358 in the second neural layer 3356b. Each node 3358 of the third neural layer 3356c generates a scalar value by applying the respective internal mathematical function F(x) to the scalar values ​​of the nodes 3358 of the second neural layer 3356b.

[0135] Each node 3358 of neural layer 3356d receives the scalar values ​​generated by each node 3358 of the previous neural layer (not shown). Each node 3358 of neural layer 3356d generates a scalar value by applying its respective internal mathematical function F(x) to the scalar values ​​from the nodes 3358 of the second neural layer 3356b.

[0136] The last neural layer contains only a single node 3358. The last neural layer receives the scalar values ​​generated by each node 3358 of the previous neural layer 3356d. The node 3358 of the last neural layer 3356e generates a data value 3368 by applying a mathematical function F(x) to the scalar values ​​received by the nodes 3358 of neural layer 3356d.

[0137] In the example of Fig. 23 corresponds to the data value 3368 of the predicted remaining thickness of a thin film, generated from process condition data according to values ​​exhibited in the process condition vector 3352. In other embodiments, the last neural layer 3356e can generate multiple data values, each corresponding to a specific thin-film property, such as thin-film crystal orientation, thin-film uniformity, or other properties of a thin film. The last neural layer 3356e will have a corresponding node 3358 for each output data value to be generated. In the case of a predicted thin-film thickness, engineers can provide constraints that determine that the predicted thin-film thickness 3368 must fall within a selected range, such as between 0 nm and 50 nm in an example.The analysis model 3302 will adjust internal functions F(x) to ensure that the data value 3368, which corresponds to the predicted thin film thickness, falls within the specified range.

[0138] During the machine learning process, the analysis model compares the predicted remaining thickness in data value 3368 with the actual remaining thickness of the thin film, as indicated by data value 3370. As previously stated, the training set data 3306 contains thin-film property data for each set of historical process condition data, indicating the properties of the thin film resulting from the historical thin-film etching process. Accordingly, data field 3370 contains the actual remaining thickness of the thin film resulting from the etching process, as reflected in the process condition vector 3352. The analysis model 3302 compares the predicted remaining thickness from data value 3368 with the actual remaining thickness from data value 3370.Analysis model 3302 generates an error value 3372, which indicates the error or difference between the predicted remaining thickness based on data value 3368 and the actual remaining thickness based on data value 3370. Error value 3372 is used to train analysis model 3302.

[0139] The training of the analysis model 3302 can be more fully understood by discussing the internal mathematical functions F(x). While all of the nodes 3358 are labeled with an internal mathematical function F(x), the mathematical function F(x) of each node is unique. In an example, each internal mathematical function has the following form: F(x)=x1∗w1+x2∗w2+…xn∗w1+b.

[0140] In the equation above, each value x1-xn corresponds to a data value received by a node 3358 in the previous neural layer, or, in the case of the first neural layer 3356a, each value x1-xn corresponds to a respective data value from the data fields 3354 of the process condition vector 3352. Accordingly, n for a given node is equal to the number of nodes in the previous neural layer. The values ​​w1-wn are scalar weight values ​​associated with a corresponding node in the previous layer. The analysis model 3302 selects the values ​​of the weight values ​​w1-wn. The constant b is a scalar bias value and can also be multiplied by a weight value. The value generated by a node 3358 is based on the weight values ​​w1-wn. Accordingly, each node 3358 has n weight values ​​w1-wn. Although not shown above, every function F(x) can also have an activation function.The sum presented in the equation above is multiplied by the activation function. Examples of activation functions include remediated linear unit functions (ReLU functions), sigmoidal functions, hyperbolic stress functions, or other types of activation functions.

[0141] After the error value 3372 is calculated, the analysis model 3302 adjusts the weight values ​​w1-wn for the different nodes 3358 of the different neural layers 3356a-3356e. After the analysis model 3302 adjusts the weight values ​​w1-wn, it provides the process condition vector 3352 back to the neural input layer 3356a. Because the weight values ​​for the different nodes 3358 of the analysis model 3302 are different, the predicted remaining thickness 3368 will differ from the previous iteration. The analysis model 3302 again generates an error value 3372 by comparing the actual remaining thickness 3370 with the predicted remaining thickness 3368.

[0142] Analysis model 3302 again adjusts the weight values ​​w1-wn, which are associated with the various nodes 3358. Analysis model 3302 again processes the process condition vector 3352 and generates a predicted remaining thickness 3368 and an associated error value 3372. The training process involves adjusting the weight values ​​w1-wn iteratively until the error value 3372 is minimized.

[0143] Fig. Figure 23 illustrates a single process condition vector 3352 being passed to the analysis model 3302. In practice, the training process involves passing a large number of process condition vectors 3352 through the analysis model 3302, generating a predicted remaining thickness 3368 for each process condition vector 3352, and generating a related error value 3372 for each predicted remaining thickness. The training process may also include generating an accumulated error value, which indicates the average error for all of the predicted remaining thicknesses for a bundle of process condition vectors 3352. The analysis model 3302 adjusts the weight values ​​w1-wn after processing each bundle of process condition vectors 3352. The training process continues until the average error across all process condition vectors 3352 is less than a selected threshold tolerance.When the average error is smaller than the selected threshold tolerance, the training of analysis model 3302 is complete, and the analysis model is trained to accurately predict the thickness of the thin films based on the process conditions. Analysis model 3302 can then be used to predict thin film thicknesses and select process conditions that will result in a desired thin film thickness. While using the trained model 3302, a process condition vector, representing a current process condition for a thin film process currently being performed and having the same format as process condition vector 3352, is provided to the trained analysis model 3302. The trained analysis model 3302 can then predict the thickness of a thin film that will result from these process conditions.

[0144] A specific example of a neural network-based analysis model 302 was discussed in relation to Fig. 23. However, other types of neural network-based analysis models or analysis models of types other than neural networks may be used without deviating from the scope of this disclosure. Furthermore, the neural network may have different numbers of neural layers, which have different numbers of nodes, without deviating from the scope of this disclosure.

[0145] Fig. Figure 24 is a flowchart of process 3400 for training an analysis model to identify process conditions that result in orderly etching of a thin film, according to one embodiment. An example of an analysis model is analysis model 3302 from [reference missing]. Fig. 22. The various steps of process 3400 can utilize components, processes, and techniques related to Fig. 20-23 are described accordingly. Fig. 24 in relation to Fig. Described in sections 20-23.

[0146] In 3402, the process 3400 collects training set data, which includes historical thin-film data and historical process condition data. This can be accomplished by using a data acquisition system or process. The data acquisition system or process can collect training set data by accessing one or more databases associated with the semiconductor process system 3200 and collecting and organizing various types of data contained in the one or more databases. The data acquisition system or process, or other system or process, can process and format the collected data to produce a training set. The training set data 3306 can include historical thin-film data 3308 and historical process condition data 3310, as described in relation to Fig. 22 is described.

[0147] In module 3404, process 3400 inputs historical process condition data into the analysis model. For example, this could involve inputting historical process condition data 3310 into the analysis model 3302 using the training module 3304, as described in the following example: Fig. 22. The historical process condition data can be provided to the analysis model 3302 in successive discrete sets. Each discrete set can correspond to a single thin-film etching process or a section of a single thin-film etching process. The historical process condition data can be provided to the analysis model 3302 as vectors. Each set can have one or more vectors formatted for receiving and processing by the analysis model 3302. The historical process condition data can be provided to the analysis model 3302 in other formats without deviating from the scope of this disclosure.

[0148] In 3406, the process generates 3400 predicted thin-film data based on historical process condition data. Specifically, for each set of historical thin-film condition data, the analysis model 3302 generates 3310 predicted thin-film data. The predicted thin-film data represent a prediction of properties, such as the remaining thickness, of a thin film that would result from that particular set of process conditions. The predicted thin-film data may include thickness, uniformity, composition, crystal structure, or other aspects of a remaining thin film.

[0149] In 3408, the predicted thin-film data are compared with the historical thin-film data 3308. Specifically, the predicted thin-film data for each set of historical process condition data are compared with the historical thin-film data 3308 associated with that set of historical process condition data. The comparison can result in an error function that indicates how closely the predicted thin-film data match the historical thin-film data 3308. This comparison is performed for each set of predicted thin-film data. In one embodiment, this process can include generating an accumulated error function or display that shows how the totality of the predicted thin-film errors compares to the historical thin-film data 3308. The comparisons can be performed by the training module 3304 or by the analysis model 3302.The comparisons may include other types of functions or data than those described above, without deviating from the scope of this disclosure.

[0150] In step 3410, process 3400 determines whether the predicted thin-film data matches the historical thin-film data, based on the comparisons generated in step 3408. For example, the process determines whether the predicted remaining thickness after a historical etching process matches the actual remaining thickness. In one example, if the accumulated error function is lower than an error tolerance, process 3400 determines that the thin-film data matches the historical thin-film data. In another example, if the accumulated error function is higher than an error tolerance, process 3400 determines that the thin-film data does not match the historical thin-film data. In another example, the error tolerance can range from 0.1 to 0.In other words, if the accumulated percentage error is less than 0.1% or 10%, then process 3400 considers that the predicted thin-film data agree with the historical thin-film data. If the accumulated percentage error is greater than 0.1% or 10%, then process 3400 considers that the predicted thin-film data do not agree with the historical thin-film data. Other tolerance ranges may be used without deviating from the scope of this disclosure. Error values ​​may be calculated in various ways without deviating from the scope of this disclosure. The training module 3304 or the analysis model 3302 can make the determinations associated with process step 3410.

[0151] In one embodiment, if the predicted thin-film data does not match the historical thin-film data 3308 at step 3410, the process proceeds to step 3412. At step 3412, process 3400 adjusts the internal functions associated with analysis model 3302. In one example, training module 3304 adjusts the internal functions associated with analysis model 3302. From step 3412, the process returns to step 3404. At step 3404, the historical process condition data is again provided to analysis model 3302. Because the internal functions of analysis model 3302 have been adjusted, analysis model 3302 will generate different predicted thin-film data than in the previous cycle. The process continues with steps 3406, 3408, and 3410, and the accumulated error is calculated.If the predicted thin-film data do not match the historical thin-film data, the process returns to step 3412 and the internal functions of the analysis model 3302 are readjusted. This process continues iteratively until the analysis model 3302 generates predicted thin-film data that matches the historical thin-film data 3308.

[0152] In one embodiment, if the predicted thin-film data matches the historical thin-film data, process step 3410 in process 3400 then proceeds to 3414. At step 3414, the training is completed. The analysis model 3302 is now ready to be used to identify process conditions and can be employed in thin-film etching processes performed by the semiconductor process system 3200. Process 3400 may include other steps or arrangements of steps than those shown and described herein without deviating from the scope of this disclosure.

[0153] Fig. Figure 25 is a flowchart of Process 3500 for dynamically selecting process conditions for the thin-film etching process and for carrying out a thin-film etching process, according to one embodiment. The various steps of Process 3500 can utilize components, processes, and techniques that relate to Fig. 20-24 are described accordingly. Fig. 25 in relation to Fig. Described in sections 20-24.

[0154] In process 3502, process 3500 provides target thin-film condition data to the analysis model 3302. The target thin-film condition data identifies selected properties of a thin film to be formed by the thin-film etching process. The target thin-film condition data may specify a target remaining thickness, a target composition, a target crystal structure, or other properties of the thin film. The target thin-film condition data may specify a range of thicknesses. The target condition or properties that can be selected are based on thin-film property(ies) used in the training process. In the example of Fig. 25 The training process focuses on thin film thickness.

[0155] In process 3504, process 3500 provides static process conditions to analysis model 3302. These static process conditions are not adjusted for subsequent thin-film etching processes. The static process conditions may include the target feature density, which indicates the density of structures on the wafer where the thin-film etching process is performed.The static process conditions may include an effective planar crystal orientation, an effective planar roughness index, an effective sidewall area of ​​features on the surface of the semiconductor wafer, an exposed effective sidewall tilt angle, an exposed surface film functional group, an exposed sidewall film functional group, a rotation or tilt of the semiconductor wafer, process gas parameters (materials, phases of materials and temperature of materials), a remaining amount of material fluid in the fluid sources 3208 and 3210, a remaining amount of fluid in the purge sources 3212 and 3214, a humidity level within a process chamber, an age of an ampoule used in the etching process, light absorption or reflection within the process chamber, the length of pipes or tubes that will supply fluids to the process chamber, or other conditions.The static process conditions may differ from those described above without deviating from the scope of this disclosure. Furthermore, in some cases, some of the previously listed static process conditions may be dynamic process conditions that are subject to adjustment, as described in more detail below. In the example of... Fig. Five dynamic process conditions include temperature, pressure, humidity, and flow rate. Static process conditions include phase, ampoule age, etching area, etching density, and sidewall angle.

[0156] In 3506, process 3500 selects dynamic process conditions for the analysis model according to one embodiment. The dynamic process conditions can include any process conditions not designated as static process conditions. For example, the training set data may contain a large number of different types of process condition data in the historical process condition data 3310. Some of these types of process conditions are defined as the static process conditions, and some of these types of process conditions are defined as dynamic process conditions. Accordingly, when the static process conditions are supplied during operation 3504, the remaining types of process conditions can be defined as dynamic process conditions. The analysis model 3302 can initially select initial values ​​for the dynamic process conditions.Once the initial values ​​for the dynamic process conditions have been selected, the analysis model has a complete set of process conditions to be analyzed. In one embodiment, the initial values ​​for the dynamic process conditions can be selected based on previously determined starter values, or in accordance with other schemes.

[0157] The dynamic process conditions may include the flow rate of fluids or materials from fluid sources 3208 and 3210 during the etching process. The dynamic process conditions may also include the flow rate of fluids or materials from rinsing sources 3212 and 3214. Furthermore, the dynamic process conditions may include pressure, temperature, humidity, durations of various etching process steps, voltages, or electric fields generated within the process chamber. The dynamic process conditions may include other types of conditions without deviating from the scope of this disclosure.

[0158] In 3508, the analysis model 3302 generates predicted thin-film data based on the static and dynamic process conditions. The predicted thin-film data exhibit the same types of thin-film properties established in the target thin-film condition data. In particular, the predicted thin-film data exhibit the same types of predicted thin-film data from the training process described in references 21-25. For example, the predicted thin-film data may include thin-film thickness, film composition, or other thin-film parameters.

[0159] In process 3510, the process compares the predicted thin-film data with the target thin-film data. Specifically, analysis model 3302 compares the predicted thin-film data with the target thin-film data. The comparison indicates how closely the predicted thin-film data matches the target thin-film data. The comparison can show whether or not predicted thin-film data falls within tolerances or ranges established by the target thin-film data. For example, if the target thin-film thickness is between 1 nm and 9 nm, the comparison will then show whether the predicted thin-film data falls within this range.

[0160] At 3512, if the predicted thin-film data does not match the target thin-film data, the process continues to 3513. At 3514, the analysis model 3302 adjusts the dynamic process condition data. From 3514, the process returns to 3508. At 3508, the analysis model 3302 again generates predicted thin-film data, based on the static process conditions and the adjusted dynamic process conditions. The analysis model then compares the predicted thin-film data with the target thin-film data at 3510. At 3512, if the predicted thin-film data does not match the target thin-film data, the process continues to 3514, and the analysis model 3302 adjusts the dynamic process conditions again. This process continues until predicted thin-film data is generated that matches the target thin-film data. If the predicted thin-film data matches the target thin-film data 3512, the process continues with 3516.

[0161] In the 3516 process, the 3500 adjusts the thin-film process conditions of the semiconductor process system 3200 based on the dynamic process conditions resulting from the predicted thin-film data, within the target thin-film data. For example, the control system 3224 can adjust fluid flow rates, etch stop durations, pressure, temperature, humidity, or other factors in accordance with the dynamic process condition data.

[0162] In 3518, the semiconductor process system 3200 performs a thin-film etching process in accordance with the adapted dynamic process conditions identified by the analysis model. In one embodiment, the thin-film etching process is an ALE process. However, other thin-film etching processes can be used without deviating from the scope of this disclosure. In one embodiment, the semiconductor process system 3200 adapts the process parameters between individual etching stages in a thin-film etching process based on the analysis model. For example, in an ALE process, the thin film is etched layer by layer. The analysis model 3302 can identify parameters to be used for etching the next layer. Accordingly, the semiconductor process system can adapt etching conditions between the different etching stages.

[0163] Different embodiments can offer advantages. The GAA capacitors 20C, 20D, which feature either the heavily doped channels 26 or the channels 28 respectively, allow for an increase in component density. The ability to stack wafers containing the GAA capacitors 20C, 20D with wafers that either contain the GAA capacitors 20C, 20D or are free of them, allows for increased design flexibility and a novel way to create high-density DRAM packages.

[0164] In accordance with at least one embodiment, a device comprises a substrate; a first nanostructure above the substrate, comprising a semiconductor having a first resistance; a second nanostructure above the substrate, laterally displaced from the first nanostructure at approximately the same height above the substrate as the first nanostructure, comprising a conductor having a second resistance lower than the first resistance; a first gate structure above and wound around the first nanostructure; and a second gate structure above and wound around the second nanostructure.

[0165] In accordance with at least one embodiment, a device comprises a first capacitor of a second wafer. The first capacitor has a first channel having a first end contacting a first epitaxial region and a second end contacting a second epitaxial region; a first gate structure over and wound around the first channel; and a first contact over and contacting the first epitaxial region. The device further comprises a first transistor of a first wafer bonded to the second wafer, with the first transistor located over the first capacitor.The first transistor has a second channel having a first end that contacts a third epitaxial region, and a second end that contacts a fourth epitaxial region; a second gate structure over and wound around the second channel; and a backside via that contacts the third epitaxial region and is electrically connected to the first epitaxial region.

[0166] In accordance with at least one embodiment, a method comprises forming a first semiconductor fin projecting from a substrate; forming a first gate structure over the first semiconductor fin; forming first channels of the first semiconductor fin by etching regions of the first semiconductor fin exposed by the first gate structure; reducing the resistivity of the first channels of the first semiconductor fin to below about 100 ohms / square; and forming first and second source / drain regions on each side of the first gate structure and the first channels.

[0167] The foregoing outlines features of some embodiments so that those skilled in the art will better understand the aspects of this disclosure. Those skilled in the art will appreciate that they can already use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of this disclosure and that they can make various changes, substitutions, and modifications herein without deviating from the nature and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 049525

[0001] US 10164012

[0038] US 10361278

[0038]

Claims

[1] comprising a device: a substrate; a first nanostructure above the substrate, which includes a semiconductor that has a first resistance; a second nanostructure above the substrate, offset laterally from the first nanostructure, at approximately the same height above the substrate as the first nanostructure, comprising a conductor having a second resistance which is lower than the first resistance; a first gate structure over and wrapping the first nanostructure; and a second gate structure above the second nanostructure and wrapping it around. [2] Device according to claim 1, wherein the ratio of the first resistance to the second resistance is at least about 100. [3] Device according to claim 1 or 2, wherein: the first nanostructure further dopants with a first doping concentration in the semiconductor; the conductor of the second nanostructure comprises the semiconductor and dopants with a second doping concentration; and a ratio of the second doping concentration to the first doping concentration of at least approximately 100. [4] Device according to claim 3, wherein the dopants include boron, aluminium, gallium, indium or a combination thereof. [5] Device according to one of the preceding claims, wherein the conductor of the second nanostructure contains a metal nitride. [6] Device according to claim 5, wherein the metal nitride contains TiN or TaN. [7] Device according to one of the preceding claims, wherein: the first nanostructure is a nanosheet or nanowire of a field-effect transistor; and The second nanostructure is a nanosheet or nanowire of an integrated capacitor. [8] comprising a device: a first capacitor of a second wafer, wherein the first capacitor has: - a first channel having a first end that contacts a first epitaxial region and a second end that contacts a second epitaxial region; - a first gate structure over the first channel and wrapping around it; and - making initial contact over the first epitaxial area and contacting it; and a first transistor of a first wafer which is bonded to the second wafer, wherein the first transistor is located above the first capacitor, wherein the first transistor has: - a second channel having a first end that contacts a third epitaxial region and a second end that contacts a fourth epitaxial region; - a second gate structure above and surrounding the second channel; and - a backside via that contacts the third epitaxial region and is electrically connected to the first epitaxial region. [9] Device according to claim 8, wherein the first channel has a semiconductor with a doping concentration of about 10 16 atoms / cm² 3 up to about 10 21 atoms / cm² 3 is endowed. [10] Device according to claim 8 or 9, wherein the first channel contains a metal nitride. [11] Device according to any one of claims 8 to 10 above, further comprising: a second transistor of the second wafer; and a third transistor of the first wafer, wherein the third transistor is located above the second transistor, wherein a fifth epitaxial region of the third transistor is electrically connected to a sixth epitaxial region of the second transistor by at least one metal-to-metal bond at an interface of the first wafer and the second wafer. [12] Device according to claim 11, wherein a third channel of the second transistor has a doping concentration that is less than about 1 13 atoms / cm² 3 is. [13] Device according to any one of the preceding claims 8 to 12, wherein the backside via is separated from the fourth epitaxial area by a buffer layer. [14] Procedure encompassing: Formation of a first semiconductor fin protruding from a substrate; Forming a first gate structure over the first semiconductor fin; Forming first channels of the first semiconductor fin by etching areas of the first semiconductor fin exposed by the first gate structure; Reducing the resistivity of the first channels of the first semiconductor fin to below 100 ohms / square; and Forming a first source / drain region and a second source / drain region on each side of the first gate structure and the first channels. [15] Method according to claim 14, wherein reducing the resistivity comprises: Doping of semiconductor layers of the first semiconductor fin with a dopant concentration of approximately 1 16 atoms / cm² 3 up to about 1 21 atoms / cm² 3 . [16] Method according to claim 15, wherein the doping is a solid-phase diffusion process. [17] Method according to claim 15 or 16, wherein the doping is carried out on areas of a wafer that are exposed by a mask for forming capacitors, and the mask is located at least over areas of the wafer for forming active transistors. [18] Method according to any one of claims 14 to 17, comprising reducing the resistivity: Replacing the first channels with a metal nitride. [19] Method according to claim 18, wherein reducing the resistivity further comprises: Replacing the first source / drain region and the second source / drain region with the metal nitride. [20] Method according to claim 18 or 19, further comprising: Forming a barrier layer on the substrate prior to the formation of the first semiconductor fin, with the barrier layer located between the channels and the substrate.