A multifunctional silicon-based optoelectronic neurosynaptic device and a preparation method thereof

Abstract

The application discloses a multifunctional silicon-based optoelectronic neural synapse device, which comprises a silicon-on-oxide layer, a photoelectric response layer and a top electrode, wherein the silicon-on-oxide layer is composed of an oxide layer and a silicon substrate, the oxide layer is located on the silicon substrate, the photoelectric response layer is located on the oxide layer and is a semiconductor perovskite film, and the top electrode is located on the photoelectric response layer and is an inert metal material. The device can perform electrical signal writing under lower energy consumption and low crosstalk, and has completed multiple light regulation functions. The application further provides a preparation method of the multifunctional silicon-based optoelectronic neural synapse device. The preparation method has the advantages of low cost, high fault tolerance and simple operation.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of neuromorphic chips, and particularly relates to a multifunctional silicon-based optoelectronic synapse device and a preparation method thereof. BACKGROUND

[0002] With the rise of the Internet of Things and big data, people's demand for low-energy and high-performance computing is growing. However, traditional computing based on the Von Neumann architecture is difficult to meet the needs of human society due to the separation of storage and calculation, resulting in slow data transmission speed and high energy consumption. Neuromorphic computing has a different information processing method than computing based on the Von Neumann architecture, with features such as storage and calculation integration, which is expected to greatly improve computing performance and reduce energy consumption. Neuromorphic computing mainly simulates the way the human brain processes information. In the human brain, neurons achieve functions such as learning and memory by changing synaptic weights between synapses. Therefore, to achieve neuromorphic computing, the development of artificial synapses (i.e., synapse devices) that simulate synapses is crucial.

[0003] Optoelectronic synapse devices are an important hardware basis for neuromorphic computing. The literature Optoelectronic Synaptic Devices for Neuromorphic Computing, Y Wang, L Yin, W Huang et al., Advanced Intelligent Systems, 2021, 3(1), discloses that optoelectronic synapse devices have advantages such as low power consumption, high fault tolerance, high connectivity, and distributed parallel processing compared to traditional CMOS transistors.

[0004] Although optoelectronic synapse devices have developed rapidly in recent years, there are still some technical difficulties. Two-terminal structure devices are the most suitable for simulating synapse functions.

[0005] Chinese patent CN107579155B discloses a device including a "metal / a-Si / metal" surface plasmonic waveguide and an "upper electrode / dual resistive switching layer / lower electrode" memristor embedded therein; the surface plasmonic waveguide has a vertical three-layer structure of "second metal layer / dielectric layer / first metal layer" from top to bottom; the memristor has a vertical four-layer structure of "upper electrode / second resistive switching layer / first resistive switching layer / lower electrode" from top to bottom, and the first resistive switching layer and the second resistive switching layer of the memristor are horizontally connected to the dielectric layer of the surface plasmonic waveguide as a light signal propagation channel; the synapse device reads the resistance value through a light signal, but the change in resistance value is still achieved by applying a voltage, and the problem of not being able to write through a light signal is not solved, and electrical signal writing will cause high energy consumption and high crosstalk.

[0006] A Chinese patent with the patent number CN111312899B discloses a photoelectric neural synapse device with zero energy consumption and a preparation method. The neural synapse device structure includes a top electrode, a hole transport layer, a photoelectric response layer, an electron transport layer, and a bottom electrode. The photoelectric neural synapse device is subject to ohmic contact of metal and semiconductor, cannot be well regulated by voltage for contact barrier, and thus can only simulate a few neural synapse functions. In addition, the photoelectric neural synapse has many layers, complex process, and poor integration. SUMMARY

[0007] The present application provides a multifunctional silicon-based photoelectric neural synapse device which can perform optical signal writing at low energy consumption and low crosstalk, and has completed multiple optical regulation functions.

[0008] A multifunctional silicon-based photoelectric neural synapse device, comprising:

[0009] a bottom electrode layer, the bottom electrode layer being a silicon-on-insulator (SOI) layer, the SOI layer being on a silicon substrate with an oxide layer;

[0010] a photoelectric response layer, the photoelectric response layer being located on the bottom electrode layer, the photoelectric response layer being a semiconductor perovskite film;

[0011] and a top electrode, the top electrode being located on the photoelectric response layer, the top electrode being an inert metal material.

[0012] In the present application, the photoelectric response layer with perovskite is directly in contact with the silicon-on-insulator layer. Under light conditions, the defects existing at the contact interface and the potential well formed by the heterojunction built-in electric field can capture and temporarily store electric charges. When the light stops, the electric charges are gradually released from the interface under the effect of thermal desorption, producing decay current, and thus multiple neural synapse functions can be simulated.

[0013] The thickness of the photoelectric response layer is 200-300 nm.

[0014] If the thickness is too high, light will be absorbed or reflected in the metal layer, and cannot be incident on the photoelectric response layer or be insufficient to penetrate the photoelectric response layer. If the thickness is too thin, the photoelectric response layer cannot effectively absorb light, and the energy consumption required for regulating multiple neural synapse functions is high.

[0015] The thickness of the SOI is 200-500 nm.

[0016] The thickness of the top electrode is 50-100 nm.

[0017] The inert metal material is gold, platinum, or palladium.

[0018] The working principle of the multifunctional silicon-based photoelectric neural synapse device provided by this invention is as follows:

[0019] The silicon-based photoelectric synaptic device disclosed in this invention exhibits the photovoltaic effect due to the built-in electric fields of the Schottky junction and semiconductor heterojunction, enabling it to operate without applied bias voltage and achieve zero power consumption. The Schottky barrier and the semiconductor heterojunction barrier are modulated by the electrical bias voltage, allowing changes in the direction of photogenerated carrier movement and their capture and desorption behavior at the interface. When light is incident, the resistance of the photoresponse layer can be altered, solving the problem of inability to perform optical writing. By changing the polarity applied to the device, the device's response to optical signals can achieve enhancement and suppression effects, enabling the simulation of various synaptic functions, such as two-pulse facilitation / inhibition (PPF / PPD), duration-dependent plasticity (SDDP), number-dependent plasticity (SNDP), and frequency-dependent plasticity (SRDP). This solves the problem of limited functionality caused by the inability of two-terminal devices to effectively modulate the synaptic behavior with electric fields.

[0020] This invention also provides a method for fabricating the aforementioned multifunctional silicon-based photoelectric neural synapse device, comprising:

[0021] (1) The SOI is ultrasonically cleaned and dried, and an adhesive is spin-coated onto the dried SOI to obtain an SOI coated with an adhesive, wherein the spin-coating speed is 2000–4000 rpm.

[0022] (2) Photoresist is spin-coated onto an SOI coated with an adhesive, and after drying, a spin-coated SOI is obtained. The surface of the spin-coated SOI is exposed, developed and etched by ICP using a mask to obtain an imaged SOI.

[0023] (3) The MAPbI3 precursor solution is spin-coated onto the patterned SOI surface to form a photoresponse layer on the patterned SOI surface. Using a mask and vacuum thermal evaporation technology, a patterned metal thin film is deposited on the surface of the photoresponse layer to obtain a multifunctional silicon-based photoelectric neural synapse device.

[0024] In step (1):

[0025] The ultrasonic cleaning time is 20–40 min.

[0026] The drying parameters are: drying temperature of 80–120℃ and drying time of 1–5 min.

[0027] After spin coating the adhesive onto the dried SOI, the SOI is annealed at 80–120°C and then dried for 2–5 minutes.

[0028] In step (2):

[0029] The spin coating process comprises first performing a uniform coating, and then performing a glue throwing;

[0030] The uniform coating process is: the rotation speed in the uniform coating stage is 300-500 rpm, and the uniform coating time is 5-10 s;

[0031] The glue throwing process is: the rotation speed in the glue throwing stage is 4000-6000 rpm, the glue throwing time is 35-50 s, the drying temperature is 80-120℃, and the drying time is 2-5 min.

[0032] The exposure dose is 30-80 mJ / cm 2 .

[0033] The developing solution used in the developing process is AR-300-26, and the developing solution is diluted with deionized water before developing, the volume ratio of the developing solution to the deionized water is 1:5-1:10, and the developing time is 40-60 s.

[0034] The ICP etching process is: the gas types are C4F8, SF6 and He, the gas flow rates are 10-50 sccm and 100-200 sccm, and the etching time is 30-80 s.

[0035] In step (3):

[0036] The preparation method of the MAPbI3 precursor solution comprises:

[0037] Lead iodide (PbI2) and methyl amine iodide (MAI) are dissolved in dimethylformamide (DMF) to form a mixed solution, wherein the amount of PbI2 is 400-600 mg, the amount of MAI is 100-200 mg, and the volume of DMF is 600-800 mL, then dimethyl sulfoxide (DMSO) is added to the mixed solution, the amount of DMSO is 50-100 μL, and the reaction is carried out by magnetic stirring to form a uniform MAPbI3 precursor solution.

[0038] The spin coating process comprises first performing a uniform coating, then performing a glue throwing, and finally performing an annealing treatment;

[0039] The uniform coating process is: the rotation speed in the uniform coating stage is 300-500 rpm, and the uniform coating time is 4-8 s;

[0040] The glue throwing process is: the rotation speed in the glue throwing stage is 4000-6000 rpm, the glue throwing time is 30-40 s, preferably, the glue throwing time is 5-10 s, and a reverse solvent chlorobenzene is added;

[0041] The annealing process is: annealing temperature is 60-120℃, annealing time is 5-30min.

[0042] The electrode line width of the top electrode after patterning is 10-30um, the electrode line width of the bottom electrode after patterning is 1-10um, the number of electrode lines of the top electrode after patterning and the number of electrode lines of the bottom electrode after patterning are both 5-10, the electrode lines of the top electrode after patterning and the electrode lines of the bottom electrode after patterning are perpendicular and cross to form 25-100 effective area 10-300um 2 neuromorphic receptor synapse devices.

[0043] The rotation speed of the adhesion agent is a key factor for controlling the thickness of the adhesion agent, and the regulation of the thickness of the adhesion agent is important for improving the affinity of the substrate to the photoresist and improving the integrity of the pattern of the photoetching. The adhesion agent is selected because it is non-toxic, fast and suitable for mass production. The exposure dose, the type of etching gas selected, the etching time and the process of removing the glue all affect the interface of the final SOI. If the exposure dose is too low, the development selectivity will decrease, and if the etching time is too long, the oxide layer will be partially etched, causing surface roughness and affecting the contact with the photoelectric response layer, so the required neuromorphic function cannot be achieved. The concentration and rotation speed of the solution determine the thickness of the photoelectric response layer, and the thickness should be at the optimal value to achieve the ideal absorption ratio of light in the photoelectric response layer and the SOI layer, and to achieve the simulation of the neuromorphic function.

[0044] Compared with the prior art, the excellent effects of the present application are:

[0045] (1) The present application can work under various electrode polarity conditions by forming a Schottky junction between the metal top electrode and the photoelectric response layer, and a semiconductor heterojunction between the photoelectric response layer and the SOI layer, achieving zero electric power consumption. Under different electrode polarity modulation, the transport and capture performance of the junction region for carriers changes, and the generated photocurrent also changes with the change trend of the light stimulus, so it can simulate multiple neuromorphic functions, solve the problem of single light modulation function of the electrode polarity of the two-terminal photoelectric neuromorphic device, and overcome the technical prejudice that the two-terminal device cannot effectively regulate the light response trend of the neuromorphic device through electric bias.

[0046] (2) The device is integrated by using photolithography and etching process, and the photoelectric response layer is prepared by using low-temperature solution method, which has the advantages of low cost, high fault tolerance and simple operation. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1A structural diagram of a multifunctional silicon-based optoelectronic synaptic device provided for a specific implementation;

[0048] Figure 2 A graphical flowchart of the silicon oxide layer provided for a specific implementation method;

[0049] Figure 3 Top electrode image array diagram provided for specific implementation embodiments;

[0050] Figure 4 A diagram showing the dual-pulse facilitation index of a multifunctional silicon-based optoelectronic synaptic device under different voltages, provided for a specific implementation.

[0051] Figure 5 A diagram showing the duration-dependent plasticity of stimulation under different voltages for a multifunctional silicon-based optoelectronic synaptic device provided for a specific implementation.

[0052] Figure 6 A plasticity diagram of the number of stimulations required for a multifunctional silicon-based optoelectronic synaptic device provided for a specific implementation embodiment;

[0053] Figure 7 A diagram showing the frequency-dependent plasticity of a multifunctional silicon-based optoelectronic synaptic device under different voltages, provided for a specific embodiment. Detailed Implementation

[0054] The technical solution of the present invention will be further described in detail below with reference to several preferred embodiments and accompanying drawings, such as... Figure 1 As shown, the present invention provides a multifunctional silicon-based photoelectric neural synapse device, comprising:

[0055] Top electrode (1), the top electrode is located on the photoresponse layer, and the top electrode is an inert metal Au;

[0056] Photoresponse layer (2), the photoresponse layer is located on the SOI, and the photoresponse layer is a semiconductor perovskite thin film;

[0057] Bottom electrode layer (3), the bottom electrode layer is SOI, SOI is on a silicon substrate with an oxide layer and is used as the bottom electrode.

[0058] The photoelectric response layer is prepared by a precursor solution spin coating and low-temperature annealing deposition process; the top electrode is an Au thin film with good conductivity and capable of forming a Schottky junction with the photoelectric response layer, and has a certain pass rate for light of a specific wavelength, and is deposited by a vacuum thermal evaporation method. The application stimulates the multifunctional silicon-based photoelectric neural synapse device by light through the top electrode, and applies positive and negative voltages to the multifunctional silicon-based photoelectric neural synapse device by using a semiconductor parameter analyzer to verify the double-pulse facilitation / inhibition (PPF / PPD), stimulation duration-dependent plasticity (SDDP), stimulation number-dependent plasticity (SNDP) and stimulation frequency-dependent plasticity (SRDP) of the multifunctional silicon-based photoelectric neural synapse device.

[0059] The application provides a preparation method of a multifunctional silicon-based photoelectric neural synapse device.

[0060] (1) preparing an imaged SOI, as shown in the figure, and the specific steps are as follows: Figure 2

[0061] The SOI is ultrasonically cleaned for 20 min, and then dried on a hot plate at 105 DEG C for 2 min; the AR-300-80 type adhesion promoter is spin coated on the dried SOI and baked to form a film, the spin coating speed is 4000 rpm, the annealing temperature is 105 DEG C, and the baking time is 2 min;

[0062] The AR-P5350 type photoresist is spin coated on the SOI with adhesion, and baked to form a film, the spin coating is divided into a spin coating stage and a photoresist spinning stage, wherein the spin coating process is that the spin coating stage speed is 500 rpm, and the spin coating time is 5 s; the photoresist spinning process is that the spin coating stage speed is 4000 rpm, the spin coating time is 40 s, the baking temperature is 105 DEG C, and the baking time is 4 min;

[0063] After baking, the MA / BA6 Gen4 type double-side alignment photoetching machine is used to perform ultraviolet exposure on the photoresist through a self-designed linear pattern chromium-plated quartz photoetching mask plate, the pin part width of the pattern is 1 mm, the line width is 10 mu m, the number of lines is 8, and the exposure dose is 55 mJ / cm 2 . Then, the AR-300-26 type developing solution is used for developing, and after the developing is completed, the surface is cleaned with deionized water to control the developing effect. The developing solution of the type needs to be diluted with deionized water, the ratio of the developing solution to the deionized water is 1:7, and the developing time is 45 s. Then, the SOI is subjected to ICP etching, the gas species used are 30 sccm of C4F8, 30 sccm of SF6 or 120 sccm of He, and the etching time is 60 s, so as to obtain the imaged SOI.

[0064] ​(2) Preparation of photoelectric response layer: lead iodide (PbI2) and methyl iodide amine (MAI) are dissolved in dimethylformamide (DMF) to form a mixed solution, wherein the amount of PbI2 is 461 mg, the amount of MAI is 159 mg, and the volume of DMF is 1 mL, then dimethyl sulfoxide (DMSO) is added to the mixed solution, the amount of DMSO is 100 μL, and the magnetic stirring is used for sufficient reaction to form a uniform MAPbI3 precursor solution. The precursor solution is spin-coated on the prepared patterned SOI wafer, and before spin-coating, the SOI wafer should be subjected to ultraviolet ozone cleaning to enhance the ion cleanliness of the surface, improve the adhesion and uniformity of the thin film, and be beneficial to enhancing the photoelectric response;

[0065] The spin-coating scheme is as follows: a KW-4B type spin coater is used, the spin-coating parameters are set as two steps, the glue uniformizing stage is 300-500 rpm for 5 s, the glue throwing stage is 4000 rpm for 35 s. In the glue uniformizing process, the anti-solvent chlorobenzene is dropped in the best time window, the time window is the 9th second during the glue throwing stage, and after the glue throwing is completed, the obtained liquid film is subjected to annealing crystallization treatment, the annealing temperature is 80 DEG C, and the annealing time is 10 min.

[0066] (3) Preparation of metal top electrode layer:

[0067] A metal thin film is deposited on the photoelectric response layer by vacuum thermal evaporation technology through a self-designed metal hard mask, the electrode width is 30 μm, the number of lines is 8, the pattern direction of the top electrode is perpendicular to the pattern direction of the bottom electrode, and 64 nerve synapse devices with an effective area of 300 μm 2 are formed by crossing, by using this method, the integration of the multifunctional silicon-based optoelectronic nerve synapse device is realized, and the obtained array is as shown in Figure 3 .

[0068] The performance of the multifunctional silicon-based optoelectronic nerve synapse device provided by the application is as follows:

[0069] As shown in Figure 4 , the multifunctional silicon-based optoelectronic nerve synapse device exhibits different PPF / PPD properties under different voltages. The double-pulse facilitation index (PPF index) is defined as the ratio of the current A2 generated by the second continuous light stimulation to the current A1 generated by the first stimulation. The specific method for realizing the analog PPF / PPD is that when the semiconductor parameter analyzer does not apply any bias, it can be regarded as an ammeter. The device can produce significant photoresponse in the wavelength range between near-ultraviolet light and near-infrared light, and in this embodiment, the wavelength of the light stimulation signal used is 532 nm, and the light power is 10 μW / cm 2The pulse width is 200ms, and the interval between two adjacent optical pulse signals is Δt.

[0070] Under 0V operating conditions, the shorter the interval between two adjacent optical pulse signals, the greater the decrease in photocurrent induced by the second pulse signal compared to the first. At a 20ms interval, the current of the second pulse is 95% of that of the first, showing a significant decrease. Under positive bias, the wavelength of the optical excitation signal used is 532nm, and the optical power is 10μW / cm². 2 With a pulse width of 200 ms, due to the voltage's modulation of the contact barrier, the device exhibits opposite trends in response intensity changes to two adjacent photostimulation signals. As the interval shortens, the photocurrent generated by the second photostimulation signal is significantly greater than that of the first. At an operating voltage of -0.8V, the wavelength of the photostimulation signal used is 532 nm, and the optical power is 10 μW / cm². 2 With a pulse width of 1000ms, the photocurrent generated by the second photostimulation first increases and then decreases as the interval time increases. The simultaneous implementation of PPF and PPD on a single device provides a basis for training the weights of the constructed neural network.

[0071] like Figure 5 As shown, the multifunctional silicon-based photoelectric synaptic device exhibits different SDDP properties under different operating voltages. Specifically, the device is subjected to light stimulation for varying durations, and the resulting photocurrent is measured. When no bias voltage is applied by the semiconductor parameter analyzer, it can be considered as an ammeter. In self-driven operation mode, the device exhibits photocurrent at a wavelength of 532 nm and a voltage of 10 μW / cm². 2 The photocurrent generated by illumination at different times decreases with increasing illumination time, reaching 80 pA at 100 ms and dropping to 40 pA at 5 s. Under a positive bias of 1.1 V, the photocurrent gradually increases with illumination time, increasing from 2 nA at 100 ms to 4 nA at 5 s. Under a negative bias of 0.8 V, the photocurrent decreases from -0.4 nA at 100 ms to -0.3 nA with increasing illumination time. The SDDP property, as an important function of neural synapses, is one of the characteristics that distinguishes neuromorphic visual receptors from general photodetectors.

[0072] The device exhibits different SDDP properties under different operating voltages. Specifically, the device is subjected to light stimulation for varying durations, and the resulting photocurrent is measured. When no bias voltage is applied by the semiconductor parameter analyzer, it can be considered as an ammeter. In self-driven operation mode, the device responds to light at a wavelength of 532 nm with a photocurrent of 10 μW / cm². 2The photocurrent generated by illumination at different times decreases with increasing illumination time, reaching 80 pA at 100 ms and dropping to 40 pA at 5 s. Under positive bias, the photocurrent gradually increases with increasing illumination time, rising from 2 nA at 100 ms to 4 nA at 5 s. Under negative bias, the photocurrent decreases from -0.4 nA at 100 ms to -0.3 nA with increasing illumination time. The SDDP property, as an important function of neural synapses, is one of the characteristics that distinguishes neuromorphic visual receptors from general photodetectors.

[0073] like Figure 6 As shown, the multifunctional silicon-based photoelectric neural synapse device exhibits different SNDP properties under different operating voltages. Specifically, in self-driven mode, the device is subjected to a wavelength of 532 nm and a voltage of 10 mW / cm². 2 With a pulsed light stimulation signal of 100ms pulse width and 200ms period, the generated photocurrent gradually decreases with the increase of stimulation cycles. By the 100th pulse, the photocurrent has decreased to near zero, resulting in a very weak response to light. Under positive operating voltage, at a wavelength of 532nm, and a wavelength of 10mW / cm²... 2 Under pulsed light stimulation with a pulse width of 100ms and a period of 200ms, the photocurrent generated by the device gradually increases. By the 100th stimulation, the photocurrent generated is 2.3 times that of the first stimulation. Under negative operating voltage, at a wavelength of 532nm, and a wavelength of 10mW / cm², the device... 2 Under pulsed light stimulation with a pulse width of 1000ms and a period of 1100ms, the photocurrent generated by the device gradually decreases. The photocurrent generated by the 10th light stimulation is only 0.6 times that of the first pulse. SNDP plays an important role in realizing addition operations.

[0074] like Figure 7 As shown, a multifunctional silicon-based photoelectric neural synapse device exhibits different SRDP properties under different operating voltages. Specifically, the device is subjected to light stimulation at different frequencies a certain number of times, and the ratio of the generated photocurrent to the photocurrent generated during a single stimulation is measured. In self-driven operation mode, the device is subjected to 10 different frequencies of light at a wavelength of 532nm and a wavelength of 10mW / cm². 2 When subjected to a pulsed light stimulation signal with a pulse width of 200ms, the generated photocurrent gradually decreases as the stimulation frequency increases. However, when the device is subjected to 10 pulses at different frequencies with a wavelength of 532nm and a pulse current of 10mW / cm² under a positive bias, the resulting photocurrent gradually decreases. 2 When subjected to a pulsed light stimulation signal with a pulse width of 100ms, the generated photocurrent gradually increases with the increase of the stimulation frequency. Under negative bias, the device is subjected to 10 pulses at a wavelength of 532nm and a pulse current of 10mW / cm² at different frequencies. 2The photo-generated current gradually decreases with the increase of the stimulation frequency when the pulse width of the pulse light stimulation signal is 1000 ms. The SRDP can filter signals of different frequencies, and has important applications in feature extraction and image recognition.

Claims

1. A multifunctional silicon-based optoelectronic neurosynaptic device, characterized by, Comprising: a bottom electrode layer, the bottom electrode layer being silicon on oxide; a photoelectric response layer, the photoelectric response layer being a semiconductor perovskite film and located on the bottom electrode layer; and a top electrode, the top electrode being an inert metal material and located on the photoelectric response layer. The inert metal material is gold, platinum or palladium.

2. The multifunctional silicon-based optoelectronic neurosynaptic device of claim 1, wherein, The thickness of the photoelectric response layer is 200-300 nm.

3. The method of claim 1 or 2, wherein the method further comprises: Comprising: (1) ultrasonic cleaning, drying silicon on oxide, spin coating an adhesion promoter on the dried silicon on oxide to obtain silicon on oxide coated with an adhesion promoter, wherein the spin coating speed is 2000-4000 rpm; (2) spin coating photoresist on the silicon on oxide coated with an adhesion promoter, drying to obtain silicon on oxide coated with photoresist, and using a mask to sequentially expose, develop and inductively coupled plasma etch the surface of the silicon on oxide coated with photoresist to obtain silicon on oxide with an image; (3) spin coating a MAPbI3 precursor solution on the surface of the silicon on oxide with an image to form a photoelectric response layer on the surface of the silicon on oxide with an image, and using a mask to deposit a patterned metal film on the surface of the photoelectric response layer by vacuum thermal evaporation to obtain a multifunctional silicon-based photoelectric synapse device.

4. The method of claim 3, wherein the method further comprises: In step (1), after spin coating the adhesion promoter on the dried silicon on oxide, annealing is performed at 80-120°C, followed by drying for 2-5 min.

5. The method of claim 3, wherein the method further comprises: In step (2), the spin coating process includes first applying the photoresist and then spinning the photoresist. The uniform coating process has a rotation speed of 300-500 rpm and a uniform coating time of 5-10 s. The spinning process has a rotation speed of 4000-6000 rpm, a spinning time of 35-50 s, a drying temperature of 80-120°C, and a drying time of 2-5 min.

6. The method of claim 3, wherein the method further comprises: In step (2), the developing solution used in the developing process is AR-300-26, and the developing solution is diluted with deionized water before developing, with a volume ratio of the developing solution to the deionized water being 1:5-1:10, and a developing time of 40-60 s.

7. The method of claim 3, wherein the method further comprises: In step (2), the inductively coupled plasma etching process has a gas type of C4F8, SF6 or He, a gas flow rate of 10-50 sccm and 100-200 sccm, and an etching time of 30-80 s.

8. The method of claim 3, wherein the method further comprises: In step (3), the preparation method of the MAPbI3 precursor solution comprises: dissolving lead iodide and methyl iodide amine in dimethylformamide to form a mixed solution, wherein the amount of lead iodide is 400-600 mg, the amount of methyl iodide amine is 100-200 mg, and the volume of dimethylformamide is 600-800 mL, then adding dimethyl sulfoxide to the mixed solution, the amount of dimethyl sulfoxide is 50-100 μL, and the solution is fully reacted by magnetic stirring to form a uniform MAPbI3 precursor solution.

9. The method of claim 3, wherein the method further comprises: The electrode line width of the top electrode after patterning is 10-30 μm, the electrode line width of the bottom electrode after patterning is 1-10 μm, the number of electrode lines of the top electrode after patterning and the number of electrode lines of the bottom electrode after patterning are both 5-10, the electrode lines of the top electrode after patterning and the electrode lines of the bottom electrode after patterning are perpendicular and cross to form 25-100 effective area 10-300 μm 2 neuromorphic sensor synaptronic devices.

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