Imaging element, manufacturing method, and electronic device

Abstract

The present technology relates to an imaging element capable of forming a photoelectric conversion section having a steep impurity distribution, a manufacturing method, and an electronic device. A first and a second photoelectric conversion section that are stacked are provided between a first surface and a second surface opposite to the first surface of a semiconductor substrate, an impurity distribution of the first photoelectric conversion section is a distribution having a peak on the first surface side, and an impurity distribution of the second photoelectric conversion section is a distribution having a peak on the second surface side. A side on which the impurity concentration of the first photoelectric conversion section is low and a side on which the impurity concentration of the second photoelectric conversion section is low face each other. The present technology can be applied to, for example, an imaging element in which a plurality of photoelectric conversion sections are stacked in a semiconductor substrate.

Description

TECHNICAL FIELD

[0001] The present technology relates to an imaging element, a manufacturing method, and an electronic apparatus, for example, an imaging element, a manufacturing method, and an electronic apparatus having a steep distribution. BACKGROUND

[0002] In a conventional general CCD image sensor or CMOS image sensor, a configuration is adopted in which green, red, and blue pixels are arranged on one plane, and a green, red, or blue photoelectric conversion signal is obtained from each pixel. The arrangement method of the green, red, and blue pixels includes, for example, a Bayer arrangement in which a set of two green pixels, one red pixel, and one blue pixel is arranged.

[0003] The Bayer arrangement has a loss in sensitivity because, in the red pixel, green light and blue light do not pass through the color filter and are not used for photoelectric conversion. Furthermore, since the color signal is generated by performing an interpolation process between the pixels, a false color can be generated. Furthermore, the CCD image sensor and the CMOS image sensor are miniaturized. Due to the miniaturization of the image sensor, the pixel size can be reduced, the number of photons incident on the unit pixel can be reduced, the sensitivity can be reduced, and the S / N can be reduced.

[0004] As a method of solving these problems, an image sensor in which three photoelectric conversion layers are stacked in the vertical direction to obtain photoelectric conversion signals of three colors in one pixel is known. As a structure in which three color photoelectric conversion layers are stacked on one pixel, for example, a sensor including a photoelectric conversion unit provided above a silicon substrate and detecting green light and generating signal charges corresponding to the green light, and detecting blue light and red light by stacking two PDs (photodiodes) inside the silicon substrate has been proposed (for example, see Patent Documents 1 and 2).

[0005] Due to the difference in absorption coefficient, the PDs stacked inside the silicon substrate photoelectrically convert the blue light near the light-receiving surface and photoelectrically convert the red light in the layer below the light-receiving surface. When manufacturing an image sensor having such a structure, for example, a method has been proposed in which, when the back surface is the light-receiving surface, a PD for blue light configured to have a PN junction is first formed, a predetermined thickness of silicon is then deposited by epitaxial growth, and then a PD for red light is formed (see Patent Document 3).

[0006] LIST OF CITATIONS

[0007] PATENT LITERATURE

[0008] Patent Document 1: JP 2003-332551 A

[0009] Patent Literature 2: JP 2005-340571 A

[0010] Patent Literature 3: JP 2011-138927 A SUMMARY

[0011] TECHNICAL PROBLEM

[0012] In a conventional manufacturing method for manufacturing an image sensor having a structure in which three kinds of photoelectric conversion layers are stacked in one pixel, for example, after a PD for blue light is formed, high-temperature epitaxial growth is performed. Therefore, it is possible that P-type and N-type impurities of the PD for blue light diffuse and thus it can be impossible to form a steep impurity profile of the blue light. Therefore, in particular in a fine pixel, it is not possible to sufficiently secure a saturated signal amount of the blue light.

[0013] Further, in a manufacturing case in which epitaxial growth is not performed, it is necessary to implant impurities to a deeper position with high energy, and thus it is difficult to form a steep impurity profile.

[0014] The present technology is made in view of such a situation, and makes it possible to form a steep profile.

[0015] TECHNICAL SOLUTION TO THE PROBLEM

[0016] An imaging element of one aspect of the present technology includes a stacked first photoelectric conversion section and a second photoelectric conversion section provided between a first surface and a second surface opposite to the first surface of a semiconductor substrate, wherein an impurity profile of the first photoelectric conversion section is a profile having a peak on the first surface side, and an impurity profile of the second photoelectric conversion section is a profile having a peak on the second surface side.

[0017] A manufacturing method of one aspect of the present technology is a manufacturing method executed by a manufacturing apparatus for manufacturing an imaging element, the manufacturing method including: manufacturing an imaging element including a stacked first photoelectric conversion section and a second photoelectric conversion section provided between a first surface and a second surface opposite to the first surface of a semiconductor substrate, wherein an impurity profile of the first photoelectric conversion section is a profile having a peak on the first surface side, and an impurity profile of the second photoelectric conversion section is a profile having a peak on the second surface side.

[0018] An electronic apparatus of one aspect of the present technology includes: an imaging element including stacked first and second photoelectric conversion sections provided between a first surface and a second surface opposite to the first surface of a semiconductor substrate, wherein an impurity distribution of the first photoelectric conversion section is a distribution having a peak on the first surface side, and an impurity distribution of the second photoelectric conversion section is a distribution having a peak on the second surface side; and a processing unit that processes a signal from the imaging element.

[0019] In an imaging element of one aspect of the present technology, stacked first and second photoelectric conversion sections are provided between a first surface and a second surface opposite to the first surface of a semiconductor substrate, an impurity distribution of the first photoelectric conversion section is a distribution having a peak on the first surface side, and an impurity distribution of the second photoelectric conversion section is a distribution having a peak on the second surface side.

[0020] In a manufacturing method of one aspect of the present technology, the imaging element is manufactured.

[0021] In an electronic apparatus of one aspect of the present technology, the imaging element is included, and a signal from the imaging element is processed.

[0022] The electronic apparatus can be a stand-alone apparatus, or an internal module that constitutes a single apparatus. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A schematic configuration of an imaging element to which the present technology is applied is shown.

[0024] Figure 2 is a plan view showing a configuration of an imaging element.

[0025] Figure 3 A cross-sectional configuration example according to an embodiment of an imaging element is shown.

[0026] Figure 4 A manufacturing method of an imaging element is explained.

[0027] Figure 5 A manufacturing method of an imaging element is explained.

[0028] Figure 6 A manufacturing method of an imaging element is explained.

[0029] Figure 7 An impurity distribution of a photodiode is explained.

[0030] Figure 8 An impurity distribution of a photodiode is explained.

[0031] Figure 9 A conventional manufacturing method of an imaging element is explained.

[0032] Figure 10 Another manufacturing method of an imaging element will be described.

[0033] Figure 11 Another cross-sectional configuration example of an imaging element is shown.

[0034] Figure 12 Another manufacturing method of an imaging element will be described.

[0035] Figure 13 Another manufacturing method of an imaging element will be described.

[0036] Figure 14 Another manufacturing method of an imaging element will be described.

[0037] Figure 15 Impurity distribution of a photodiode is shown.

[0038] Figure 16 Another cross-sectional configuration example of an imaging element is shown.

[0039] Figure 17 A configuration of an example of an electronic apparatus is shown.

[0040] Figure 18 A schematic configuration example of an endoscopic surgery system is shown.

[0041] Figure 19 A block diagram showing a functional configuration example of a camera head and a CCU is shown.

[0042] Figure 20 A block diagram showing a schematic configuration example of a vehicle control system is shown.

[0043] Figure 21 An explanatory diagram showing an example of mounting positions of an outside-vehicle information detecting unit and an imaging unit is shown. DETAILED DESCRIPTION

[0044] Hereinafter, a mode for implementing the present technology (hereinafter referred to as an embodiment) will be described.

[0045] <Overall configuration of imaging device>

[0046] Figure 1 A schematic overall configuration diagram showing an imaging element 1 according to the first embodiment is shown. Figure 1 The imaging element 1 in the first embodiment is a back-illuminated CMOS imaging device.

[0047] Figure 1The imaging element 1 includes a pixel region 3 including a plurality of pixels 2 arranged on a substrate 11 made of silicon, a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0048] The pixels 2 each are composed of a photodiode as a photoelectric conversion element and a plurality of pixel transistors, and the plurality of pixels 2 are regularly arranged in a two-dimensional array on the substrate 11. The pixel transistors constituting each pixel 2 can be four pixel transistors including a transfer transistor, a reset transistor, a selection transistor, and an amplification transistor, or can be three transistors except for the selection transistor.

[0049] The pixel region 3 includes a plurality of pixels 2 regularly arranged in a two-dimensional array. The pixel region 3 includes an effective pixel region (not illustrated) in which light is actually received, signal charges generated by photoelectric conversion are amplified, and the signal charges are read out to the column signal processing circuit 5, and a black reference pixel region (not illustrated) for outputting an optical black serving as a reference of a black level. The black reference pixel region is usually formed at a periphery of the effective pixel region.

[0050] The control circuit 8 generates clock signals, control signals, and the like serving as operation bases of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like, in accordance with a vertical synchronization signal, a horizontal synchronization signal, and a main clock signal. Then, the clock signals, the control signals, and the like generated by the control circuit 8 are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

[0051] The vertical drive circuit 4 is composed of, for example, a shift register, and sequentially selects and scans each pixel 2 of the pixel region 3 row by row in the vertical direction. Therefore, a pixel signal based on signal charges generated in the photodiode of each pixel 2 in accordance with the intensity of received light is supplied to the column signal processing circuit 5 through a vertical signal line 9.

[0052] One column signal processing circuit 5 is arranged, for example, for each column of pixels 2, and signal processes the signal output from each row of pixels 2, such as noise removal and signal amplification, using a signal from the black reference pixel region (not illustrated, but formed at a periphery of the effective pixel region) for each pixel column. A horizontal selection switch (not illustrated) is provided between an output terminal of the column signal processing circuit 5 and a horizontal signal line 10.

[0053] The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs a horizontal scanning pulse, and thus sequentially selects each column signal processing circuit 5 to output a pixel signal of each column signal processing circuit 5 to the horizontal signal line 10.

[0054] The output circuit 7 performs signal processing on a signal supplied from each column signal processing circuit 5 in turn through the horizontal signal line 10, and outputs the signal.

[0055] <Planar configuration of pixel>

[0056] Figure 2 A schematic planar configuration of the pixel 2 of the imaging element 1 is shown. As shown, the pixel 2 includes a photoelectric conversion region 15 in which first to third photoelectric conversion sections for photoelectrically converting light having red, green, and blue wavelengths are layered in three layers, and a charge readout section corresponding to each photoelectric conversion section. In the present embodiment, the charge readout section is composed of first to third pixel transistors TrA, TrB, and TrC corresponding to the first to third photoelectric conversion sections. In the imaging element 1 of the present embodiment, vertical light splitting is performed in the pixel 2. Figure 2

[0057] The first to third pixel transistors TrA, TrB, and TrC are formed around the photoelectric conversion region 15, and each is composed of four MOS type transistors. The first pixel transistor TrA outputs signal charges generated and accumulated by the first photoelectric conversion section, which will be described later, as a pixel signal, and includes a first transfer transistor Tr1, a reset transistor Tr4, an amplification transistor Tr5, and a selection transistor Tr6.

[0058] The second pixel transistor TrB outputs signal charges generated and accumulated by the second photoelectric conversion section, which will be described later, as a pixel signal, and includes a second transfer transistor Tr2, a reset transistor Tr7, an amplification transistor Tr8, and a selection transistor Tr9.

[0059] The third pixel transistor TrC outputs signal charges generated and accumulated by the third photoelectric conversion section, which will be described later, as a pixel signal, and includes a third transfer transistor Tr3, a reset transistor Tr10, an amplification transistor Tr11, and a selection transistor Tr12.

[0060] The reset transistors Tr4, Tr7, and Tr10 each include source / drain regions 43 and 44 and a gate electrode 40. The amplification transistors Tr5, Tr8, and Tr11 each include source / drain regions 44 and 45 and a gate electrode 41. The selection transistors Tr6, Tr9, and Tr12 each include source / drain regions 45 and 46 and a gate electrode 42.

[0061] ​In these pixel transistors TrA, TrB, and TrC, the floating diffusion portions FD1, FD2, and FD3 are connected to the source / drain regions 43 of the corresponding reset transistors Tr4, Tr7, and Tr10. Further, the floating diffusion portions FD1, FD2, and FD3 are connected to the gate electrodes 41 of the corresponding amplification transistors Tr5, Tr8, and Tr11. Further, the power supply voltage wiring Vdd is connected to the source / drain region 44 common to the reset transistors Tr4, Tr7, Tr10 and the amplification transistors Tr5, Tr8, Tr11. Further, the selection signal wiring VSL is connected to the source / drain regions 46 of the selection transistors Tr6, Tr9, and Tr12.

[0062] <Pixel cross-sectional configuration>

[0063] Figure 3 A schematic cross-sectional configuration of the pixel 2a of the imaging element 1 is shown. In Figure 3 , the first to third pixel transistors TrA, TrB, TrC, and the like are not shown.

[0064] The imaging element 1 of the present embodiment is a backside illumination type imager in which light is incident from the backside opposite to the side on which the pixel transistors are formed, that is, the frontside of the semiconductor substrate 17. In Figure 3 , the upper side is the light-receiving surface side (light incident surface side) of the backside, and the lower side is the frontside which is a circuit formation surface on which the pixel transistors, peripheral circuits such as logic circuits, and the like are formed. The light-receiving surface and the circuit formation surface have a positional relationship in which they face each other.

[0065] The photoelectric conversion region 15 has a configuration in which a first photoelectric conversion portion and a second photoelectric conversion portion composed of a first photodiode PD1 and a second photodiode PD2 formed on the semiconductor substrate 17, and a third photoelectric conversion portion composed of an organic photoelectric conversion film 36a formed on the backside of the semiconductor substrate 17 are stacked in the light incident direction.

[0066] The first photodiode PD1 and the second photodiode PD2 are formed in a well region 16 which is a first conductive type (p-type in the present embodiment) semiconductor region of the semiconductor substrate 17 made of silicon.

[0067] A p-type semiconductor region 18 having a high p-type impurity concentration is formed above the semiconductor substrate 17 in the figure. The first photodiode PD1 is composed of the p-type semiconductor region 18 and an n-type semiconductor region 19 formed on the light-receiving surface side of the semiconductor substrate 17 and having a second conductive type (n-type in the present embodiment) impurity.

[0068] Although the first conductive type will be described as p-type and the second conductive type will be described as n-type hereinafter, the first conductive type can be n-type and the second conductive type can be p-type. When the first conductive type is n-type and the second conductive type is p-type, the present technology can be implemented by appropriately replacing n-type with p-type and p-type with n-type in the description hereinafter.

[0069] An electrode 23 connected to the transfer transistor Trl is formed in contact with the n-type semiconductor region 19, and the transfer transistor Trl reads out the electric charge accumulated in the first photodiode PDl to the FDl Figure 3

[0070] The second photodiode PD2 is constituted by the n-type semiconductor region 21 formed on the front surface side of the semiconductor substrate 17 and the high-concentration p-type semiconductor region 22 formed at the interface of the semiconductor substrate 17 on the front surface side as a hole accumulation layer. Since the p-type semiconductor region 22 is formed at the interface of the semiconductor substrate 17, the dark current generated at the interface of the semiconductor substrate 17 can be suppressed.

[0071] A p-type semiconductor region 20 is formed between the first photodiode PDl and the second photodiode PD2.

[0072] The second photodiode PD2 formed in the region farthest from the light-receiving surface is a photoelectric conversion section that photoelectrically converts light having a red wavelength. Further, the first photodiode PDl formed on the light-receiving surface side is a photoelectric conversion section that photoelectrically converts light having a blue wavelength.

[0073] In the pixel 2a of Figure 3 In the pixel 2a of

[0074] The upper surface of the organic photoelectric conversion film 36a is covered with a passivation film (nitride film) 36b, and the organic photoelectric conversion film 36a and the passivation film 36b are sandwiched between the upper electrode 34a and the lower electrode 34b.

[0075] A planarization film 51 is formed on the upper side of the upper electrode 34a, and an on-chip lens 52 is provided on the planarization film 51. On the other hand, an insulating film 35 for moderating the step portion of the edge of the lower electrode 34b is provided in the region where the lower electrode 34b is not formed on the same plane as the lower electrode 34b. The upper electrode 34a and the lower electrode 34b are made of a light-transmissive material and are formed of a transparent conductive film such as an indium tin oxide (ITO) film or an indium zinc oxide film. ​

[0076] In the present embodiment, the material of the organic photoelectric conversion film 36a is a material for photoelectrically converting green light, but the organic photoelectric conversion film 36a can be formed of a material for photoelectrically converting light having a blue or red wavelength, and the first photodiode PD1 and the second photodiode PD2 can be configured to correspond to the other wavelengths.

[0077] For example, when the organic photoelectric conversion film 36a absorbs blue light, the first photodiode PD1 formed on the light-receiving surface side of the semiconductor substrate 17 can be provided as a photoelectric conversion section that photoelectrically converts green light, and the second photodiode PD2 can be provided as a photoelectric conversion section that photoelectrically converts red light.

[0078] When the organic photoelectric conversion film 36a absorbs red light, the first photodiode PD1 formed on the light-receiving surface side of the semiconductor substrate 17 can be provided as a photoelectric conversion section that photoelectrically converts blue light, and the second photodiode PD2 can be provided as a photoelectric conversion section that photoelectrically converts green light.

[0079] As the organic photoelectric conversion film that photoelectrically converts blue light, an organic photoelectric conversion material containing a coumalin dye, tri-8-hydroxyquinoline Al (Alq3), or a phthalocyanine dye, or the like can be used. Further, as the organic photoelectric conversion film for photoelectrically converting red light, an organic photoelectric conversion material containing a phthalocyanine dye can be used.

[0080] As in the present embodiment, it is desirable to set the light that is photoelectrically converted in the semiconductor substrate 17 to blue and red, and to set the light that is photoelectrically converted in the organic photoelectric conversion film 36a to green. This is because in this case, the spectral characteristics between the first photodiode PD1 and the second photodiode PD2 can be improved.

[0081] The lower electrode 34b of the organic photoelectric conversion film 36a formed on the semiconductor substrate 17 side is connected to the through electrode 32. For the through electrode 32, Al (aluminum), Ti (titanium), or W (tungsten), or the like can be used, for example. The through electrode 32 is formed from the back surface side to the front surface side of the semiconductor substrate 17.

[0082] On the front surface side of the semiconductor substrate 17, a multilayer wiring layer 27 having wiring 28 stacked in multiple layers (three layers in the present embodiment) is formed with the interlayer insulating film 29 interposed therebetween. Further, a support substrate 61 formed in the manufacturing stage is formed on the surface of the multilayer wiring layer 27.

[0083] <Manufacture of Imaging Element>

[0084] Reference will be made to Figures 4 to 6 An explanation will be made for manufacturing an imaging element having Figure 3A manufacturing method of a manufacturing apparatus of an imaging element 1 of a structure of a pixel 2a shown.

[0085] In step Sll, a semiconductor substrate 17 is prepared. As the semiconductor substrate 17, a Si (silicon) substrate can be used.

[0086] In step S12, an n-type diffusion layer (hereinafter, appropriately referred to as a first n-type diffusion layer 19) corresponding to the n-type semiconductor region 19 is formed on the side on which the on-chip lens 52 is laminated in the pixel 2a (on the side of the light-receiving surface al of the semiconductor substrate 17). Figure 3

[0087] In step S13, a p-type diffusion layer (hereinafter, appropriately referred to as a first p-type diffusion layer 18) corresponding to the p-type semiconductor region 18 is formed. The first p-type diffusion layer 18 is formed as a p-type high-concentration impurity layer at a shallower position in contact with the light-receiving surface in a manner in contact with the first n-type diffusion layer 19.

[0088] In step S14, the impurities are activated by performing activation annealing using a method such as RTA (Rapid Thermal Anneal) to form the n-type semiconductor region 19 and the p-type semiconductor region 18.

[0089] In step S15, a support substrate 101 made of, for example, silicon is attached to the light-receiving surface al side of the semiconductor substrate 17.

[0090] In step S16, the semiconductor substrate 17 is inverted, and the semiconductor substrate 17 (silicon substrate) is polished to a desired film thickness. In a subsequent step, an n-type semiconductor region 21 is formed, and if this n-type semiconductor region 21 is required to function as a photodiode that receives light having a red wavelength, the semiconductor substrate 17 is polished to a thickness that can ensure sufficient sensitivity to light having a red wavelength. The thickness that can ensure sufficient sensitivity to light having a red wavelength is, for example, at least about 3 μm.

[0091] In step S17, a p-type semiconductor region 20 (hereinafter, appropriately referred to as a second p-type diffusion layer 20) that functions as a barrier layer is formed by low-concentration ion implantation of a p-type impurity from the side opposite to the light-receiving surface side and on which the multilayer wiring layer 27 is laminated (referred to as the circuit formation surface a2 side) toward the n-type semiconductor region 19 (the first n-type diffusion layer 19).

[0092] ​The second p-type diffusion layer 20 can be provided as a barrier layer, and can be formed before the first n-type diffusion layer 19 is formed on the light-receiving surface al side. That is, the processing order can be changed so that the processing in step S17 is performed before step S12, and thus the second p-type diffusion layer 20 is formed, and then the first n-type diffusion layer 19 is formed.

[0093] In step S18( Figure 5 ), a second n-type diffusion layer 21 is formed on the second p-type diffusion layer 20 by ion implantation in the vertical direction from the circuit formation surface a2 side. The second n-type diffusion layer 21 is a region that functions as an n-type semiconductor region 21 constituting a second photodiode PD2. The second photodiode PD2 can be formed by performing ion implantation in stages in such a manner that the concentration of n-type impurities gradually increases from the second n-type diffusion layer 21 toward the circuit formation surface a2 side of the semiconductor substrate 17.

[0094] In step S19, a region corresponding to a p-type semiconductor region 22 (hereinafter, appropriately referred to as a third p-type diffusion layer 22) is formed on the upper side (the outermost surface) of the second p-type diffusion layer 20, in other words, on the circuit formation surface a2 side of the semiconductor substrate 17. The third p-type diffusion layer 22 is formed by ion implantation of p-type impurities at a high concentration. By providing the third p-type diffusion layer 22, a dark current can be suppressed. That is, the third p-type diffusion layer 22 functions as a dark current suppression region.

[0095] In step S20, the impurities are activated by activation annealing using an RTA or the like to form the n-type semiconductor region 21 and the p-type semiconductor region 22.

[0096] By performing the processing up to step S20, the stacked photodiodes are formed in the vertical direction from the light-receiving surface on the back surface side to the front surface side. That is, the first photodiode PD1 and the second photodiode PD2 are formed on the semiconductor substrate 17.

[0097] In step S21, a gate electrode 23, an FD, or the like of a vertical transfer transistor is formed on the surface side of the circuit formation surface a2.

[0098] In step S22, for example, deposition of an interlayer insulating film 29 made of silicon oxide is performed, and a multilayer wiring layer 27 made of a metal material is formed. As the metal material for forming the multilayer wiring layer 27, for example, copper, tungsten, or aluminum, or the like can be used.

[0099] In step S23( Figure 6 ), a support substrate 61 made of, for example, silicon is attached to the upper portion of the multilayer wiring layer 27.

[0100] In step S24, the element including the semiconductor substrate 17 is reversed again, and the support substrate 101 attached to the light-receiving surface a1 side is removed.

[0101] In step S25, after the hole pattern for the through electrode 32 is patterned, the semiconductor substrate 17 is opened by dry etching. Thereafter, on the light-receiving surface a1 side of the semiconductor substrate 17 and on the side wall of the trench for opening the through electrode 32, an insulating film 33 serving as an antireflection film is formed. As the antireflection film, a film having a high refractive index, a low defect level at the interface with the semiconductor layer, and a negative fixed charge is used as described below.

[0102] As the material having a negative fixed charge, for example, hafnium oxide (Hf02), aluminum oxide (AI2O3), zirconium oxide (Zr02), tantalum oxide (Ta205), and titanium oxide (Ti02), and the like can be used.

[0103] After the trench is formed, an insulating film such as silicon oxide is embedded by a method such as ALD (Atomic Layer Deposition). Further, the insulating film formed at the bottom of the trench for forming the through electrode 32 is removed by a method such as dry etching. In a state where the insulating film 33 is formed on the side wall of the trench, the through electrode 32 is formed by embedding a metal material in the trench.

[0104] In step S26, a lower electrode 34b is formed in a desired region on the through electrode 32. The lower electrode 34b is made of a transparent conductive film material, and for example, indium tin oxide (ITO) or indium zinc oxide (IZO) can be used. After the lower electrode 34b is formed, an organic photoelectric conversion film 36a is formed. Here, an organic photoelectric conversion film material that selectively absorbs green light is used as the organic photoelectric conversion film 36a, and then a upper electrode 34a made of a transparent conductive film material is formed thereon.

[0105] Although not illustrated, after step S26, a planarization film 51 and an on-chip lens 52, and the like are formed to form Figure 3 the pixel 2a illustrated in FIG. 1 (the imaging element 1 including the pixel 2a).

[0106] <Impurity Concentration of Imaging Element>

[0107] As described above, the pixel 2a (the imaging element 1 including the pixel 2a) includes a first photodiode PD1 and a second photodiode PD2. The first photodiode PD1 and the second photodiode PD2 are each formed by ion implantation. Further, ion implantation is performed from the light-receiving surface a1 side and the circuit formation surface a2 side of the semiconductor substrate 17.

[0108] As described above, in steps S12 to S14 (Figure 4 In step S18 to S20, a first p-type diffusion layer 18 and a first n-type diffusion layer 19 constituting the first photodiode PD1 are formed by ion implantation from the light-receiving surface a1. Furthermore, in steps S18 to S20... Figure 5 In the process, ion implantation is performed from the circuit formation surface a2 side to form a second n-type diffusion layer 21 and a third p-type diffusion layer 22 constituting the second photodiode PD2.

[0109] Thus, by setting the ion implantation surface for forming the first photodiode PD1 and the ion implantation surface for forming the second photodiode PD2 to be different surfaces, the first photodiode PD1 and the second photodiode PD2 can be formed with a steep impurity distribution. This will refer to... Figure 7 Please provide an explanation.

[0110] Figure 7 The diagram shows... Figure 3 The pixel 2a shown includes a p-type semiconductor region 18 (first p-type diffusion layer 18), an n-type semiconductor region 19 (first n-type diffusion layer 19), an n-type semiconductor region 21 (second n-type diffusion layer 21), and a p-type semiconductor region 22 (third p-type diffusion layer 22).

[0111] At the same time, for easy observation, Figure 7 Use and Figure 3 The pixel 2a is shown with different diagonal lines to illustrate the area. Although in Figure 7 It is not explicitly shown, but there is a p-type semiconductor region 20 (second p-type diffusion layer 20) between the n-type semiconductor region 19 and the n-type semiconductor region 21.

[0112] exist Figure 7 In the diagram, the upper side is assumed to be the light-receiving surface a1, and the lower side is the circuit formation surface a2. As described above, the first p-type diffusion layer 18 and the first n-type diffusion layer 19 are formed by ion implantation from the light-receiving surface a1. Therefore, as shown by the arrows on the left side of the diagram, the impurity concentration is higher on the light-receiving surface a1 side in each diffusion layer. The arrows in the diagram indicate that the impurity concentration increases in the direction shown by the arrows.

[0113] Viewed from the light-receiving surface a1 side of the semiconductor substrate 17, in the first p-type diffusion layer 18, the p-type impurity concentration is higher on the light-receiving surface a1 side and decreases as the distance from the light-receiving surface a1 side increases (as it becomes deeper). Similarly, in the first n-type diffusion layer 19, the n-type impurity concentration is higher on the light-receiving surface a1 side and decreases as the distance from the light-receiving surface a1 side increases (as it becomes deeper).

[0114] The first photodiode PD1 is a region having an impurity distribution in which the impurity concentration decreases in a direction in which the distance from the light-receiving surface al increases when viewed from the light-receiving surface al side. In other words, the first photodiode PD1 is a region in which the impurity distribution has a peak in impurity concentration on the light-receiving surface al side.

[0115] Although there is a portion in which the first p-type diffusion layer 18 and the first n-type diffusion layer 19 overlap, this overlapping portion can be formed thinner than the corresponding portion in the conventional imaging element 1' that will be described with reference to Figure 8 B. That is, the first photodiode PD1 having a steep impurity distribution can be formed.

[0116] Next, viewed from the circuit formation surface a2 side of the semiconductor substrate 17. In the third p-type diffusion layer 22, the p-type impurity concentration is higher on the circuit formation surface a2 side and decreases as the distance from the circuit formation surface a2 side increases (as it becomes deeper). Likewise, in the second n-type diffusion layer 21, the n-type impurity concentration is higher on the circuit formation surface a2 side and decreases as the distance from the circuit formation surface a2 side increases (as it becomes deeper).

[0117] The second photodiode PD2 is a region having an impurity distribution in which the impurity concentration decreases in a direction in which the distance from the circuit formation surface a2 increases when viewed from the circuit formation surface a2 side. In other words, the second photodiode PD2 is a region in which the impurity distribution has a peak in impurity concentration on the circuit formation surface a2 side.

[0118] Although the above is described when viewed from the circuit formation surface a2 side, the following is described when viewed from the light-receiving surface al side. In the third p-type diffusion layer 22, the p-type impurity concentration is lower on the light-receiving surface al side and increases as the distance from the light-receiving surface al side increases (as it becomes deeper). Likewise, in the second n-type diffusion layer 21, the n-type impurity concentration is lower on the light-receiving surface al side and increases as the distance from the light-receiving surface al side increases (as it becomes deeper).

[0119] The second photodiode PD2 is a region having an impurity distribution in which the impurity concentration increases in a direction in which the distance from the light-receiving surface al increases when viewed from the light-receiving surface al side.

[0120] The impurity distribution of the first photodiode PD1 is different from that of the second photodiode PD2. That is, as described above, the impurity concentration of the first photodiode PD1 is higher on the light-receiving surface a1, while the impurity concentration of the second photodiode PD2 is lower on the light-receiving surface a1. Therefore, when observing the degree of impurity concentration, the first photodiode PD1 and the second photodiode PD2 are oriented in different directions. Furthermore, when observing the impurity concentration, the first photodiode PD1 and the second photodiode PD2 are positioned facing each other on the side with the lower impurity concentration.

[0121] Pixel 2a, manufactured through the above process, is compared with a reference. Figure 8 The pixel 2a is compared with the pixel 2a produced in a different process (conventional process) than described above. Figure 8 A is with Figure 7 The same figure is shown, and pixel 2a is produced by the above process. Figure 8 B shows pixel 2a' manufactured through conventional processing (marked with an upper right slash to distinguish it from pixel 2a manufactured through the aforementioned processing).

[0122] Figure 8 Pixel 2a shown in A is compared with the reference. Figure 7 The situation is the same, and therefore, the explanation is omitted. Figure 8 Pixel 2a' shown in B also has the same Figure 8 The same structure as pixel 2a shown in A, wherein a first p-type diffusion layer 18', a first n-type diffusion layer 19', a second p-type diffusion layer 20' (not shown), a second n-type diffusion layer 21' and a third p-type diffusion layer 22' are sequentially stacked on the light-receiving surface a1 side.

[0123] In the conventional manufacturing method of pixel 2a', a first p-type diffusion layer 18', a first n-type diffusion layer 19', a second p-type diffusion layer 20' (not shown), a second n-type diffusion layer 21', and a third p-type diffusion layer 22' are formed by ion implantation from the lower side of the figure, i.e., the circuit formation surface a2 side. (Refer to...) Figure 9 Briefly describe the manufacturing method.

[0124] In step S51, a first p-type diffusion layer 18' and a first n-type diffusion layer 19' are formed. Figure 9 In the semiconductor substrate 17', the lower side is the light-receiving surface a1, and the upper side is the temporary circuit formation surface a2'. In step S51, ions are implanted from the circuit formation surface a2' side, and activation annealing is performed to form a first p-type diffusion layer 18' and a first n-type diffusion layer 19'. In step S51, the first p-type diffusion layer 18' and the first n-type diffusion layer 19' are formed near the surface of the semiconductor substrate 17'.

[0125] In step S52, silicon is added to the semiconductor substrate 17' by epitaxial growth for growing a crystal layer with aligned crystal axes to form a silicon layer 131. The silicon layer 131 is the portion in the figure corresponding to the circuit formation surface a2, starting from the temporary circuit formation surface a2'.

[0126] In step S53, a second p-type diffusion layer 20', a second n-type diffusion layer 21', and a third p-type diffusion layer 22' are formed. The second p-type diffusion layer 20', the second n-type diffusion layer 21', and the third p-type diffusion layer 22' are formed by ion implantation and activation annealing from the circuit formation surface a2 side.

[0127] The state of pixel 2a' in step S52 is the same as that in step S16 ( Figure 4 The state of pixel 2a after processing is roughly the same. Since the processing after step S53 can be performed in the same way as the processing after step S17, its description is omitted here.

[0128] In conventional manufacturing methods, after forming the first p-type diffusion layer 18' and the first n-type diffusion layer 19', a silicon layer 131 for forming the second p-type diffusion layer 20', the second n-type diffusion layer 21', and the third p-type diffusion layer 22' is formed by epitaxial growth. Because epitaxial growth is performed through high-temperature heat treatment, it also affects the formation of the first p-type diffusion layer 18' and the first n-type diffusion layer 19'.

[0129] Figure 9 The first p-type diffusion layer 18' shown in step S51 is compared with the first p-type diffusion layer 18' shown in step S52. Impurities diffuse into the first p-type diffusion layer 18' shown in step S51 through heat treatment during epitaxial growth.

[0130] Therefore, the vertical width of the first p-type diffusion layer 18' shown in step S52 becomes wider than the vertical width of the first p-type diffusion layer 18' shown in step S51. Furthermore, the vertical width of the first n-type diffusion layer 19' shown in step S52 becomes wider than the vertical width of the first n-type diffusion layer 19' shown in step S51.

[0131] Refer again Figure 8 B. The area of ​​overlap between the first p-type diffusion layer 18' and the first n-type diffusion layer 19' is... Figure 8 The area where the first p-type diffusion layer 18 and the first n-type diffusion layer 19 overlap is large, as shown in Figure A. This is because, as described above, the first p-type diffusion layer 18' and the first n-type diffusion layer 19' become larger, and therefore, the area where the first p-type diffusion layer 18' and the first n-type diffusion layer 19' overlap increases.

[0132] In the pixel 2a' manufactured by the conventional method, the region where the first p-type diffusion layer 18' overlaps with the first n-type diffusion layer 19' is large, and thus, it is difficult to form a steep impurity distribution. However, in the pixel 2a to which the present embodiment is applied, it is possible to reduce the region where the first p-type diffusion layer 18 overlaps with the first n-type diffusion layer 19, and thus, it is possible to form a steep impurity distribution.

[0133] In the pixel 2a' manufactured by the conventional method and the pixel 2a to which the present embodiment is applied, the impurity concentration distribution is different in addition to the difference in the degree of overlap between the p-type diffusion layer and the n-type (whether it is steep).

[0134] Reference Figure 8 B. From the light-receiving surface a1 side of the semiconductor substrate 17'. In the first p-type diffusion layer 18', the p-type impurity concentration is lower on the light-receiving surface a1 side and increases as the distance from the light-receiving surface a1 side increases (as it becomes deeper). Similarly, in the first n-type diffusion layer 19', the n-type impurity concentration is lower on the light-receiving surface a1 side and increases as the distance from the light-receiving surface a1 side increases (as it becomes deeper).

[0135] The first photodiode PD1' is a region having an impurity distribution in which the impurity concentration increases in a direction in which the distance from the light-receiving surface a1 increases when viewed from the light-receiving surface a1 side. In view of this, it is different from the impurity distribution of the pixel 2a of the present technology shown in A to which the present embodiment is applied. Figure 8

[0136] Further, the second n-type diffusion layer 21' and the third p-type diffusion layer 22' are also regions having an impurity distribution in which the impurity concentration increases in a direction in which the distance from the light-receiving surface a1 increases when viewed from the light-receiving surface a1 side. That is, in the third p-type diffusion layer 22', the p-type impurity concentration is lower on the light-receiving surface a1 side and increases as the distance from the light-receiving surface a1 side increases (as it becomes deeper). Similarly, in the second n-type diffusion layer 21', the n-type impurity concentration is lower on the light-receiving surface a1 side and increases as the distance from the light-receiving surface a1 side increases (as it becomes deeper).

[0137] The second photodiode PD2' is a region having an impurity distribution in which the impurity concentration increases in a direction in which the distance from the light-receiving surface a1 increases when viewed from the light-receiving surface a1 side.

[0138] ​In the pixel 2a' manufactured by the conventional method, the first photodiode PD1' and the second photodiode PD2' have the same impurity distribution. That is, as described above, the first photodiode PD1' has a low impurity concentration on the light-receiving surface a1 side, and the second photodiode PD2' also has a low impurity concentration on the light-receiving surface a1 side. In this way, the first photodiode PD1' and the second photodiode PD2' are oriented in the same direction when the impurity concentration is observed.

[0139] As described above, the impurity distribution is also different between the pixel 2a' manufactured by the conventional method and the pixel 2a to which the present technology is applied.

[0140] According to the present technology, it is possible to form a photodiode having a steep distribution laminated in the semiconductor substrate 17. Furthermore, it is possible to form a steep distribution even if the pixel 2a is miniaturized, and thus it is possible to realize an imager (image sensor) having a high SN ratio in which photodiodes are laminated in the vertical direction.

[0141] For example, when a blue light photodiode is formed on the back surface side (light-receiving surface a1 side), it is possible to form a steep impurity distribution of the blue light photodiode. Furthermore, even in a fine pixel, it is possible to realize an imager (image sensor) in which photodiodes are laminated in the vertical direction and have a large blue light saturation signal amount and a high SN ratio.

[0142] <Other manufacturing method of imaging element>

[0143] A manufacturing method of the pixel 2a (imaging element) shown in Fig. 1 will be described below. Figure 10 The manufacturing method of the pixel 2a (imaging element) shown in Fig. 1 will be described below. Figure 3 Another manufacturing method of a manufacturing apparatus of the pixel 2a (imaging element) shown in Fig. 1 will be described below.

[0144] As another manufacturing method, a case where an SOI (Silicon On Insulator) substrate 201 is used as the semiconductor substrate 17 will be described. In step S101, the SOI substrate 201 is prepared. The SOI substrate 201 is a substrate having a structure in which a layer of a silicon oxide film called a BOX layer 202 is inserted into a silicon substrate. A silicon layer on the BOX layer 202 and a silicon layer under the BOX layer 202 are characterized in that they are insulated by the BOX layer 202 of the silicon oxide film.

[0145] In the drawing, it is assumed that the upper surface is the light-receiving surface a1 and the lower surface is the circuit formation surface a2. The film thickness from the BOX layer 202 to the light-receiving surface a1 is a desired film thickness. The desired film thickness can be a film thickness that is desired to be the final film thickness of the semiconductor substrate 17.

[0146] In step S102, a first n-type diffusion layer 19 corresponding to the n-type semiconductor region 19 is formed on the light-receiving surface a1 side.

[0147] In step S103, a first p-type diffusion layer 18 corresponding to the p-type semiconductor region 18 is formed. The first p-type diffusion layer 18 is formed as a p-type high-concentration impurity layer at a shallower position in contact with the light-receiving surface in a manner in contact with the first n-type diffusion layer 19.

[0148] In step S104, the impurities are activated by activation annealing using a method such as RTA to form the n-type semiconductor region 19 and the p-type semiconductor region 18.

[0149] In step S105, a support substrate 101 made of, for example, silicon is adhered to the light-receiving surface side of the SOI substrate 201 (semiconductor substrate 17).

[0150] In step S106, the SOI substrate 201 is inverted and polished until the SOI substrate 201 has a desired film thickness. When the SOI substrate 201 is used, it is polished until the BOX layer 202 is eliminated.

[0151] The state of the pixel 2a when the processing of step S106 ends is the same as the state of the pixel 2a when the processing of step S16( Figure 4 ) ends. Because the processing after step S106 can be performed in the same manner as the processing after step S17, the explanation thereof is omitted here.

[0152] In this way, even when the SOI substrate 201 is used, it is possible to manufacture the pixel 2a having a structure as shown in Figure 3 and an impurity distribution as described with reference to Figure 7 .

[0153] <Other configurations of imaging device>

[0154] Figure 3 The pixel 2a shown in FIG. 8 has a configuration in which the first and second photodiodes PD1 and PD2 (first and second photoelectric conversion sections) are provided in the silicon substrate 17, and a third photoelectric conversion section made of the organic photoelectric conversion film 36a is provided on the silicon substrate 17.

[0155] It is possible to configure a pixel 2b in which the third photoelectric conversion section made of the organic photoelectric conversion film 36a is also formed in the silicon substrate 17, and the first to third photoelectric conversion sections are formed in the silicon substrate 17.

[0156] Figure 11 A configuration of the pixel 2b is shown, and a configuration example of the pixel 2b in which the first to third photoelectric conversion sections are formed in the silicon substrate 17 is shown. Figure 11 The pixel 2b shown in FIG. 9 has a structure in which, from the upper side in the figure, the on-chip lens 52, the planarization film 51, the semiconductor substrate 17, and the multilayer wiring layer 27 are stacked in this order.

[0157] Further, in the semiconductor substrate 17, a p-type semiconductor region 301, an n-type semiconductor region 302, a p-type semiconductor region 303, an n-type semiconductor region 304, a p-type semiconductor region 305, an n-type semiconductor region 306, and a p-type semiconductor region 307 are stacked in this order from the light-receiving surface side. An electrode 308 is provided as an electrode of a transistor that transports the electric charge accumulated in the n-type semiconductor region 302, and an electrode 309 is provided as an electrode of a transistor that transports the electric charge accumulated in the n-type semiconductor region 304.

[0158] In the semiconductor substrate 17, when the multilayer wiring layer 27 side is viewed from the on-chip lens 52 side, a first photodiode PD1, a second photodiode PD2, and a third photodiode PD3 are stacked.

[0159] The first photodiode PD1 is a region including the n-type semiconductor region 302. The n-type semiconductor region 302 is also appropriately described as a first n-type diffusion layer 302. Further, the p-type semiconductor region 301 formed on the n-type semiconductor region 302 is also described as a first p-type diffusion layer 301.

[0160] The second photodiode PD2 is a region including the n-type semiconductor region 304. The n-type semiconductor region 304 is also appropriately described as a second n-type diffusion layer 304. Further, the p-type semiconductor region 303 formed on the n-type semiconductor region 304 is also described as a second p-type diffusion layer 303.

[0161] The third photodiode PD3 is a region including the n-type semiconductor region 306. The n-type semiconductor region 306 is also appropriately described as a third n-type diffusion layer 306. Further, the p-type semiconductor region 305 formed on the n-type semiconductor region 306 is also described as a third p-type diffusion layer 305. Further, the p-type semiconductor region 307 formed under the n-type semiconductor region 306 is also described as a fourth p-type diffusion layer 307.

[0162] With Figure 3 The member corresponding to the third photoelectric conversion part made of the organic photoelectric conversion film 36a of the pixel 2a illustrated in FIG. 6 is the first photodiode PD1 formed in the silicon substrate of the pixel 2b illustrated in FIG. 7. Figure 11

[0163] In this way, the present technology can be applied to the pixel 2b in which the first photodiode PD1, the second photodiode PD2, and the third photodiode PD3 are stacked in the silicon substrate.

[0164] Reference will be made to Figures 12 to 14 for manufacturing Figure 11 ​A manufacturing method of a manufacturing apparatus of the pixel 2b (including the imaging element 1 of the pixel 2b) shown.

[0165] In step S201, a semiconductor substrate 17 is prepared. As the semiconductor substrate 17, a Si (silicon) substrate can be used. Further, an SOI substrate can be used as the semiconductor substrate 17.

[0166] In step S202, a second n-type diffusion layer 304 corresponding to the n-type semiconductor region 304 is formed by ion implantation on the light-receiving surface al side.

[0167] In step S203, a second p-type diffusion layer 303 corresponding to the p-type semiconductor region 303 is formed on the light-receiving surface al side. The second p-type diffusion layer 303 functions as a barrier layer, and is formed by low-concentration ion implantation of a p-type impurity.

[0168] In step S204, a first n-type diffusion layer 302 corresponding to the n-type semiconductor region 302 is formed on the light-receiving surface al side. The first n-type diffusion layer 302 is formed by ion implantation, for example, from the surface of the light-receiving surface al side of the semiconductor substrate 17 in a manner having a peak within 100 nm.

[0169] In step S205, a first p-type diffusion layer 301 corresponding to the p-type semiconductor region 301 is formed. The first p-type diffusion layer 301 is formed as a p-type high-concentration impurity layer at a shallow position in contact with the light-receiving surface in a manner in contact with the first n-type diffusion layer 302.

[0170] In step S206, impurities are activated by activation annealing using a method such as RTA to form the p-type semiconductor region 301, the n-type semiconductor region 302, the p-type semiconductor region 303, and the n-type semiconductor region 304.

[0171] In step S207( Figure 13 ) a support substrate 351 made of, for example, silicon is adhered to the light-receiving surface side of the semiconductor substrate 17.

[0172] In step S208, the semiconductor substrate 17 (silicon substrate) is inverted and polished to a desired film thickness.

[0173] In step S209, a p-type impurity is ion implanted at a low concentration from the circuit formation surface a2 side opposite the light-receiving surface side and on which the multilayer wiring layer 27 is stacked, toward the upper side of the second n-type diffusion layer 304 to form a p-type semiconductor region 305 (third p-type diffusion layer 305) serving as a barrier layer.

[0174] In step S210, a third n-type diffusion layer 306 is formed by ion implantation from the circuit formation surface a2 side in the vertical direction on the upper portion of the third p-type diffusion layer 305. The third n-type diffusion layer 306 is a region for forming a third photodiode PD3. The third photodiode PD3 can be formed by stage ion implantation in which the n-type impurity concentration gradually increases from the third n-type diffusion layer 306 to the circuit formation surface a2 side of the semiconductor substrate 17.

[0175] In step S211, a fourth p-type diffusion layer 307 corresponding to the p-type semiconductor region 307 is formed on the upper side (the outermost surface) of the third n-type diffusion layer 306, in other words, on the circuit formation surface a2 side of the semiconductor substrate 17. The fourth p-type diffusion layer 307 is formed by ion implanting a p-type impurity at a high concentration. By providing the fourth p-type diffusion layer 307, the dark current can be suppressed. That is, the fourth p-type diffusion layer 307 functions as a dark current suppression region.

[0176] In step S212( Figure 14 ), the impurities are activated by activation annealing using a method such as RTA to form the n-type semiconductor region 306 and the p-type semiconductor region 307.

[0177] By performing the processing up to step S212, the stacked photodiode is formed in the vertical direction from the light-receiving surface on the back surface side to the front surface side. That is, the first photodiode PD1, the second photodiode PD2, and the third photodiode PD3 are formed on the semiconductor substrate 17.

[0178] In step S213, a gate electrode 308, 309 of a vertical transfer transistor, and an FD, and the like are formed on the surface side of the circuit formation surface a2.

[0179] In step S214, deposition of an interlayer insulating film 29 made of silicon oxide, for example, is performed, and a multilayer wiring layer 27 made of a metal material is formed. After the multilayer wiring layer 27 is formed, a support substrate 61 made of silicon, for example, is attached to the upper portion of the formed multilayer wiring layer 27.

[0180] The element is inverted again, and the support substrate 351 attached to the light-receiving surface a1 side is removed. Then, a planarization film 51 and an on-chip lens 52, and the like are formed on the light-receiving surface a1, and thus, the pixel 2b (the imaging element 1 including the pixel 2b) illustrated in FIG. 1 is formed. Figure 11

[0181] In this way, even when the pixel 2b in which three layers of photodiodes PD are stacked is formed in the silicon substrate 17, each photodiode PD can be formed as a photodiode having a steep impurity distribution as in the case described with reference to Figure 7 and Figure 8 the drawings.​

[0182] In reference Figures 12 to 14 In the manufacturing process shown, after the p-type and n-type diffusion layers are formed, the step for epitaxial growth is not performed. Therefore, it is possible to prevent impurities in the p-type and n-type diffusion layers from being activated by the heat treatment during the epitaxial growth step.

[0183] Reference Figure 15 Explain the impurity concentrations of the first photodiode PD1, the second photodiode PD2, and the third photodiode PD3. Figure 15 The diagram shows a first n-type diffusion layer 302, a second n-type diffusion layer 304, and a third n-type diffusion layer 306. The arrows shown on the left side of the diagram indicate the direction of the impurity concentration.

[0184] Because in step S204 ( Figure 12 The first n-type diffusion layer 302 is formed by ion implantation from the light-receiving surface a1 side, so it is formed as a region with high impurity concentration on the light-receiving surface a1 side.

[0185] Because in step S202( Figure 12 The second n-type diffusion layer 304 is formed by ion implantation from the light-receiving surface a1 side, so it is formed as a region with high impurity concentration on the light-receiving surface a1 side.

[0186] Although not shown, like the first n-type diffusion layer 302 and the second n-type diffusion layer 304, the first p-type diffusion layer 301 and the second p-type diffusion layer 303 are also formed by ion implantation from the light-receiving surface a1 side, and therefore, they are formed as regions with high impurity concentration on the light-receiving surface a1 side.

[0187] Because in step S210 ( Figure 13 In this process, the third n-type diffusion layer 306 is formed by ion implantation from the circuit formation surface a2 side, thus forming a region with a high impurity concentration on the circuit formation surface a2 side. In other words, the third n-type diffusion layer 306 is formed as a region with a low impurity concentration on the light-receiving surface a1 side.

[0188] Although not shown, like the third n-type diffusion layer 306, the third p-type diffusion layer 305 and the fourth p-type diffusion layer 307 are also formed by ion implantation from the circuit formation surface a2 side, and therefore, they are formed as regions with high impurity concentrations on the circuit formation surface a2 side.

[0189] The first n-type diffusion layer 302 (including the first photodiode PD1 with the first n-type diffusion layer 302) and the second n-type diffusion layer 304 (including the second photodiode PD2 with the second n-type diffusion layer 304) have a peak value with high impurity concentration on the light-receiving surface a1 side and have an impurity distribution with impurities diffusing toward the circuit formation surface a2 side.

[0190] The third n-type diffusion layer 306 (including the third photodiode PD3 of the third n-type diffusion layer 306) has a peak of high impurity concentration on the circuit formation surface a2 side, and has an impurity distribution in which the impurities diffuse toward the light receiving surface al side.

[0191] In this way, as with the pixel 2a in the first embodiment, it is also possible to form the pixel 2b in the second embodiment by laminating photodiodes having different direction concentration distributions in the silicon substrate.

[0192] Further, the pixel 2b having such an impurity distribution is able to be used as an image sensor having a high SN ratio even if it is configured as a fine pixel.

[0193] <Other configurations of pixel>

[0194] A pixel 2c having a structure in which a high refractive index layer is provided in the pixel 2a shown in FIG. 1 or the pixel 2b shown in FIG. 2 will be described. Figure 3 Figure 11 A pixel 2c in which a high refractive index layer is provided in the pixel 2a shown in FIG. 1 will be described.

[0195] Figure 16 A pixel 2c in which a high refractive index layer is provided in the pixel 2a shown in FIG. 1 will be described. Figure 3 Figure 3 The high refractive index layer is formed by a p-type semiconductor region 401 corresponding to the p-type semiconductor region 18 in the pixel 2a shown in FIG. 1 and an n-type semiconductor region 402 corresponding to the n-type semiconductor region 19.

[0196] The p-type semiconductor region 401 is formed in a shape having a concave-convex surface on the light receiving surface al side and the circuit formation surface a2 side. Because the p-type semiconductor region 401 is configured in a shape having a concave-convex surface, the n-type semiconductor region 402 is also formed in a shape having a concave-convex surface on the light receiving surface al side and the circuit formation surface a2 side. Further, because the n-type semiconductor region 402 is configured in a shape having a concave-convex surface, the surface of the p-type semiconductor region 403 on the light receiving surface al side is also formed as a concave-convex surface.

[0197] By forming the p-type semiconductor region 401 and the n-type semiconductor region 402 in a concave-convex shape, the incident light is incident on the silicon substrate 17 at a certain angle. For example, light incident on the silicon substrate 17 at a right angle is refracted by the concave-convex structure of the p-type semiconductor region 401 and the n-type semiconductor region 402, converted into light having a predetermined angle, and incident on the silicon substrate 17.

[0198] In other words, the light incident on the pixel 2c is scattered by the p-type semiconductor region 401 and the n-type semiconductor region 402 having a concave-convex structure, and incident on the pixel 2c. By scattering the incident light, more light propagates in the direction of the side wall of the pixel 2c. Although the light incident on the pixel 2c is scattered by the p-type semiconductor region 401 and the n-type semiconductor region 402 having a concave-convex structure, the light is not scattered by the p-type semiconductor region 403 and the n-type semiconductor region 404.​​Figure 16 It is not shown in the figure, but when a pixel isolation part with reflective function is provided between pixels 2c, the light incident on pixel 2c is scattered by the high refractive index layer and reflected by the pixel isolation part, and therefore returns to pixel 2c.

[0199] Furthermore, as the number of reflections increases, the optical distance for silicon absorption lengthens, thereby improving sensitivity. Because the optical distance for silicon absorption can be extended, a structure with increased optical path length can be formed, and even long-wavelength incident light can be effectively focused onto the photodiode (PD). Therefore, sensitivity can be improved even for incident light with long wavelengths.

[0200] Therefore, as described above, when multiple photodiodes are formed in the silicon substrate 17, and the photodiode near the circuit formation surface a2 (the photodiode far from the light-receiving surface a1) focuses long-wavelength incident light (such as red light), it is possible to effectively focus long-wavelength incident light, and thus, the sensitivity can be improved.

[0201] Despite Figure 16 In the case of pixel 2c shown, a high refractive index layer is provided on the light-receiving surface a1 side, but it is also possible to provide a high refractive index layer on both the light-receiving surface a1 side and the circuit formation surface a2 side. Furthermore, it is also possible to form pixel 2c with a high refractive index layer provided only on the circuit formation surface a2 side.

[0202] A high-refractive-index layer can be formed with a desired uneven shape using, for example, dry etching or wet etching methods. For example, when according to a reference... Figures 4 to 6 The manufacturing process described Figure 16 When pixel 2c is shown, it is used as a step S12 ( Figure 4 The steps prior to the processing of the silicon substrate 17 are to process the surface (light-receiving surface a1) of the silicon substrate 17 into a shape with an uneven surface using a dry etching method or a wet etching method.

[0203] By forming an uneven shape on the surface of the silicon substrate 17, the n-type semiconductor region 402 (corresponding to) formed by ion implantation in step S12 is formed. Figure 4 The n-type semiconductor region 19 is also formed as a layer with an uneven shape. Furthermore, the p-type semiconductor region 401 (corresponding to the one formed by ion implantation in step S13) is also formed. Figure 4 The p-type semiconductor region 18 in the middle is also formed as a layer with an uneven shape.

[0204] In this manner, p-type semiconductor region 401 and n-type semiconductor region 402 with concave and convex shapes can be formed. This allows for comparison with a reference... Figures 4 to 6The steps after forming the p-type semiconductor region 401 and the n-type semiconductor region 402 having the concave-convex shape are performed in the same manner as described above, and thus, it is possible to manufacture the pixel 2c in which the first photodiode PD1 and the second photodiode PD2 are stacked by performing the same steps Figure 16 The pixel 2c shown in FIG. 1 is manufactured by the manufacturing method described above.

[0205] If the pixel 2c shown in FIG. 1 is manufactured by a conventional manufacturing method, for example, with reference to Figure 9 the manufacturing method described above, the first photodiode PD1 and the second photodiode PD2 in the pixel 2c are formed by ion implantation from the circuit formation surface a2 side. When the high refractive index layer is formed by a conventional manufacturing method, the high refractive index layer is formed by processing from the light receiving surface al. Figure 16

[0206] In the case of such a manufacturing process, when the high refractive index layer is formed or the p-type semiconductor region 401 is removed by processing, the processing process can cause damage. Thus, characteristics such as a dark current can be deteriorated.

[0207] However, according to the manufacturing method to which the present technology is applied, as described above, it is possible to form the high refractive index layer without deteriorating the characteristics, and to form the pixel 2c in which a plurality of photodiodes having the high refractive index layer are stacked.

[0208] According to the present technology, it is possible to form a photodiode having a steep distribution stacked in the semiconductor substrate 17. Furthermore, it is possible to form the steep distribution even if the pixel 2a is miniaturized, and thus, it is possible to realize an imaging device (image sensor) having a high SN ratio in which photodiodes are stacked in the vertical direction.

[0209] <Example of Application to Electronic Device>

[0210] The present technology is not limited to application to an imaging element. That is, the present technology can be applied to all electronic devices using an imaging element for an imaging unit, such as an imaging device such as a digital still camera or a video camera; a portable terminal device having an imaging function; and a copying machine using an imaging element for an image reader. The imaging element can be formed as a single chip, or can be formed as a module having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together.

[0211] Figure 17 is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

[0212] Figure 17 ​The imaging element 1000 includes an optical unit 1001 including a lens group and the like, an imaging element (imaging device) 1002, and a DSP (Digital Signal Processor) circuit 1003 as a camera signal processing circuit. The imaging element 1 of the present application Figure 1 The imaging element 1000 further includes a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other through a bus 1009.

[0213] The optical unit 1001 takes in incident light (image light) from an object and forms an image on an imaging surface of the imaging element 1002. The imaging element 1002 converts the amount of incident light formed on the imaging surface by the optical unit 1001 into an electric signal in units of pixels and outputs the electric signal as a pixel signal. As the imaging element 1002, the imaging element 1 of the present application Figure 1

[0214] The display unit 1005 is configured, for example, as a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays a moving image or a still image taken by the imaging element 1002. The recording unit 100 records a moving image or a still image taken by the imaging element 1002 in a recording medium such as a hard disk or a semiconductor memory.

[0215] The operation unit 1007 issues an operation command for various functions of the imaging element 1000 in response to an operation of a user. The power supply unit 1008 appropriately supplies various power supplies serving as operation power for the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.

[0216] <Example applied to endoscope surgery system>

[0217] The technology according to the present application (the present technology) can be applied to various products. For example, the technology according to the present application can be applied to an endoscope surgery system.

[0218] Figure 18 A schematic configuration example of an endoscope surgery system to which the technology according to the present application (the present technology) can be applied is illustrated.

[0219] Figure 18 ​A state in which a surgeon (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000 is shown. As shown in the figure, the endoscopic surgery system 11000 includes: an endoscope 11100; other surgical instruments 11110 such as a gas tube 11111 and an energy treatment tool 11112; a support arm device 11120 that supports the endoscope 11100; and a cart 11200 equipped with various devices used for endoscopic surgery.

[0220] The endoscope 11100 includes a lens barrel 11101 that is inserted into a body cavity of the patient 11132 from a region of a predetermined length from a distal end, and a camera head 11102 that is connected to a proximal end of the lens barrel 11101. Although in the example shown, the endoscope 11100 is illustrated as being configured as a so-called rigid scope having a rigid lens barrel 11101, the endoscope 11100 can be configured as a so-called flexible scope having a flexible lens barrel.

[0221] The lens barrel 11101 is provided at the distal end with an opening in which an objective lens is mounted. A light source device 11203 is connected to the endoscope 11100, the light source device 11203 generates light that is guided to the distal end of the lens barrel 11101 by a light guide that extends inside the lens barrel 11101, and the light is irradiated toward an observation target in the body cavity of the patient 11132 via the objective lens. The endoscope 11100 can be a direct vision endoscope, or can be an oblique vision endoscope or a side vision endoscope.

[0222] The inside of the camera head 11102 is provided with an optical system and an imaging element, and reflected light (observation light) from the observation target is converged on the imaging element by the optical system. The imaging element photoelectrically converts the observation light, and generates an electric signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as raw (RAW) data.

[0223] The CCU 11201 is configured from a central processing unit (CPU) and a graphics processing unit (GPU), and comprehensively controls the operation of the endoscope 11100 and a display device 11202. In addition, the CCU 11201 receives the image signal from the camera head 11102, and performs various types of image processing such as development processing (demosaicing processing) on the image signal for displaying an image based on the image signal.

[0224] The display device 11202 displays an image based on the image signal that has undergone image processing by the CCU 11201 under the control of the CCU 11201.

[0225] The light source device 11203 includes a light source such as a light emitting diode (LED) and supplies irradiation light for imaging a surgical site or the like to the endoscope 11100.

[0226] The input device 11204 is an input interface of the endoscope surgery system 11000. The user can input various types of information or instructions to the endoscope surgery system 11000 via the input device 11204. For example, the user inputs an instruction for changing an imaging condition (a kind of irradiation light, a magnification or a focal distance, or the like) of the endoscope 11100.

[0227] The treatment tool control device 11205 controls driving of an energy treatment tool 11112 for cauterizing or cutting tissue or sealing a blood vessel or the like. In order to secure a field of view of the endoscope 11100 and secure a work space of a surgeon, the pneumoperitoneum device 11206 supplies gas to a body cavity of the patient 11132 through a pneumoperitoneum tube 11111 to inflate the body cavity of the patient 11132. The recorder 11207 is a device capable of recording various types of surgery information. The printer 11208 is a device capable of printing various types of surgery information in various formats such as text, images, or graphics.

[0228] The light source device 11203 that supplies irradiation light to the endoscope 11100 when imaging a surgical site can be configured, for example, by an LED, a laser light source, or a white light source composed of a combination thereof. When the white light source is formed by a combination of RGB (red green blue) laser light sources, the output intensity and the output timing of each color (each wavelength) can be controlled with high precision, and thus, the light source device 11203 adjusts the white balance of an imaged image. Further, in this case, the laser light of each RGB laser light source is irradiated to an observation target in a time-division manner, and the driving of the imaging element of the camera head 11102 is controlled in synchronization with the irradiation timing, so that images respectively corresponding to RGB can be captured in a time-division manner. According to this method, even if a color filter is not provided in the imaging element, a color image can be obtained.

[0229] Further, the driving of the light source device 11203 can be controlled to change the intensity of the output light at predetermined time intervals. The imaging element of the camera head 11102 can be controlled in synchronization with the timing at which the light intensity is changed to acquire images in a time-division manner, and a high dynamic range image having no so-called underexposed black spots and overexposed white spots can be generated by synthesizing the images.

[0230] Further, the light source device 11203 can be configured to be able to supply light of a predetermined wavelength band corresponding to a specific light observation. In the specific light observation, for example, so-called narrow-band imaging is performed in which a predetermined tissue such as a blood vessel of a mucosal surface layer is imaged with high contrast by irradiating light of a narrow wavelength band than that of the irradiation light (i.e., white light) at the time of normal observation, using the wavelength dependency of light absorption by human tissue. Alternatively, in the specific light observation, fluorescence observation using fluorescence generated by irradiation of excitation light can be performed. In the fluorescence observation, by locally injecting an agent such as indocyanine green (ICG) into human tissue and irradiating the human tissue with excitation light corresponding to the fluorescence wavelength of the agent, and the like, a fluorescence image can be obtained by irradiating the human tissue with the excitation light and observing the fluorescence from the human tissue (autofluorescence observation). The light source device 11203 can be configured to be able to supply narrow-band light and / or excitation light corresponding to the above-described specific light observation.

[0231] Figure 19 is a block diagram illustrating an example of the functional configuration of the camera head 11102 and the CCU 11201. Figure 18

[0232] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0233] The lens unit 11401 is an optical system provided at the connection portion with respect to the barrel 11101. The observation light that enters from the distal end of the barrel 11101 is guided to the camera head 11102 and is incident on the lens unit 11401. The lens unit 11401 is configured as a combination of a plurality of lenses including a zoom lens and a focus lens.

[0234] ​The number of imaging elements constituting the imaging unit 11402 can be one (so-called single board type) or a plurality (so-called multi board type). In the case where the imaging unit 11402 is configured as a multi board type, the imaging elements can generate image signals corresponding to, for example, RGB, and the image signals can be combined to obtain a color image. Alternatively, the imaging unit 11402 can be configured to include a pair of imaging elements for acquiring right eye image signals and left eye image signals corresponding to three-dimensional (3D) display, respectively. By performing 3D display, the surgeon 11131 can more accurately understand the depth of the biological tissue of the surgical site. Further, in the case where the imaging unit 11402 is configured as a multi board type, a plurality of lens units 11401 can be provided corresponding to the respective imaging elements.

[0235] Further, the imaging unit 11402 can not necessarily be provided in the camera head 11102. For example, the imaging unit 11402 can be provided inside the lens barrel 11101 immediately after the objective lens.

[0236] The drive unit 11403 includes an actuator and, under the control of the camera head control unit 11405, moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis. Therefore, the magnification and the focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0237] The communication unit 11404 is configured from a communication device for transmitting / receiving various information to / from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 as raw (RAW) data through the transmission cable 11400.

[0238] Further, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes, for example, information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and the focus of the captured image.

[0239] The imaging conditions such as the frame rate, the exposure value, the magnification, and the focus can be appropriately specified by the user, or can be automatically set by the control unit 11413 of the CCU 11201 in accordance with the acquired image signal. In the latter case, the so-called AE (auto exposure) function, AF (auto focus) function, and AWB (auto white balance) function are incorporated in the endoscope 11100.

[0240] The camera head control unit 11405 controls driving of the camera head 11102 in accordance with a control signal received from the CCU 11201 via the communication unit 11404.

[0241] The communication unit 11411 includes a communication device for transmitting / receiving various types of information to / from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0242] Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal or the control signal can be transmitted by electric communication or optical communication, or the like.

[0243] The image processing unit 11412 performs various types of image processing on an image signal that is raw (RAW) data transmitted from the camera head 11102.

[0244] The control unit 11413 performs various controls related to photographing of a surgical site or the like using the endoscope 11100, and performs various controls related to display of a photographed image obtained by photographing a surgical site or the like. For example, the control unit 11413 generates a control signal for controlling driving of the camera head 11102.

[0245] Further, the control unit 11413 causes the display device 11202 to display a photographed image obtained by imaging a surgical site or the like, in accordance with an image signal that has been image-processed by the image processing unit 11412. In this case, the control unit 11413 can recognize various objects in the photographed image using various image recognition techniques. For example, the control unit 11413 can recognize a surgical instrument such as forceps, a specific biological site, bleeding, and fog generated when the energy treatment tool 11112 is used, by detecting the edge shape and color of an object included in the photographed image. When the control unit 11413 causes the display device 11202 to display the photographed image, the control unit 11413 can use the recognition result to cause various types of surgery assistance information to be superimposed and displayed on the image of the surgical site. When surgery assistance is superimposed and displayed, the surgery assistance information is presented to the surgeon 11131, the burden on the surgeon 11131 can be lightened, and the surgeon 11131 can reliably perform surgery.

[0246] The transmission cable 11400 that connects the camera head 11102 and the CCU 11201 is an electric signal cable compatible with electric signal communication, an optical fiber compatible with optical communication, or a composite cable of both.

[0247] Here, in the illustrated example, although wired communication is performed using transmission cable 11400, communication between camera head 11102 and CCU 11201 can be performed wirelessly.

[0248] <Example applied to moving objects>

[0249] The technology according to this application (the technology) can be applied to a variety of products. For example, the technology according to this application (the technology) can be implemented as a device mounted on any type of mobile body, such as a car, electric vehicle, motorcycle, hybrid vehicle, bicycle, personal mobile device, airplane, drone, ship, and robot.

[0250] Figure 20 This is a block diagram illustrating a schematic construction example of a vehicle control system that is an example of a mobile body control system capable of applying the technology according to this application.

[0251] The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. Figure 20 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a vehicle body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, the functional structure of the comprehensive control unit 12050 is illustrated with a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0252] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 serves as a control device for devices such as: a drive force generating device (such as an internal combustion engine or drive motor) for generating drive force for the vehicle; a drive force transmission mechanism for transmitting drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating braking force for the vehicle.

[0253] The vehicle system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the vehicle system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power window devices, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a portable device that replaces the key or signals from various switches can be input to the vehicle system control unit 12020. The vehicle system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power window devices, and lights, etc.

[0254] The vehicle exterior information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, and a pavement marking, based on the received image.

[0255] The imaging unit 12031 is a light sensor that receives light and outputs an electric signal corresponding to the intensity of the received light. The imaging unit 12031 is capable of outputting the electric signal as an image or outputting the electric signal as ranging information. Furthermore, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared rays.

[0256] The vehicle interior information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the vehicle interior information detection unit 12040 can calculate the degree of fatigue or the degree of concentration of the driver, or can determine whether the driver is dozing, based on the detection information input from the driver state detection unit 12041.

[0257] The microcomputer 12051 is capable of calculating a control target value of a driving force generation device, a steering mechanism, or a brake device, based on vehicle exterior or interior information obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and is capable of outputting a control command to the drive system control unit 12010. For example, the microcomputer 12051 is capable of performing cooperative control aimed at realizing an advanced driver assistance system (ADAS) function including vehicle collision avoidance, impact mitigation, following travel based on a distance to a preceding vehicle, a constant speed cruise, vehicle collision warning, or lane departure warning.

[0258] Furthermore, the microcomputer 12051 is capable of controlling a driving force generation device, a steering mechanism, a brake device, and the like, based on vehicle surrounding information obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, to perform cooperative control aimed at realizing automated driving or the like, which does not need to rely on the operation of the driver and autonomously drives.

[0259] Further, the microcomputer 12051 is able to output a control command to the body system control unit 12020 in accordance with the outside-of-vehicle information obtained by the outside-of-vehicle information detecting unit 12030. For example, the microcomputer 12051 is able to perform cooperative control such as switching a high beam to a low beam for anti-dazzling in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-of-vehicle information detecting unit 12030, to control a headlamp.

[0260] The audio / image output unit 12052 transmits an output signal of at least one of sound and an image to an output device that is able to visually or aurally notify information to a passenger of the vehicle or a person outside of the vehicle. In Figure 20 In the example shown, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as the output device. The display unit 12062 may, for example, include at least one of a vehicle-mounted display and a head-up display.

[0261] Figure 21 An example of a mounting position of the imaging unit 12031 is illustrated.

[0262] In Figure 21 The imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0263] The imaging units 12101, 12102, 12103, 12104, and 12105 may, for example, be provided at positions such as a front nose, a side mirror, a rear bumper, and a rear door, and an upper portion of a cabin windshield of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper portion of the cabin windshield mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirror mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or the rear door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper portion of the cabin windshield is mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic signal, a traffic sign, and a lane, and the like.

[0264] Figure 21 Examples of imaging ranges of the imaging units 12101 to 12104 are illustrated. An imaging range 12111 represents an imaging range of the imaging unit 12101 provided at the front nose, imaging ranges 12112 and 12113 respectively represent imaging ranges of the imaging units 12102 and 12103 provided at the side mirror, and an imaging range 12114 represents an imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye image of the vehicle 12100 viewed from above can be obtained by superimposing image data captured by the imaging units 12101 to 12104.

[0265] At least one of the imaging units 12101 to 12104 can have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 can be a stereo camera constituted by a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0266] For example, by obtaining the distance between each three-dimensional object within the imaging ranges 12111 to 12114 and the change in the distance over time (relative to the speed of the vehicle 12100) based on the distance information obtained by the imaging units 12101 to 12104, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object existing on the travel path of the vehicle 12100 that is traveling in substantially the same direction as the travel direction of the vehicle 12100 at a predetermined speed (for example, 0 km / h or more), in particular, the closest three-dimensional object. Further, the microcomputer 12051 can set in advance the inter-vehicle distance to be ensured from the preceding vehicle, and can perform automatic brake control (also including follow-up stop control) or automatic acceleration control (also including follow-up start control). In this way, cooperative control for the purpose of achieving autonomous travel that does not require the driver to perform an operation can be performed.

[0267] For example, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data of two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, based on the distance information obtained by the imaging units 12101 to 12104, extract the three-dimensional object data, and use the three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles in the vicinity of the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that are difficult to visually recognize. Then, the microcomputer 12051 can determine a collision risk that indicates the degree of risk of collision with each obstacle, and when the collision risk has a value equal to or higher than a set value and there is a possibility of collision, the microcomputer 12051 can output a warning to the driver through the audio speaker 12061 or the display unit 12062 to assist the driver in avoiding collision, and forcibly decelerate or evade steering by the drive system control unit 12010.

[0268] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 is able to recognize a pedestrian by judging whether or not a pedestrian is present in an image captured by the imaging units 12101 to 12104. The method of recognizing a pedestrian is performed, for example, by the following steps: extracting feature points in an image captured by the imaging units 12101 to 12104 that are infrared cameras; and performing pattern matching processing on a series of feature points that represent the outline of an object, to judge whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in an image captured by the imaging units 12101 to 12104, and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 so as to display a square outline for emphasis superimposed on the recognized pedestrian. Further, the audio / image output unit 12052 can control the display unit 12062 so as to display an icon or the like that represents a pedestrian at a desired position.

[0269] Further, the system used here refers to an entire device composed of a plurality of devices.

[0270] The advantageous effects described in the present specification are merely exemplary and are not limiting, and other advantageous effects can be obtained.

[0271] Embodiments of the present technology are not limited to the above-described embodiments, but can be modified in various forms within the scope of the present technology without departing from the gist of the present technology.

[0272] Meanwhile, the present technology can also adopt the following configuration. (1)

[0274] An imaging element including a first photoelectric conversion section and a second photoelectric conversion section that are stacked between a first surface of a semiconductor substrate and a second surface opposite the first surface,

[0275] wherein an impurity distribution of the first photoelectric conversion section is a distribution having a peak on the first surface side, and

[0276] an impurity distribution of the second photoelectric conversion section is a distribution having a peak on the second surface side. (2)

[0278] The imaging element according to (1), wherein a side on which the impurity concentration of the first photoelectric conversion section is low and a side on which the impurity concentration of the second photoelectric conversion section is low face each other. (3)

[0280] The imaging element according to (1) or (2), further comprising a third photoelectric conversion section including an organic photoelectric conversion film that is stacked on the first surface side and is sandwiched between a lower electrode and an upper electrode. (4)

[0282] The imaging element according to (1) or (2), further comprising a third photoelectric conversion section provided in the semiconductor substrate. (5)

[0284] The imaging element according to any one of (1) to (4), wherein the first surface side of the first photoelectric conversion section is formed in a concave-convex shape. (6)

[0286] A manufacturing method implemented by a manufacturing apparatus for manufacturing an imaging element, the manufacturing method comprising:

[0287] Manufacturing an imaging element including a first photoelectric conversion section and a second photoelectric conversion section provided in a semiconductor substrate between a first surface and a second surface opposite to the first surface,

[0288] wherein an impurity distribution of the first photoelectric conversion section is a distribution having a peak on the first surface side, and

[0289] an impurity distribution of the second photoelectric conversion section is a distribution having a peak on the second surface side. (7)

[0291] The manufacturing method according to (6), further comprising: forming the first photoelectric conversion section by ion implantation from the first surface side; and

[0292] forming the second photoelectric conversion section by ion implantation from the second surface side. (8)

[0294] The manufacturing method according to (7), further comprising: forming a third photoelectric conversion section including an organic photoelectric conversion film provided on the first surface side and sandwiched between a lower electrode and an upper electrode. (9)

[0296] The manufacturing method according to (7), further comprising: forming a third photoelectric conversion section by ion implantation from the first surface side. (10)

[0298] The manufacturing method according to any one of (6) to (9), wherein a concave-convex surface is formed on the first surface before forming the first photoelectric conversion section. (11)

[0300] The manufacturing method according to any one of (6) to (10), wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate. (12)

[0302] An electronic apparatus including an imaging element and a processing unit that processes a signal from the imaging element,

[0303] The imaging element includes a stacked first photoelectric conversion section and a second photoelectric conversion section disposed between a first surface of a semiconductor substrate and a second surface opposite the first surface,

[0304] wherein an impurity distribution of the first photoelectric conversion section is a distribution having a peak on the first surface side, and

[0305] an impurity distribution of the second photoelectric conversion section is a distribution having a peak on the second surface side.

[0306] List of Reference Signs

[0307] 1 imaging element

[0308] 2 pixel

[0309] 3 pixel region

[0310] 4 vertical drive circuit

[0311] 5 column signal processing circuit

[0312] 6 horizontal drive circuit

[0313] 7 output circuit

[0314] 8 control circuit

[0315] 9 vertical signal line

[0316] 10 horizontal signal line

[0317] 11 substrate

[0318] 12 step

[0319] 15 photoelectric conversion region

[0320] 16 well region

[0321] 17 semiconductor substrate

[0322] 18 p-type semiconductor region

[0323] 19 n-type semiconductor region

[0324] 20 p-type semiconductor region

[0325] 21 n-type semiconductor region

[0326] 22 p-type semiconductor region

[0327] 23 gate electrode

[0328] 27 multilayer wiring layer

[0329] 28 wiring

[0330] 29 interlayer insulating film

[0331] 32 through electrode

[0332] 33 insulating film

[0333] 34a upper electrode

[0334] 34b lower electrode

[0335] 35 insulating film

[0336] 36a organic photoelectric conversion film

[0337] 36b passivation film

[0338] 40 gate electrode

[0339] 41 gate electrode

[0340] 42 gate electrode

[0341] 43 drain region

[0342] 44 drain region

[0343] 45 drain region

[0344] 46 drain region

[0345] 51 planarization film

[0346] 52 on-chip lens

[0347] 61 support substrate

[0348] 101 support substrate

[0349] 131 silicon layer

[0350] 201 SOI substrate

[0351] 202 BOX layer

[0352] 301 p-type semiconductor region

[0353] 302 n-type semiconductor region

[0354] 303 p-type semiconductor region

[0355] 304 n-type semiconductor region

[0356] 305 p-type semiconductor region

[0357] 306 n-type semiconductor region

[0358] 307 p-type semiconductor region

[0359] 308, 309 gate electrode

[0360] 351 support substrate

[0361] 401 p-type semiconductor region

[0362] 402 n-type semiconductor region

[0363] 403 p-type semiconductor region

Claims

1. An imaging element comprising a plurality of pixels, each pixel comprising a first photoelectric conversion portion and a second photoelectric conversion portion stacked between a first surface of a semiconductor substrate and a second surface opposite to the first surface, wherein a pixel isolation portion with reflective function is disposed between adjacent pixels. in, The first photoelectric conversion unit has a first layer and a second layer in the stacking direction. When viewed from the first surface side, the impurity concentration of the first layer in the first photoelectric conversion unit decreases in the direction of increasing distance from the first surface. The surfaces of the first layer near the first and second surfaces are configured with an uneven shape, and the surfaces of the second layer near the first and second surfaces are also configured with an uneven shape. The second photoelectric conversion unit has a third layer and a fourth layer in the stacking direction. When viewed from the second surface side, the impurity concentration of the fourth layer in the second photoelectric conversion unit decreases in the direction of increasing distance from the second surface.

2. The imaging element according to claim 1, wherein, The side of the first photoelectric conversion unit with a low impurity concentration and the side of the second photoelectric conversion unit with a low impurity concentration face each other.

3. The imaging element according to claim 1 or 2 further includes a third photoelectric conversion unit, the third photoelectric conversion unit comprising an organic photoelectric conversion film stacked on the first surface side and sandwiched between the lower electrode and the upper electrode.

4. The imaging element according to claim 1 or 2 further includes a third photoelectric conversion unit disposed in the semiconductor substrate.

5. The imaging element according to claim 1 or 2, wherein, When viewed from the first surface side, the impurity concentration of the second layer in the first photoelectric conversion section decreases in the direction of increasing distance from the first surface, and When viewed from the second surface side, the impurity concentration of the third layer in the second photoelectric conversion unit decreases in the direction of increasing distance from the second surface.

6. A manufacturing method performed by a manufacturing apparatus for manufacturing an imaging element, the manufacturing method comprising: An imaging element is manufactured, comprising a plurality of pixels. Each pixel is disposed between a first photoelectric conversion unit and a second photoelectric conversion unit stacked between a first surface and a second surface opposite to the first surface of a semiconductor substrate. Pixel isolation units with reflective functions are disposed between adjacent pixels. The first photoelectric conversion unit has a first layer and a second layer in the stacking direction. When viewed from the first surface side, the impurity concentration of the first layer in the first photoelectric conversion unit decreases in the direction of increasing distance from the first surface. The surfaces of the first layer near the first and second surfaces are configured with an uneven shape, and the surfaces of the second layer near the first and second surfaces are also configured with an uneven shape. The second photoelectric conversion unit has a third layer and a fourth layer in the stacking direction. When viewed from the second surface side, the impurity concentration of the fourth layer in the second photoelectric conversion unit decreases in the direction of increasing distance from the second surface.

7. The manufacturing method according to claim 6, further comprising: The first photoelectric conversion unit is formed by ion implantation from the first surface side; and The second photoelectric conversion unit is formed by ion implantation from the second surface side.

8. The manufacturing method according to claim 7, further comprising: A third photoelectric conversion unit is formed, the third photoelectric conversion unit including an organic photoelectric conversion film disposed on the first surface side and sandwiched between the lower electrode and the upper electrode.

9. The manufacturing method according to claim 7, further comprising: The third photoelectric conversion unit is formed by ion implantation from the first surface side.

10. The manufacturing method according to any one of claims 6 to 9, wherein, The semiconductor substrate is a silicon-on-insulator substrate.

11. The manufacturing method according to any one of claims 6 to 9, wherein, When viewed from the first surface side, the impurity concentration of the second layer in the first photoelectric conversion section decreases in the direction of increasing distance from the first surface, and When viewed from the second surface side, the impurity concentration of the third layer in the second photoelectric conversion unit decreases in the direction of increasing distance from the second surface.

12. An electronic device comprising an imaging element and a processing unit for processing signals from said imaging element. The imaging element is the imaging element as described in any one of claims 1 to 5.

Images