Method for operating a converter, control unit for carrying out the method, and converter

Abstract

The present invention relates to a method for operating a converter. The converter comprises: first and second input terminals for receiving a DC voltage; an output terminal for providing an output voltage variable between a first and a second voltage level; a first and a second series connection of two or more switches, each of which is a semiconductor switch; and one or more capacitor units. The method comprises the steps of compensating for different power losses of the switches by controlling the switches such that one or more of the one or more capacitor units are charged above a corresponding third voltage level and / or one or more of the one or more capacitor units are charged below a corresponding third voltage level, thereby distributing the DC voltage unequally to the switches.

Description

Technical Field

[0001] The invention relates to a method for operating a converter, a control unit for a converter, wherein the control unit is adapted to perform such a method, and a converter. The converter may be a multilevel converter. Background Art

[0002] The field of the present invention relates to converters (which may be referred to as power converters) and methods for operating such converters. Such converters may be used in power supplies such as data center power supplies, photovoltaic (PV) inverters, charging systems (e.g., electric vehicle (EV) charging stations), and similar applications that provide power to electrical devices. Summary of the Invention

[0003] Specifically, embodiments of the present invention are based on the following considerations made by the inventors:

[0004] Quasi-operation of a multi-level flying capacitor topology is an alternative concept aimed at achieving efficient medium voltage (MV) switching to achieve cost, density and efficiency (CDE) advantages of high power MV converters. Figure 1 An example of such a converter is shown with a multi-level flying capacitor topology / structure. In other words, the converter corresponds to a multi-level converter. A multi-level converter can be used to convert voltage from AC to DC (or vice versa), creating intermediate voltage levels to better represent the AC voltage. The main reason for using such a multi-level converter is to evenly distribute the maximum voltage across the lower voltage levels of the converter's switches.

[0005] Figure 1The illustrated converter can operate as a two-level converter. That is, the switches of the converter can be individually controlled and switched so that the output terminal OUT1 of the converter 1 can provide an output voltage Vout that can vary between a first voltage level and a second voltage level. The first voltage level can correspond to the voltage level applied to the first input terminal IN1 of the converter 1, and the second voltage level can correspond to the voltage level applied to the second input terminal IN2 of the converter 1. The voltage Vin (also referred to as the input voltage) applied to the input terminals of the converter 1, particularly the voltage received by the first input terminal IN1 and the second input terminal IN2, corresponds to the difference between the first voltage level and the second voltage level. In other words, the input voltage Vin received by the first and second input terminals corresponds to the voltage applied between the first and second input terminals IN1 and IN2 of the converter 1. Specifically, the switches of the converter can be controlled so that in the first stable state of the converter 1, the output voltage Vout of the converter 1 is equal to the first voltage level, and in the second stable state of the converter 1, the output voltage Vout is equal to the second voltage level.

[0006] The output voltage Vout of the converter may potentially be equal to more than two voltage levels, especially in Figure 1 In the case of the converter structure shown, it is equal to two additional voltage levels between the first voltage level and the second voltage level. Figure 1 The operation of the converter 1 as a two-level converter can also be referred to as operating the converter 1 as a quasi-two-level (Q2L) converter. The two additional voltage levels can specifically correspond to the voltage across capacitor unit C1 and the voltage across capacitor unit C2 of the converter 1. The two-level configuration allows the use of low-voltage semiconductor devices, particularly low-voltage semiconductor switches, for the switches of the converter, thereby reducing the cost of the converter and increasing the effective operating voltage level.

[0007] An example of an application of the present invention could be the conversion of electrical energy generated by solar PV installations to higher voltages for efficient transmission. Typically, these higher voltage levels could be 10 kV, 20 kV or 35 kV. In order to withstand such high levels of the required voltage range, the semiconductor devices (especially semiconductor switches) cannot be used. Therefore, different multi-level configurations based on low voltage devices (especially low voltage switches) can be used to obtain the required voltage range. Figure 1 The flying capacitor topology shown is one possible example of a multi-level configuration.

[0008] A flying capacitor configuration with typical multilevel operation requires a large capacitor bank to store the power required for the intermediate voltage levels. However, quasi-two-level operation (i.e., operating a multilevel converter as a two-level converter) uses a small amount of capacitance during the transition between the first and second stable states of the converter (also known as the transition phase). This significantly reduces the required size of the capacitor bank, improving efficiency and power density (reducing volume and weight).

[0009] The lifespan of a converter depends on the health of each of its components. The converter's switches (also known as switching devices), particularly in the form of transistors and diodes, are the most vulnerable components due to the constant stress from their switching behavior and internal resistance. This stress is caused by power losses during operation and is generated as heat, measured in watts.

[0010] Due to non-ideal behavior of the components, these thermal stresses are unevenly distributed, so over time, the health of some transistors degrades significantly compared to others.

[0011] Specifically, the switches are not ideal and may have slightly different characteristics, such as on-resistance, gate threshold voltage, turn-on / off times, and thermal impedance. Furthermore, the thermal interface of the switches may have microscopic imperfections, which may allow air particles to accumulate between the housing and the heat sink. This reduces the thermal impedance between the switches and the external heat sink. Due to these factors, the thermal stress on the converter's switches is unevenly distributed across the converter's switches. As a result, after a period of sustained operation, some switches are significantly less healthy than others. The converter's health and lifespan are determined by the healthiest component, and therefore the component with the worst condition / shortest lifespan. In other words, if the health and lifespan of a single switch of the converter decreases, the converter's health and lifespan will decrease accordingly.

[0012] In view of the above problems and shortcomings, embodiments of the present invention aim to improve the above problems. Specifically, an object is to provide a method for operating a converter, which can increase the life of the converter.

[0013] This object is achieved by the embodiments of the present invention as described in the accompanying independent claims. Advantageous implementations of the embodiments of the present invention are further defined in the dependent claims. Specifically, the embodiments of the present invention achieve this object by redistributing some stress, particularly thermal stress, from switches in less healthy states to switches in more healthy states.

[0014] A first aspect of the present invention provides a method for operating a converter. The converter includes: first and second input terminals for receiving a DC voltage; an output terminal for providing an output voltage variable between a first voltage level and a second voltage level; a first and second series connection of two or more switches, each of which is a semiconductor switch; and one or more capacitor units. The first input terminal is electrically connected to the output terminal via the first series connection of the two or more switches. The second input terminal is electrically connected to the output terminal via the second series connection of the two or more switches. Each of the one or more capacitor units electrically connects a first node between the two switches in the first series connection to a second node between the two switches in the second series connection, wherein the number of nodes between the first node and the output terminal is equal to the number of nodes between the second node and the output terminal. The DC voltage can be equally distributed to the switches in the first and second series connections by controlling the switches so that each of the one or more capacitor units is charged to a corresponding third voltage level. The method comprises the following steps: compensating for the different power losses of the switches by controlling the switches so that one or more of the one or more capacitor units are charged above the corresponding third voltage level and / or one or more of the one or more capacitor units are charged below the corresponding third voltage level, so that the DC voltage is unequally distributed to the switches.

[0015] In other words, according to the method of the first aspect, the switches are controlled so that one or more of the one or more capacitor units are charged above the corresponding third voltage level and / or one or more of the one or more capacitor units are charged below the corresponding third voltage level. Thus, the DC voltage is distributed unequally to the switches, which can compensate for the different power losses of the switches.

[0016] Thus, the method allows to redistribute some stress (especially thermal stress) from the switches with lower health to the switches with higher health. Thus, the method can improve the life of the converter, which is determined by the components with the worst health and therefore by the switches with the worst health / shortest life.

[0017] The terms "electrically connected" and "connected" may be used synonymously.

[0018] The method may be a method for operating a multi-level converter. That is, the converter may be a multi-level converter. Specifically, the method is a method for operating the multi-level converter as a two-level or three-level converter. The converter may be a DC / AC or DC / DC converter.

[0019] Specifically, the one or more capacitor units are electrically connected to different first nodes and second nodes. That is, only one capacitor unit among the one or more capacitor units is electrically connected to each first node and second node.

[0020] Specifically, the number of capacitor units is respectively one less than the number of switches in the first series connection and the number of switches in the second series connection.

[0021] The switches of the converter (as semiconductor switches) can be transistors, such as one or more insulated-gate bipolar transistors (IGBTs), one or more field-effect transistors (FETs), one or more metal-oxide-semiconductor field-effect transistors (MOSFETs), one or more bipolar junction transistors (BJTs) and / or one or more junction field-effect transistors (JFETs). The switches of the converter can be of the same transistor type or correspond to at least two different transistor types. In particular, a diode can be electrically connected in anti-parallel to the switch, in particular when the switch is one or more IGBTs and / or MOSFETs. The diode can be an intrinsic body diode of the corresponding transistor. In particular, the switch is a power switch.

[0022] Each capacitor unit may correspond to one capacitor. Alternatively, each capacitor unit may correspond to two capacitors electrically connected in series. In the case where each capacitor unit corresponds to two capacitors electrically connected in series, the converter may include two capacitors connected in series, the two capacitors electrically connecting the first input terminal and the second input terminal of the converter to each other.

[0023] In one implementation of the first aspect, the method includes the following steps: compensating for different power losses of the switch by controlling the switch so that one or more of the one or more capacitor units are charged above the corresponding third voltage level and / or one or more of the one or more capacitor units are charged or discharged below the corresponding third voltage level; optionally, performing the above steps in one or more transition phases between a first stable state of the converter (in the first stable state, the output voltage is equal to the first voltage level) and a second stable state of the converter (in the second stable state, the output voltage is equal to the second voltage level). In other words, such control of the switch can optionally be performed / occur in one or more transition phases between the first stable state of the converter and the second stable state of the converter.

[0024] The output voltage may vary between the first voltage level in the first steady state of the converter and the second voltage level in the second steady state of the converter.

[0025] The DC voltage may be equally distributed to the switches of the first series connection and the second series connection by controlling the switches such that each of the one or more capacitor units is charged to the respective third voltage level during the one or more conversion phases between the first stable state and the second stable state of the converter.

[0026] In an implementation of the first aspect, the method includes the following steps: determining the power loss of the corresponding switch by measuring the temperature of one or more switches among the switches as a power loss indicator of the corresponding switch. Specifically, the method includes the following steps: determining the power loss of the corresponding switch by measuring the temperature of each switch among the switches as a power loss indicator of the corresponding switch.

[0027] Specifically, the power loss of the switch refers to the switching power loss of the switch. In other words, the power loss of the switch refers to the switching power loss of the switch.

[0028] Specifically, the higher the temperature of the switch, the higher the power loss of the switch. Specifically, the higher the power loss of the switch, the greater the stress on the switch, and thus the worse the health of the switch.

[0029] In an implementation of the first aspect, the method includes the following steps: determining the switch with the highest power loss among the switches; and controlling the switches so that a portion of the DC voltage allocated to the switch with the highest power loss is reduced.

[0030] By reducing the portion of the DC voltage allocated to the switch with the highest power loss, the switching power loss of the switch can be reduced.

[0031] In an implementation of the first aspect, the method includes the following steps: controlling the switches so that a portion of the DC voltage allocated to the switch with the highest power loss is reduced and the remaining DC voltage is evenly distributed to the remaining switches.

[0032] In one implementation of the first aspect, the method includes the following steps: determining a combined power loss for each switch pair, the switch pair including a first switch in the first series connection and a second switch in the second series connection, wherein the number of switches between the first switch and the output terminal is equal to the number of switches between the second switch and the output terminal. Furthermore, the method may include the following steps: determining a switch pair having the highest combined power loss among the combined power losses of the switch pairs in the first and second series connections; and controlling the switches such that a portion of the DC voltage allocated to the first and second switches of the switch pair having the highest combined power loss is reduced.

[0033] By reducing a portion of the DC voltage allocated to the first switch and the second switch of the switch pair having the highest combined power loss, the switching power loss of the first switch and the second switch can be reduced.

[0034] In an implementation of the first aspect, the method includes the following steps: controlling the switches so that a portion of the DC voltage allocated to the first switch and the second switch of the switch pair with the highest combined power loss is reduced and the remaining DC voltage is equally distributed to the remaining switches.

[0035] In one implementation of the first aspect, the method includes the following steps: determining a combined power loss of one or more of the switch pairs by determining the sum of the temperature of the first switch of the corresponding switch pair and the temperature of the second switch of the corresponding switch pair as a combined power loss indicator of the corresponding switch pair. Specifically, the method may include the following steps: determining a combined power loss of each of the switch pairs by determining the sum of the temperature of the first switch of the corresponding switch pair and the temperature of the second switch of the corresponding switch pair as the combined power loss indicator of the corresponding switch pair.

[0036] Specifically, the higher the sum of the temperatures of the two switches of a switch pair, the higher the power loss of the switch pair. Specifically, the higher the power loss of a switch pair, the greater the stress on the switches of the switch pair, and thus the worse the health of the switch pair.

[0037] In an implementation of the first aspect, in order to reduce a portion of the DC voltage distributed to a switch electrically connected to the output terminal, the method includes the following steps: controlling the switch so that a capacitor unit of the one or more capacitor units is charged below the corresponding third voltage level, wherein the capacitor unit is electrically connected to the first node of the first series connection and the second node of the second series connection, and the first node of the first series connection and the second node of the second series connection are closest to the output terminal in terms of the number of nodes.

[0038] The switch electrically connected to the output terminal may be referred to as an output switch or a third switch. The capacitor unit electrically connected to the first node of the first series connection and the second node of the second series connection, the first node of the first series connection and the second node of the second series connection being closest to the output terminal in terms of the number of nodes, may be referred to as an output capacitor unit or a third capacitor unit.

[0039] Specifically, the less the capacitor unit (output capacitor unit) is charged below the corresponding third voltage level, the more the portion of the DC voltage allocated to the switch (output switch) is reduced.

[0040] That is, the lower or smaller the voltage level to which the capacitor unit (output capacitor unit) is charged is than the corresponding third voltage level, the more the switching power loss of the switch (output switch) is reduced.

[0041] Specifically, to reduce the portion of the DC voltage allocated to the switch (output switch), the method includes the following steps: controlling the switch so that the capacitor unit (output capacitor unit) in the one or more capacitor units is charged or discharged below the corresponding third voltage level. Alternatively, to reduce the portion of the DC voltage allocated to the switch (output switch), the method includes the following steps: controlling the switch so that during the one or more conversion phases, the capacitor unit (output capacitor unit) in the one or more capacitor units is charged or discharged below the corresponding third voltage level.

[0042] Specifically, the less the capacitor unit (output capacitor unit) is charged below the corresponding third voltage level, the more the portion of the DC voltage allocated to the switch (output switch) decreases. Specifically, the more the capacitor unit (output capacitor unit) is discharged below the corresponding third voltage level, the more the portion of the DC voltage allocated to the switch (output switch) decreases.

[0043] That is, the lower or smaller the voltage level to which the capacitor unit (output capacitor unit) is charged is, the more the switching power loss of the switch (output switch) is reduced. The lower or smaller the voltage level to which the capacitor unit (output capacitor unit) is discharged is, the more the switching power loss of the switch (output switch) is reduced.

[0044] Specifically, when the capacitor unit (output capacitor unit) is discharged (i.e., not charged), the capacitor unit (output capacitor unit) can be charged. Specifically, when the capacitor unit (output capacitor unit) is charged to the third voltage level or above, the capacitor unit (output capacitor unit) can be discharged.

[0045] In an implementation of the first aspect, in order to reduce a portion of the DC voltage allocated to a switch electrically connected to the output terminal through one or more switches, the method includes the following steps: controlling the switch so that a first capacitor unit among the one or more capacitor units is charged to above the corresponding third voltage level, wherein the first capacitor unit is connected to a terminal of the two terminals of the switch that is closer to the output terminal in terms of the number of nodes; and / or controlling the switch so that a second capacitor unit among the one or more capacitor units is charged to below the corresponding third voltage level, wherein the second capacitor unit is connected to the other terminal of the two terminals of the switch.

[0046] The switch electrically connected to the output terminal through one or more switches may be referred to as a fourth switch.

[0047] Specifically, the more the first capacitor unit is charged above the corresponding third voltage level, the more the portion of the DC voltage allocated to the switch (fourth switch) is reduced; and / or the less the second capacitor unit is charged below the corresponding third voltage level, the more the portion of the DC voltage allocated to the switch (fourth switch) is reduced.

[0048] Specifically, in order to reduce a portion of the DC voltage allocated to the switch (the fourth switch), the method includes the following steps: controlling the switch so that, optionally in the one or more conversion phases, the first capacitor unit among the one or more capacitor units is charged to above the corresponding third voltage level; and / or controlling the switch so that, optionally in the one or more conversion phases, the second capacitor unit among the one or more capacitor units is charged or discharged to below the corresponding third voltage level.

[0049] In other words, the first capacitor unit of the one or more capacitor units may optionally be charged to above the corresponding third voltage level during the one or more conversion phases. The second capacitor unit of the one or more capacitor units may optionally be additionally or alternatively charged or discharged to below the corresponding third voltage level during the one or more conversion phases.

[0050] Specifically, the more the first capacitor unit is charged above the corresponding third voltage level, the more the portion of the DC voltage allocated to the switch (fourth switch) decreases. Specifically, the less the second capacitor unit is charged below the corresponding third voltage level, the more the portion of the DC voltage allocated to the switch (fourth switch) decreases. Specifically, the more the second capacitor unit is discharged below the third voltage level, the more the portion of the DC voltage allocated to the switch (fourth switch) decreases.

[0051] Specifically, the greater the number of nodes between the output terminal and the first node connected to the capacitor unit, the greater the corresponding third voltage level of the capacitor unit.

[0052] In order to implement the method according to the first aspect of the present invention, some or all of the implementations and optional features of the first aspect described above may be combined with each other.

[0053] A second aspect of the present invention provides a control unit for a converter, wherein the control unit is configured to execute the method for controlling switches of the converter according to the first aspect above.

[0054] The control unit of the second aspect and its implementation and optional features can achieve the same advantages as the method of the first aspect and its corresponding implementation and optional features.

[0055] The implementation and optional features of the method of the first aspect are correspondingly applicable to the control unit of the second aspect.

[0056] Specifically, the converter may be a multi-level converter. The above description of the converter operable by the method of the first aspect is correspondingly applicable to the converter controllable by the control unit of the second aspect.

[0057] Specifically, the converter controllable by the control unit includes: first and second input terminals for receiving a DC voltage; an output terminal for providing an output voltage variable between a first voltage level and a second voltage level; a first and second series connection of two or more switches, each of which is a semiconductor switch; and one or more capacitor units. The first input terminal is electrically connected to the output terminal via the first series connection of the two or more switches. The second input terminal is electrically connected to the output terminal via the second series connection of the two or more switches. Each of the one or more capacitor units electrically connects a first node between the two switches in the first series connection and a second node between the two switches in the second series connection, wherein the number of nodes between the first node and the output terminal is equal to the number of nodes between the second node and the output terminal.

[0058] The control unit may include or correspond to a processor, a microprocessor, a controller, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or any combination of the above components.

[0059] Specifically, the control unit is configured to equally distribute the DC voltage to the switches of the first series connection and the second series connection by controlling the switches so that each of the one or more capacitor units is charged to a corresponding third voltage level. In other words, the control unit is specifically configured to control the switches so that each of the one or more capacitor units is charged to a corresponding third voltage level, so as to equally distribute the DC voltage to the switches of the first series connection and the second series connection of the converter.

[0060] Specifically, the control unit is used to control the switches so that one or more of the one or more capacitor units are charged above the corresponding third voltage level and / or one or more of the one or more capacitor units are charged below the corresponding third voltage level, so that the DC voltage is unequally distributed to the switches, thereby compensating for the different power losses of the switches.

[0061] In one implementation of the second aspect, the control unit is configured to control the switch so that one or more of the one or more capacitor units are charged to a level above the corresponding third voltage level and / or one or more of the one or more capacitor units are charged or discharged to a level below the corresponding third voltage level, thereby compensating for different power losses of the switch. The control unit may be configured to perform such control of the switch during one or more transition stages between a first stable state of the converter (in which the output voltage is equal to the first voltage level) and a second stable state of the converter (in which the output voltage is equal to the second voltage level).

[0062] In an implementation of the second aspect, the control unit is configured to determine the power loss of the corresponding switch by measuring the temperature of one or more switches among the switches as the power loss indicator of the corresponding switch. Specifically, the control unit may be configured to determine the power loss of the corresponding switch by measuring the temperature of each switch among the switches as the power loss indicator of the corresponding switch.

[0063] In an implementation of the second aspect, the control unit is configured to determine a switch with the highest power loss among the switches; and control the switches so that a portion of the DC voltage allocated to the switch with the highest power loss is reduced.

[0064] In an implementation of the second aspect, the control unit is configured to control the switches so that a portion of the DC voltage allocated to the switch with the highest power loss is reduced and the remaining DC voltage is evenly distributed to the remaining switches.

[0065] In one implementation of the second aspect, the control unit is configured to determine a combined power loss of each switch pair, the switch pair comprising a first switch in the first series connection and a second switch in the second series connection, wherein the number of switches between the first switch and the output terminal is equal to the number of switches between the second switch and the output terminal. Furthermore, the control unit may be configured to determine a switch pair having the highest combined power loss among the combined power losses of the switch pairs in the first and second series connections; and control the switches such that a portion of the DC voltage allocated to the first and second switches of the switch pair having the highest combined power loss is reduced.

[0066] In an implementation of the second aspect, the control unit is used to control the switches so that a portion of the DC voltage allocated to the first switch and the second switch of the switch pair with the highest combined power loss is reduced and the remaining DC voltage is equally distributed to the remaining switches.

[0067] In one implementation of the second aspect, the control unit is configured to determine a combined power loss of one or more of the switch pairs by determining a sum of a temperature of the first switch of the corresponding switch pair and a temperature of the second switch of the corresponding switch pair as a combined power loss indicator of the corresponding switch pair. Specifically, the control unit may be configured to determine a combined power loss of each of the switch pairs by determining a sum of a temperature of the first switch of the corresponding switch pair and a temperature of the second switch of the corresponding switch pair as a combined power loss indicator of the corresponding switch pair.

[0068] In an implementation of the second aspect, in order to reduce a portion of the DC voltage allocated to a switch electrically connected to the output terminal, the control unit is configured to control the switch so that a capacitor unit among the one or more capacitor units is charged below the corresponding third voltage level, wherein the capacitor unit is electrically connected to the first node of the first series connection and the second node of the second series connection, and the first node of the first series connection and the second node of the second series connection are closest to the output terminal in terms of the number of nodes.

[0069] In one implementation of the second aspect, to reduce a portion of the DC voltage allocated to a switch electrically connected to the output terminal via one or more switches, the control unit is configured to control the switch such that a first capacitor unit among the one or more capacitor units is charged to a level above the corresponding third voltage level, wherein the first capacitor unit is connected to a terminal of the switch that is closer to the output terminal in terms of the number of nodes. Furthermore, the control unit may be configured to control the switch such that a second capacitor unit among the one or more capacitor units is charged to a level below the corresponding third voltage level, wherein the second capacitor unit is connected to the other of the two terminals of the switch.

[0070] In order to implement the control unit according to the second aspect of the present invention, some or all of the implementations and optional features of the second aspect described above may be combined with each other.

[0071] A third aspect of the present invention provides a converter. The converter includes: first and second input terminals for receiving a DC voltage; an output terminal for providing an output voltage variable between a first voltage level and a second voltage level; a first and second series connection of two or more switches, each of which is a semiconductor switch; one or more capacitor units; and a control unit for controlling the switches. The first input terminal is electrically connected to the output terminal via the first series connection of the two or more switches. The second input terminal is electrically connected to the output terminal via the second series connection of the two or more switches. Each of the one or more capacitor units electrically connects a first node between the two switches in the first series connection to a second node between the two switches in the second series connection, wherein the number of nodes between the first node and the output terminal is equal to the number of nodes between the second node and the output terminal. The control unit is configured to equally distribute the DC voltage to the switches in the first and second series connections by controlling the switches so that each of the one or more capacitor units is charged to a corresponding third voltage level. The control unit is configured to compensate for the different power losses of the switches by controlling the switches so that one or more of the one or more capacitor units are charged above the corresponding third voltage level and / or one or more of the one or more capacitor units are charged below the corresponding third voltage level, so that the DC voltage is unequally distributed to the switches.

[0072] In other words, the control unit is configured to control the switches so that each of the one or more capacitor units is charged to a corresponding third voltage level, so that the DC voltage is evenly distributed to the switches of the first series connection and the second series connection of the converter. Furthermore, the control unit is configured to control the switches so that one or more of the one or more capacitor units is charged above the corresponding third voltage level and / or one or more of the one or more capacitor units is charged below the corresponding third voltage level, so that the DC voltage is unevenly distributed to the switches, thereby compensating for different power losses of the switches.

[0073] The converter of the third aspect and its implementation and optional features can achieve the same advantages as the method of the first aspect and its corresponding implementation and optional features.

[0074] The implementation and optional features of the method according to the first aspect are correspondingly applicable to the converter according to the third aspect, in particular to the control unit of the converter according to the third aspect. Specifically, the above description of the converter operable by the method of the first aspect and the converter controllable by the control unit of the second aspect is correspondingly applicable to the converter according to the third aspect.

[0075] Specifically, the converter may be a multilevel converter. The converter may be a DC / AC or DC / DC converter. As described above, the control unit of the converter according to the third aspect may be the control unit according to the second aspect. The above description of the control unit of the second aspect may also apply to the control unit of the converter according to the third aspect.

[0076] The control unit may include or correspond to a processor, a microprocessor, a controller, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or any combination of the above components.

[0077] In an implementation of the third aspect, each capacitor unit corresponds to one capacitor or two capacitors electrically connected in series. In the case where each capacitor unit corresponds to two capacitors electrically connected in series, the converter may include two capacitors connected in series, the two capacitors electrically connecting the first input terminal and the second input terminal of the converter to each other.

[0078] In order to implement the converter according to the third aspect of the present invention, some or all of the implementations and optional features of the third aspect described above may be combined with each other.

[0079] A fourth aspect of the present invention provides a computer program comprising program code for executing the method according to the first aspect or any implementation thereof as described above. Specifically, the present invention may provide a computer program comprising program code for executing the method according to the first aspect or any implementation thereof when implemented on a computer.

[0080] A fifth aspect of the present invention provides a computer comprising a memory and a processor, wherein the memory and the processor are configured to store and execute program code to perform the method according to the first aspect or any implementation thereof.

[0081] A sixth aspect of the present invention provides a non-transitory storage medium storing executable program code, which, when executed by a control unit (such as a computer), enables the method according to the first aspect or any implementation thereof to be performed as described above.

[0082] The computer program according to the fourth aspect, the computer according to the fifth aspect, and the non-transitory storage medium according to the sixth aspect can achieve the same advantages as the method of the first aspect and its corresponding implementation methods and corresponding optional features.

[0083] It should be noted that all devices, elements, units and components described in this application can be implemented by software or hardware elements or any type of combination thereof. All steps performed by the various entities described in this application and the functions described to be performed by the various entities are intended to indicate that the corresponding entities are used to perform the corresponding steps and functions. Although in the description of the following specific embodiments, the specific functions or steps performed by the external entities are not reflected in the description of the specific detailed elements of the entities that perform the specific steps or functions, it should be clear to the technician that these methods and functions can be implemented by corresponding hardware or software elements or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] The following description of specific embodiments, in conjunction with the accompanying drawings, will illustrate the above aspects and their implementation forms, wherein:

[0085] Figure 1 An example of a converter structure provided by an embodiment of the present invention is shown;

[0086] Figure 2 The example operation of the method provided by the embodiment of the present invention is shown Figure 1 When the converter is shown Figure 1 Three different switching states of the converter shown;

[0087] Figure 3 The example operation of the method provided by the embodiment of the present invention is shown Figure 1 When the converter is shown Figure 1 The voltage present in the converter is plotted against time. Specifically, Figure 3 a shows Figure 1 The upper switch S of the converter shown U1 、S U2 and S U3 The voltage versus time curve, Figure 3 b shows Figure 1 A voltage versus time curve of the output voltage of the converter shown;

[0088] Figure 4 as well as Figure 5Two examples of converter structures provided by embodiments of the present invention are shown respectively;

[0089] Figure 6 The example operation of the method provided by the embodiment of the present invention is shown Figure 1 When the converter is shown Figure 1 a voltage versus time curve of the voltage present in the converter shown;

[0090] Figure 7 The example operation of the method provided by the embodiment of the present invention is shown Figure 1 When the converter is shown Figure 1 Three different switching states of the converter shown;

[0091] Figure 8 The example operation of the method provided by the embodiment of the present invention is shown Figure 1 When the converter is shown Figure 1 Three different switching states of the converter shown;

[0092] Figure 9 The embodiment of the present invention provides a method for determining Figure 1 An example of a portion of a control unit for the switching power losses of the converter shown;

[0093] Figure 10 Two examples of converter structures provided by embodiments of the present invention are shown;

[0094] Figure 11 、 Figure 12 and Figure 13 Examples of converter structures provided by embodiments of the present invention are respectively shown.

[0095] In the drawings, corresponding elements are marked with the same legend symbols. DETAILED DESCRIPTION

[0096] Figure 1 An example of a converter structure provided by an embodiment of the present invention is shown.

[0097] The above description of the converter according to the third aspect applies accordingly to Figure 1 The converter 1 shown. Referring to the above description of the method of the first aspect, the method according to the first aspect is operated Figure 1 Converter 1 is shown.

[0098] Figure 1 The converter 1 shown can be implemented in combination with the converter of the third aspect as described above, such as Figure 1That is, the converter 1 includes: a first input terminal IN1 and a second input terminal IN2 for receiving a DC voltage Vin; and an output terminal OUT1 for providing an output voltage Vout that can be changed between a first voltage level and a second voltage level.

[0099] The converter 1 further comprises three switches (S U3 、S U2 、S U1 ) of the first series connection (SC U ) and three switches (S L1 、S L2 、S L3 ) of the second series connection (SC L ). Figure 1 The first series connection SC shown U and the second series connection SC L The number of switches in each of is only an example and may be only two switches or more than two switches. Figure 1 As shown, the switch S of the converter 1 U3 、S U2 、S U1 、S L1 、S L2 、S L3 are MOSFETs, each MOSFET being connected in antiparallel with a diode. This is merely an example, and the switches may correspond to different semiconductor switches, in particular transistors. Figure 1 As shown, the first series connection SC U The number of switches is equal to the second series connection SC L The number of switches.

[0100] The converter 1 further comprises two capacitor units C1 and C2. This is only an example, and therefore, the number of capacitor units in the converter 1 may be only one capacitor unit or more than two capacitor units. Specifically, the number of capacitor units is respectively greater than that of the first series connection SC. U The number of switches and the second series connection SC L The number of switches is one less. Each capacitor unit C1, C2 includes or corresponds to Figure 1 The capacitor shown. The capacitor can optionally be realized by one or more capacitor elements connected electrically in series and / or in parallel. In addition, the converter 1 includes a control unit ( Figure 1 Not shown in Figure 4 a), for controlling the switch of the conversion 1.

[0101] like Figure 1As shown, the first input terminal IN1 is connected to the first series SC U (especially the first series connection SC U The three switches S U3 、S U2 、S U1 ) is electrically connected to the output terminal OUT1. The second input terminal IN2 is connected to the second series connection SC L (especially the second series connection SC L The three switches S L1 、S L2 、S L3 ) is electrically connected to the output terminal OUT1. Each of the two capacitor units C1 and C2 connects the first series connection SC U The first node between the two switches is connected in series with the second SC L The second nodes between the two switches are electrically connected to each other, wherein the number of nodes between the first node and the output terminal OUT1 is equal to the number of nodes between the second node and the output terminal OUT1. Figure 1 As shown, the capacitor unit C1 connects the first series connection SC U The switch S U2 and S U1 The node between the first node and the second series connection SC L The switch S L1 and S L2 The nodes between the output terminal OUT1 and the switch S are electrically connected to each other. U2 and S U1 The number of nodes between the output terminal OUT1 and the switch S is equal to L1 and S L2 The number of nodes between nodes. That is, the number is equal to zero nodes.

[0102] The control unit is configured to equally distribute the DC voltage Vin to the first series connection and the second series connection SC in the following manner: U and SC L The switch S U3 、S U2 、S U1 、S L1 、S L2 、S L3 : Control the switch S U3 、S U2 、S U1 、S L1 、SL2 、S L3 , so that each of the capacitor units C1 and C2 is charged to a corresponding third voltage level. The control unit is configured to compensate the switch S in the following manner. U3 、S U2 、S U1 、S L1 、S L2 、S L3 Different power losses: Control the switch S U3 、S U2 、S U1 、S L1 、S L2 、S L3 , so that one or more of the capacitor units C1, C2 are charged above the corresponding third voltage level and / or one or more of the capacitor units C1, C2 are charged below the corresponding third voltage level, so that the DC voltage Vin is unequally distributed to the switches S U3 、S U2 、S U1 、S L1 、S L2 、S L3 The control unit is specifically configured to execute the method of the first aspect as described above, and to control the switch S of the converter 1. U3 、S U2 、S U1 、S L1 、S L2 、S L3 switch.

[0103] exist Figure 1 In the converter shown, when the first series connection SC U The number of switches between the switches and the output terminal OUT1 is equal to the second series connection SC L The number of switches between the switch and the output terminal, the first series SC U The switch (first switch) and the second series connection SC L The switch (second switch) forms a switch pair. Therefore, the switch S U1 and S L1 , the switch S U2 and S L2 and the switch S U3 and S L3 When controlling the switches of the converter 1, the switches of each switch pair can be controlled inversely. That is, when one switch in a switch pair is in a conducting state, the other switch in the switch pair may be in a non-conducting state, and vice versa.

[0104] Before describing the operation example of the converter provided by the embodiment of the present invention, Figure 4 as well as Figure 5 , wherein the number of switches and capacitor units of the converter 1 is not limited to Figure 1 Quantities shown, as described above.

[0105] Figure 4 as well as Figure 5 Two examples of converter structures provided by embodiments of the present invention are shown respectively. Figure 4 as well as Figure 5 The converter structure shown corresponds to Figure 1 The converter structure shown is different only in the number of switches and capacitor units. Figure 1 The description of the converter shown applies accordingly Figure 4 as well as Figure 5 converter shown.

[0106] Figure 4 a The first series connection SC of the switches of the converter 1 is shown U and the second series connection SC L Accordingly, two or more switches S are included U(N-1) ,……,S U1 and S L(N-1) ,……,S L1 . Figure 4 The converter 1 shown in a includes at least one capacitor unit C1. Figure 4 In a, the switch S for controlling the converter 1 is shown as an example. U(N-1) ,……,S U1 、S L(N-1) ,……,S L1 The control unit 2 of the converter. As shown by the arrow, the control unit 2 is used to control the two series connections SC of the switches U and SC L The switch S U(N-1) ,……,S U1 、S L(N-1) ,……,S L1 Each of them.

[0107] Figure 4 b shows the first series connection SC of the switches of the converter 1 U and the second series connection SC L Accordingly, three or more switches S are included U(N-1) 、S U(N-2) ,……,S U1 and S L(N-1) 、SL(N-2) ,……,S L1 . Figure 4 The converter 1 shown in b includes at least two capacitor units C(N-2) and C1.

[0108] Therefore, according to Figure 4 , each switch is connected in series SC U and SC L The number of switches corresponds to N-1 (ie, the number of switches of the converter corresponds to 2*(N-1)), and the number of capacitor units corresponds to N-2, where N is an integer greater than or equal to three (N>3). Figure 4 a and Figure 4 As can be seen from b, the number of capacitor units (N-2) is respectively greater than that of the first series connection SC U The number of switches and the second series connection SC L The number of switches (N-1) is one less. U , SC L The number of switches and capacitor units is such that the converter can be called an N-level converter, in particular an N-level two-level converter or an N-level quasi-two-level (Q2L) converter. That is, in each series connection SC U and SC L In the case of including two switches, the converter may be referred to as a three-level (3-level) converter. U and SC L In case three switches are included, the converter may be referred to as a four-level (4-level) converter, and so on.

[0109] Figure 5 a The first series connection SC of the switches of the converter 1 is shown U and the second series connection SC L Accordingly, four switches S are included. U4 、S U3 、S U2 、S U1 and S L4 、S L3 、S L2 、S L1 . Figure 5 The converter 1 shown in a includes three capacitor units C1, C2 and C3. Figure 5 The converter 1 shown in a can be called a five-level (5-level) converter. Figure 5 b shows the first series connection SC of the switches of the converter 1 U and the second series connection SC LAccordingly, five switches S are included. U5 、S U4 、S U3 、S U2 、S U1 and S L5 、S L4 、S L3 、S L2 、S L1 . Figure 5 The converter 1 shown in b includes four capacitor units C1, C2, C3 and C4. Therefore, Figure 5 The converter 1 shown in FIG. 1b can be referred to as a six-level (6-level) converter. The number of switches and capacitor units is not limited and can be further increased depending on the device voltage level and the required effective voltage. In other words, the greater the number of switches, the lower the voltage level of the switches can be for the corresponding voltage Vin applied to the input terminals IN1 and IN2 of the converter.

[0110] Figure 10 、 Figure 11 、 Figure 12 and Figure 13 Another converter structure is shown, which can be called a nested T-type converter. The nested T-type converter structure basically corresponds to Figure 1 、 Figure 4 、 Figure 5 The converter structure shown in , except that, for the nested T-type converter structure, each capacitor unit corresponds to two capacitors connected in series. One or both of the two capacitors can optionally be implemented by one or more capacitor elements connected in series and / or in parallel. In addition, Figure 10 、 Figure 11 、 Figure 12 and Figure 13 A series connection SC comprising two capacitors Ca and Cb electrically connects the first input terminal IN1 and the second input terminal IN2 of the converter 1 to each other. Figure 1 、 Figure 4 、 Figure 5 The description applies accordingly to Figure 10 、 Figure 11 、 Figure 12 and Figure 13 converter shown.

[0111] Figure 10 Two examples of converter structures provided by embodiments of the present invention are shown. Figure 10 a shows the corresponding Figure 4 a nested T-type converter structure. Figure 4 A description to describe Figure 10a, and only the differences are described below. The at least one capacitor unit C1 corresponds to two capacitors C11 and C12 electrically connected in series. In addition, Figure 10 As shown in a, the node between the two capacitors Ca and Cb of the series connection SC and the node between the two capacitors C11 and C12 of the at least one capacitor unit C1 and the output terminal OUT1 can be connected to each other through at least two bidirectional switches. Each bidirectional switch can include two transistors S MU(N-1) 、S ML(N-1) and S MU1 、S ML1 , wherein each transistor is optionally connected in antiparallel with a diode. The bidirectional switch can also be implemented in different ways, in particular using one or more different transistor types.

[0112] Figure 10 b shows the corresponding Figure 4 b shows the nested T-type converter structure of the converter structure. Therefore, referring to the above Figure 4 b's description to describe Figure 10 b, and only the differences are described below. The at least two capacitor units C1 and C2 correspond to two capacitors C11, C12 and C21, C22 connected in series. Figure 10 As shown in FIG. 2 , the node between the two capacitors Ca and Cb of the series connection SC, the two capacitors C21 and C22 of the capacitor unit C2, and the node between the two capacitors C11 and C12 of the capacitor unit C1 and the output terminal OUT1 can be connected to each other through at least three bidirectional switches. Each bidirectional switch can include two transistors S MU(N-1) 、S ML(N-1) 、S MU2 、S ML2 、S MU1 、S ML1 , wherein each transistor is optionally connected in antiparallel with a diode. The bidirectional switch can also be implemented in different ways, in particular using one or more different transistor types.

[0113] Therefore, according to Figure 10 , each switch is connected in series SC U and SC L The number of switches corresponding to N-1, the number of optional bidirectional switches connecting the node between the two capacitors and the output terminal OUT1 corresponds to N-1, where N is an integer greater than or equal to three (N>3). U , SC LThe number of switches is such that the converter can be called a (2*N+1)-level nested T-type converter ((2*N+1)-L-NTT converter). That is, in each series connection SC U and SC L In the case of including two switches, the converter can be called a five-level (5-level) nested T-type converter. U and SC L In the case of including three switches, the converter may be referred to as a seven-level (7-level) nested-T converter, and so on.

[0114] Figure 10 The nested T-type converter shown can operate as a three-level converter. That is, the switches of the respective converters can be individually controlled and switched so that the output terminal OUT1 of the converter 1 can provide an output voltage Vout that can vary between a first voltage level, a second voltage level, and a third voltage level. The first voltage level can correspond to the voltage level applied to the first input terminal IN1 of the converter 1, and the second voltage level can correspond to the voltage level applied to the second input terminal IN2 of the converter 1. The third voltage level can correspond to the voltage level at the node between the two capacitors Ca and Cb electrically connected in series between the first input terminal IN1 and the second input terminal IN2.

[0115] Figure 11 、 Figure 12 and Figure 13 The examples of the converter structure provided by the embodiments of the present invention are shown respectively. Figure 10 The description applies accordingly to the description Figure 11 、 Figure 12 and Figure 13 converter shown. Figure 11 The first series connection SC of the switches of the converter 1 is shown U and the second series connection SC L Accordingly, two switches S are included. U2 、S U1 and S L2 、S L1 . Figure 11 The converter 1 shown includes a capacitor unit C1 corresponding to two capacitors C11 and C12 connected in series, and two bidirectional switches S MU2 、S ML2 and S MU1 、S ML1 .therefore, Figure 11The converter 1 shown may be referred to as a five-level (5-level) nested-T converter.

[0116] Regarding the two series connections SC U and SC L The number of switches and capacitor units, Figure 12 The nested T-type converters shown correspond to Figure 1 The two capacitor units C1 and C2 correspond to two capacitors C11, C12 and C21, C22 electrically connected in series, respectively. Figure 12 The converter 1 shown comprises three bidirectional switches S MU3 、S ML3 ;S MU2 、S ML2 ;S MU1 、S ML1 . Figure 12 The converter 1 shown can be referred to as a seven-level (7-level) nested T-type converter. U and SC L The number of switches and capacitor units, Figure 13 The nested T-type converters shown correspond to Figure 5 The three capacitor units C1, C2 and C3 correspond to two capacitors C11 and C12, C21 and C22, and C31 and C32 electrically connected in series, respectively. Figure 13 The converter 1 shown comprises four bidirectional switches S MU4 、S ML4 ;S MU3 、S ML3 ;S MU2 、S ML2 ;S MU1 、S ML1 . Figure 12 The converter 1 shown may be referred to as a nine-level (9-level) nested-T converter.

[0117] In the following, combined Figure 2 、 Figure 3 、 Figure 6 、 Figure 7 as well as Figure 8 , according to the method example described in the present invention Figure 1 The description also applies to the operation of the converter with Figure 1 The converter structure shown is different from Figure 1 The number of switches and capacitors shown is different from that of the converters with different numbers of switch and capacitor units, and the converters with nested T-type converter structures. That is, the following description applies accordingly to Figure 4 、 Figure 5 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 In other words, the method of the present invention can be used to operate the converter including Figure 1 、 Figure 4 、 Figure 5 The converter structure shown as an example in FIG can also be used to operate Figure 10 、 Figure 11 、 Figure 12 and Figure 13 The nested T-type converter is shown in the example, with two series connections of the switches SC U , SC L The number of switches is independent of the number of capacitor units of the corresponding converter.

[0118] For the following description, it is assumed that the first voltage level V IN1 Applied to the first input terminal IN1, the second voltage level V IN2 applied to the second input terminal IN2, wherein the first voltage level V IN1 is greater than the second voltage level V IN2 (V IN1 >V IN2 ). Therefore, the DC voltage Vin applied to the input of the converter (in particular between the two input terminals IN1 and IN2) may correspond to the difference between these two voltage levels (Vin=V IN1 –V IN2 ). In addition, assuming that the second voltage level V IN2 Corresponding to ground (V IN2 = GND), specifically corresponding to zero volts (V IN2 =0V). The following description applies accordingly to the second voltage level V IN2 Corresponding to the case of a voltage level different from ground GND or zero volts. According to one embodiment, the first voltage level V IN1 may be equal to a positive DC voltage level, the second voltage level V IN2 The following description applies correspondingly to the case where an AC voltage is applied to the input of the converter 1 , in particular between the two input terminals IN1 and IN2 .

[0119] exist Figure 1 In normal operation of the converter 1 shown, the DC voltage Vin can be equally distributed between the two series-connected SC U and SC L For example, the output voltage Vout corresponding to the second voltage level V IN2The steady state (second steady state) of the converter 1: the switches of the converter 1 are controlled so that the second series connection SC L The switch S L1 、S L2 and S L3 is in the on-state, and the first series connection SC U The switch S U1 、S U2 and S U3 In a non-conducting state. The terms "on", "in the on state" and "in the conducting state" may be used as synonyms. The terms "off", "in the off state" and "in the non-conducting state" may be used as synonyms. For this steady state (second steady state), in normal operation, the DC voltage Vin is evenly distributed among the first series connection SC U The non-conducting switch S U1 、S U2 and S U3 That is, in the above steady state, the switch S U1 The voltage across the two ends V SU1 , the switch S U2 The voltage across the two ends V SU2 and the switch S U3 The voltage across the two ends V SU3 Equal to each other.

[0120] In order to achieve the first steady state of the converter (in the first steady state), the output voltage Vout is equal to the first voltage level V IN1 ) and the second steady state of the converter (in the second steady state, the output voltage Vout is equal to the second voltage level V IN2 ), Figure 1 The converter 1 shown can be operated as a two-level (2-level) converter with short time intervals that form a quasi-multilevel circuit. These short time intervals can also be referred to as transition phases. A key reason for adopting this method of operation, which uses short transition phases to switch between the converter's two stable states, is that it enables the use of low-voltage components (switches) in a series connection to achieve higher voltage levels. Due to the small step size and slow voltage transition rate, the requirements for isolation design and electromagnetic interference suppression are much lower, and the capacitor unit is more compact and lightweight. Figure 2 The switching states of the converter are shown during two conversion phases and during the first steady state of the converter.

[0121] Figure 2 The example operation of the method provided by the embodiment of the present invention is shown Figure 1 When the converter is shown Figure 1 The three different switching states of the converter are shown. Figure 2 In FIG, the current flowing through the converter is shown as a bold dashed line. Figure 2 As shown, Figure 1 The converter 1 may optionally include a further output terminal OUT2 connected to the second input terminal IN2 of the converter 1 .

[0122] Specifically, Figure 2 a and Figure 2 b shows the states of the converter in the two conversion phases when the converter switches between the second steady state and the first steady state, Figure 2 c shows the first steady state. As a starting state, the converter 1 can be in the second steady state of the converter 1 ( Figure 2 Not shown), wherein the second series connection SC L The switch S L1 、S L2 and S L3 In the on-state, the first series connection SC U The switch S U1 、S U2 and S U3 In order to switch the converter 1 to the first steady state, the second series connection SC L The switch S L1 switches to the non-conducting state and the first series connection SC U The switch S U1 Switches to the on state. Current flows from the capacitor unit C1 to the output terminal OUT1, and the output voltage Vout is equal to the voltage V of the capacitor C1. C1 . Figure 2 a shows the switching state of the converter during this short switching phase. This switching phase may last for about 1 microsecond. Therefore, after a very short time interval (for example, about 1 microsecond), the second series connection SC L The switch S L2 switches to the non-conducting state and the first series connection SC U The switch S U2 Switches to the on state. Therefore, the current flowing out of the capacitor C1 stops, the current starts flowing from the capacitor 2 to the output terminal OUT1, and the output voltage Vout becomes equal to the voltage V of the capacitor C2. C2 . Figure 2b shows the switching state of the converter during this short transition phase. This transition phase may also last about 1 microsecond. Therefore, after an equal amount of very short time (e.g., about 1 microsecond), the second series connection SC L The switch S L3 switches to the non-conducting state and the first series connection SC U The switch S U3 Switched to the conducting state. Therefore, there is now current flowing out of the capacitors C1 and C2. That is, the current flows through the first series connection SC L The conduction switch S U3 、S U2 and S U1 , flows from the first input terminal IN1 to the output terminal OUT1. Therefore, the output voltage Vout is equal to the first voltage level V applied to the first input terminal IN1. IN1 This state corresponds to the first stable state, as Figure 2 c. To switch the converter from the first stable state to the second stable state, the above description applies accordingly, wherein the switch that has been switched to the non-conductive state can now be switched to the conductive state, and vice versa. Figure 2 The sequence starting from the state shown in c can be Figure 2 The conversion phase shown in b is followed by Figure 2 The conversion phase shown in a is finally Figure 2 The second steady state of the converter is not shown.

[0123] Complete the series connection SC U or SC L The switches of the series connection SC are switched to the conducting state or the non-conducting state (ie, the series connection SC is not switched at the same time). U or SC L At least two switches are switched sequentially) with a delay interval to establish an intermediate voltage level V C1 and V C2 , without overloading the device voltage rate. The intermediate voltage level V C1 and V C2 Produced by the capacitor units C1, C2 of the converter 1, which are directly interconnected with the switches, such as Figure 1 To maintain the desired voltage level across the capacitor unit, the Figure 6The switches of the converter are switched accordingly as described exemplarily. That is, by switching the switches of the converter accordingly, the capacitor unit can be charged to increase the voltage of the capacitor unit. Thus, by switching the switches of the converter accordingly, the capacitor unit can be discharged to reduce the voltage of the capacitor unit.

[0124] Figure 3 The example operation of the method provided by the embodiment of the present invention is shown Figure 1 When the converter is shown Figure 1 The voltage in the converter shown here varies with time. Figure 1 When the converter switches from the second steady state to the first steady state and then switches back to the second steady state, Figure 3 a shows the time variation of the switch S U1 The voltage across the two ends V SU1 , the switch S U2 V at both ends SU2 and the switch S U3 The voltage across the two ends V SU3 , Figure 3 b shows the output voltage Vout of the converter. Figure 3 The illustrated region 1 corresponds to the second stable state of the converter. Figure 3 The area 4 shown corresponds to Figure 2 c shows the first steady state of the converter. Figure 3 The illustrated regions 2 and 3 correspond to very short transition phases or transition states (e.g., approximately 1 microsecond) when switching from the second stable state to the first stable state, respectively. Figure 3 The illustrated regions 5 and 6 correspond to a very short transition phase or transition state (eg, approximately 1 microsecond) when switching from the first stable state to the second stable state, respectively. Figure 3 Regions 2 and 6 shown correspond to Figure 2 The state of the converter shown in a, Figure 3 Regions 3 and 5 shown correspond to Figure 2 b shows the state of the converter. Figure 3 As shown, the voltage Vin applied to the input terminal of the converter is applied to the switch S U1 、S U2 and S U3 is evenly distributed among them and is not higher than the voltage V of the capacitor unit C1 C1 .

[0125] The power loss of each switch of the converter includes conduction loss and switching loss. The conduction loss depends on the switch current and the on-resistance, which is an internal characteristic of the switch. The switching loss depends on the switch current, the voltage across the switch, the on / off time and the switching frequency:

[0126] P sw =P swOn +P swOff =V*I*t on *f sw +V*I*t off *f sw (1)

[0127] In the above equation, P sw Indicates the switching loss of the switch, P swOn represents the loss when the switch is switched to the on state, P swOff represents the loss when the switch is switched to the non-conducting state, V represents the voltage across the switch, I represents the switch current, and t on represents the turn-on time (the time required to switch the switch to the conducting state), t off represents the turn-off time (the time required to switch the switch to the non-conducting state), f sw represents the switching frequency.

[0128] Real switches are not ideal; their characteristics vary, including on-resistance, gate threshold voltage, turn-on / off times, and thermal impedance. Furthermore, the thermal interface of these switches may have microscopic imperfections, which can trap air particles between the housing and the heat sink. This reduces the thermal impedance between the switch and the external heat sink. Due to these factors, the switch stress caused by power loss is unevenly distributed among the switches connected in series. Consequently, after a period of sustained operation, the health of some switches may be significantly lower than that of others. Failure of a single device can lead to failure of the entire converter.

[0129] Therefore, the present invention proposes that the first series connection SC U The switch S U1 、S U2 、S U3 and the second series connection SC L The switch S L1 、S L2 、S L3The voltage distribution of the voltage Vin received by the input terminals IN1 and IN2 is actively changed so that a lower voltage is applied to one or more switches with lower / poorer health, and a higher voltage is applied to other switches with higher / better health. In other words, it is recommended that the stress of devices with lower / poorer health be shared with devices with higher / better health.

[0130] In order to equally distribute the voltage Vin receivable by the two input terminals IN1 and IN2, the switches of the converter are controlled such that each of the two capacitor units C1, C2 is charged to a respective third voltage level. K The third voltage level can be defined as (K*Vin) / (N C +1), where Vin is the voltage received by the two input terminals IN1 and IN2, and N C is the number of capacitor units in the converter, and K is the index of the capacitor unit (wherein the index is greater than or equal to one, K≥1). The capacitor unit closest to the output terminal has the lowest index K (K=1). Therefore, Figure 1 In the case of the converter shown, the third voltage level of the capacitor unit C1 may be equal to Vin / 3, and the third voltage level of the capacitor unit C2 may be equal to 2Vin / 3.

[0131] For nested T-type converters, such as Figure 10 、 Figure 11 、 Figure 12 and Figure 13 As shown, the capacitor unit C K The third voltage level can be defined as (2*K*Vin) / (2*N c ), wherein Vin is the voltage received by the two input terminals IN1 and IN2, and K is the index of the capacitor unit (wherein the index is greater than or equal to one, K≥1). N C is the number of capacitor units in the converter, wherein the series connection of the two capacitors Ca, Cb electrically connected to the first input terminal and the second input terminal of the converter is counted as one capacitor unit. The capacitor unit closest to the output terminal has the lowest index K (K=1), and the series connection of the two capacitors Ca, Cb electrically connecting the first input terminal and the second input terminal of the converter is regarded as the capacitor unit with the highest index K. Therefore, for Figure 11In the nested T-type converter shown, the third voltage level of the capacitor unit C1 can be equal to 2Vin / 4, and the voltage level is equally distributed between the capacitors C11 and C12 of the capacitor unit C1 (C11=C12=Vin / 4). That is, the third voltage level of each capacitor of the capacitor unit corresponds to half of the third voltage level of the capacitor unit. The third voltage level of the series connection of the two capacitors Ca and Cb (regarded as the capacitor unit C2) can be equal to Vin equally distributed between the capacitors Ca and Cb (Ca=Cb=Vin / 2). Figure 12 , the third voltage level of the capacitor unit may be as follows: C1=2Vin / 6, C11=C12=Vin / 6; C2=4Vin / 6, C21=C22=2Vin / 6; Ca=Cb=3Vin / 6. Figure 13 , the third voltage level of the capacitor unit can be as follows: C1=2Vin / 8, C11=C12=Vin / 8; ​​C2=4Vin / 8, C21=C22=2Vin / 8; ​​C3=6Vin / 8, C31=C32=3Vin / 8; ​​Ca=Cb=4Vin / 8.

[0132] refer to Figure 1 If the voltage level to which the capacitor unit C2 is charged is higher than / greater than the third voltage level of the capacitor unit C2, the switch S U3 and S L3 The voltage across the switch S U2 and S L2 The voltage across the switch S will increase, and vice versa. U3 and S L3 The stress is redistributed to the remaining switches S U2 、S U1 、S L1 and S L2 If the voltage level to which the capacitor unit C2 is charged or discharged is lower than / less than the third voltage level of the capacitor unit C2, the switch S U3 and S L3 The voltage across the switch S will increase. U2 and S L2 The voltage across the terminals will decrease. The terms "decrease" and "reduce" can be used as synonyms. The terms "increase" and "raise" can be used as synonyms.

[0133] In other words, the more the capacitor unit C2 is charged above the corresponding third voltage level, the more the capacitor unit C2 is allocated to the switch S U3 and SL3 The voltage Vin is reduced as much as possible, and is allocated to the switch S U2 and S L2 Therefore, the less the capacitor unit C2 is charged below the corresponding / corresponding third voltage level or the more the capacitor unit C2 is discharged below the corresponding / corresponding third voltage level, the more the voltage Vin is allocated to the switch S U3 and S L3 The voltage Vin increases as the part is allocated to the switch S U2 and S L2 The voltage Vin decreases more as the part thereof increases.

[0134] Then, the voltage of the capacitor unit C1 will determine the voltage distribution of the capacitor unit C2, thereby determining the switch S U2 、S L2 With the switch S U1 、S L1 If the capacitor unit C1 is charged to the corresponding third voltage level of the capacitor unit C1, the capacitor unit C2 and the remaining stress and power loss will be in the remaining switch pair S. U2 、S L2 and S U1 、S L1 Otherwise, if the voltage level to which the capacitor unit C1 is charged is higher than / greater than the third voltage level of the capacitor unit C1, the switch S U2 and S L2 The voltage across the switch S U1 and S L1 The voltage across the switch will increase, and vice versa. U2 and S L2 The power loss will be lower than the switch S U1 and S L1 The above description illustrates how charging and / or discharging the capacitor units C1 and C2 of the converter can redistribute the voltage between the switches of the converter to redistribute the stress from switches with poor health to switches with good health. This will increase the life of the entire converter.

[0135] The above description of the method of the first aspect is applicable to the description of the operation Figure 1 The converter shown here is a method to achieve a longer converter life. Figure 1 The switch S of the converter shown U1 and S L1Each corresponds to a switch (which may be referred to as an output switch or a third switch) electrically connected to the output terminal OUT1. The capacitor unit C1 corresponds to a capacitor unit electrically connected to the first node of the first series connection and the second node of the second series connection, the first node of the first series connection and the second node of the second series connection being closest to the output terminal in terms of the number of nodes. Figure 1 The switch S of the converter shown U3 、S U2 、S L2 and S L3 Each corresponds to a switch electrically connected to the output terminal OUT1 through one or more switches. U3 and S L3 , the capacitor unit C2 corresponds to a first capacitor unit, the first capacitor unit is connected to the switch S U3 、S L3 Of the two terminals of the switch S, the terminal closer to the output terminal OUT1 in terms of the number of nodes. U2 and S L2 , the capacitor unit C1 corresponds to a first capacitor unit, the first capacitor unit is connected to the switch S U2 、S L2 The terminal of the switch S is closer to the output terminal OUT1 in terms of the number of nodes. U2 and S L2 , the capacitor unit C2 corresponds to a second capacitor unit, the second capacitor unit is connected to the switch S U2 、S L2 The other of the two terminals.

[0136] Figure 6 The example operation of the method provided by the embodiment of the present invention is shown Figure 1 When the converter is shown Figure 1 The voltage versus time curve of the voltage present in the converter is shown. Specifically, Figure 6 It is shown as an example Figure 1 The first series connection SC of the converter 1 is shown U The switch S U2 and S U3 The switching sequence is used to charge / discharge the capacitor unit C2 to change the voltage of the capacitor unit C2.

[0137] exist Figure 6 The top diagram shows the switch S U3The second figure shows the switching between the conducting state "on" and the non-conducting state "off" as a function of time t. U2 The switching between the conducting state "ON" and the non-conducting state "OFF" is performed as a function of time t. The second to last figure shows the current I through the capacitor unit C2 as a function of time t. C2 The bottom graph shows the voltage V of the capacitor unit C2 as a function of time t. C2 .

[0138] Figure 6 The left diagram of a shows a mixed sequence for a balancing operation, ie charging and discharging the capacitor unit C2 to allow the voltage of the capacitor unit C2 to remain constant, for example at the respective third voltage level, when the sequence is repeated. Figure 6 The right diagram of a shows another mixed sequence for balancing operation, ie discharging and charging the capacitor unit C2 to allow the voltage of the capacitor unit C2 to remain constant, for example at the respective third voltage level, when the sequence is repeated.

[0139] Figure 6 The right diagram of b shows a charging sequence, i.e. charging the capacitor unit C2 to allow the voltage of the capacitor unit C2 to increase, for example, to be higher than the corresponding third voltage level. In other words, Figure 6 The right diagram of b shows a charging sequence for charging the capacitor unit C2 to, for example, above the corresponding third voltage level. Figure 6 The left diagram of b shows a discharge sequence, ie, discharging the capacitor unit C2 to allow the voltage of the capacitor unit C2 to decrease, for example, to be lower than the corresponding third voltage level. In other words, Figure 6 The left diagram of b shows a discharge sequence for discharging the capacitor unit C2, such as to below the corresponding third voltage level. Figure 6 The description regarding the charging and discharging of the capacitor unit C2 , respectively, applies correspondingly to the charging and discharging of the other capacitor unit (capacitor unit C1 ) of the converter.

[0140] The switching phase between the first steady state and the second steady state of the converter may be changed Figure 1 The voltage levels of the capacitor units C1 and C2 of the converter are shown. That is, the voltage levels of the capacitor units C1 and C2 can be changed according to the delay sequence between the switches of the converter. That is, in order to switch the converter between the first stable state and the second stable state, the first series connection SC can be switched sequentially with a very short switching delay between the switches. U The switch S U3 、SU2 and S U1 This also applies to the second series connection SC L The switch S L3 、S L2 and S L1 . See below Figure 6 Description of the first series connection SC U The switch S U3 、S U2 and S U1 The second series connection SC L The switch S L3 、S L2 and S L1 For reverse switching. That is, the switch S L3 and the switch S U3 For reverse switching. For example, when the switch S U3 is switched to the on state, the switch S L3 is switched to the non-conducting state and vice versa. The same applies to the switch pair S U2 and S L2 And the switch pair S U1 and S L1 “Switching a switch to a conducting state / non-conducting state” and “turning a switch on / off” may be used as synonyms.

[0141] about Figure 6 a The switching sequence on the left side, the region 1 corresponds to the state of the converter, in which the first series connection SC U The switch S U3 、S U2 and S U1 is in the non-conducting state, so the second series connection SC L All switches S L3 、S L2 and S L1 Therefore, the current flows from the output terminal OUT1 to the second input terminal IN2. Figure 7 This corresponds to the second steady state of the converter. Figure 6 As shown in the area 2 on the left side of a, the switch S U3 switches to the on state, and the switch S U2 and S U1 is in the non-conducting state. Therefore, the capacitor unit C2 uses the current I C2 To charge, Figure 6 a and Figure 7b is shown in area 2 on the left. The amount of voltage added to or subtracted from the capacitor cell is proportional to the device current and operating time and inversely proportional to its capacitance, as shown by the formula Δv = iΔt / C. The operating time may be short and the capacitance may be small, so the voltage change may be limited and the switch (switching device) operates within the power-saving voltage range. Then, as Figure 6 As shown in the area 3 on the left side of a, the switch S U2 switches to the on state, and the switch S U3 In the on state, the switch S U1 Therefore, the current does not flow through the capacitor unit C2, but flows through the capacitor unit C1 to charge the capacitor unit C1, as shown in FIG. Figure 6 The area 3 shown Figure 7 Then, in the region 4, the switch S U1 Switch to the conducting state so that all the switches S U3 、S U2 and S U1 Therefore, the current and voltage of the capacitor units C1 and C2 no longer change. This corresponds to Figure 8 The corresponding Figure 6 The first stable state of region 4 is shown.

[0142] Figure 6 The switching sequence shown on the right side of a is Figure 6 The switching order shown on the left side of a is reversed. Figure 6 a) The first series connection SC is connected in the order of regions 1, 2, 3, 4, 5, 6, and 1 as shown on the left side of the diagram. U The switch S U3 、S U2 and S U1 When switching from the non-conductive state to the conductive state (i.e., when switching the converter from the second stable state to the first stable state), the capacitor units C1 and C2 are charged. U The switch S U3 、S U2 and S U1 When switching from the conductive state to the non-conductive state (ie, when switching the converter from the first stable state to the second stable state), the capacitor units C1 and C2 are discharged.

[0143] In contrast, according to Figure 6a The order of regions 1, 6, 5, 4, 3, 2, 1 is shown on the right side of the diagram. The first series connection SC is connected in the order of regions 1, 6, 5, 4. U The switch S U3 、S U2 and S U1 When switching from the non-conductive state to the conductive state (i.e., when switching the converter from the second stable state to the first stable state), the capacitor units C1 and C2 are discharged. In addition, the first series connection SC is connected in the order of regions 4, 3, 2, and 1. U The switch S U3 、S U2 and S U1 When switching from the conductive state to the non-conductive state (ie, when switching the converter from the first stable state to the second stable state), the capacitor units C1 and C2 are charged.

[0144] The discharge sequence is opposite to the charge sequence. Figure 6 As shown on the right side of a, the region 1 represents the second steady state of the converter as the starting state of the switching sequence. Figure 6 In the area 6 shown on the right side of a, the switch S U1 switches to the on state, and the switch S U2 and S U1 is in the non-conducting state. Therefore, the capacitor unit C1 is discharged because current flows out of it, as corresponding to Figure 6 The area 6 shown Figure 8 c. Therefore, Figure 7 c shows the flow through Figure 6 The current of the capacitor unit C1 in the region 3 (charging the capacitor unit C1) is Figure 8 c shows the flow through Figure 6 The current of the capacitor unit C1 in the region 6 (discharging the capacitor unit C1) is opposite. Then, as Figure 6 As shown in the area 5 on the left side of a, the switch S U2 switches to the on state, and the switch S U1 Keeping the conductive state, the switch S U3 Therefore, the capacitor unit C2 is kept in a non-conductive state due to the current I C2 Discharge flows out of it, such as Figure 6 and Figure 8 As shown in region 5 in b. Therefore, Figure 7 The flow shown in b Figure 6 The current I of the capacitor unit C2 in the region 2 is shown C2 (Charging the capacitor unit C2) and Figure 8 The flow shown in b Figure 6 The current of the capacitor cell C2 (discharging the capacitor cell C2) is opposite in the region 5. The rate of discharge of the capacitor cell is the same as the rate of charge of the capacitor cell.

[0145] In addition, only the capacitor units C1 and C2 may be charged in one cycle in the switching order of regions 1, 2, 3, 4, 2, and 1 (for example, the capacitor units are switched from the second steady state to the first steady state and then switched back to the second steady state), as shown in FIG. Figure 6 b is shown as the capacitor unit C2 on the right side. Figure 6 b is shown on the right side, in the switch S U2 Before turning the switch S U3 switches to the on-state, and in the S U2 In addition, the capacitor units C1 and C2 may be discharged only in one cycle (for example, the capacitor units are switched from the second stable state to the first stable state and then switched back to the second stable state) in the switching order of regions 1, 5, 3, 4, 5, and 1. Figure 6 b is shown as the capacitor unit C2 on the left. Figure 6 b As shown on the left, in the switch S U2 Then the switch S U3 switches to the on state, and the switch S U2 before switching it to the non-conducting state.

[0146] Figure 1 The different switching states of the converter shown are based on the first series connection SC in Table 1 below. U The switch S U3 、S U2 and S U1 The switching states of the converter are shown in FIG. Figure 6 、 Figure 7 as well as Figure 8 As described above, in different switching states of the converter, the second series connection SC L The switch S L3 、S L2 and S L1 With respect to the first series connection SC UThe corresponding switches of the capacitors C1 and C2 are in opposite / reverse switching states. In Table 1, "0" indicates that the switch is in the non-conducting state, and "1" indicates that the switch is in the conducting state. Table 1 also indicates, for different switching states, whether the capacitor units C1 and C2 are charging ("Ch"), discharging ("Dis"), or neither ("-"). In Table 1, the term "second stable state" is abbreviated as "SSS", the term "transition phase" (also referred to as transition state) is abbreviated as "TP", and the term "first stable state" is abbreviated as "FSS".

[0147] Table 1: Figure 1 Different states of the converter shown

[0148] Figure 6 、 Figure 7 as well as Figure 8 The area shown in 1 2 3 4 5 6 Converter Status SSS TP TP FSS TP TP <![CDATA[S U3 ]]> 0 1 1 1 0 0 <![CDATA[S U2 ]]> 0 0 1 1 1 0 <![CDATA[S U1 ]]> 0 0 0 1 1 1 C1 - - Ch - - Dis C2 - Ch - - Dis -

[0149] Figure 7 as well as Figure 8 The following respectively illustrate the example operations of the method provided by the embodiment of the present invention. Figure 1 When the converter is shown Figure 1 The three different switching states of the converter are shown. Figure 7 as well as Figure 8 In FIG, the current flowing through the converter is shown as a bold dashed line.

[0150] Figure 7 The switching state shown in a corresponds to the second stable state of the converter, and thus corresponds to Figure 6 Region 1 is shown. In this state, the capacitor units C1 and C2 are neither charged nor discharged. Figure 7 The switching state shown in b corresponds to the switching phase of the converter, in which the capacitor unit C2 is charged. Figure 6 Area 2 shown. Figure 7 The switching state shown in c corresponds to the switching phase of the converter, in which the capacitor unit C1 is charged. Figure 6 Area 3 shown.

[0151] Figure 8 The switching state shown in a corresponds to the first stable state of the converter, and thus corresponds to Figure 6 Region 4 is shown. In this state, the capacitor units C1 and C2 are neither charged nor discharged. Figure 8 The switching state shown in b corresponds to the switching phase of the converter, in which the capacitor unit C2 is discharged. Figure 6 Area 5 shown. Figure 8 The switching state shown in c corresponds to the switching phase of the converter, in which the capacitor unit C1 is discharged. Figure 6Area 6 shown.

[0152] In order to determine the switch S of the converter U3 、S U2 、S U1 、S L1 、S L2 and S L3 The power loss of each switch can be used to determine the health of the switch. The temperature of each switch can be measured as an indicator of the power loss of the corresponding switch. The higher the power loss of a switch, the greater the stress on the switch, and therefore the worse the health of the switch.

[0153] Therefore, the switch S U3 、S U2 、S U1 、S L1 、S L2 and S L3 The switch with the highest temperature and the highest power loss is the switch S U3 、S U2 、S U1 、S L1 、S L2 and S L3 Therefore, the switch S can be controlled U3 、S U2 、S U1 、S L1 、S L2 and S L3 , so that a portion of the voltage Vin (received by the input terminals IN1 and IN2) allocated to the switch with the highest power loss is reduced.

[0154] In other words, the switch S can be controlled U3 、S U2 、S U1 、S L1 、S L2 and S L3 , causing the capacitor units C1 and C2 to charge and / or discharge, thereby reducing the voltage allocated to the switch with the highest power loss and redistributing the voltage allocated to the switch with the highest power loss to other switches of the converter. Thus, stress on the switch with the highest power loss can be reduced. Stress on other switches may not be significantly increased due to the redistribution, because the redistributed voltage can be evenly distributed among the other switches, so that the voltage redistributed to each of the other switches is not too much.

[0155] According to an embodiment, the combined power loss of each switch pair of the converter, ie the combined power loss of the two switches of each switch pair, may be determined.

[0156] As mentioned above, the switch S U1 and S L1 , the switch S U2 and S L2 and the switch S U3 and S L3 Each forms a switch pair. The switch pair with the highest combined power loss among the combined power losses of the switch pairs of the converter can be determined. By determining the switch pair with the highest combined power loss, the switch pair with the worst health among the switch pairs can be determined. Then, the switch S can be controlled U3 、S U2 、S U1 、S L1 、S L2 and S L3 , so that a portion of the voltage Vin (received by the input terminals IN1 and IN2) allocated to the two switches of the switch pair with the highest combined power loss is reduced.

[0157] To determine the combined power loss of a switch pair of the converter, the sum of the temperature of the first switch of the switch pair and the temperature of the second switch of the switch pair can be determined (in particular, calculated). In other words, the sum of these two temperatures can serve as an indicator of the combined power loss of the switch pair.

[0158] Figure 9 The embodiment of the present invention provides a method for determining Figure 1 An example of a portion of a control unit that controls the switching power losses of the converter is shown.

[0159] Figure 9 The part of the control unit shown is used to determine the combined power loss of the switch pairs of the converter by determining the temperature of the switch pairs and to determine the switch pair with the highest power consumption by comparing the temperatures of the switch pairs with one another. To this end, the temperature of the switch S is measured using a known method. U3 、S U2 、S U1 、S L1 、S L2 and S L3 Temperature T SU3 、T SU2 、T SU1 、T SL1 、T SL2 、T SL3 , i.e., using a known method to measure the temperature of each switch. Then, the temperatures of the two switches of each switch pair are added together to calculate the combined power loss index of the corresponding switch pair. In other words, Figure 9 As shown, the temperature T SU3and T SL3 Add(T SU3 +T SL3 ), so that the sum of these two temperatures becomes the temperature including the switch S U3 and S L3 The combined power loss indicator of the switch pair. SU2 and T SL2 Add(T SU2 +T SL2 ), so that the sum of these two temperatures becomes the temperature including the switch S U2 and S L2 The combined power loss indicator of the switch pair. SU1 and T SL1 Add(T SU1 +T SL1 ), so that the sum of these two temperatures becomes the temperature including the switch S U1 and S L1 The combined power loss indicator of the switch pair. For this calculation, Figure 9 The figure shows the temperature T SU3 and T SL3 This is merely an example, as the temperature may additionally or alternatively be calculated by different known methods.

[0160] like Figure 9 As shown, measure the switch S U3 and S L3 Temperature T SU3 and T SL3 Afterwards, the measurement result is amplified by an emitter follower circuit using operational amplifiers U1 and U2. The amplified signal is then applied to an inverting summing circuit comprising resistors R1, R2, R3 and R4 and operational amplifier U3. In addition, the temperature T is calculated. SU3 and T SL3 Add(T SU3 +T SL3 ) can also include an operational amplifier U4 and resistors R5 and R6. Next, the sum of the individual temperatures representing the power losses of the individual combinations of the switch pairs is compared using the comparison unit 3. Thus, Figure 9 The part of the control unit shown in FIG. 1 is used to determine a switch pair of the switch pairs having the highest combined power loss based on the measured switch temperatures.

[0161] According to an example scenario, the switch S U3 、S U2 、S U1 、S L1 、S L2 and S L3 The temperature can be expressed as follows:

[0162] T SU3 =60℃, T SU2 =30℃, T SU1 =32℃, T SL1 =35℃, T SL2 =29℃ and T SL3 =30℃.

[0163] Therefore, the combined temperature is as follows:

[0164] T SU3 +T SL3 =90℃>T SU1 +T SL1 =67℃>T SU2 +T SL2 =59℃.

[0165] That is, including the switch S U3 and S L3 The switch pair of has the highest combined power loss among the switch pairs because the two switches S U3 and S L3 The sum of the temperatures of the switch S is higher than the sum of the temperatures of the two switches of the other switch pair. U2 and S L2 The switch pair of has the lowest combined power loss among the switch pairs because the two switches S U2 and S L2 The sum of the temperatures of the two switches of the other switch pair is lower than the sum of the temperatures of the two switches of the other switch pair.

[0166] Therefore, in the above scenario, in order to increase the life of the converter, the voltage applied to the switch S can be reduced. U3 and S L3 The voltage can then be redistributed equally to the other switches S of the converter. U2 、S U1 、S L1 、S L2 Alternatively, the voltage amount may be redistributed later so that more of the voltage amount is allocated to the switch S U2 and S L2 Instead of the switch S U1 and S L1 , because including the switch S U1 and S L1 The combined power loss of the switch pair is higher than that of the switch S U2 and S L2 The combined power loss of the switch pair.

[0167] To achieve this, the capacitor unit C2 can be charged to above the corresponding third voltage level (2Vin / 3), but lower than the voltage Vin received by the input terminals IN1 and IN2. As a result, the voltage allocated to the switch S U3 and S L3 This reduces the switching S U3 and S L3 The power loss of the switch S U3 and S L3 Charging the capacitor unit C2 to above the corresponding third voltage level (2Vin / 3) will increase the stress allocated to the other switches S U2 、S U1 、S L1 、S L2 The remainder of the voltage Vin is increased to the same extent as the voltage allocated to the switch S U3 and S L3 The voltage Vin is reduced to the same extent / range as the portion of the voltage Vin. U1 and S L1 The power loss is redistributed to the switch S U2 and S L2 , the capacitor unit C1 may be charged or discharged to a voltage level that is lower than / less than the corresponding third voltage level (Vin / 3) of the capacitor unit C1 but higher than 0V.

[0168] The invention has been described with reference to various exemplary embodiments and implementations. However, other variations will be apparent to and will be realized by those skilled in the art in practicing the claimed invention, based on a study of the drawings, the present disclosure, and the independent claims. In the claims and the specification, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element or other unit may fulfil the functions of several entities or items recited in the claims. The recitation of certain measures in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A method for operating a converter (1), characterized in that - The converter (1) comprises: - a first input terminal and a second input terminal (IN1, IN2) for receiving a DC voltage (Vin), - Output terminal (OUT1) for providing a first voltage level (V IN1 ) and a second voltage level (V IN2 ) changes between the output voltage (Vout), - Two or more switches as semiconductor switches (S U(N-1) 、S U1 ;S L1 、S L(N-1) ) of the first series connection and the second series connection (SC U , SC L ), - one or more capacitor units (C1), wherein - the first input terminal (IN1) is connected to the second input terminal (IN1) through the two or more switches (S U(N-1) 、S U1 ) of the first series connection (SC U ) is electrically connected to the output terminal (OUT1), - The second input terminal (IN2) is connected to the second input terminal (IN2) through the two or more switches (S L1 、S L(N-1) ) of the second series connection (SC L ) is electrically connected to the output terminal (OUT1), - Each of the one or more capacitor units (C1) connects the first series connection (SC U ) between the first node of the two switches connected in series with the second (SC L ) are electrically connected to each other, wherein the number of nodes between the first node and the output terminal (OUT1) and the number of nodes between the second node and the output terminal (OUT1) are equal to each other, - The DC voltage (Vin) can be equally distributed to the first series connection and the second series connection (SC) in the following manner U , SC L ) of the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ): Control the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ), so that each of the one or more capacitor units (C1) is charged to a corresponding third voltage level; - The method comprises the following steps: - Compensate the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ) of different power losses: Control the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ), so that - one or more of said one or more capacitor units (C1) are charged above said respective third voltage level, and / or - one or more of said one or more capacitor units (C1) are charged below said respective third voltage level, The DC voltage (Vin) is distributed unevenly to the switches (S U(N-1) 、S U1 、S L1 、S L(N-1) ).

2. The method according to claim 1, characterized in that The method comprises the following steps: - Compensate the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ) of different power losses: Control the switch (S U(N-1) 、S U1 ;S L1 、S L(N-1) ), so that - one or more of said one or more capacitor units (C1) are charged above said respective third voltage level, and / or - one or more of the one or more capacitor units (C1) are charged or discharged below the respective third voltage level; The above steps are performed in one or more transition phases between a first steady state of the converter (1) and a second steady state of the converter (1), wherein in the first steady state, the output voltage (Vout) is equal to the first voltage level (V IN1 ), in the second steady state, the output voltage (Vout) is equal to the second voltage level (V IN2 ).

3. The method according to claim 1 or 2, characterized in that The method comprises the following steps: - The switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ) in one or more switches: measuring the temperature of the corresponding switch as a power loss indicator of the corresponding switch.

4. The method according to any one of the preceding claims, characterized in that The method comprises the following steps: - Determine the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ) of the power loss; - Control the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ), so that the DC voltage (Vin) of a portion allocated to the switch with the highest power loss is reduced.

5. The method according to claim 4, characterized in that The method comprises the following steps: - Control the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ), so that a portion of the DC voltage (Vin) allocated to the switch with the highest power loss is reduced and the rest of the DC voltage (Vin) is equally distributed to the rest of the switches.

6. The method according to any one of the preceding claims, characterized in that The method comprises the following steps: - determining the combined power loss of each switch pair comprising the first series connection (SC U ) of the first switch and the second series connection (SC L ), wherein the number of switches between the first switch and the output terminal (OUT1) and the number of switches between the second switch and the output terminal (OUT1) are equal to each other; - determining the first series connection and the second series connection (SC U , SC L ) a switch pair having the highest combined power loss among the combined power losses of the switch pairs; - Control the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ), so that a portion of the DC voltage (Vin) allocated to the first switch and the second switch of the switch pair with the highest combined power loss is reduced.

7. The method according to claim 6, characterized in that The method comprises the following steps: - Control the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ), so that a portion of the DC voltage (Vin) allocated to the first switch and the second switch of the switch pair with the highest combined power loss is reduced and the remaining DC voltage (Vin) is evenly distributed to the remaining switches (S U(N-1) 、S U1 、S L1 、S L(N-1) ).

8. The method according to claim 6 or 7, characterized in that The method comprises the following steps: - determining a combined power loss of one or more of the switch pairs by determining a sum of a temperature of the first switch of the corresponding switch pair and a temperature of the second switch of the corresponding switch pair as a combined power loss indicator of the corresponding switch pair.

9. The method according to any one of the preceding claims, characterized in that In order to reduce the amount of power allocated to the switch (S) directly electrically connected to the output terminal (OUT1) U1 ;S L1 ), the method comprising the steps of: - Control the switch (S U3 、S U2 、S U1 、S L1 、S L2 、S L3 ), so that the capacitor unit (C1) of the one or more capacitor units (C1, C2) is charged to below the corresponding third voltage level, wherein the capacitor unit (C1) is connected to the first series connection (SC U ) of the first node and the second series connection (SC L ), the first node of the first series connection and the second node of the second series connection are closest to the output terminal (OUT1) in terms of the number of nodes.

10. The method according to claim 9, characterized in that - the less the first capacitor unit (C1) of the one or more capacitor units (C1, C2) is charged below the corresponding third voltage level, the more power is allocated to the switch (S) directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) the more the portion of the DC voltage (Vin) decreases.

11. The method according to claim 9 or 10, characterized in that In order to reduce the amount allocated to the switch (S U1 ;S L1 ), the method comprising the steps of: - Control the switch (S U3 、S U2 、S U1 、S L1 、S L2 、S L3 ), so that in the one or more conversion phases, the capacitor unit (C1) of the one or more capacitor units is charged or discharged to below the corresponding third voltage level.

12. The method according to claim 11, characterized in that - the less the first capacitor unit (C1) of the one or more capacitor units (C1, C2) is charged below the corresponding third voltage level, the more power is allocated to the switch (S) directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) the more the portion of the DC voltage (Vin) decreases, or - the more the capacitor unit (C1) is discharged below the corresponding third voltage level, the more the switch (S) directly electrically connected to the output terminal (OUT1) is allocated U1 ;S L1 ) the more the portion of the DC voltage (Vin) decreases.

13. The method according to any one of the preceding claims, characterized in that In order to reduce the one or more switches (S) allocated to and directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ), the method comprising the steps of: - Control the switch (S U3 、S U2 、S U1 、S L1 、S L2 、S L3 ), so that a first capacitor unit (C1) of the one or more capacitor units (C1, C2) is charged to above the corresponding third voltage level, wherein the first capacitor unit (C1) is connected to the one or more switches (S) directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ) which is closer to the output terminal (OUT1) in terms of the number of nodes; and / or - Control the switch (S U3 、S U2 、S U1 、S L1 、S L2 、S L3 ), so that a second capacitor unit (C2) of the one or more capacitor units (C1, C2) is charged to below the corresponding third voltage level, wherein the second capacitor unit (C2) is connected to the one or more switches (S) directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ) of the other of the two terminals.

14. The method according to claim 13, characterized in that - the more the first capacitor unit (C1) is charged above the respective third voltage level, the more the one or more switches (S) assigned to and directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ) the more the portion of the DC voltage (Vin) is reduced; and / or - the less the second capacitor unit (C2) is charged below the corresponding third voltage level, the more the one or more switches (S) assigned to and directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ) the more the portion of the DC voltage (Vin) decreases.

15. The method according to claim 13 or 14, characterized in that In order to reduce the one or more switches (S) assigned to and directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ), the method comprising the steps of: - Control the switch (S U3 、S U2 、S U1 、S L1 、S L2 、S L3 ), so that in the one or more conversion phases, the first capacitor unit (C1) of the one or more capacitor units (C1, C2) is charged to above the corresponding third voltage level; and / or - Control the switch (S U3 、S U2 、S U1 、S L1 、S L2 、S L3 ), so that in the one or more conversion phases, the second capacitor unit (C2) of the one or more capacitor units (C1, C2) is charged or discharged to below the corresponding third voltage level.

16. The method according to claim 15, characterized in that - the more the first capacitor unit (C1) is charged above the respective third voltage level, the more the one or more switches (S) assigned to and directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ) the more the portion of the DC voltage (Vin) is reduced; and / or - the less the second capacitor unit (C2) is charged below the corresponding third voltage level, the more the one or more switches (S) assigned to and directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ) the more the portion of the DC voltage (Vin) decreases, or - the more the second capacitor unit (C2) is discharged below the third voltage level, the more the one or more switches (S) assigned to and directly electrically connected to the output terminal (OUT1) U1 ;S L1 ) switch (S) that is directly electrically connected U2 ;S L2 ) the more the portion of the DC voltage (Vin) decreases.

17. The method according to any one of the preceding claims, characterized in that The greater the number of nodes between the output terminal (OUT1) and the first node connected to a capacitor unit, the greater the corresponding third voltage level of the capacitor unit.

18. A control unit (2) for a converter (1), characterized in that The control unit (2) is adapted to carry out the method for controlling switches of the converter (1) according to any one of the preceding claims.

19. A converter (1), characterized in that - The converter comprises: - a first input terminal and a second input terminal (IN1, IN2) for receiving a DC voltage (Vin), - Output terminal (OUT1) for providing a first voltage level (V IN1 ) and a second voltage level (V IN2 ) changes between the output voltage (Vout), - Two or more switches as semiconductor switches (S U(N-1) 、S U1 ;S L1 、S L(N-1) ) of the first series connection and the second series connection (SC U , SC L ), - one or more capacitor units (C1), - a control unit (2) according to claim 18, configured to control the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ); - the first input terminal (IN1) is connected to the second input terminal (IN1) through the two or more switches (S U(N-1) 、S U1 ) of the first series connection (SC U ) is electrically connected to the output terminal (OUT1); - The second input terminal (IN2) is connected to the second input terminal (IN2) through the two or more switches (S L1 、S L(N-1) ) of the second series connection (SC L ) is electrically connected to the output terminal (OUT1); - Each of the one or more capacitor units (C1) connects the first series connection (SC U ) between the first node of the two switches connected in series with the second (SC L ) are electrically connected to each other, wherein the number of nodes between the first node and the output terminal (OUT1) and the number of nodes between the second node and the output terminal (OUT1) are equal to each other; - The control unit (2) is used to - Distributing the DC voltage (Vin) equally between the first series connection and the second series connection (SC) by U , SC L ) of the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ): Control the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ), so that each of the one or more capacitor units (C1) is charged to a corresponding third voltage level, - Compensate the switch (S U(N-1) 、S U1 、S L1 、S L(N-1) ) of different power losses: Control the switch (S U(N-1) 、S U1 ;S L1 、S L(N-1) ), so that - one or more of said one or more capacitor units (C1) are charged above said respective third voltage level, and / or - one or more of said one or more capacitor units (C1) are charged below said respective third voltage level, The DC voltage (Vin) is distributed unevenly to the switches (S U(N-1) 、S U1 、S L1 、S L(N-1) ).

20. The converter (1) according to claim 19, characterized in that - Each capacitor unit (C1) corresponds to one capacitor (C1) or two capacitors (C11, C12) electrically connected in series; - In the case where each capacitor unit (C1) corresponds to two capacitors (C11, C12) connected electrically in series, the converter comprises two capacitors (Ca, Cb) connected in series (SC), the two capacitors (Ca, Cb) electrically connecting the first input terminal (IN1) and the second input terminal (IN2) of the converter (1) to each other.

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