An in-memory computing method, device and electronic equipment for few-shot learning of images

Abstract

The application discloses an in-memory computing method and device for graph few-shot learning and electronic equipment, relates to the field of machine learning and artificial intelligence, and develops a memory-enhanced graph network model to realize a graph few-shot learning function and adopts an in-memory computing architecture for hardware implementation. The method comprises the following steps: initializing parameters of an encoder, and dividing a graph data set into a training set and a test set; randomly selecting a preset category and a preset number of support sets in the training set, inputting the support sets into a controller and the encoder to obtain first binary feature vectors; storing the first binary feature vectors and labels corresponding to the first binary feature vectors into an external memory unit; randomly selecting a preset category and a preset number of query sets in the training set, inputting the query sets into the controller and the encoder to obtain second binary feature vectors; and determining a predicted category of samples based on the first binary feature vectors and the second binary feature vectors, so that the category of samples can be quickly determined.

Description

Technical Field

[0001] This invention relates to the fields of machine learning and artificial intelligence, and in particular to an in-memory computation method, apparatus and electronic device for graph few-shot learning. Background Technology

[0002] With the development of machine learning and artificial intelligence, deep learning has become an extremely important part of both, and the arrival of the big data era has accelerated its development. However, in real-world open environments, data acquisition and labeling are both very time-consuming and labor-intensive, and neural networks need to improve their generalization ability with a limited number of samples.

[0003] Memory Augmented Neural Networks (MANNs) utilize external memory units to store task-related information, which can be retrieved when needed. This learning method effectively addresses the few-shot learning problem. In terms of hardware implementation, MANNs can employ a traditional digital central processing unit (CPU) combined with dynamic random access memory (DRAM). However, due to the von Neumann bottleneck, accessing large amounts of data leads to high latency and high power consumption. Although external memory units based on content-addressable memory (CAM) enable high-speed parallel retrieval, MANNs still face challenges in both algorithm and hardware implementation.

[0004] Algorithmically, memory-augmented networks constructed using traditional deep learning algorithms (such as convolutional neural networks) can successfully process data in Euclidean space, such as images and text. However, for graph data located in non-Euclidean space, the performance of memory-augmented networks built using traditional convolutional neural networks is poor. This is because graph data is irregular, and the nodes in the graph are interconnected. Graph neural networks can effectively extract features from graph data, and memory-augmented networks constructed from them can achieve few-sample learning of graphs. However, these memory-augmented networks face the problem of time-consuming and energy-intensive parameter optimization.

[0005] In terms of hardware implementation, although the CAM-based external memory unit can reduce latency and power consumption during retrieval, the MANN controller is still implemented using a GPU, resulting in significant power consumption during feature extraction. Furthermore, because the controller and external memory employ different device architectures and peripheral circuit designs, it is difficult to integrate them onto the same chip, which limits the scalability of the MANN network. Summary of the Invention

[0006] The purpose of this invention is to provide an in-memory computation method, apparatus, and electronic device for graph few-shot learning. By developing a memory-enhanced graph network and implementing it entirely in hardware using an array of in-memory computing devices, the invention solves the algorithmic and hardware implementation problems faced by graph few-shot learning.

[0007] In a first aspect, the present invention provides an in-memory computation method for graph few-shot learning, applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units, the method comprising:

[0008] The encoder parameters are initialized, and the graph dataset is divided into a training set and a test set.

[0009] A preset category and a preset number of support sets are randomly selected from the training set, and the support sets are input to the controller and the encoder to obtain a first binary feature vector;

[0010] The first binary feature vector and the label corresponding to the first binary feature vector are stored in the external memory unit;

[0011] A preset category and a preset number of query sets are randomly selected from the training set, and the query sets are input to the controller and the encoder to obtain a second binary feature vector;

[0012] The predicted category of the sample is determined based on the first binary feature vector and the second binary feature vector.

[0013] With the above technical solution, the in-memory computation method for graph few-shot learning provided by the present invention is applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units. It can initialize the encoder parameters, divide the graph dataset into training and test sets, randomly select a preset category and a preset number of support sets from the training set, input the support sets to the controller and encoder to obtain a first binary feature vector, store the first binary feature vector and its corresponding label in the external memory unit, randomly select the preset category and the preset number of query sets from the training set, input the query sets to the controller and encoder to obtain a second binary feature vector, and determine the predicted category of the sample based on the first and second binary feature vectors. This method can quickly determine the sample category, reduce time and energy consumption, and improve the reliability and stability of the memory-enhanced graph network.

[0014] In one possible implementation, determining the predicted category of a sample based on the first binary feature vector and the second binary feature vector includes:

[0015] Determine the feature similarity between the first binary feature vector and the second binary feature vector;

[0016] The predicted category of a sample is determined based on the feature similarity.

[0017] In one possible implementation, after determining the predicted category of a sample based on the first binary feature vector and the second binary feature vector, the method further includes:

[0018] During the training of the memory augmentation graph network, the prediction error value is determined based on the prediction category and the label;

[0019] The encoder parameters are updated based on the prediction error value.

[0020] In one possible implementation, the step of randomly selecting a preset category and a preset number of support sets from the training set, and inputting the support sets to the controller and the encoder to obtain a first binary feature vector includes:

[0021] A preset category and a preset number of support sets are randomly selected from the training set, and the support sets are input to the controller. The echo state graph network of the controller is used to extract features from the graph dataset to obtain the node features of the graph dataset.

[0022] The node features are input into the encoder, and the binary neural network of the encoder converts the node features into the first binary feature vector.

[0023] In one possible implementation, determining the feature similarity between the first binary feature vector and the second binary feature vector includes:

[0024] During the retrieval process, the dot product formula is used to calculate the feature similarity between the first binary feature vector and the second binary feature vector.

[0025] In one possible implementation, the categories of the training set and the test set do not overlap.

[0026] In a second aspect, the present invention also provides an in-memory computing device for graph few-shot learning, applied in a memory-enhanced graph network including interconnected controllers, encoders, and external memory units, the device comprising:

[0027] An initialization module is used to initialize the parameters of the encoder and divide the graph dataset into a training set and a test set.

[0028] The first acquisition module is used to randomly select a preset category and a preset number of support sets in the training set, input the support sets to the controller and the encoder, and obtain a first binary feature vector.

[0029] The first storage module is used to store the first binary feature vector and the label corresponding to the first binary feature vector into the external memory unit;

[0030] The second acquisition module is used to randomly select a preset category and a preset number of query sets in the training set, and input the query sets into the controller and the encoder to obtain a second binary feature vector.

[0031] The first determining module is used to determine the predicted category of a sample based on the first binary feature vector and the second binary feature vector.

[0032] In one possible implementation, the device further includes:

[0033] The third acquisition module is used to randomly select a preset category and a preset number of support sets in the test set, input the support sets to the controller and the encoder, and obtain the first binary feature vector.

[0034] The second storage module is used to store the first binary feature vector and the tag corresponding to the first binary feature vector into the external memory unit;

[0035] The fourth obtaining module is used to randomly select one of the preset categories and the preset number of query sets in the test set, and input the query sets to the controller and the encoder to obtain a second binary feature vector;

[0036] The second determining module is used to determine the predicted category of the sample based on the first binary feature vector and the second binary feature vector.

[0037] In one possible implementation, the first determining module includes:

[0038] The first determining submodule is used to determine the feature similarity between the first binary feature vector and the second binary feature vector;

[0039] The second determination submodule is used to determine the predicted category of the sample based on the feature similarity.

[0040] In one possible implementation, the device further includes:

[0041] The third determining module is used to determine the prediction error value based on the prediction category and the label during the training of the memory augmentation graph network.

[0042] An update module is used to update the encoder parameters based on the prediction error value.

[0043] In one possible implementation, the first obtaining module includes:

[0044] The submodule is used to randomly select a preset category and a preset number of support sets in the training set, input the support sets to the controller, and extract features from the graph dataset through the echo state graph network of the controller to obtain the node features of the graph dataset.

[0045] The conversion submodule is used to input the node features into the encoder and convert the node features into the first binary feature vector through the binary neural network of the encoder.

[0046] In one possible implementation, the first determining submodule includes:

[0047] The calculation unit is used to calculate the feature similarity between the first binary feature vector and the second binary feature vector using the dot product formula during retrieval.

[0048] In one possible implementation, the categories of the training set and the test set do not overlap.

[0049] The beneficial effects of the in-memory computing device for graph few-shot learning provided in the second aspect are the same as those of the in-memory computing method for graph few-shot learning described in the first aspect or any possible implementation of the first aspect, and will not be repeated here.

[0050] Thirdly, the present invention also provides an electronic device comprising: one or more processors; and one or more machine-readable media having instructions stored thereon, which, when executed by the one or more processors, cause the device to perform in-memory computing of graph few-shot learning as described in any possible implementation of the second aspect.

[0051] The beneficial effects of the electronic device provided in the third aspect are the same as those of the in-memory computing device for graph few-sample learning described in the second aspect or any possible implementation of the second aspect, and will not be elaborated here. Attached Figure Description

[0052] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0053] Figure 1 This illustration shows a schematic diagram of the structure of a memory-enhanced graph network provided in an embodiment of this application;

[0054] Figure 2 The diagram illustrates a flowchart of an in-memory computation method for graph few-shot learning provided in an embodiment of this application.

[0055] Figure 3 This illustration shows a flowchart of another in-memory computation method for graph few-shot learning provided in an embodiment of this application;

[0056] Figure 4 This illustration shows an in-memory computing hardware diagram for implementing graph few-shot learning according to an embodiment of this application;

[0057] Figure 5 This paper shows a structural flowchart of an in-memory computing device for graph few-shot learning provided in an embodiment of this application;

[0058] Figure 6 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present invention;

[0059] Figure 7 This is a schematic diagram of the chip structure provided in an embodiment of the present invention. Detailed Implementation

[0060] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0061] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0062] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0063] Figure 1 This illustration shows a schematic diagram of the structure of a memory-enhanced graph network provided in an embodiment of this application, as shown below. Figure 1 As shown, the memory-enhanced graph network includes a controller 101, an encoder 102, and an external memory unit 103 that are interconnected.

[0064] Figure 2 This illustration shows a flowchart of an in-memory computation method for graph few-shot learning provided in an embodiment of this application, applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units, such as... Figure 2 As shown, the in-memory computation method for small sample learning in this graph includes:

[0065] Step 201: Initialize the parameters of the encoder and divide the graph dataset into a training set and a test set.

[0066] In this application, the categories of the training set and the test set do not overlap.

[0067] Step 202: Randomly select a preset category and a preset number of support sets in the training set, and input the support sets into the controller and the encoder to obtain the first binary feature vector.

[0068] In this application, a preset category and a preset number of support sets can be randomly selected from the training set, and the support sets can be input to the controller. The controller's echo state graph network can be used to extract features from the graph dataset to obtain the node features of the graph dataset. Further, the node features are input to the encoder, and the encoder's binary neural network can be used to convert the node features into the first binary feature vector.

[0069] Step 203: Store the first binary feature vector and the label corresponding to the first binary feature vector in the external memory unit.

[0070] Step 204: Randomly select one of the preset categories and the preset number of query sets in the training set, and input the query sets into the controller and the encoder to obtain the second binary feature vector.

[0071] Step 205: Determine the predicted category of the sample based on the first binary feature vector and the second binary feature vector.

[0072] It should be noted that, in this application, the devices used for in-memory computing are not limited to random access memory (RRAM) devices, but also include non-volatile devices such as flash memory, ferroelectric field-effect transistors (FeFET), and non-volatile magnetic random access memory (MRAM).

[0073] The in-memory computation method for few-shot learning of graphs provided in this invention is applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units. It initializes the encoder parameters, divides the graph dataset into training and test sets, randomly selects a preset category and a preset number of support sets from the training set, and inputs the support sets to the controller and encoder to obtain a first binary feature vector. The first binary feature vector and its corresponding label are stored in the external memory unit. A preset category and a preset number of query sets are randomly selected from the training set, and the query sets are input to the controller and encoder to obtain a second binary feature vector. Based on the first and second binary feature vectors, the predicted category of a sample is determined. This method can quickly determine the sample category, reduce time and energy consumption, and improve the reliability and stability of the memory-enhanced graph network.

[0074] Optional, Figure 3 This illustration shows a flowchart of another in-memory computation method for graph few-shot learning provided in an embodiment of this application, applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units. See [link to relevant documentation]. Figure 3 The in-memory computation method for small sample learning of this graph includes:

[0075] Step 301: Initialize the parameters of the encoder and divide the graph dataset into a training set and a test set.

[0076] In this application, the parameters of the encoder can be initialized, and the graph dataset can be divided into a training set and a test set, with no overlap between the categories of the training set and the test set.

[0077] Step 302: Randomly select a preset category and a preset number of support sets in the training set, and input the support sets into the controller and the encoder to obtain the first binary feature vector.

[0078] In this application, a preset category and a preset number of support sets can be randomly selected from the training set, and the support sets can be input to the controller. The controller's echo state graph network can be used to extract features from the graph dataset to obtain the node features of the graph dataset. The node features can be input to the encoder, and the encoder's binary neural network can be used to convert the node features into the first binary feature vector.

[0079] Optionally, the controller can employ an echo state graph network, utilizing a random matrix to extract node features from the graph. The node state iteration process is shown in formula (1), where the features of the i-th node at time step t are... Represented as:

[0080]

[0081]

[0082] in, Let u represent the node characteristics of the i-th node at time step (t-1). i The input matrix W represents the input information of the i-th node. in With node state X i Multiply to get u i N(i) represents the set of neighboring nodes of the i-th node, and the input matrix W in and hidden matrix W h It is a random matrix, and α represents the leakage rate.

[0083] Optionally, the encoder can employ a single-layer binary neural network to convert the node features output by the echo state map network into binary feature vectors and store them in an external memory unit. The weight binarization function and activation function used during the forward propagation of the encoder are sign functions, as shown in formula (3):

[0084]

[0085] Step 303: Store the first binary feature vector and the label corresponding to the first binary feature vector into the external memory unit.

[0086] In this application, the external memory unit can store the first binary feature vector of a node and its corresponding label.

[0087] In this application, during training, a Support Set can be selected from the training set at any time. The Support Set consists of m categories, with n samples randomly selected from each category. The samples in the Support Set can be used by the controller and encoder to obtain a second binary feature vector, and this second binary feature vector and its corresponding label are stored in an external memory unit.

[0088] Step 304: Randomly select a preset category and a preset number of query sets from the training set, and input the query sets into the controller and the encoder to obtain a second binary feature vector.

[0089] Furthermore, a query set can be randomly selected from the training set, where the query set and the support set have the same categories. From the remaining samples in these m categories, n samples are selected, and the samples in the query set are used to obtain a second binary feature vector through the controller and encoder.

[0090] Step 305: Determine the predicted category of the sample based on the first binary feature vector and the second binary feature vector.

[0091] In this application, the feature similarity between the first binary feature vector and the second binary feature vector can be determined; further, the predicted category of the sample is determined based on the feature similarity.

[0092] Specifically, during the retrieval process, the dot product formula can be used to calculate the feature similarity between the first binary feature vector and the second binary feature vector, as shown in formula (4):

[0093] Dot product(A, B) = A·B.

[0094] Step 306: During the training of the memory augmentation graph network, the prediction error value is determined based on the prediction category and the label.

[0095] In this application, the prediction error value can be calculated based on the predicted category and the true category of the query set.

[0096] Step 307: Update the encoder parameters based on the prediction error value.

[0097] In this application, the parameters in the encoder can be adjusted based on the prediction error value to improve the learning ability.

[0098] In this application, the following steps may be performed during reasoning:

[0099] Step S1: Randomly select a preset category and a preset number of support sets in the test set, and input the support sets into the controller and the encoder to obtain the first binary feature vector.

[0100] Step S2: Store the first binary feature vector and the label corresponding to the first binary feature vector into the external memory unit.

[0101] Step S3: Randomly select one of the preset categories and the preset number of query sets in the test set, and input the query sets into the controller and the encoder to obtain the second binary feature vector.

[0102] Step S4: Determine the predicted category of the sample based on the first binary feature vector and the second binary feature vector.

[0103] Figure 4 This illustration shows an in-memory computing hardware diagram for implementing graph few-shot learning according to an embodiment of this application. Figure 4 As shown, the controller includes a random RRAM (Random Access Memory) array, the encoder includes a programmable RRAM array, and the external memory unit includes a programmable RRAM array. The external memory unit can store the encoder input and retrieve the encoder's contents. The randomness of the resistance change of the main transformer's storage devices during the set acquisition (SET) process is used to realize the random matrix (input matrix W) in the controller. in and hidden matrix W h The binary weights and feature vectors of the external memory cell in the encoder are realized by utilizing the binary state of the resistive random access memory device. By utilizing the randomness and binary resistive state characteristics of the memristor device, a random matrix and a binary matrix are realized on the same memristor array. Since the memristor device has the ability to be erased and rewritten, the hardware implementation of the memory-enhanced graph network has the characteristic of being reconfigurable.

[0104] The in-memory computation method for few-shot learning of graphs provided in this invention is applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units. It initializes the encoder parameters, divides the graph dataset into training and test sets, randomly selects a preset category and a preset number of support sets from the training set, and inputs the support sets to the controller and encoder to obtain a first binary feature vector. The first binary feature vector and its corresponding label are stored in the external memory unit. A preset category and a preset number of query sets are randomly selected from the training set, and the query sets are input to the controller and encoder to obtain a second binary feature vector. Based on the first and second binary feature vectors, the predicted category of a sample is determined. This method can quickly determine the sample category, reduce time and energy consumption, and improve the reliability and stability of the memory-enhanced graph network.

[0105] Figure 5 This illustration shows a schematic diagram of an in-memory computing device for graph few-shot learning, provided in an embodiment of this application. It is applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units, such as... Figure 5 As shown, the in-memory computing device 400 for few-sample learning includes:

[0106] Initialization module 401 is used to initialize the parameters of the encoder and divide the graph dataset into training set and test set;

[0107] The first acquisition module 402 is used to randomly select a preset category and a preset number of support sets in the training set, input the support sets to the controller and the encoder, and obtain a first binary feature vector.

[0108] Storage module 403 is used to store the first binary feature vector and the tag corresponding to the first binary feature vector into the external memory unit;

[0109] The second obtaining module 404 is used to randomly select a preset category and a preset number of query sets in the training set, and input the query sets to the controller and the encoder to obtain a second binary feature vector;

[0110] The first determining module 405 is used to determine the predicted category of the sample based on the first binary feature vector and the second binary feature vector.

[0111] In one possible implementation, the device further includes:

[0112] The third acquisition module is used to randomly select a preset category and a preset number of support sets in the test set, input the support sets to the controller and the encoder, and obtain the first binary feature vector.

[0113] The second storage module is used to store the first binary feature vector and the tag corresponding to the first binary feature vector into the external memory unit;

[0114] The fourth obtaining module is used to randomly select one of the preset categories and the preset number of query sets in the test set, and input the query sets to the controller and the encoder to obtain a second binary feature vector;

[0115] The second determining module is used to determine the predicted category of the sample based on the first binary feature vector and the second binary feature vector.

[0116] In one possible implementation, the first determining module includes:

[0117] The first determining submodule is used to determine the feature similarity between the first binary feature vector and the second binary feature vector;

[0118] The second determination submodule is used to determine the predicted category of the sample based on the feature similarity.

[0119] In one possible implementation, the device further includes:

[0120] The third determining module is used to determine the prediction error value based on the prediction category and the label during the training of the memory augmentation graph network.

[0121] An update module is used to update the encoder parameters based on the prediction error value.

[0122] In one possible implementation, the first obtaining module includes:

[0123] The submodule is used to randomly select a preset category and a preset number of support sets in the training set, input the support sets to the controller, and extract features from the graph dataset through the echo state graph network of the controller to obtain the node features of the graph dataset.

[0124] The conversion submodule is used to input the node features into the encoder and convert the node features into the first binary feature vector through the binary neural network of the encoder.

[0125] In one possible implementation, the first determining submodule includes:

[0126] The calculation unit is used to calculate the feature similarity between the first binary feature vector and the second binary feature vector using the dot product formula during retrieval.

[0127] In one possible implementation, the categories of the training set and the test set do not overlap.

[0128] The in-memory computing device for few-shot learning of graphs provided in this invention is applied to a memory-enhanced graph network including an interconnected controller, encoder, and external memory unit. It can initialize the encoder parameters, divide the graph dataset into a training set and a test set, randomly select a preset category and a preset number of support sets from the training set, input the support sets to the controller and encoder to obtain a first binary feature vector, store the first binary feature vector and its corresponding label in the external memory unit, randomly select the preset category and the preset number of query sets from the training set, input the query sets to the controller and encoder to obtain a second binary feature vector, and determine the predicted category of the sample based on the first and second binary feature vectors. This allows for rapid determination of the sample category, reduces time and energy consumption, and improves the reliability and stability of the memory-enhanced graph network.

[0129] This invention provides an in-memory computing device for few-shot learning of graphs, applicable to a system including a controller and at least one detection circuit electrically connected to the controller, such as... Figures 1 to 4 The in-memory computation method for small sample learning of any of the graphs shown will not be elaborated here to avoid repetition.

[0130] The electronic device in this embodiment of the invention can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, a mobile electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc., while a non-mobile electronic device can be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This embodiment of the invention does not impose specific limitations.

[0131] The electronic device in this embodiment of the invention can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this embodiment of the invention does not impose specific limitations.

[0132] Figure 6 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention is shown. Figure 6 As shown, the electronic device 500 includes a processor 510.

[0133] like Figure 6 As shown, the processor 510 described above can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention.

[0134] like Figure 6 As shown, the electronic device 500 may further include a communication line 540. The communication line 540 may include a path for transmitting information between the components.

[0135] Optional, such as Figure 6 As shown, the above-described electronic device may further include a communication interface 520. There may be one or more communication interfaces 520. The communication interface 520 may use any transceiver-like device for communicating with other devices or communication networks.

[0136] Optional, such as Figure 6 As shown, the electronic device may further include a memory 530. The memory 530 stores computer execution instructions for implementing the present invention, and its execution is controlled by a processor. The processor executes the computer execution instructions stored in the memory to implement the method provided in the embodiments of the present invention.

[0137] like Figure 6As shown, memory 530 can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 530 can exist independently and be connected to processor 510 via communication line 540. Memory 530 can also be integrated with processor 510.

[0138] Optionally, the computer execution instructions in the embodiments of the present invention may also be referred to as application code, and the embodiments of the present invention do not specifically limit this.

[0139] In a specific implementation, as one example, such as Figure 6 As shown, processor 510 may include one or more CPUs, such as Figure 6 CPU0 and CPU1 in the CPU.

[0140] In a specific implementation, as one example, such as Figure 6 As shown, the terminal device may include multiple processors, such as Figure 6 The first processor 5101 and the second processor 5102 are included. Each of these processors can be a single-core processor or a multi-core processor.

[0141] Figure 7 This is a schematic diagram of the chip structure provided in an embodiment of the present invention. Figure 7 As shown, the chip 600 includes one or more processors 510.

[0142] Optional, such as Figure 7 As shown, the chip also includes a communication interface 520 and a memory 530. The memory 530 may include read-only memory and random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (NVRAM).

[0143] In some implementations, such as Figure 7 As shown, memory 530 stores the following elements: execution modules or data structures, or subsets thereof, or extended sets thereof.

[0144] In embodiments of the present invention, such as Figure 7 As shown, the corresponding operation is executed by calling the operation instructions stored in the memory (which can be stored in the operating system).

[0145] like Figure 7 As shown, the processor 510 controls the processing operations of any one of the terminal devices. The processor 510 can also be called a central processing unit (CPU).

[0146] like Figure 7 As shown, memory 530 may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of memory 530 may also include NVRAM. For example, in an application, memory, communication interfaces, and memory are coupled together via a bus system, which may include, in addition to a data bus, a power bus, a control bus, and a status signal bus, etc. However, for clarity, in... Figure 7 The general labeled all buses as Bus System 640.

[0147] like Figure 7As shown, the methods disclosed in the above embodiments of the present invention can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0148] On the one hand, a computer-readable storage medium is provided, which stores instructions that, when executed, implement the functions performed by the terminal device in the above embodiments.

[0149] On the one hand, a chip is provided that is used in a terminal device. The chip includes at least one processor and a communication interface. The communication interface and at least one processor are coupled together. The processor is used to run instructions to implement the functions performed by the in-memory computing method learned by small sample learning in the above embodiments.

[0150] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0151] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0152] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. An in-memory computing method for few-shot learning of images, the method comprising: The method is applied to a memory-enhanced graph network comprising a controller, an encoder and an external memory unit connected with each other, and comprises the following steps: initializing parameters of the encoder, and dividing a graph data set into a training set and a test set; randomly selecting a preset category and a preset number of support sets in the training set, inputting the support sets into the controller and the encoder, and obtaining a first binary feature vector; storing the first binary feature vector and a label corresponding to the first binary feature vector into the external memory unit; randomly selecting a preset category and a preset number of query sets in the training set, inputting the query sets into the controller and the encoder, and obtaining a second binary feature vector, which comprises the following steps: Randomly select a preset category and a preset number of the support set in the training set, input the support set into the controller, use a random matrix to perform feature extraction on the graph data set by an echo state diagram network of the controller, obtain node features of the graph data set, and the feature of the i th node at the t th time step in the node state iteration process is represented as: ； ； wherein, represents the node feature of the i-th node at the (t-1)-th time step, represents the input information of the i-th node, the input matrix is multiplied with the node state to obtain ; represents the neighbor node set of the i-th node, the input matrix and the hidden matrix is a random matrix, represents the leakage rate; inputting the node features into the encoder, converting the node features output by the echo state graph network into the binary feature vector through a binary neural network of the encoder, and storing the binary feature vector into the external memory unit; determining a predicted category of a sample based on the first binary feature vector and the second binary feature vector.

2. The method of claim 1, wherein, After the graph data set is divided into the training set and the test set, the method further comprises the following steps: randomly selecting a preset category and a preset number of support sets in the test set, inputting the support sets into the controller and the encoder, and obtaining the first binary feature vector; storing the first binary feature vector and a label corresponding to the first binary feature vector into the external memory unit; randomly selecting a preset category and a preset number of query sets in the test set, inputting the query sets into the controller and the encoder, and obtaining a second binary feature vector; determining a predicted category of a sample based on the first binary feature vector and the second binary feature vector.

3. The method according to claim 1 or 2, characterized in that, The determination of the predicted category of the sample based on the first binary feature vector and the second binary feature vector comprises the following steps: determining a feature similarity of the first binary feature vector and the second binary feature vector; determining the predicted category of the sample based on the feature similarity.

4. The method of claim 1, wherein, After the determination of the predicted category of the sample based on the first binary feature vector and the second binary feature vector, the method further comprises the following steps: in the process of training the memory-enhanced graph network, determining a prediction error value according to the predicted category and the label; updating the parameters of the encoder based on the prediction error value.

5. The method of claim 3, wherein, The determination of the feature similarity of the first binary feature vector and the second binary feature vector comprises the following steps: in the retrieval, the dot product formula is used to calculate the feature similarity of the first binary feature vector and the second binary feature vector.

6. The method of claim 1, wherein, The categories of the training set and the test set are not crossed.

7. An in-memory computing device for graph few-sample learning, characterized in that, The device is applied to the in-memory computing method for graph few-shot learning according to any one of claims 1-6, and comprises the following modules: an initialization module, configured to initialize parameters of the encoder, and divide a graph data set into a training set and a test set; a first obtaining module, configured to randomly select a preset category and a preset number of support sets in the training set, input the support sets into the controller and the encoder, and obtain a first binary feature vector; a first storage module, configured to store the first binary feature vector and a label corresponding to the first binary feature vector into the external memory unit; a second obtaining module, configured to randomly select a preset category and a preset number of query sets in the training set, input the query sets into the controller and the encoder, and obtain a second binary feature vector; a first determining module, configured to determine a predicted category of a sample based on the first binary feature vector and the second binary feature vector.

8. The apparatus of claim 7, wherein, The first determining module includes: a first determining submodule, configured to determine a feature similarity of the first binary feature vector and the second binary feature vector; a second determining submodule, configured to determine a predicted category of a sample based on the feature similarity; The device further includes: a third determining module, configured to determine a prediction error value according to the predicted category and the label in the process of training the memory-enhanced graph network; an updating module, configured to update parameters of the encoder based on the prediction error value.

9. An electronic device, comprising: include: one or more processors; and one or more machine-readable media having stored thereon instructions that, when executed by the one or more processors, cause the electronic device to perform the in-memory computing method for graph few-shot learning of any one of claims 1-6.

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