Method for improving deep trench isolation critical dimension
By creating blank areas or disconnecting connections at the deep trench intersections, the problem of excessively large critical dimensions in deep trench isolation was solved, resulting in improved wafer yield and image sensor sensitivity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2022-06-30
- Publication Date
- 2026-05-22
AI Technical Summary
In existing technologies, the critical dimensions of deep trench isolation are too large, making it difficult to control the etching depth, which affects wafer yield and image sensor sensitivity, especially in ultra-thin stacked products where it is difficult to correct through OPC.
A blank area or disconnection is formed at the intersection of deep trenches. By designing the masking layer layout, the critical size of the intersection area is reduced, and a complete deep trench is formed using an etching process.
By reducing the critical dimensions of the cross-section, excessive etching is avoided, thereby improving the sensitivity of the image sensor, enhancing image quality, and increasing wafer yield.
Smart Images
Figure CN115036260B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for improving the critical dimensions of deep trench isolation. Background Technology
[0002] like Figure 1 As shown, for back-illuminated CMOS image sensors (BSI), deep trench isolation (DTI) isolates pixel areas by forming a gate mesh layer to prevent electronic crosstalk in the pixel areas. The morphology (CD & depth) of DTI not only affects the sensitivity of the image sensor but also the wafer yield. Ultra-thin stacking (UTS) products are particularly sensitive to the morphology of DTI, possessing a trench depth of 2μm, which is more challenging than the conventional BSI process (DTI trench depth of 0.4μm).
[0003] Because deep trench etching (DTI) processes are time-consuming and deep, and the masking layer undergoes morphological changes due to the effects of etching ions, the critical dimension (CD) gradually increases over time. Therefore, the size of the DTI critical dimension (CD) directly affects the trench depth and overall morphology. In current UTS mass production, a larger critical dimension in the deep trench isolation crossover region makes it more difficult to correct using OPC, leading to excessive trench depth reaching the silicon substrate and causing WP fail. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a method for improving the critical dimensions of deep trench isolation, which is used to improve the problem of excessively large critical dimensions at the intersection area of existing deep trenches forming a grid structure.
[0005] To achieve the above and other related objectives, the present invention provides a method for improving the critical dimensions of deep trench isolation, the method comprising:
[0006] A masking layer layout is provided, the masking layer layout including at least one first deep trench and at least one second deep trench, the first deep trench extending along a first direction and the second deep trench extending along a second direction, wherein the first deep trench and the second deep trench are intersected to form an intersection area;
[0007] A blank area is formed at the intersection;
[0008] The wafer is etched using the masking layer pattern to form the first deep trench and the second deep trench within the wafer.
[0009] Optionally, the method of forming the blank area in the intersection area includes: disconnecting the first deep trench and / or the second deep trench at the intersection area.
[0010] Optionally, there are multiple first deep trenches and multiple second deep trenches, and the multiple first deep trenches and multiple second deep trenches are arranged intersectingly to form a grid structure.
[0011] Optionally, when the first deep trench is disconnected at the intersection area, the blank area is a first isolation area formed between the disconnection point of the first deep trench and the second deep trench, and the width of the first isolation area in the first direction is 50nm to 200nm.
[0012] Optionally, before performing the etching process, a mask layer is formed at the first interval region, and the thickness of the mask layer ranges from [value missing]. .
[0013] Optionally, when the second deep trench is disconnected at the intersection area, the blank area is a second gap area formed between the disconnection point of the second deep trench and the first deep trench, and the width of the second gap area in the second direction is 50nm to 200nm.
[0014] Optionally, before performing the etching process, the mask layer is formed at the second gap region, and the thickness of the mask layer ranges from [value missing]. .
[0015] Optionally, when both the first deep trench and the second deep trench are disconnected at the intersection area, the blank area is the disconnection area formed by the first deep trench and the second deep trench at the intersection area.
[0016] Optionally, the width of the break zone in the first direction and the width in the second direction are both within the range of 90nm to 200nm.
[0017] Optionally, before performing the etching process, a mask layer is formed at the break area, and the thickness of the mask layer ranges from [value missing]. .
[0018] As described above, the method of improving the critical dimension of deep trench isolation according to the present invention is such that the deep trenches forming the grid structure are not fully connected at the intersection area during layout design, but are fully opened during actual etching. By means of the above method, the critical dimension (CD) of the deep trenches at the intersection area can be reduced, thereby avoiding excessive etching of the deep trenches, thereby improving the sensitivity of the image sensor and improving the image quality. Attached Figure Description
[0019] Figure 1 The diagram shows a schematic of an existing masking layer layout with deep trenches.
[0020] Figure 2 The flowchart shown is a method for improving the critical dimensions of deep trenches provided by the present invention.
[0021] Figure 3 The diagram shown is a schematic representation of the masking layer with deep trenches according to the present invention.
[0022] Figure 4 The diagram shown is a schematic layout of the masking layer of the first type of grid structure of the present invention.
[0023] Figure 5 The diagram shown is a schematic diagram of the masking layer layout of the second type of grid structure of the present invention.
[0024] Figure 6 The diagram shown is a schematic diagram of the masking layer layout for the third type of grid structure of the present invention.
[0025] Component designation explanation
[0026] 10. Covert Layer Map
[0027] 11 First deep trench
[0028] 12 Second deep trench
[0029] 21 Intersection
[0030] 22 blank areas
[0031] 3l First Interval Zone
[0032] 32 Second Interval Zone
[0033] 33 Disconnection Zone Detailed Implementation
[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0035] Please see Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0036] This embodiment provides a method for improving the critical dimensions of deep trenches, the method comprising:
[0037] A masking layer layout 10 is provided, the masking layer layout 10 including at least one first deep trench 11 and at least one second deep trench 12, the first deep trench 11 extending along a first direction and the second deep trench 12 extending along a second direction, wherein the first deep trench 11 and the second deep trench 12 are intersected to form an intersection area 21.
[0038] A blank area 22 is formed at the intersection area 21;
[0039] The wafer is etched using the masking layer pattern to form the first deep trench 11 and the second deep trench 12 within the wafer.
[0040] like Figure 3 As shown, in this embodiment, the first direction and the second direction are perpendicular to each other, and the first direction is the direction represented by coordinate X, and the second direction is the direction represented by coordinate Y.
[0041] Specifically, the method for forming the blank area 22 in the intersection area 21 includes: disconnecting the first deep trench 11 and / or the second deep trench 12 at the intersection area 21.
[0042] Specifically, there are multiple first deep trenches 11 and multiple second deep trenches 12, and the multiple first deep trenches 11 and multiple second deep trenches 12 are arranged intersectingly to form a grid structure.
[0043] like Figure 4 As shown, in this embodiment, the grid structure formed by the first deep trench 11 and the second deep trench 12 is used to isolate the pixel area of the image sensor and prevent electronic crosstalk from occurring in the pixel area.
[0044] As an example, when the first deep trench 11 is disconnected at the intersection area 21, the blank area 22 is a first gap area 31 formed between the disconnection point of the first deep trench 11 and the second deep trench 12, and the width of the first gap area 31 in the first direction is 50nm to 200nm.
[0045] Specifically, before the etching process, a mask layer is formed at the first interval region 31, and the thickness of the mask layer ranges from [value missing]. .
[0046] like Figure 4 As shown, in this embodiment, although the mask layer is formed at the first spacing region 31, the etching material beneath it needs to be etched in the subsequent etching process to form the complete first deep trench 11 within the wafer. Therefore, the thickness of the mask layer is limited. Optionally, in this embodiment, the thickness of the mask layer is... The mask layer is made of photoresist.
[0047] As another example, when the second deep trench 12 is disconnected at the intersection area 21, the blank area 22 is a second gap area 32 formed between the disconnection point of the second deep trench 12 and the first deep trench 11, and the width of the second gap area 32 in the second direction is 50nm to 200nm.
[0048] Specifically, before the etching process, a mask layer is formed at the second interval region 32, and the thickness of the mask layer ranges from [value missing]. .
[0049] like Figure 5 As shown, in this embodiment, although the mask layer is formed at the second spacing region 32, the etching material beneath it needs to be etched in the subsequent etching process to form the complete second deep trench 12 within the wafer. Therefore, the thickness of the mask layer is limited. Optionally, in this embodiment, the thickness of the mask layer is... The mask layer is made of photoresist.
[0050] As a third example, when the first deep trench 11 and the second deep trench 12 are both disconnected at the intersection area 21, the blank area 22 is the disconnection area 33 formed by the first deep trench 11 and the second deep trench 12 at the intersection area 21.
[0051] Specifically, the width of the disconnection region 33 ranges from 90nm to 200nm in both the first direction and the second direction. In this embodiment, the width of the disconnection region 33 (the width in the first direction and the width in the second direction) can be determined based on the depth of the first deep trench 11 and the second deep trench 12 to be formed.
[0052] Specifically, before the etching process, a mask layer is formed at the break region 33, and the thickness of the mask layer ranges from [value missing]. .
[0053] like Figure 6 As shown, in this embodiment, the thickness of the mask layer needs to ensure that the break region 33 is fully opened in the subsequent etching process, that is, the etching material located below the mask layer can be etched to form the complete first deep trench 11 and second deep trench 12 within the wafer. Optionally, the thickness of the mask layer in this embodiment is... The mask layer is made of photoresist.
[0054] In this embodiment, by forming a blank area 22 (first interval area 31, second interval area 32 or disconnect area 33) at the intersection area 21, the critical dimension width of the first deep trench 11 and the second deep trench 12 formed at the intersection area 21 is reduced, thereby avoiding excessive etching of the deep trenches at the intersection area, and thus improving the overall WP performance.
[0055] In summary, the method for improving the critical dimension of deep trench isolation in this invention involves incomplete connection of the deep trenches forming the grid structure at the intersection area during layout design, but full opening during actual etching. This method reduces the critical dimension (CD) of the deep trenches at the intersection area, thereby preventing excessive trench etching and improving the sensitivity of the image sensor and image quality. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0056] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for improving critical dimensions of deep trench isolation, characterized in that, The method includes: A masking layer layout is provided, the masking layer layout including at least one first deep trench and at least one second deep trench, the first deep trench extending along a first direction and the second deep trench extending along a second direction, wherein the first deep trench and the second deep trench are intersected to form an intersection area; A blank area is formed at the intersection area, and the blank area is a first interval area formed between the break point of the first deep trench and the second deep trench, or a second interval area formed between the break point of the second deep trench and the first deep trench, or a break area formed at the intersection area when both the first deep trench and the second deep trench are disconnected at the intersection area. The width of the first interval region in the first direction is 50nm to 200nm; The width of the second gap region in the second direction is 50nm to 200nm; The width of the disconnection zone in the first direction and the width in the second direction both range from 90 nm to 200 nm. A mask layer is formed at the first interval region, and the thickness of the mask layer ranges from 5000 Å to 9000 Å; the mask layer is formed at the second interval region, and the thickness of the mask layer ranges from 5000 Å to 9000 Å; the mask layer is formed at the break region, and the thickness of the mask layer ranges from 5000 Å to 9000 Å. The wafer is etched using the masking layer pattern to form the first deep trench and the second deep trench within the wafer.
2. The method for improving critical dimensions of deep trench isolation according to claim 1, characterized in that, The method of forming the blank area in the intersection area includes: disconnecting the first deep trench and / or the second deep trench at the intersection area.
3. The method for improving critical dimensions of deep trench isolation according to claim 2, characterized in that, There are multiple first deep trenches and multiple second deep trenches, and the multiple first deep trenches and multiple second deep trenches are arranged intersectingly to form a grid structure.