Bidirectional transient voltage suppression protection device and method of manufacturing the same

Abstract

The application provides a bidirectional transient voltage suppression protection device and a manufacturing method thereof, and the bidirectional transient voltage suppression protection device comprises a substrate with a first conductive type; an epitaxial layer on the substrate, the epitaxial layer having a second conductive type; a MOS transistor comprising a gate structure, a source region and a drain region, the gate structure being on the epitaxial layer, and the source region and the drain region being in the epitaxial layer on both sides of the gate structure respectively; the source region and the drain region having the first conductive type, so that the substrate, the epitaxial layer and the source region form a first triode, and so that the substrate, the epitaxial layer and the drain region form a second triode. The technical scheme of the application can realize bidirectional high-symmetry transient voltage suppression function and play a better protection role on the back-end alternating current circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a bidirectional transient voltage suppression protection device and a manufacturing method thereof. BACKGROUND

[0002] The transient voltage suppression protection device is a high-performance protection device in the form of a diode, which has the advantages of small size, fast response and large instantaneous power absorption. When the two poles of the diode are subjected to a reverse transient high-energy impact, it can change the high impedance between the two poles to low impedance at the speed of picoseconds, absorb a surge power of up to several kilowatts, and clamp the voltage between the two poles at a predetermined value, effectively protecting the precision components in the electronic circuit from damage caused by various surge pulses. With the increasing size of electronic products, requirements for ESD protection devices in terms of parameter performance and product size are increasing in various applications such as set-top box interfaces, display card interfaces, and USB interfaces. The bidirectional transient voltage suppression protection device is used in various overvoltage AC protection circuits. Regardless of the polarity of the voltage applied to the two ends, it can be turned on as long as the voltage is greater than the trigger voltage, achieving a bidirectional overvoltage protection function. At the same time, higher requirements are placed on the symmetry of the voltage in both directions.

[0003] As shown in Figure 1 The conventional bidirectional transient voltage suppression protection device adopts an NPN transistor structure composed of an N-type substrate 11, a P-type epitaxial layer 12, and an N-type doped region. It can be regarded as two unidirectional transient voltage suppression protection diodes "back-to-back" connected, but no matter how the adjustment is made, it will simultaneously affect the voltage of the upper and lower diodes, resulting in a suboptimal voltage symmetry of the upper and lower diodes.

[0004] Therefore, how to achieve high symmetry of the bidirectional transient voltage suppression protection device is a problem that needs to be solved at present. SUMMARY

[0005] The present application aims to provide a bidirectional transient voltage suppression protection device and a manufacturing method thereof, which can achieve a bidirectional high-symmetry transient voltage suppression function and provide better protection for the back-end AC circuit.

[0006] To achieve the above-mentioned purpose, the present application provides a bidirectional transient voltage suppression protection device, comprising:

[0007] a substrate having a first conductivity type;

[0008] an epitaxial layer located on the substrate, the epitaxial layer having a second conductivity type;

[0009] A MOS transistor comprises a gate structure, a source region and a drain region, the gate structure is located on the epitaxial layer, and the source region and the drain region are located in the epitaxial layer on both sides of the gate structure respectively; the source region and the drain region have a first conductivity type, so that the substrate, the epitaxial layer and the source region form a first triode, and the substrate, the epitaxial layer and the drain region form a second triode.

[0010] Optionally, the junction depth of the drain region is greater than the junction depth of the source region, and the doping concentration of the drain region is greater than the doping concentration of the source region.

[0011] Optionally, the breakdown voltage of the first triode is equal to the breakdown voltage of the second triode.

[0012] Optionally, if the first conductivity type is N type and the second conductivity type is P type, in the first triode, the substrate is a collector, the epitaxial layer is a base, and the source region is an emitter; in the second triode, the substrate is an emitter, the epitaxial layer is a base, and the drain region is a collector; the emitter of the first triode and the source region and the gate structure of the MOS transistor are connected to a power supply end, and the collector of the first triode is connected to a ground end; if the first conductivity type is P type and the second conductivity type is N type, in the first triode, the substrate is an emitter, the epitaxial layer is a base, and the source region is a collector; in the second triode, the substrate is a collector, the epitaxial layer is a base, and the drain region is an emitter; the collector of the first triode and the source region and the gate structure of the MOS transistor are connected to a power supply end, and the emitter of the first triode is connected to a ground end.

[0013] Optionally, the gate structure comprises a gate oxide layer and a gate layer from bottom to top.

[0014] Optionally, the bidirectional transient voltage suppression protection device further comprises:

[0015] A first insulating medium layer is located on the epitaxial layer, a first opening exposing part of the top surface of the epitaxial layer is formed in the first insulating medium layer, the gate oxide layer is located on the epitaxial layer exposed by the first opening, and the gate layer is located on part of the gate oxide layer.

[0016] A second insulating medium layer is located on the first insulating medium layer, the gate oxide layer and the gate layer, a second opening exposing the source region is formed in the second insulating medium layer and the gate oxide layer on the source region, and a third opening exposing the gate layer is formed in the second insulating medium layer on the gate layer.

[0017] Optionally, the bidirectional transient voltage suppression protection device further comprises:

[0018] a first metal electrode on the second insulating dielectric layer, the first metal electrode filling the second opening and the third opening, so that the first metal electrode is connected with the source region and the gate layer;

[0019] a second metal electrode on the bottom surface of the substrate.

[0020] Optionally, the bidirectional transient voltage suppression protection device further comprises:

[0021] a passivation layer extending from the second insulating dielectric layer to part of the first metal electrode.

[0022] The present application also provides a manufacturing method of a bidirectional transient voltage suppression protection device, comprising:

[0023] providing a substrate, the substrate having a first conductive type;

[0024] forming an epitaxial layer on the substrate, the epitaxial layer having a second conductive type;

[0025] forming a MOS transistor, the MOS transistor comprising a gate structure, a source region and a drain region, the gate structure being formed on the epitaxial layer, the source region and the drain region being formed in the epitaxial layer on both sides of the gate structure respectively; the source region and the drain region having the first conductive type, so that the substrate, the epitaxial layer and the source region constitute a first triode, and so that the substrate, the epitaxial layer and the drain region constitute a second triode.

[0026] Optionally, the breakdown voltage of the first triode is equal to that of the second triode.

[0027] Optionally, if the first conductivity type is N type and the second conductivity type is P type, in the first triode, the substrate is a collector, the epitaxial layer is a base, and the source region is an emitter; in the second triode, the substrate is an emitter, the epitaxial layer is a base, and the drain region is a collector; the emitter of the first triode and the source region and the gate structure of the MOS transistor are connected to a power supply terminal, the collector of the first triode is connected to a ground terminal, and the collector of the second triode is connected to the ground terminal; if the first conductivity type is P type and the second conductivity type is N type, in the first triode, the substrate is an emitter, the epitaxial layer is a base, and the source region is a collector; in the second triode, the substrate is a collector, the epitaxial layer is a base, and the drain region is an emitter; the gate structure of the MOS transistor and the collector of the first triode are connected to the power supply terminal, the emitter of the first triode is connected to the ground terminal, and the emitter of the second triode is connected to the ground terminal.

[0028] Optionally, the step of forming the MOS transistor comprises:

[0029] forming a first insulating medium layer on the epitaxial layer, the first insulating medium layer having a first opening formed therein to expose a portion of a surface of the epitaxial layer;

[0030] forming a gate oxide layer on the epitaxial layer exposed by the first opening;

[0031] forming a gate layer on a portion of the gate oxide layer, the gate oxide layer and the gate layer constituting the gate structure;

[0032] forming a source region and a drain region in the epitaxial layer on two sides of the gate layer, respectively.

[0033] Optionally, the step of forming the source region and the drain region in the epitaxial layer on two sides of the gate layer, respectively, comprises:

[0034] performing a first ion implantation on the epitaxial layer on a first side and a second side of the gate layer opposite to each other, to form the source region in the epitaxial layer on the first side of the gate layer;

[0035] performing a second ion implantation on the epitaxial layer on the second side of the gate layer, to form the drain region in the epitaxial layer on the second side of the gate layer, the drain region having a junction depth greater than a junction depth of the source region and a doping concentration greater than a doping concentration of the source region.

[0036] Optionally, the method for manufacturing the bidirectional transient voltage suppression protection device further comprises:

[0037] forming a second insulating medium layer covering the first insulating medium layer, the gate oxide layer and the gate electrode layer;

[0038] forming a second opening penetrating the second insulating medium layer and the gate oxide layer on the source region and forming a third opening penetrating the second insulating medium layer on the gate electrode layer to expose the source region and the gate electrode layer;

[0039] forming a first metal electrode on the second insulating medium layer, the first metal electrode filling the second opening and the third opening so that the first metal electrode is connected with the source region and the gate electrode layer;

[0040] forming a second metal electrode on the bottom surface of the substrate.

[0041] Optionally, after forming the first metal electrode on the second insulating medium layer and before forming the second metal electrode on the bottom surface of the substrate, the method for manufacturing the bidirectional transient voltage suppression protection device further comprises:

[0042] forming a passivation layer extending from the second insulating medium layer to part of the first metal electrode.

[0043] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0044] 1. The bidirectional transient voltage suppression protection device provided by the present application comprises a MOS transistor, the MOS transistor comprises a gate structure, a source region and a drain region, the gate structure is located on an epitaxial layer, the source region and the drain region are respectively located in the epitaxial layer on both sides of the gate structure, the substrate, the epitaxial layer and the source region constitute a first triode, the substrate, the epitaxial layer and the drain region constitute a second triode, so that the bidirectional transient voltage suppression protection device is a composite structure of a double triode and a MOS transistor, thereby realizing a bidirectional high-symmetry transient voltage suppression function and playing a better protection role on a back-end alternating current circuit.

[0045] 2. The method for manufacturing the bidirectional transient voltage suppression protection device provided by the present application comprises forming a MOS transistor comprising a gate structure, a source region and a drain region, the gate structure is formed on an epitaxial layer, the source region and the drain region are respectively formed in the epitaxial layer on both sides of the gate structure, the substrate, the epitaxial layer and the source region constitute a first triode, the substrate, the epitaxial layer and the drain region constitute a second triode, so that the bidirectional transient voltage suppression protection device is a composite structure of a double triode and a MOS transistor, thereby realizing a bidirectional high-symmetry transient voltage suppression function and playing a better protection role on a back-end alternating current circuit. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 is a schematic diagram of an NPN triode structure;

[0047] Figure 2 is a schematic diagram of a bidirectional transient voltage suppression protection device according to an embodiment of the present application;

[0048] Figures 3a-3b is a circuit diagram of the bidirectional transient voltage suppression protection device shown in Figure 2

[0049] Figure 4 is a flow chart of a manufacturing method of a bidirectional transient voltage suppression protection device according to an embodiment of the present application;

[0050] Figures 5a-5k is a schematic diagram of a device in the manufacturing method of a bidirectional transient voltage suppression protection device shown in Figure 4 wherein the accompanying drawings are used to explain the present application, and the same or similar components are denoted by the same reference numerals, and components not directly related to the description are omitted.

[0051] The reference numerals in the accompanying drawings are explained as follows: Figures 1-5k

[0052] 11-N-type substrate; 12-P-type epitaxial layer; 13-N-type doped region; 21-substrate; 22-epitaxial layer; 23-first insulating dielectric layer; 231-first opening; 241-gate oxide layer; 242-gate layer; 251-source region; 252-drain region; 26-second insulating dielectric layer; 261-second opening; 262-third opening; 27-first metal electrode; 28-passivation layer; 29-second metal electrode. DETAILED DESCRIPTION

[0053] To make the objects, advantages and features of the present application clearer, the bidirectional transient voltage suppression protection device and the manufacturing method thereof according to the present application are further described in detail below. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0054] An embodiment of the present application provides a bidirectional transient voltage suppression protection device, comprising: a substrate having a first conductivity type; an epitaxial layer on the substrate, the epitaxial layer having a second conductivity type; a MOS transistor comprising a gate structure, a source region and a drain region, the gate structure being on the epitaxial layer, and the source region and the drain region being in the epitaxial layer on both sides of the gate structure respectively; the source region and the drain region having the first conductivity type, so that the substrate, the epitaxial layer and the source region form a first triode, and the substrate, the epitaxial layer and the drain region form a second triode.

[0055] The following description is made with reference to the accompanying drawings, in which Figure 2 and Figures 3a-3b ​​The bidirectional transient voltage suppression protection device provided by the embodiment is described in detail. Figure 2 The figure is a longitudinal section view of the device.

[0056] The substrate 21 has the first conductive type and is heavily doped.

[0057] The epitaxial layer 22 is located on the substrate 21, and the epitaxial layer 22 has the second conductive type and is lightly doped.

[0058] The thickness of the epitaxial layer 22 is preferably 5-50 μm, so that the large thickness of the epitaxial layer 22 can be avoided, which leads to a large reverse dynamic resistance of the device and a high clamping voltage of the device.

[0059] The resistivity of the epitaxial layer 22 can be 0.02-200 Ω·cm.

[0060] The MOS transistor comprises a gate structure, a source region 251 and a drain region 252, the gate structure is located on the epitaxial layer 22, and the source region 251 and the drain region 252 are located in the epitaxial layer 22 on both sides of the gate structure respectively.

[0061] The gate structure comprises a gate oxide layer 241 and a gate layer 242 from bottom to top.

[0062] The bidirectional transient voltage suppression protection device further comprises:

[0063] A first insulating medium layer 23 is located on the epitaxial layer 22, and a first opening (not shown) exposing part of the surface of the epitaxial layer 22 is formed in the first insulating medium layer 23, the gate oxide layer 241 can be located on the entire epitaxial layer 22 exposed by the first opening, the gate layer 242 is located on part of the gate oxide layer 241 in the first opening, and the source region 251 and the drain region 252 are located in the epitaxial layer 22 on both sides of the gate layer 242 respectively;

[0064] A second insulating medium layer 26 is located on the first insulating medium layer 23, the gate oxide layer 241 and the gate layer 242, and a second opening (not shown) exposing the source region 251 is formed in the second insulating medium layer 26 on the source region 251 and the gate oxide layer 241, and a third opening (not shown) exposing the gate layer 242 is formed in the second insulating medium layer 26 on the gate layer 242.

[0065] It should be noted that the gate oxide layer 241 can also be located only on the portion of the epitaxial layer 22 exposed by the first opening, in which case the gate electrode layer 242 is located on the entire gate oxide layer 241; or the gate oxide layer 241 can also extend from the epitaxial layer 22 exposed by the first opening to the first insulating medium layer 23.

[0066] The first insulating medium layer 23 and the second insulating medium layer 26 can be made of insulating materials such as silicon oxide or silicon oxynitride. The thickness of the first insulating medium layer 23 can be 5 nm to 50 nm. The thickness of the second insulating medium layer 26 can be 5 nm to 50 nm.

[0067] The thickness of the gate oxide layer 241 is less than the thickness of the first insulating medium layer 23, and the thickness of the gate oxide layer 241 can be 1 nm to 10 nm. If the gate oxide layer 241 extends from the epitaxial layer 22 exposed by the first opening to the first insulating medium layer 23, the thickness of the gate oxide layer 241 on the epitaxial layer 22 is greater than the thickness of the gate oxide layer 241 on the first insulating medium layer 23.

[0068] The thickness of the gate electrode layer 242 can be 50 nm to 200 nm.

[0069] It should be noted that the thickness of the first insulating medium layer 23, the second insulating medium layer 26, the gate oxide layer 241 and the gate electrode layer 242 is not limited to the above ranges.

[0070] The junction depth of the drain region 252 is greater than the junction depth of the source region 251, and the doping concentration of the drain region 252 is greater than the doping concentration of the source region 251. Both the source region 251 and the drain region 252 are heavily doped. The junction depth of the source region 251 can be 1 μm to 20 μm, and the junction depth of the drain region 252 can be 2 μm to 30 μm. By adjusting the energy range used in ion implantation and the temperature range used in annealing process, the junction depths of the source region 251 and the drain region 252 can be adjusted.

[0071] The source region 251 and the drain region 252 have the first conductive type, so that the substrate 21, the epitaxial layer 22 and the source region 251 constitute a first triode, and the substrate 21, the epitaxial layer 22 and the drain region 252 constitute a second triode, thus the bidirectional transient voltage suppression protection device is a composite structure of double triode and MOS transistor. In which, the doping concentration and the junction depth of the source region 251 can be fixed to make the breakdown voltage of the first triode fixed, and the doping concentration and the junction depth of the drain region 252 are adjusted to make the breakdown voltage of the second triode adjusted, so that the breakdown voltages of the first triode and the second triode are equal.

[0072] If the first conductive type is N type and the second conductive type is P type, the MOS transistor is an NMOS transistor, the first triode and the second triode are both NPN triodes, and the bidirectional transient voltage suppression protection device is a composite structure of double NPN triode and NMOS transistor; in the first triode, the substrate 21 is a collector, the epitaxial layer 22 is a base, and the source region 251 is an emitter, and the emitter of the first triode and the source region 251 of the NMOS transistor are shared; in the second triode, the substrate 21 is an emitter, the epitaxial layer 22 is a base, and the drain region 252 is a collector, and the collector of the second triode and the drain region 252 of the NMOS transistor are shared. At this time, the circuit diagram of the bidirectional transient voltage suppression protection device is as shown in Figure 3a The collector of the first triode NPN is connected with a ground terminal GND, the emitter of the first triode NPN and the source of the NMOS transistor are shared, the source and the gate (i.e. the gate layer 242) of the NMOS transistor are connected with a power supply terminal VCC, the drain of the NMOS transistor and the collector of the second triode NPN' are shared, and the emitter of the second triode NPN' is connected with the ground terminal GND.

[0073] If the first conductivity type is P type and the second conductivity type is N type, the MOS transistor is a PMOS transistor, the first and second transistors are both PNP transistors, and the bidirectional transient voltage suppression protection device is a composite structure of a double PNP transistor and a PMOS transistor; in the first transistor, the substrate 21 is an emitter, the epitaxial layer 22 is a base, and the source region 251 is a collector, and the collector of the first transistor and the source region 251 of the PMOS transistor are shared; in the second transistor, the substrate 21 is a collector, the epitaxial layer 22 is a base, and the drain region 252 is an emitter, and the emitter of the second transistor and the drain region 252 of the PMOS transistor are shared. At this time, the circuit diagram of the bidirectional transient voltage suppression protection device is as shown in FIG. 2, the emitter of the first transistor PNP is connected with a ground terminal GND, the collector of the first transistor PNP is shared with the source of the PMOS transistor, the source and gate of the PMOS transistor are connected with a power supply terminal VCC, the drain of the PMOS transistor is shared with the emitter of the second transistor PNP', and the collector of the second transistor PNP' is connected with the ground terminal GND. Figure 3b

[0074] It should be noted that in the circuit diagram of the bidirectional transient voltage suppression protection device, the base does not need to be externally connected to meet the voltage resistance requirement.

[0075] The bidirectional transient voltage suppression protection device further comprises:

[0076] A first metal electrode 27 is located on the second insulating medium layer 26, and the first metal electrode 27 fills the second opening and the third opening, so that the first metal electrode 27 is connected with the source region 251 and the gate layer 242.

[0077] A second metal electrode 29 is located on the bottom surface of the substrate 21.

[0078] The bidirectional transient voltage suppression protection device further comprises a passivation layer 28, which extends from the second insulating medium layer 26 to part of the first metal electrode 27.

[0079] The thickness of the first metal electrode 27 can be 1 μm to 10 μm, the thickness of the passivation layer 28 can be 1 μm to 10 μm, and the thickness of the second metal electrode 29 can be 1 μm to 5 μm. It should be noted that the thickness of the first metal electrode 27, the passivation layer 28, and the second metal electrode 29 is not limited to the above range.

[0080] ​The first metal electrode 27 is used for wire bonding in a packaging process, and the second metal electrode 29 is used for electrical connection with a substrate through conductive materials such as die bonding glue or tin paste in the packaging process.

[0081] Since there are many particle impurities in the environment when the chip is packaged, the edge of the first metal electrode 27 at the junction with the second insulating medium layer 26 can be covered by the passivation layer 28 by extending the passivation layer 28 from the second insulating medium layer 26 to part of the first metal electrode 27, thereby avoiding particle impurities from entering the inside of the bidirectional transient voltage suppression protection device from the junction.

[0082] Figure 1 The NPN triode structure adopted by the conventional bidirectional transient voltage suppression protection device can be regarded as two unidirectional transient voltage suppression protection diodes arranged in a back-to-back manner, but no matter how the adjustment is made, the voltage of the upper and lower diodes will be affected simultaneously, resulting in that the voltage symmetry of the upper and lower diodes is not optimal, and the difference between the breakdown voltages of the two directions is generally about 1V.

[0083] The bidirectional transient voltage suppression protection device provided by the application adopts a composite structure of double triodes (i.e. the first triode and the second triode) and a MOS transistor. Taking the case that the first triode and the second triode are both NPN triodes and the MOS transistor is an NMOS transistor as an example, the emitter of the first triode and the source region 251 of the NMOS transistor are shared, and the collector of the second triode and the drain region 252 of the NMOS transistor are shared. When the first metal electrode 27 is connected to a low potential and the second metal electrode 29 is connected to a high potential, the first triode is turned on to realize overvoltage protection in one direction. When the first metal electrode 27 is connected to a high potential and the second metal electrode 29 is connected to a low potential, the NMOS transistor induces a reverse N channel between the source region 251 and the drain region 252 through the gate layer 242, and the NMOS transistor is turned on. Since the breakdown voltages of the first triode and the second triode are equal, the current flows through the emitter (i.e. the source region 251) of the first triode, passes through the reverse N channel of the NMOS transistor to the collector (i.e. the drain region 252) of the second triode, so that the second triode is turned on to realize overvoltage protection in the other direction. Therefore, under the joint action of the double triodes and the MOS transistor, bidirectional high-symmetry transient voltage suppression function can be realized, and the difference between the breakdown voltages of the two directions can be reduced to within 0.05V, so that the bidirectional transient voltage suppression protection device can be better applied to an AC protection circuit and play a better protection role in the back-end AC circuit compared with the conventional bidirectional transient voltage suppression protection device.

[0084] In summary, the bidirectional transient voltage suppression and protection device provided by the present invention includes: a substrate having a first conductivity type; an epitaxial layer located on the substrate, the epitaxial layer having a second conductivity type; and a MOS transistor comprising a gate structure, a source region, and a drain region, the gate structure being located on the epitaxial layer, and the source region and the drain region being located in the epitaxial layers on both sides of the gate structure; the source region and the drain region having the first conductivity type, such that the substrate, the epitaxial layer, and the source region constitute a first transistor, and such that the substrate, the epitaxial layer, and the drain region constitute a second transistor, thereby enabling bidirectional high-symmetry transient voltage suppression function and providing better protection for downstream AC circuits.

[0085] An embodiment of the present invention provides a method for manufacturing a bidirectional transient voltage suppression protection device, see reference. Figure 4 , Figure 4 This is a flowchart of a method for manufacturing a bidirectional transient voltage suppression protection device according to an embodiment of the present invention. The method for manufacturing the bidirectional transient voltage suppression protection device includes:

[0086] Step S1: Provide a substrate having a first conductivity type;

[0087] Step S2: Form an epitaxial layer on the substrate, the epitaxial layer having a second conductivity type;

[0088] Step S3: Forming a MOS transistor, the MOS transistor comprising a gate structure, a source region, and a drain region, the gate structure being formed on the epitaxial layer, the source region and the drain region being formed in the epitaxial layer on both sides of the gate structure; the source region and the drain region having a first conductivity type, such that the substrate, the epitaxial layer and the source region constitute a first transistor, and such that the substrate, the epitaxial layer and the drain region constitute a second transistor.

[0089] See below. Figures 3a-3b and Figures 5a-5k The manufacturing method of the bidirectional transient voltage suppression protection device provided in this embodiment will be described in detail, 5a~ Figure 5f This is a schematic diagram of the longitudinal cross-section of the device.

[0090] Follow step S1, refer to Figure 5a A substrate 21 is provided, the substrate 21 having a first conductivity type. The substrate 21 is heavily doped.

[0091] Follow step S2, see Figure 5a An epitaxial layer 22 is formed on the substrate 21, and the epitaxial layer 22 has a second conductivity type. The epitaxial layer 22 is lightly doped.

[0092] The thickness of the epitaxial layer 22 is preferably 5 μm to 50 μm, so that the device reverse dynamic resistance is not too large and the device clamping voltage is not too high.

[0093] The resistivity of the epitaxial layer 22 can be 0.02 Ω·cm to 200 Ω·cm.

[0094] According to step S3, referring to Figures 5b-5f , a MOS transistor is formed, which comprises a gate structure, a source region 251 and a drain region 252, the gate structure is formed on the epitaxial layer 22, and the source region 251 and the drain region 252 are formed in the epitaxial layer 22 on both sides of the gate structure.

[0095] The step of forming the MOS transistor can comprise: first, as shown in Figure 5b , a first insulating medium layer 23 is formed on the epitaxial layer 22; then, as shown in Figure 5c , a first opening 231 is formed in the first insulating medium layer 23 by using photolithography and etching process, which exposes part of the top surface of the epitaxial layer 22; then, as shown in Figure 5d , a gate oxide layer 241 is formed on the epitaxial layer 22 exposed by the first opening 231, and the gate oxide layer 241 can also extend to the first insulating medium layer 23; then, as shown in Figure 5e , a gate layer 242 is formed on part of the gate oxide layer 241 on the epitaxial layer 22, and the gate oxide layer 241 and the gate layer 242 constitute the gate structure; then, as shown in Figure 5f , the source region 251 and the drain region 252 are formed in the epitaxial layer 22 on both sides of the gate layer 242, respectively.

[0096] The material of the first insulating medium layer 23 can be silicon oxide or silicon oxynitride, etc. The thickness of the first insulating medium layer 23 can be It should be noted that the thickness of the first insulating medium layer 23 is not limited to the above range.

[0097] The gate oxide layer 241 can be formed by thermal oxidation process, and the temperature used in the thermal oxidation process is 900 ℃ to 1000 ℃. The thickness of the gate oxide layer 241 is less than that of the first insulating medium layer 23, and the material of the gate oxide layer 241 can be silicon oxide, and the thickness can be It should be noted that the thickness of the gate oxide layer 241 is not limited to the above range.

[0098] If the gate oxide layer 241 also extends to the first insulating medium layer 23, the thickness of the gate oxide layer 241 on the epitaxial layer 22 is greater than the thickness of the gate oxide layer 241 on the first insulating medium layer 23.

[0099] In forming the gate layer 242, a gate material can be deposited on the gate oxide layer 241 first, and then the gate material is etched to form the gate layer 242. In etching the gate material, the gate oxide layer 241 around the periphery of the gate layer 242 can be retained (as shown in Figure 5e ) or can be etched away.

[0100] The material of the gate layer 242 can be polysilicon, and the thickness can be 1000A-3000A. It should be noted that the thickness of the gate layer 242 is not limited to the above range.

[0101] Furthermore, the steps of forming the source region 251 and the drain region 252 in the epitaxial layer 22 on both sides of the gate layer 242 respectively can include: first, performing a first ion implantation on the epitaxial layer 22 on the first side and the second side of the gate layer 242 to form the source region 251 in the epitaxial layer 22 on the first side of the gate layer 242 and a doped region (not shown) in the epitaxial layer 22 on the second side of the gate layer 242; then, covering the epitaxial layer 22 (source region 251) on the first side of the gate layer 242 with photoresist, and performing a second ion implantation only on the doped region in the epitaxial layer 22 on the second side of the gate layer 242 to form the drain region 252 in the epitaxial layer 22 on the second side of the gate layer 242, the junction depth of the drain region 252 being greater than the junction depth of the source region 251, the doping concentration of the drain region 252 being greater than the doping concentration of the source region 251, and both the source region 251 and the drain region 252 being heavily doped.

[0102] The energy used in the first ion implantation and the second ion implantation can both be 60KeV-150KeV, the dose used in the first ion implantation can be 2E14cm -2 -2E16cm -2 , the dose used in the second ion implantation can be 4E14cm -2 -4E16cm -2 , and after the second ion implantation, an annealing process is performed, the temperature used in the annealing process can be 900°C-1250°C.

[0103] The junction depth of the source region 251 can be 1 μm to 20 μm, and the junction depth of the drain region 252 can be 2 μm to 30 μm. The junction depths of the source region 251 and the drain region 252 can be adjusted by adjusting the energy range used in the first ion implantation and the second ion implantation and the temperature range used in the annealing process.

[0104] It should be noted that the steps of forming the source region 251 and the drain region 252 are not limited to the above steps. For example, the steps can further include: first, covering the epitaxial layer 22 on the second side of the gate layer 242 with photoresist, and forming the source region 251 by ion implantation on the epitaxial layer 22 on the first side of the gate layer 242 only; and then, covering the epitaxial layer 22 on the first side of the gate layer 242 with photoresist, and forming the drain region 252 by ion implantation on the epitaxial layer 22 on the second side of the gate layer 242 only. The source region 251 and the drain region 252 can be obtained by adjusting the energy and dose used in the two ion implantations and the temperature of the annealing process.

[0105] The source region 251 and the drain region 252 have the first conductivity type, so that the substrate 21, the epitaxial layer 22 and the source region 251 form a first triode, and the substrate 21, the epitaxial layer 22 and the drain region 252 form a second triode. Therefore, the bidirectional transient voltage suppression protection device is a composite structure of double triodes and a MOS transistor. The doping concentration and the junction depth of the source region 251 can be fixed to fix the breakdown voltage of the first triode, and the doping concentration and the junction depth of the drain region 252 can be adjusted to adjust the breakdown voltage of the second triode, so that the breakdown voltages of the first triode and the second triode are equal.

[0106] If the first conductivity type is N type and the second conductivity type is P type, the MOS transistor is an NMOS transistor, the first triode and the second triode are both NPN triodes, and the bidirectional transient voltage suppression protection device is a composite structure of double NPN triodes and an NMOS transistor. In the first triode, the substrate 21 is a collector, the epitaxial layer 22 is a base, and the source region 251 is an emitter. The emitter of the first triode and the source region 251 of the NMOS transistor are shared. In the second triode, the substrate 21 is an emitter, the epitaxial layer 22 is a base, and the drain region 252 is a collector. The collector of the second triode and the drain region 252 of the NMOS transistor are shared. At this time, the circuit diagram of the bidirectional transient voltage suppression protection device is as shown in FIG. 4. Figure 3aAs shown, the collector of the first transistor NPN is connected with the ground terminal GND, the emitter of the first transistor NPN is shared with the source of the NMOS transistor, the source and the gate (i.e. the gate layer 242) of the NMOS transistor are connected with the power terminal VCC, the drain of the NMOS transistor is shared with the collector of the second transistor NPN', and the emitter of the second transistor NPN' is connected with the ground terminal GND.

[0107] If the first conductive type is P type and the second conductive type is N type, the MOS transistor is a PMOS transistor, the first transistor and the second transistor are both PNP transistors, and the bidirectional transient voltage suppression protection device is a composite structure of a double PNP transistor and a PMOS transistor; in the first transistor, the substrate 21 is the emitter, the epitaxial layer 22 is the base, the source region 251 is the collector, and the collector of the first transistor is shared with the source region 251 of the PMOS transistor; in the second transistor, the substrate 21 is the collector, the epitaxial layer 22 is the base, and the drain region 252 is the emitter, and the emitter of the second transistor is shared with the drain region 252 of the PMOS transistor. At this time, the circuit diagram of the bidirectional transient voltage suppression protection device is as shown in Figure 3b As shown, the emitter of the first transistor PNP is connected with the ground terminal GND, the collector of the first transistor PNP is shared with the source of the PMOS transistor, the source and the gate of the PMOS transistor are connected with the power terminal VCC, the drain of the PMOS transistor is shared with the emitter of the second transistor PNP', and the collector of the second transistor PNP' is connected with the ground terminal GND.

[0108] It should be noted that in the circuit diagram of the bidirectional transient voltage suppression protection device, the base does not need to be externally connected to meet the voltage resistance requirement.

[0109] The manufacturing method of the bidirectional transient voltage suppression protection device further comprises: first, as shown in Figure 5g then, as shown in Figure 5h then, as shown in Figure 5iAs shown, a first metal electrode 27 is formed on the second insulating medium layer 26, the first metal electrode 27 fills the second opening 261 and the third opening 262, so that the first metal electrode 27 is connected with the source region 251 and the gate layer 242; then, as shown, Figure 5j As shown, a passivation layer 28 is formed on the second insulating medium layer 26 and extends to part of the first metal electrode 27; then, as shown, Figure 5k As shown, a second metal electrode 29 is formed on the bottom surface of the substrate 21.

[0110] The material of the second insulating medium layer 26 can be silicon oxide or silicon oxynitride, etc.

[0111] The thickness of the second insulating medium layer 26 can be 1 μm to 10 μm. The thickness of the first metal electrode 27 can be 1 μm to 10 μm, the thickness of the passivation layer 28 can be 1 μm to 10 μm, and the thickness of the second metal electrode 29 can be 1 μm to 5 μm. It should be noted that the thickness of the second insulating medium layer 26, the first metal electrode 27, the passivation layer 28 and the second metal electrode 29 is not limited to the above range.

[0112] Since there are many particle impurities in the environment when packaging the chip, by extending the passivation layer 28 from the second insulating medium layer 26 to part of the first metal electrode 27, the edge of the first metal electrode 27 and the junction of the second insulating medium layer 26 can be covered by the passivation layer 28, thereby avoiding particle impurities from entering the inside of the bidirectional transient voltage suppression protection device from the junction.

[0113] The first metal electrode 27 is used for wire bonding in the packaging process, and the second metal electrode 29 is used for electrical connection with a substrate through conductive materials such as die bonding glue or tin paste in the packaging process.

[0114] Figure 1 The NPN transistor structure used in the conventional bidirectional transient voltage suppression protection device shown can be regarded as two unidirectional transient voltage suppression protection diodes "back to back", but no matter how to adjust, it will simultaneously affect the voltage of the upper and lower diodes "back to back", resulting in that the voltage symmetry of the upper and lower diodes is not optimal, and the difference between the breakdown voltages of the upper and lower directions is generally about 1 V.

[0115] The bidirectional transient voltage suppression protection device manufactured by the bidirectional transient voltage suppression protection device manufacturing method has a composite structure of a double triode (i.e. the first triode and the second triode) and a MOS transistor. Taking the first triode and the second triode as NPN triodes and the MOS transistor as an NMOS transistor as an example, the emitter of the first triode and the source region 251 of the NMOS transistor are shared, and the collector of the second triode and the drain region 252 of the NMOS transistor are shared. When the first metal electrode 27 is connected to a low potential and the second metal electrode 29 is connected to a high potential, the first triode is turned on to realize overvoltage protection in one direction. When the first metal electrode 27 is connected to a high potential and the second metal electrode 29 is connected to a low potential, the NMOS transistor induces an inversion N channel between the source region 251 and the drain region 252 through the gate layer 242, and the NMOS transistor is turned on. Since the breakdown voltages of the first triode and the second triode are equal, the current passes through the emitter of the first triode (i.e. the source region 251), flows through the inversion N channel of the NMOS transistor to the collector of the second triode (i.e. the drain region 252), so that the second triode is turned on to realize overvoltage protection in the other direction. Therefore, under the joint action of the double triode and the MOS transistor, bidirectional high-symmetry transient voltage suppression can be realized, and the difference between the breakdown voltages in the two directions can be reduced to within 0.05 V. Compared with the conventional bidirectional transient voltage suppression protection device, the bidirectional transient voltage suppression protection device can be better applied to an AC protection circuit and play a better protection role in the back-end AC circuit.

[0116] In summary, the bidirectional transient voltage suppression protection device manufacturing method provided by the application comprises the following steps: providing a substrate, the substrate having a first conductivity type; forming an epitaxial layer on the substrate, the epitaxial layer having a second conductivity type; forming a MOS transistor, the MOS transistor comprising a gate structure, a source region and a drain region, the gate structure being formed on the epitaxial layer, and the source region and the drain region being respectively formed in the epitaxial layer on both sides of the gate structure; the source region and the drain region having the first conductivity type, so that the substrate, the epitaxial layer and the source region constitute a first triode, and the substrate, the epitaxial layer and the drain region constitute a second triode, so that bidirectional high-symmetry transient voltage suppression can be realized, and a better protection role can be played in the back-end AC circuit.

[0117] The above description is only a description of the preferred embodiments of the application and does not limit the scope of the application in any way. Any modification or change made by a person skilled in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A bidirectional transient voltage suppression and protection device, characterized in that, include: The substrate has a first type of conductivity; An epitaxial layer, located on the substrate, having a second conductivity type; A MOS transistor includes a gate structure, a source region, and a drain region. The gate structure is located on the epitaxial layer, and the source region and the drain region are respectively located in the epitaxial layer on both sides of the gate structure. The source region and the drain region have a first conductivity type, such that the substrate, the epitaxial layer, and the source region constitute a first transistor, and such that the substrate, the epitaxial layer, and the drain region constitute a second transistor. Wherein, if the first conductivity type is N-type and the second conductivity type is P-type, then in the first transistor, the substrate is the collector, the epitaxial layer is the base, and the source region is the emitter; in the second transistor, the substrate is the emitter, the epitaxial layer is the base, and the drain region is the collector; the collector of the first transistor is connected to the ground terminal, and the emitter of the first transistor, as well as the source region and gate structure of the MOS transistor, are all connected to the power supply terminal, and the emitter of the second transistor is connected to the ground terminal; if the first conductivity type is P-type and the second conductivity type is N-type, then in the first transistor, the substrate is the emitter, the epitaxial layer is the base, and the source region is the collector; in the second transistor, the substrate is the collector, the epitaxial layer is the base, and the drain region is the emitter; the emitter of the first transistor is connected to the ground terminal, and the collector of the first transistor, as well as the source region and gate structure of the MOS transistor, are connected to the power supply terminal, and the collector of the second transistor is connected to the ground terminal.

2. The bidirectional transient voltage suppression and protection device as described in claim 1, characterized in that, The junction depth of the drain region is greater than that of the source region, and the doping concentration of the drain region is greater than that of the source region.

3. The bidirectional transient voltage suppression and protection device as described in claim 1, characterized in that, The breakdown voltages of the first transistor and the second transistor are equal.

4. The bidirectional transient voltage suppression and protection device as described in claim 1, characterized in that, The gate structure includes a gate oxide layer and a gate layer from bottom to top.

5. The bidirectional transient voltage suppression protection device as described in claim 4, characterized in that, The bidirectional transient voltage suppression protection device also includes: A first insulating dielectric layer is located on the epitaxial layer, and a first opening is formed in the first insulating dielectric layer to expose a portion of the top surface of the epitaxial layer. The gate oxide layer is located on the epitaxial layer exposed by the first opening, and the gate layer is located on a portion of the gate oxide layer. A second insulating dielectric layer is located on the first insulating dielectric layer, the gate oxide layer, and the gate layer. A second opening is formed in the second insulating dielectric layer and the gate oxide layer on the source region to expose the source region, and a third opening is formed in the second insulating dielectric layer on the gate layer to expose the gate layer.

6. The bidirectional transient voltage suppression protection device as described in claim 5, characterized in that, The bidirectional transient voltage suppression protection device also includes: A first metal electrode is located on the second insulating dielectric layer, and the first metal electrode fills the second opening and the third opening so that the first metal electrode is connected to the source region and the gate layer; The second metal electrode is located on the bottom surface of the substrate.

7. The bidirectional transient voltage suppression protection device as described in claim 6, characterized in that, The bidirectional transient voltage suppression protection device also includes: A passivation layer extends from the second insulating dielectric layer to a portion of the first metal electrode.

8. A method for manufacturing a bidirectional transient voltage suppression and protection device, characterized in that, include: A substrate is provided, the substrate having a first conductivity type; An epitaxial layer is formed on the substrate, the epitaxial layer having a second conductivity type; A MOS transistor is formed, the MOS transistor comprising a gate structure, a source region, and a drain region, the gate structure being formed on the epitaxial layer, and the source region and the drain region being formed in the epitaxial layer on both sides of the gate structure; the source region and the drain region have a first conductivity type, such that the substrate, the epitaxial layer, and the source region constitute a first transistor, and such that the substrate, the epitaxial layer, and the drain region constitute a second transistor; Wherein, if the first conductivity type is N-type and the second conductivity type is P-type, then in the first transistor, the substrate is the collector, the epitaxial layer is the base, and the source region is the emitter; in the second transistor, the substrate is the emitter, the epitaxial layer is the base, and the drain region is the collector; the collector of the first transistor is connected to the ground terminal, and the emitter of the first transistor, as well as the source region and gate structure of the MOS transistor, are all connected to the power supply terminal, and the emitter of the second transistor is connected to the ground terminal; if the first conductivity type is P-type and the second conductivity type is N-type, then in the first transistor, the substrate is the emitter, the epitaxial layer is the base, and the source region is the collector; in the second transistor, the substrate is the collector, the epitaxial layer is the base, and the drain region is the emitter; the emitter of the first transistor is connected to the ground terminal, and the collector of the first transistor, as well as the source region and gate structure of the MOS transistor, are connected to the power supply terminal, and the collector of the second transistor is connected to the ground terminal.

9. The method for manufacturing the bidirectional transient voltage suppression protection device as described in claim 8, characterized in that, The breakdown voltages of the first transistor and the second transistor are equal.

10. The method for manufacturing the bidirectional transient voltage suppression protection device as described in claim 8, characterized in that, The steps for forming the MOS transistor include: A first insulating dielectric layer is formed on the epitaxial layer, and a first opening is formed in the first insulating dielectric layer to expose a portion of the surface of the epitaxial layer; A gate oxide layer is formed on the epitaxial layer exposed by the first opening; A gate layer is formed on a portion of the gate oxide layer, and the gate oxide layer and the gate layer constitute the gate structure; Source and drain regions are formed in the epitaxial layers on both sides of the gate layer, respectively.

11. The method for manufacturing the bidirectional transient voltage suppression protection device as described in claim 10, characterized in that, The steps of forming the source region and the drain region in the epitaxial layers on both sides of the gate layer include: A first ion implantation is performed on the epitaxial layers on the first and second sides opposite to the gate layer to form the source region in the epitaxial layer on the first side of the gate layer; A second ion implantation is performed on the epitaxial layer on the second side of the gate layer to form the drain region in the epitaxial layer on the second side of the gate layer. The junction depth of the drain region is greater than the junction depth of the source region, and the doping concentration of the drain region is greater than the doping concentration of the source region.

12. The method for manufacturing the bidirectional transient voltage suppression protection device as described in claim 10, characterized in that, The manufacturing method of the bidirectional transient voltage suppression protection device further includes: A second insulating dielectric layer is formed covering the first insulating dielectric layer, the gate oxide layer, and the gate layer; A second opening is formed through the second insulating dielectric layer and the gate oxide layer on the source region, and a third opening is formed through the second insulating dielectric layer on the gate layer to expose the source region and the gate layer; A first metal electrode is formed on the second insulating dielectric layer, and the first metal electrode fills the second opening and the third opening so that the first metal electrode is connected to the source region and the gate layer; A second metal electrode is formed on the bottom surface of the substrate.

13. The method for manufacturing the bidirectional transient voltage suppression protection device as described in claim 12, characterized in that, After forming the first metal electrode on the second insulating dielectric layer and before forming the second metal electrode on the bottom surface of the substrate, the method for manufacturing the bidirectional transient voltage suppression protection device further includes: A passivation layer is formed extending from the second insulating dielectric layer to a portion of the first metal electrode.

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