Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of achieving high integration. The semiconductor device of the embodiments includes a semiconductor substrate, a first insulating layer formed from a main surface of the semiconductor substrate toward an inner side of the semiconductor substrate, and a transistor formed over the first insulating layer. The transistor includes a first semiconductor layer formed over the first insulating layer and insulated from the semiconductor substrate, a second insulating layer provided over a second region among a first region, the second region, and a third region arranged in a first direction along a main surface of the first semiconductor layer, and a first conductive layer provided over the second insulating layer. A first contact portion is connected to the first region of the first semiconductor layer, a second contact portion is connected to the third region of the first semiconductor layer, and a third contact portion is connected to the first conductive layer.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-35988 (filed on March 8, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] This embodiment relates to a semiconductor device. Background Technology

[0003] There are known semiconductor devices that include a semiconductor substrate and a plurality of transistors formed on the semiconductor substrate. Summary of the Invention

[0004] The implementation provides a semiconductor device capable of achieving high integration.

[0005] One embodiment of a semiconductor device includes: a semiconductor substrate; a first insulating layer formed from a main surface of the semiconductor substrate toward an inner side of the semiconductor substrate; and a transistor formed on the first insulating layer. The transistor includes: a first semiconductor layer formed on the first insulating layer and insulated from the semiconductor substrate, comprising a first region, a second region, and a third region sequentially arranged along a first direction along the main surface of the semiconductor substrate; a second insulating layer disposed on the second region of the first semiconductor layer; and a first conductive layer disposed on the second insulating layer. A first contact portion is connected to the first region of the first semiconductor layer, a second contact portion is connected to the third region of the first semiconductor layer, and a third contact portion is connected to the first conductive layer. Attached Figure Description

[0006] Figure 1 This is an equivalent circuit diagram showing the schematic structure of the semiconductor device of the first embodiment.

[0007] Figure 2 This is a schematic three-dimensional view of the semiconductor device.

[0008] Figure 3 yes Figure 2 A schematic enlarged view.

[0009] Figure 4 This is a schematic top view of the semiconductor device.

[0010] Figure 5 yes Figure 4 A schematic enlarged diagram.

[0011] Figure 6 yes Figure 5 A schematic enlarged view.

[0012] Figure 7 yes Figure 5 A schematic enlarged view.

[0013] Figure 8 It is Figure 7 The diagram shows a schematic cross-sectional view of the structure when cut along line AA′ and viewed in the direction of the arrow.

[0014] Figure 9 It is Figure 7 The diagram shows a schematic cross-sectional view of the structure when cut along line BB′ and viewed in the direction of the arrow.

[0015] Figure 10 yes Figure 4 A schematic enlarged view.

[0016] Figure 11 Is with Figure 10 A schematic enlarged view of the corresponding circuit area.

[0017] Figure 12 It is Figure 11 The diagram shows a schematic cross-sectional view of the structure when cut along line CC′ and viewed in the direction of the arrow.

[0018] Figure 13 It is Figure 11 The diagram shows a schematic cross-sectional view of the structure when cut along line CC′ and viewed in the direction of the arrow.

[0019] Figure 14 This is a schematic enlarged view of the circuit region of the semiconductor device in the second embodiment.

[0020] Figure 15 It is Figure 14 The diagram shows a schematic cross-sectional view of the structure when cut along line DD′ and viewed in the direction of the arrow.

[0021] Figure 16 This is a schematic enlarged view of the circuit region of the semiconductor device in the third embodiment.

[0022] Figure 17 It is Figure 16 The diagram shows a schematic cross-sectional view of the structure when cut along line EE′ and viewed in the direction of the arrow.

[0023] Figure 18 This is a schematic enlarged view of the circuit region of the semiconductor device in the fourth embodiment.

[0024] Figure 19 This is a schematic enlarged view of the circuit region of the semiconductor device according to the fifth embodiment.

[0025] Label Explanation

[0026] TP…transistor pair, Tr…transistor, Tr1…first transistor, Tr2…second transistor, S…semiconductor substrate, STI…insulator layer, D1, D2…drain regions, G1, G2…gate regions, S12…source region, 151…N-type well, 152, 161-165…difference layers, 160…semiconductor layer, 171, 172…gate insulating layer, 181, 182…gate electrode, CS1-CS9…contacts. Detailed Implementation

[0027] Next, the semiconductor device of the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and for ease of explanation, some structures may be omitted. Furthermore, common parts in multiple embodiments may be labeled with the same reference numerals and their descriptions may be omitted.

[0028] In this specification, a predetermined direction parallel to the main surface of the substrate is referred to as the X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the surface of the substrate is referred to as the Z direction. Furthermore, in this specification, terms such as "upper" and "lower" are based on the substrate. For example, the direction moving away from the substrate along the Z direction is called "upper," and the direction moving towards the substrate along the Z direction is called "lower." Additionally, when referring to a structure as a lower surface or lower end, it means the surface or end of the structure on the substrate side; when referring to an upper surface or upper end, it means the surface or end of the structure on the side opposite to the substrate.

[0029] In addition, in this specification, "semiconductor device" has various meanings, including memory dies, memory chips, memory cards, SSDs and other memory systems including controller dies, smartphones, tablet computers and other structures including mainframe computers, or sensors, computing devices and other structures not primarily for the purpose of data storage.

[0030] Furthermore, in this specification, "electrically connected" between the first and second structures means that the first and second structures are connected directly or via circuits such as wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0031] [First Implementation]

[0032] [structure]

[0033] Hereinafter, the structure of the semiconductor device of the first embodiment will be described with reference to the accompanying drawings.

[0034] Figure 1This is a schematic equivalent circuit diagram illustrating the structure of a semiconductor device applied to a first embodiment of a semiconductor memory device.

[0035] The semiconductor device of this embodiment includes a memory cell array MA and peripheral circuit PC, which serves as a control circuit for controlling the memory cell array MA.

[0036] The memory cell array MA has multiple memory blocks MB. Each memory block MB has multiple string cells SU. Each string cell SU has multiple memory strings MS. One end of each memory string MS is connected to the peripheral circuit PC via a bit line BL. The other end of each memory string MS is connected to the peripheral circuit PC via a common source line SL.

[0037] The memory string (MS) has a drain selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MC), and a source selection transistor (STS). Hereinafter, the drain selection transistor (STD) and the source selection transistor (STS) are sometimes simply referred to as selection transistors (STD, STS).

[0038] A memory cell MC is a field-effect transistor (memory transistor) that has a semiconductor layer that functions as a channel region, a gate insulating film including a charge accumulation film, and a gate electrode. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge accumulation film. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to one memory string MS. These word lines WL are collectively connected to all the memory strings MS in one memory block MB.

[0039] A selection transistor (STD, STS) is a field-effect transistor that has a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. Selection gate lines (SGD, SGS) are connected to the gate electrode of the selection transistor (STD, STS). The drain selection gate line SGD is correspondingly provided with a string cell SU and is connected to all the memory strings MS in one string cell SU. The source selection gate line SGS is connected to all the memory strings MS in multiple string cells SU in one memory block MB.

[0040] The peripheral circuit PC includes: a working voltage generation circuit 21 that generates the working voltage, an address decoder 22 that decodes the address data, a block selection circuit 23 and a voltage selection circuit 24 that transmit the working voltage to the memory cell array MA according to the output signal of the address decoder 22, a sense amplifier module 25 connected to the bit line BL, and a sequencer 26 that controls them.

[0041] The operating voltage generation circuit 21 has multiple operating voltage output terminals 31. The operating voltage generation circuit 21 includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit. According to the control signal from the sequencer 26, the operating voltage generation circuit 21 sequentially generates various operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS) during read, write, and erase operations relative to the memory cell array MA, and outputs them to the multiple operating voltage output terminals 31. The operating voltage output from the operating voltage output terminals 31 is appropriately adjusted according to the control signal from the sequencer 26.

[0042] Address decoder 22 includes multiple block select lines BLKSEL and multiple voltage select lines 33. Address decoder 22 sequentially refers to the address data in the address register according to the control signal from sequencer 26, decodes the address data, and turns on the block drive transistor 35 and voltage select transistor 37 corresponding to the address data, while turning off other block drive transistors 35 and voltage select transistors 37. For example, the voltage of the block select line BLKSEL and voltage select line 33 corresponding to the address data is set to "H", while other voltages are set to "L". Furthermore, when using P-channel transistors instead of N-channel transistors, opposite voltages are applied to these lines.

[0043] Furthermore, in the illustrated example, address decoder 22 has one block select line (BLKSEL) for each memory block (MB). However, this configuration can be modified accordingly. For example, it is also possible to have one block select line (BLKSEL) for every two or more memory blocks (MB).

[0044] The block select circuit 23 includes multiple block select sections 34 corresponding to memory blocks MB. Each of these block select sections 34 includes multiple block drive transistors 35 corresponding to word lines WL and select gate lines (SGD, SGS). The block drive transistors 35 are, for example, field-effect transistors. The drain electrodes of the block drive transistors 35 are electrically connected to their corresponding word lines WL or select gate lines (SGD, SGS). The source electrodes are electrically connected to the operating voltage output terminal 31 via wiring CG and voltage selection circuit 24. The gate electrodes are all connected to the corresponding block select line BLKSEL.

[0045] In addition, the block selection circuit 23 includes a plurality of transistors (not shown). These transistors are field-effect transistors connected between the select gate lines (SGD, SGS) and the ground voltage supply terminal. These transistors enable the select gate lines (SGD, SGS) of the non-selected memory block MB to be connected to the ground voltage supply terminal. Furthermore, the plurality of word lines WL of the non-selected memory block MB are in a floating state.

[0046] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to word lines WL and select gate lines (SGD, SGS). Each of these voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS) via wiring CG and block selection circuit 23. The source terminals are electrically connected to the corresponding operating voltage output terminals 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0047] The sensing amplifier module 25 is connected to multiple bit lines BL. The sensing amplifier module 25 includes, for example, multiple sensing amplifier units corresponding to the bit lines BL. Each sensing amplifier unit includes a clamping transistor that charges the bit line BL based on the voltage generated in the operating voltage generation circuit 21, a sensing transistor that senses the voltage or current of the bit line BL, and multiple latching circuits that hold the output signal of the sensing transistor, write data, etc.

[0048] The sequencer 26 outputs control signals to the operating voltage generation circuit 21, the address decoder 22, and the sense amplifier module 25 according to the input command and the state of the semiconductor device. For example, the sequencer 26 sequentially refers to the command data in the command register according to the clock signal, decodes the command data, and outputs it to the operating voltage generation circuit 21, the address decoder 22, and the sense amplifier module 25.

[0049] Figure 2 This is a schematic perspective view of the semiconductor device according to this embodiment. Furthermore, Figure 2 This is an illustrative diagram and does not show the detailed configuration of each structure. More specific configurations of each structure will be provided in [reference needed]. Figures 4-6 Then it will be discussed.

[0050] like Figure 2 As shown, the semiconductor device of this embodiment includes a semiconductor substrate S, a circuit layer CL disposed on the semiconductor substrate S, and a storage layer ML disposed above the circuit layer CL.

[0051] The semiconductor substrate S is, for example, a semiconductor substrate formed from single-crystal silicon (Si). The semiconductor substrate S, for example, has a double-well structure in which an N-type well is formed on the surface of a P-type semiconductor substrate, and a P-type well is further formed within the N-type well. Furthermore, an insulating layer STI, such as silicon oxide (SiO2), is provided on the semiconductor substrate S.

[0052] The circuit layer CL has the ability to form the peripheral circuit PC ( Figure 1 The transistor Tr comprises multiple transistors S and multiple wirings Da, Db, Dc and contacts CS connected to these transistors Tr. Some of the transistors Tr are, for example, field-effect transistors that utilize the surface of the semiconductor substrate S as a channel region (gate region). The functional region on the surface of the semiconductor substrate S, which functions as part of the transistor Tr, is surrounded by an insulating layer STI. Other transistors Tr are, for example, field-effect transistors that utilize the surface of a semiconductor layer formed on the insulating layer STI as a channel region (gate region). This structure will be described in detail later.

[0053] The memory layer ML has multiple structures included in the memory cell array MA. The memory layer ML has multiple conductive layers 110 arranged in the Z direction, semiconductor pillars 120 extending in the Z direction and facing the multiple conductive layers 110, a gate insulating film 130 disposed between the multiple conductive layers 110 and the semiconductor pillars 120, and a conductive layer 140 connected to the lower end of the semiconductor pillars 120.

[0054] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction, and multiple layers are arranged in the Z direction. The conductive layer 110 may, for example, contain a laminate of titanium nitride (TiN) and tungsten (W), or it may contain polycrystalline silicon containing impurities such as phosphorus or boron. In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layers 110.

[0055] One or more of the bottommost conductive layers 110 in a plurality of conductive layers 110 serve as source-select gate lines (SGS). Figure 1 ) and multiple source selection transistors (STS) connected thereto. Figure 1 The gate electrode functions as a word line WL. Additionally, multiple conductive layers 110 located above it serve as word lines WL. Figure 1 ) and multiple storage units MC connected thereto Figure 1 The gate electrode functions as a drain-select gate line (SGD). Additionally, one or more conductive layers 110 located above it serve as drain-select gate lines (SGD). Figure 1 ) and multiple drain-select transistors STD connected thereto. Figure 1 The gate electrode of the ) performs its function.

[0056] Multiple semiconductor pillars 120 are arranged in the X and Y directions. The semiconductor pillars 120 are, for example, undoped polycrystalline silicon (Si) or similar semiconductor layers. The semiconductor pillars 120 have a generally cylindrical shape, with an insulating layer 121, such as silicon oxide, disposed in the central portion. Furthermore, the outer peripheral surfaces of the semiconductor pillars 120 are each surrounded by a conductive layer 110. The lower end of the semiconductor pillar 120 is connected to the conductive layer 140. The upper end of the semiconductor pillar 120 is connected to a bit line BL extending in the Y direction via a semiconductor layer 124 containing N-type impurities such as phosphorus (P), contact portions Ch and Cb. Each semiconductor pillar 120 serves as a memory string MS ( Figure 1 The channel regions of the multiple memory cells (MC) and selection transistors (STD, STS) contained in the ) function.

[0057] For example, such as Figure 3 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a bulk insulating film 133 stacked between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the bulk insulating film 133 are insulating films such as silicon oxide. The charge storage film 132 is a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the bulk insulating film 133 have a generally cylindrical shape and extend along the outer peripheral surface of the semiconductor pillar 120 in the Z direction.

[0058] In addition, Figure 3 An example is shown where the gate insulating film 130 has a charge storage film 132 such as silicon nitride, but the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0059] For example, such as Figure 2 As shown, the conductive layer 140 includes a conductive film 141 connected to the lower end of the semiconductor pillar 120 and a conductive film 142 disposed on the lower surface of the conductive film 141. The conductive film 141 may contain, for example, a conductive semiconductor such as polycrystalline silicon containing N-type impurities such as phosphorus (P). The conductive film 142 may contain, for example, a conductive semiconductor such as polycrystalline silicon containing N-type impurities such as phosphorus (P), or may contain a metal such as tungsten (W), or may contain silicides.

[0060] Next, refer to Figures 4-7 The semiconductor device of this embodiment will be described in more detail. Furthermore, Figures 4-7 The diagram shows a schematic structure; the actual structure can be modified as appropriate. Additionally, for ease of explanation, [the diagram is shown in the original text]. Figures 4-7 In the text, a portion of the structure is omitted.

[0061] [Storage Layer ML]

[0062] Figure 4This is a schematic top view of the semiconductor device according to this embodiment. Figure 4 In the example, a semiconductor substrate S has a four memory cell array MA arranged in the X and Y directions.

[0063] Figure 5 It is shown Figure 4 A schematic top view of the structure in the region represented by A illustrates the structure in the storage layer ML. (See diagram below.) Figure 5 As shown, each memory cell array MA has multiple memory blocks MB (MB_A to MB_H) arranged in the Y direction. In addition, each memory block MB has two memory regions MR extending in the X direction and arranged in the X direction, a contact region CR between the two memory regions MR, and a through contact region TR between the contact region CR and the memory region MR.

[0064] exist Figure 5 In the example, the contact area CR and the through contact area TR are arranged in an alternating pattern. That is, in storage blocks MB_A, MB_D, MB_E, and MB_H, on one side in the X direction (e.g., Figure 5 The area on the right side) is configured with a through contact area TR, and on the other side in the X direction (e.g., Figure 5 The area on the left side is configured with a contact area CR. On the other hand, in storage blocks MB_B, MB_C, MB_F, and MB_G, on one side in the X direction (e.g., Figure 5 The area on the right side) is configured with a contact area CR, and on the other side in the X direction (e.g., Figure 5 The area on the left side of the memory block (MB) is provided with a through contact area TR. Additionally, the contact area CR of each memory block (MB) is adjacent to one contact area CR and one through contact area TR in the Y direction. Similarly, the through contact area TR of each memory block (MB) is adjacent to one contact area CR and one through contact area TR in the Y direction.

[0065] Figure 6 yes Figure 5 A partial enlarged view is a schematic top view illustrating the structure within the storage region MR. Figure 6In this example, five string cells SU arranged in the Y direction are provided in the storage region MR of each memory block MB. In each string cell SU, multiple semiconductor pillars 120 and gate insulating films 130 are provided in both the X and Y directions. Furthermore, an inter-string cell insulating layer SHE is provided between two string cells SU arranged in the Y direction. The conductive layers 110 that function as drain-select gate lines SGD are separated in the Y direction by the inter-string cell insulating layer SHE. These conductive layers 110 are respectively connected to contact portions CC. Near the contact portions CC, a generally cylindrical insulating member HR that supports the insulating layer 101 during the manufacturing process is provided. Additionally, an inter-block insulating layer ST is provided between the memory blocks MB arranged in the Y direction. The multiple conductive layers 110 are separated in the Y direction by the inter-block insulating layer ST.

[0066] Figure 7 yes Figure 5 A partial enlarged view is a schematic top view showing the structure in the contact area CR and the through contact area TR.

[0067] The contact area CR includes a wiring area wla extending in the X direction and a contact area wlb arranged in the Y direction. The wiring area wla includes a portion of a plurality of conductive layers 110 arranged in the Z direction. A portion of these conductive layers 110 extends along the inter-block insulating layer ST in the X direction. Furthermore, no contact portion CC is provided in the wiring area wla. The contact area wlb includes a plurality of contact portions CC arranged in the X direction and a portion of a plurality of conductive layers 110 arranged in the Z direction. Each portion of these conductive layers 110 has a connection portion connected to one of the plurality of contact portions CC and an opening for connecting the other contact portions CC to the underlying conductive layer 110.

[0068] The through-contact region TR includes a wiring region wlc extending in the X direction and a contact region wld arranged in the Y direction. The wiring region wlc includes a portion of a plurality of conductive layers 110 arranged in the Z direction. A portion of these conductive layers 110 extends along the inter-block insulating layer ST in the X direction. Furthermore, no through-contact portion C4 is provided in the wiring region wlc. The contact region wld includes a plurality of through-contact portions C4 arranged in the X direction and a portion of a plurality of conductive layers 110 arranged in the Z direction. A portion of these conductive layers 110 has a plurality of through holes corresponding to the through-contact portions C4.

[0069] In addition, as referenced Figure 5 As explained, each memory block (MB) has one side positioned in the X direction (e.g., Figure 5 , Figure 7 The storage area MR on the right side) and the storage area on the other side in the X direction (e.g., Figure 5 , Figure 7 The two storage regions MR (on the left) each include a portion of a plurality of conductive layers 110 arranged in the Z direction. A portion of these conductive layers 110 is connected via a wiring region wla ( Figure 7 ) and wiring area wlc ( Figure 7 They are interconnected. In addition, these multiple conductive layers 110 are connected to multiple transistors Tr disposed on the surface of the semiconductor substrate S via multiple contacts CC, wiring m0 extending in the Y direction, and through contacts C4.

[0070] Figure 8 It is Figure 7 The diagram shows a schematic cross-sectional view of the structure when cut along line AA′ and viewed in the direction of the arrow. (See diagram below.) Figure 8 As shown, the contact portion CC extends in the Z direction and is connected to the conductive layer 110 at its lower end. In addition, an insulating layer 102 of silicon oxide (SiO2) or the like is provided between the contact portions CC.

[0071] Figure 9 It is Figure 7 The structure shown is a schematic cross-sectional view when cut along line BB′ and viewed in the direction of the arrow. (See diagram.) Figure 9 As shown, the through contact C4 extends in the Z direction through multiple conductive layers 110 and insulating layers 101, connecting to the wiring Db in the circuit layer CL. Furthermore, each through contact C4 is electrically insulated from the conductive layer 110 by an insulating layer or the like. For example, in the illustrated example, an insulating layer 103, such as silicon oxide (SiO2), covering the outer peripheral surface of each through contact C4, is provided between each through contact C4 and the conductive layer 110, and each through contact C4 is electrically insulated from the conductive layer 110 by the insulating layer 103. However, this structure is merely an example, and the specific structure can be adjusted appropriately. For example, multiple insulating layers, such as silicon nitride (SiN), arranged in the Z direction with multiple insulating layers 101 spaced apart, can be provided between the through contact C4 and the conductive layer 110, and each through contact C4 is electrically insulated from the conductive layer 110 by these multiple insulating layers, such as silicon nitride. In such a case, for example, a structure such as... Figure 9 The insulating layer 103 shown may also be omitted.

[0072] [Circuit Layer CL]

[0073] Figure 10 It is shown in the location Figure 5A schematic top view of the transistor arrays TA1 and TA2 configured in the circuit layer CL below the memory layer ML. Transistor arrays TA1 and TA2 are arranged adjacent to each other in the X direction. Transistor arrays TA1 and TA2 include multiple transistors Tr for driving memory blocks MB_A to MB_H. Circuit regions CL_A to CL_H are provided in the circuit layer CL. These circuit regions CL_A to CL_H are respectively configured near the contact region CR and the through contact region TR connected to each memory block MB_A to MB_H. Transistors Tr that drive each memory block MB_A to MB_H are respectively configured in the circuit regions CL_A to CL_H. The labels “A” to “H” on each transistor Tr correspond to the labels at the end of the memory blocks MB_A to MB_H driven by these transistors Tr. For example, in the region of transistor array TA1 shown on the left side of the figure, circuit regions CL_A, CL_D, CL_E, and CL_H are configured to drive memory blocks MB_A, MB_D, MB_E, and MB_H respectively, spanning two adjacent memory blocks MB in the Y direction. Similarly, in the region of transistor array TA2 shown on the right side of the figure, circuit regions CL_B, CL_C, CL_F, and CL_G are configured to drive memory blocks MB_B, MB_C, MB_F, and MB_G respectively, spanning two adjacent memory blocks MB in the Y direction. Furthermore, the configuration of these circuit regions CL_A to CL_H is merely one example; other configurations may also be used.

[0074] Figure 11 It is Figure 10 A magnified top view of a portion of transistor array TA1. Furthermore, since transistor array TA2 has the same structure as transistor array TA1, its description is omitted. Transistor array TA1 includes multiple transistors Tr arranged in a matrix in the X and Y directions. These multiple transistors Tr serve as block drive transistors 35 ( Figure 1 This allows it to perform its function. Furthermore, in the illustrated example, the alignment period of transistor Tr in the Y direction coincides with the alignment period of memory block MB in the Y direction.

[0075] Multiple transistors Tr include a first transistor Tr1 and a second transistor Tr2. A pair of first transistors Tr1 and second transistors Tr2 adjacent in the Y direction constitutes a transistor pair TP. Transistor pairs TP are arranged in both the X and Y directions. Each transistor pair TP has, in the Y direction, a drain region D1, a gate region G1, a source region S12, a gate region G2, and a drain region D2. Drain region D1 and gate region G1 function as the drain and gate of the first transistor Tr1. Gate region G2 and drain region D2 function as the gate and drain of the second transistor Tr2. Source region S12 functions as the shared source of the first transistor Tr1 and the second transistor Tr2. The adjacent first transistors Tr1 and second transistors Tr2 of two adjacent transistor pairs TP in the Y direction drive the same memory block MB. For example, configured in… Figure 11 The transistors Tr above and below the circuit region CL_D shown in the diagram serve as block driver transistors 35 for driving the memory block MB_D. Figure 1 To fulfill its function.

[0076] Figure 12 It is Figure 11 The diagram shows a schematic cross-sectional view of a transistor TP cut along line CC' and viewed in the direction of the arrow. An insulating layer STI is formed on a semiconductor substrate S, for example, made of single-crystal silicon (Si), embedded in a trench T formed from the main surface S1 of the semiconductor substrate S toward the inner side of the semiconductor substrate S. The insulating layer STI is formed, for example, of silicon oxide (SiO2). Figure 11 As shown, the insulating layer STI has a plurality of insulating regions STIa arranged in the X and Y directions corresponding to the transistor pair TP. The insulating regions STIa are formed in a generally rectangular shape. In addition, the insulating layer STI has a plurality of insulating regions STIb arranged in the X and Y directions. The insulating regions STIb are respectively disposed between two adjacent insulating regions STIa in the X direction and connected to the central portion of the two insulating regions STIa in the Y direction. The width of the insulating region STIb in the X and Y directions is smaller than the width of the insulating region STIa in the X and Y directions, respectively. An N-type well 151 is formed on the semiconductor substrate S, surrounding the insulating layer STI from the main surface S1 to a predetermined depth. Moreover, an impurity layer 152 doped with a high concentration of N-type impurities is formed on the N-type well 151 on the main surface S1 side of the semiconductor substrate S.

[0077] A semiconductor layer 160 is formed on each insulating region ST1a of the insulating layer STI. For example... Figure 11As shown, semiconductor layer 160 is formed in a region on the upper surface of an insulating region STIa, thereby insulating it from the semiconductor substrate S. Semiconductor layer 160 is formed, for example, from polycrystalline silicon or monocrystalline silicon. Semiconductor layer 160 sequentially has a drain region D1, a gate region G1, a source region S12, a gate region G2, and a drain region D2 in the Y direction. Semiconductor layer 160 has impurity layers 162 and 164 containing low concentrations of P-type impurities in the channel portions corresponding to gate regions G1 and G2 and other body portions. Semiconductor layer 160 has impurity layers containing low concentrations of N-type impurities in the drain regions D1 and D2 and the source region S12, and impurity layers 161, 163, and 165 doped with high concentrations of N-type impurities in the contact regions of these impurity layers. Gate insulating layers 171 and 172 are formed on the gate regions G1 and G2 of semiconductor layer 160, respectively. Gate insulating layers 171 and 172 are formed, for example, from silicon oxide (SiO2). Gate electrodes 181 and 182 are formed on gate insulating layers 171 and 172, respectively. Gate electrodes 181 and 182 are formed, for example, from a conductive layer of polysilicon (Si).

[0078] Contacts CS1, CS2, and CS3 are respectively connected to the impurity layer 161 of the drain region D1, the impurity layer 163 of the source region S12, and the gate electrode 181 of the first transistor Tr1. Contacts CS5 and CS6 are respectively connected to the impurity layer 165 of the drain region D2 and the gate electrode 182 of the second transistor Tr2. A contact CS4 is connected to the first transistor Tr1 side of the impurity layer 152 of the semiconductor substrate S located between adjacent insulating layers S11 in the Y direction, and a contact CS7 is connected to the second transistor Tr2 side. Furthermore, in addition to the contact CS of the semiconductor substrate S, for example... Figure 11 As shown, they are also located on both sides of the gate regions G1 and G2 of each transistor pair TP in the Y direction.

[0079] Contact CS1 is connected to the word line WL of the corresponding memory block MB_D, and contact CS5 is connected to the word line WL of the corresponding memory block MB_E. Contact CS2 is connected to the routing CG. Contacts CS3 and CS6 are connected to the corresponding block select line BLKSEL.

[0080] [Write the job]

[0081] Next, the writing operation of data to the selected memory block MB in such a semiconductor device will be explained.

[0082] Figure 13The diagram illustrates the voltage applied to each part when the first transistor Tr1 driving memory block MB_D is set to the block select state and the second transistor Tr2 driving memory block MB_E is set to the block deselect state. At this time, a programming voltage Vpgm is applied to contact CS2 via wiring CG. A voltage Vpgmh (>Vpgm) is applied to contact CS3 via the block select line BLKSEL. A voltage Vss (=0V) is applied to contact CS6 via the block select line BLKSEL. As a result, the first transistor Tr1 becomes active, and the programming voltage Vpgm applied to wiring CG is transmitted to contact CS1 via the channel formed in the gate region G1. Consequently, the programming voltage Vpgm is applied to the word line WL of the selected memory block MB_D. On the other hand, the second transistor Tr2 becomes in the off state. Therefore, the word line WL of the deselected memory block MB_E becomes floating.

[0083] In the above-described writing operation, a voltage Vpgm to Vpgmh is applied as the substrate voltage V to the contact portion CS4 of the semiconductor substrate S connected to the first transistor Tr1 side of the drive selection memory block MB_D. BB Additionally, voltages Vpgm to Vpgmh are applied to the contact portions CS on both sides of the gate region G1 of the first transistor Tr1, which drives the selection memory block MB_D, in the X direction. As a result, a depletion layer DR is formed at the bottom of the insulating layer STI corresponding to the first transistor Tr1. Furthermore, a voltage Vss (0V) is applied as the substrate voltage V to the contact portion CS7 of the semiconductor substrate S connected to the side of the second transistor Tr2. BB To apply the voltage as described above, contacts CS3 and CS4 can be electrically connected, and contacts CS6 and CS7 can be electrically connected. Alternatively, approximately the same voltage can be applied to each of these contacts CS.

[0084] Furthermore, the voltage application mode of the other transistors adjacent to the first transistor Tr1 of the drive selection memory block MB_D in the Y direction is the same as that of the transistors in the Y direction, except that it is reversed relative to the voltage application mode of the transistors in the Y direction described above, so detailed description is omitted.

[0085] [Effects of the first embodiment]

[0086] Conventional transistors (Tr) are typically formed using a double-well or triple-well structure on a semiconductor substrate (S), separating adjacent transistors (Tr) through an insulating layer (STI). However, with the increasing layer stacking and integration of semiconductor devices, the leakage current from adjacent transistors increases if transistor integration is pursued. This makes it difficult to reduce the spacing between components, leading to an increase in the proportion of the chip area occupied by transistors. This trend is particularly pronounced in high-voltage transistors such as memory block selection transistors in semiconductor memory devices.

[0087] According to the first embodiment, since the transistor Tr is formed on the insulating layer STI and is insulated from the semiconductor substrate S, leakage between adjacent transistors Tr is not a problem, and the spacing between components can be reduced accordingly. In addition, by disposing the insulating layer STI on the underside of the semiconductor layer 160, the semiconductor layer 160 and the semiconductor substrate S are separated, thereby improving the back bias characteristics.

[0088] Furthermore, in this embodiment, during write operation, a high voltage Vpgm to Vpgmh is applied to the N-type well 151 via the contact portion CS4 and the high-concentration N-type impurity layer 152. This forms a depletion layer DR at the bottom of the insulating layer STI. As a result, it is possible to prevent the formation of a reversal layer at the bottom of the insulating layer STI directly below the gate electrode 181 to which the programming voltage Vpgm is applied. Consequently, the capacitance between the gate electrode 181 and the bottom of the insulating layer STI is reduced, enabling high-speed operation. In this embodiment, as... Figure 11 As shown, since the impurity layer 152 is separated into individual memory blocks MB by the insulating layer STI, the programming voltage Vpgm can be applied only to the range of the selected circuit region CL_D.

[0089] Furthermore, in the conventional configuration where transistors for word line driving are formed within the semiconductor substrate S, a triple-well structure is required to supply a negative voltage to the word line WL. However, in this embodiment, since the semiconductor layer 160 is insulated from the semiconductor substrate S, a triple-well structure is not necessary. Consequently, the manufacturing process is simplified, and latch-up problems are avoided.

[0090] [Second Implementation]

[0091] Figure 14 This is a magnified top view of a portion of the transistor array TA1 in the second embodiment. Figure 15 It is Figure 14The diagram shows a schematic cross-sectional view of a transistor TP cut along the DD′ line and viewed in the direction of the arrow. Furthermore, in the second embodiment, the same reference numerals are used for the same parts as in the first embodiment, and descriptions of repeated parts are omitted.

[0092] In the second embodiment, such as Figure 15 As shown, an impurity layer 153 with a high concentration of P-type impurities is formed in the junction region between the P-type semiconductor substrate S and the insulating layer STI. Furthermore, in the second embodiment, no N-type well is provided on the surface of the semiconductor substrate S; therefore, no contact portion CS for applying a high voltage to the N-type well is provided.

[0093] [Effects of the second implementation method]

[0094] According to the second embodiment, in addition to the effects of the first embodiment, since a high concentration of P-type impurity layer 153 is formed on the bottom surface of the insulating layer STI, it is difficult to form an inversion layer near the bottom of the insulating layer STI even when a high voltage Vpgmh is applied to the gate electrodes 181 and 182 of the transistor Tr. Therefore, it is not necessary to apply a high voltage Vpgm to Vpgmh to the surface of the semiconductor substrate S as in the first embodiment, and the contact portion CS for this purpose can be omitted. As a result, further integration of the circuit can be achieved.

[0095] [Third Implementation]

[0096] Figure 16 This is a magnified top view of a portion of the transistor array TA1 in the third embodiment. Figure 17 It is Figure 16 The diagram shows a schematic cross-sectional view of a single transistor TP cut along line EE′ and viewed in the direction of the arrow. Furthermore, in the third embodiment, the same reference numerals are used for the same parts as in the first embodiment, and descriptions of repeated parts are omitted.

[0097] In the third embodiment, based on the first embodiment, in order to apply a voltage to the body of the semiconductor layer 160, impurity layers 166 and 167, which are doped with a high concentration of N-type impurities, are provided at both ends of the semiconductor layer 160 in the Y direction. Contact portions CS8 and CS9 are respectively connected to the impurity layers 166 and 167. A voltage Vss (0V) is applied to the contact portions CS8 and CS9, for example.

[0098] [Effects of the third embodiment]

[0099] According to the third embodiment, in addition to the effects of the first embodiment, since a bias voltage is applied to the body of the semiconductor layer 160, the reverse bias characteristics can be further improved, thereby stabilizing the operation of the transistor Tr.

[0100] [Fourth Implementation]

[0101] Figure 18 This is a magnified top view of a portion of the transistor array TA1 in the fourth embodiment. Furthermore, in the fourth embodiment, the same reference numerals are used for the same parts as in the first embodiment, and descriptions of repeated parts are omitted.

[0102] The insulating layer STI of the fourth embodiment includes a plurality of insulating regions STIc arranged in the X and Y directions corresponding to two adjacent transistor pairs TP in the X direction. The insulating regions STIc are formed in a generally rectangular shape. Two adjacent semiconductor layers 160 in the X direction are formed on each insulating region STIc. The two semiconductor layers 160 are formed in a region on the upper surface of one insulating region STIc, thereby insulating it from the semiconductor substrate S.

[0103] [Fifth Implementation]

[0104] Figure 19 This is a magnified top view of a portion of the transistor array TA1 in the fifth embodiment. Furthermore, in the fifth embodiment, the same reference numerals are used for the same parts as in the first embodiment, and descriptions of repeated parts are omitted.

[0105] The insulating layer STI of the fourth embodiment includes a plurality of insulating regions STId extending in the Y direction and arranged in the X direction, corresponding to a plurality of transistor pairs TP arranged in the Y direction. A plurality of semiconductor layers 160 arranged in the Y direction are formed on each insulating region STId. These plurality of semiconductor layers 160 are formed in a region located on the upper surface of one insulating region STId, thereby insulating it from the semiconductor substrate S.

[0106] [Effects of the 4th and 5th Embodiments]

[0107] By arranging multiple transistor pairs TP on a shared insulating region STIc, STId as in these fourth and fifth embodiments, the spacing between transistor pairs TP on the insulating region STIc, STId can be further reduced, enabling further high integration.

[0108] The insulating layer STI is manufactured as follows: A trench T is formed in a semiconductor substrate S. The insulating layer STI is then filled into the trench T. The surface of the insulating layer STI is planarized, for example, by CMP (chemical mechanical polishing). However, if the area of ​​the insulating layer STI is too large relative to the surface area of ​​the semiconductor substrate S, dishing will occur. Therefore, within a predetermined upper limit, the shared use of the insulating layer STI for multiple transistor pairs TP can be appropriately achieved.

[0109] [other]

[0110] While embodiments 1 to 5 have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, in the above embodiments, two transistors Tr are formed from one semiconductor layer 160, but four transistors Tr can also be formed from one cross-shaped semiconductor layer. Furthermore, while the above embodiments exemplify N-channel high-voltage transistors for driving semiconductor memory devices, these embodiments can also be applied to P-channel high-voltage transistors by reversing the polarity. Moreover, the above embodiments can also be applied to low-voltage P-type or N-type transistors. Furthermore, the above embodiments can also be applied to semiconductor devices other than semiconductor memory devices. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: Semiconductor substrate; A first insulating layer is formed from the main surface of the semiconductor substrate toward the inner side of the semiconductor substrate; and Transistors are formed on the first insulating layer. The transistor has: The first semiconductor layer is formed on the first insulating layer and is insulated from the semiconductor substrate, and includes a first region, a second region and a third region arranged sequentially along a first direction along the main surface of the semiconductor substrate; A second insulating layer is disposed on the second region of the first semiconductor layer; and A first conductive layer is disposed on the second insulating layer. A first contact portion is connected to the first region of the first semiconductor layer. A second contact portion is connected to the third region of the first semiconductor layer. A third contact portion is connected to the first conductive layer. The semiconductor device also includes: A first impurity layer of a first conductivity type is disposed in the first region of the first semiconductor layer; A second impurity layer of a second conductivity type is disposed in the second region of the first semiconductor layer; A third impurity layer of a first conductivity type is disposed in the third region of the first semiconductor layer; and A fourth impurity layer of the first conductivity type is disposed in the region of the semiconductor substrate that is in contact with the first insulating layer. A fourth contact portion is connected to the portion of the fourth impurity layer that appears on the main surface of the semiconductor substrate. A voltage greater than or equal to the voltage applied to the second contact portion is applied to the fourth contact portion.

2. A semiconductor device comprising: Semiconductor substrate; A first insulating layer is formed from the main surface of the semiconductor substrate toward the inner side of the semiconductor substrate; and Transistors are formed on the first insulating layer. The transistor has: The first semiconductor layer is formed on the first insulating layer and is insulated from the semiconductor substrate, and includes a first region, a second region and a third region arranged sequentially along a first direction along the main surface of the semiconductor substrate; A second insulating layer is disposed on the second region of the first semiconductor layer; and A first conductive layer is disposed on the second insulating layer. A first contact portion is connected to the first region of the first semiconductor layer. A second contact portion is connected to the third region of the first semiconductor layer. A third contact portion is connected to the first conductive layer. The semiconductor device also includes: A first impurity layer of a first conductivity type is disposed in the first region of the first semiconductor layer; A second impurity layer of a second conductivity type is disposed in the second region of the first semiconductor layer; A third impurity layer of a first conductivity type is disposed in the third region of the first semiconductor layer; and The fifth impurity layer of the second conductivity type is disposed in the region of the semiconductor substrate that is in contact with the first insulating layer.

3. The semiconductor device according to claim 1, The first semiconductor layer includes a fourth region. The first region is located between the second region and the fourth region. A sixth impurity layer of a second conductivity type disposed in the fourth region of the first semiconductor layer is provided. A fifth contact portion is connected to the sixth impurity layer.

4. The semiconductor device according to claim 1 or 2, It also includes a memory cell array electrically connected to the transistor.

5. A semiconductor device comprising: Semiconductor substrate; A first insulating layer is disposed in a groove formed from the main surface of the semiconductor substrate toward the inner side of the semiconductor substrate; and Multiple transistor pairs are formed on the first insulating layer and arranged in a first direction along the main surface of the semiconductor substrate and in a second direction intersecting the first direction and along the main surface. Each of the plurality of transistors has: The first semiconductor layer is formed on the first insulating layer and is insulated from the semiconductor substrate, and includes a first region, a second region, a third region, a fourth region and a fifth region arranged sequentially along a first direction along the main surface of the semiconductor substrate; The second insulating layer is disposed on the second region and the fourth region of the first semiconductor layer, respectively; and The first conductive layer is disposed on the second insulating layer. A first contact portion is connected to the first region of the first semiconductor layer. A second contact portion is connected to the third region of the first semiconductor layer. The first conductive layer in the second region is connected to the third contact portion. A fifth contact portion is connected in the fifth region of the first semiconductor layer. The first conductive layer in the fourth region is connected to the sixth contact portion. The portions corresponding to the first to third regions constitute the first transistor, and the portions corresponding to the third to fifth regions constitute the second transistor. The semiconductor device further includes a memory cell array having multiple memory blocks electrically connected to the first transistor and the second transistor. The plurality of transistor pairs include: The first transistor pair; The second transistor pair is adjacent to the first transistor pair in the first direction; The third transistor pair is adjacent to the first transistor pair in the second direction; and The fourth transistor pair is adjacent to the second transistor pair in the second direction and to the third transistor pair in the first direction. The first transistor of the first transistor pair, which is located on the side opposite to the second transistor, the second transistor of the second transistor pair, which is located on the side opposite to the first transistor, the first transistor of the third transistor pair, which is located on the side opposite to the fourth transistor, and the second transistor of the fourth transistor pair, which is located on the side opposite to the third transistor, are electrically connected to the same memory block of the memory cell array.

6. The semiconductor device according to claim 5, The first insulating layer comprises: Four first insulating regions are arranged in the first direction and the second direction, corresponding to the first to fourth transistor pairs, respectively; and Two second insulating regions are respectively disposed between two adjacent first insulating regions in the second direction and connected to these two first insulating regions.

7. The semiconductor device according to claim 5 or 6, The first insulating layer comprises: A plurality of first insulating regions are arranged corresponding to the plurality of transistor pairs in the first direction and the second direction, respectively; and Multiple second insulating regions are respectively disposed between two adjacent first insulating regions in the second direction, and connected to these two first insulating regions. The main surface of the semiconductor substrate includes a sixth region surrounded by the plurality of first insulating regions and the plurality of second insulating regions. The first transistor and the second transistor, which are electrically connected to the same memory block, are arranged in the first direction, separated by the sixth region.

8. The semiconductor device according to claim 7, A fourth contact portion is connected to the sixth region of the semiconductor substrate. During a write operation on the same memory block, a voltage greater than or equal to the voltage applied to the second contact is applied to the fourth contact.

9. The semiconductor device according to claim 5, The first insulating layer comprises: A third insulating region is provided corresponding to the first transistor pair and the third transistor pair; and The fourth insulating region is provided corresponding to the second transistor pair and the fourth transistor pair.

10. The semiconductor device according to claim 5, The first insulating layer comprises: A fifth insulating region is provided corresponding to the first transistor pair and the second transistor pair; and The sixth insulating region is provided corresponding to the third transistor pair and the fourth transistor pair.

Images