A Successive Approximation Digital-to-Analog Converter Based on Residual Accumulated Charge

Abstract

The present invention discloses a successive approximation digital-to-analog converter based on residual accumulated charge, which belongs to the technical field of analog-to-digital conversion integrated circuits. After the analog-to-digital converter compares the SAR ADC successively, it does not immediately reset the DAC capacitor array, but obtains its residual voltage charge; the residual voltage charge is stored and transferred through a capacitor switch circuit, and is accumulated together with the next sampling input, and sent to the DAC comparison array for the next logical conversion. After multiple accumulations, the residual voltage charge can be identified, thereby improving the resolution. The present invention adopts a method of residual voltage charge accumulation, which can improve the accuracy of the ADC without increasing the area, and can dynamically adjust the convergence time by the number of accumulations. The present invention discloses a method for improving the resolution of a SAR ADC applied to a low-frequency signal environment by using residual voltage charge accumulation.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital conversion integrated circuits, and more specifically, relates to a successive approximation digital-to-analog converter based on residual accumulated charge. Background Art

[0002] Analog-Digital Converter (ADC) is a system that converts an analog signal, such as sound picked up by a microphone or light entering a digital camera, into a digital signal. It usually refers to an electronic component that converts an analog signal into a digital signal. The usual analog-to-digital converter converts an input voltage signal into an output digital signal. Since the digital signal itself has no practical meaning, it only represents a relative size. Therefore, any analog-to-digital converter requires a reference analog quantity as a conversion standard. The more common reference standard is the maximum convertible signal size. The output digital quantity represents the size of the input signal relative to the reference signal.

[0003] For every bit of accuracy improvement of traditional charge redistribution SAR-ADC, the area of ​​the capacitor array consumed almost doubles, so the accuracy of SAR-ADC is generally around 12 bits. Summary of the invention

[0004] In view of the above defects or improvement needs of the prior art, the present invention provides a successive approximation digital-to-analog converter based on residual accumulated charge, the purpose of which is to improve the accuracy of the ADC without increasing the area by using the residual voltage charge accumulation method, and to dynamically adjust the convergence time by the number of accumulations, thereby solving the technical problem that a large amount of capacitor arrays are often consumed to improve the accuracy of SAR-ADC.

[0005] To achieve the above object, according to one aspect of the present invention, a successive approximation digital-to-analog converter based on residual accumulated charge is provided, comprising:

[0006] Successive approximation analog-to-digital conversion SAR-ADC circuit is used to convert the tth input analog value V in(t) and the residual voltage V corresponding to the t-1th time x(t-1) Loaded onto the capacitor array, so that the SAR logic module will be identified for the tth time analog value V D(t) The analog-to-digital conversion obtains the N-bit D (t) , the corresponding residual voltage for the tth time is V x(t) =V in(t) +V x(t-1) -V D(t) , V in(t) =V in(t+1) , V x(0) =0; t∈[1,M];

[0007] The switched capacitor circuit is connected to one side of the lower plate of the capacitor array and is used to convert the t+1th input analog value V in(t+1) and the residual voltage V corresponding to the tth time x(t) Superposition is performed to obtain the superimposed analog quantity {V in(t+1) +V x(t)};

[0008] A buffer driving circuit is connected to the switch capacitor circuit and the upper plate of the capacitor array, and is used to convert the superimposed analog quantity {V in(t+1) +V x(t)} voltage is transmitted to the SAR-ADC circuit to convert the superimposed analog quantity {V in(t+1) +V x(t)}The corresponding identified analog quantity V D(t+1) Converted into N-bit digital code D (t+1) ;

[0009] An averaging circuit is connected to the SAR-ADC circuit and is used to average the M digital codes {D (t) , D (t+1) , ..., D (t+M-1)}Average to get N+M 1 / 2 The target digital code of the bit is increased from N to N+M. 1 / 2 Bit.

[0010] In one embodiment, the switched capacitor circuit comprises:

[0011] The first capacitor C1 is used to sample the t+1th input analog value V in(t+1) The corresponding charge;

[0012] The second capacitor C2 is used to sample the residual voltage V corresponding to the tth time x(t) The corresponding charge;

[0013] An operational amplifier connected to the first capacitor and the second capacitor, used to convert the t+1th input analog value V in(t) and the residual voltage V corresponding to the tth time x(t) To overlay;

[0014] The third capacitor C3 is loaded on the negative input terminal and the output terminal of the operational amplifier and is used to maintain the superimposed analog value {V in(t+1) +V x(t)} corresponding to the charge amount, so that the output end of the operational amplifier will be the superimposed analog quantity {V in(t+1) +V x(t)}Sent to the SAR-ADC circuit through the buffer driving circuit for analog-to-digital conversion.

[0015] In one embodiment, the buffer driving circuit is a buffer circuit, which is used to convert the superimposed analog value {V in(t+1) +V x(t)} is transmitted to the SAR-ADC circuit to enhance the driving capability of the switched capacitor circuit.

[0016] In one embodiment, the SAR-ADC circuit comprises:

[0017] The capacitor array is used to sample the superimposed analog quantity {V in(t+1) +V x(t)};

[0018] A comparator is connected to one side of the lower plate of the capacitor array and is used to convert the superimposed analog quantity {V in(t+1) +V x(t)} and the set voltage V CM The digital code corresponding to the analog quantity is obtained by successive comparison; the residual voltage V corresponding to the t+1 input is inputted by virtual short x(t+1) -V CM The corresponding amount of charge is transferred from the capacitor array to the second capacitor C2 and the fourth capacitor C4 connected in parallel therewith;

[0019] A SAR logic module is connected to the comparator and the lower plate of the capacitor array, and is used to convert the comparison results of the comparator into an N-bit digital code D. (t+1) ; Keep digital code D (t+1) Output, the voltage of the upper plate of the capacitor array is the voltage corresponding to the digital code, and the lower plate of the capacitor array is fed back to V CM According to the charge conservation of the lower plate of the capacitor, the lower plate will transfer a residual charge corresponding to the residual voltage to C2 and C4.

[0020] According to another aspect of the present invention, a successive approximation digital-to-analog conversion method based on residual accumulated charge is provided, which is used to perform the above method; comprising:

[0021] Step S1: Use the SAR-ADC circuit to convert the tth input analog value V in(t) and the residual voltage V corresponding to the t-1th time x(t-1) Transfer to the capacitor array so that the SAR logic module can transfer the tth recognized analog value V D(t) The analog-to-digital conversion obtains the N-bit D (t) , the corresponding residual voltage for the tth time is V x(t) =V in(t) +V x(t-1) -VD(t) , V in(t) =V in(t+1) , V x(0) =0; t∈[1,M];

[0022] Step S2: Use the switched capacitor circuit to convert the t+1th input analog value V in(t+1) and the residual voltage V corresponding to the tth time x(t) Superposition is performed to obtain the superimposed analog quantity {V in(t+1) +V x(t)};

[0023] Step S3: Using a buffer drive circuit to in(t+1) +V x(t)} is transmitted back to the SAR-ADC circuit to convert the superimposed analog value {V in(t+1) +V x(t)}The corresponding identified analog quantity V D(t+1) Converted into N-bit digital code D (t+1) ;

[0024] Step S4: Using an averaging circuit to average the M digital codes {D (t) , D (t+1) , ..., D (t+M-1)}Average to get N+M 1 / 2 The target digital code of the bit is increased from N to N+M. 1 / 2 Bit.

[0025] In one embodiment, the residual voltage V corresponding to the tth time is obtained in the successive approximation digital-to-analog conversion method based on the residual accumulated charge. x(t) The method is:

[0026] Get the tth conversion digital code D (t) After that, the upper plate switch of the capacitor array is kept unchanged, and the residual voltage charge in the capacitor array is transferred to the parallel C2 and C4 connected to the switch capacitor circuit and one side of the lower plate of the capacitor array through the virtual short function of the operational amplifier.

[0027] In one embodiment, the step S1 comprises:

[0028] By short-circuiting the output terminal and the negative input terminal of the comparator in the SAR-ADC circuit, the residual voltage charge is transferred to the next sampling process until the charge amount less than 1LSB is accumulated to exceed 1LSB and then recognized by the comparator;

[0029] By virtually shorting the comparator, the residual voltage V corresponding to the t-time input x(t) A corresponding amount of charge is transferred from the capacitor array to the switch capacitor array.

[0030] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0031] (1) After the successive approximation digital-to-analog converter based on residual accumulated charge provided by the present invention compares the SAR-ADC successively, it does not immediately reset the DAC capacitor array, but obtains its residual voltage charge; the residual voltage charge is stored and transferred through the capacitor switch circuit, and is accumulated together with the next sampling input, and sent to the DAC comparison array for the next logical conversion. After multiple accumulations of residual voltage charge, it can be identified, thereby improving the resolution. In view of this idea of ​​residual voltage accumulation, the present invention proposes a feasible digital control logic and circuit implementation.

[0032] (2) The present invention discloses a method for improving the resolution of a SAR-ADC applied to a low-frequency signal environment by accumulating residual voltage charge. The low frequency here refers to a frequency far lower than the sampling signal, such as less than 1kHz. The residual voltage of each conversion is included in the next conversion, so that each residual voltage participates in the next conversion. The N-bit coarse quantization residual value participates in m changes, and each residual value is 1 / N 2 The value within the step, the total residual value of m times accumulated reaches m / N 2 If statistically distributed noise is not considered, then m transformations can increase the bit length from N to N+M 1 / 2 . BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a schematic structural diagram of a successive approximation digital-to-analog converter based on residual accumulated charge provided by an embodiment of the present invention;

[0034] Figure 2 The flowchart of a successive approximation digital-to-analog conversion method based on residual accumulated charge provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] like Figure 1 and Figure 2 As shown, the present invention provides a successive approximation digital-to-analog converter based on residual accumulated charge, comprising:

[0037] Successive approximation analog-to-digital conversion SAR-ADC circuit is used to convert the tth input analog value V in(t) and the residual voltage V corresponding to the t-1th time x(t-1) Loaded onto the capacitor array, so that the SAR logic module will be identified for the tth time analog value V D(t) The analog-to-digital conversion obtains the N-bit D (t) , the corresponding residual voltage for the tth time is V x(t) =V in(t) +V x(t-1) -V D(t) , V in(t) =V in(t+1) , V x(0) =0; t∈[1,M];

[0038] The switched capacitor circuit is connected to the lower plate of the capacitor array to convert the t+1th input analog value V in(t+1) and the residual voltage V corresponding to the tth time x(t) Superposition is performed to obtain the superimposed analog quantity {V in(t+1) +V x(t)};

[0039] The buffer driving circuit is connected to the switch capacitor circuit and the upper plate side of the capacitor array to convert the superimposed analog quantity {V in(t+1) +V x(t)} is transmitted to the SAR-ADC circuit to convert the superimposed analog quantity {V in(t+1) +V x(t)}The corresponding identified analog quantity V D(t+1) Converted into N-bit digital code D (t+1) ;

[0040] The averaging circuit is connected to the SAR-ADC circuit and is used to convert the M digital codes {D (t) , D (t+1) , ..., D (t+M-1)}Average to get N+M 1 / 2 The target digital code of bits is increased from N to N+M. 1 / 2 Bit.

[0041] by Figure 1 Taking the example of the present invention, the working process of the successive approximation digital-to-analog converter based on residual accumulated charge is described as follows:

[0042] 1. The circuit starts, switches S3 and S5 are closed, switches S0, S1, S2, S4, S6, and S7 are opened, and V in Sampling is performed, and the charge of C1 is: Q 采 =Vin *C1;

[0043] 2. Switch S4 and switch S6 are closed, and switches S0, S1, S2, S3, S5, and S7 are open. At this time, due to the negative feedback of C1, the voltage across C1 is 0, and all the charge of C1 is transferred to C3. Therefore, the output voltage of the op amp is V in ;

[0044] 3. Switch S0 is closed, switch S1, switch S2, switch S3, switch S4, switch S5, switch S6, and switch S7 are opened, and the capacitor array starts sampling. Q 采 =32C*(V in -V CM );

[0045] 4. SAR-ADC starts converting;

[0046] 5. After the SAR-ADC conversion is completed, V X =V CM -V in +Σb i CiT ref / C total , V X The value is very close to V CM In fact, V X -V CM The value of carries the information of residual voltage charge. Theoretically, after the SAR conversion is completed, the residual charge is: Q 残余 =32C(V in -V CM )-Σ(b i *V ref -V X )*Ci;

[0047] 6. After the SAR ADC conversion is completed, the upper plates of the capacitor array are connected to V ref / GND, at this time, it keeps this connection, and then closes the switch S7, and through negative feedback, the lower plate of the capacitor is fed back from Vx to V CM , then due to charge conservation, the lower plate of the capacitor will have (Vx-V CM )*32C charge is transferred to C2 and C4, that is, the residual voltage charge Q 残余 Transfer to C2 and C4. Since C2:C4=1:31, due to the charge sharing principle, the voltage on C2 is the residual voltage Vx-VCM.

[0048] 7. Close switches S1, S5, and S3, and open switches S2, S4, and S6. Then close switches S2, S4, and S6, and open switches S1, S3, and S5, so that the residual voltage information is transmitted along with the next V in It is sent to the capacitor array, and after multiple cycles, the AD conversion accuracy can be greatly improved.

[0049] This AD improves conversion accuracy at the expense of conversion speed, and both the area and power consumption can be made very small, so it is suitable for AD conversion of low-frequency signals.

[0050] In one embodiment, the switched capacitor circuit comprises:

[0051] The first capacitor C1 is used to sample the t+1th input analog value V in(t+1) The corresponding charge;

[0052] The second capacitor C2 is used to sample the residual voltage V corresponding to the tth time x(t) The corresponding charge;

[0053] An operational amplifier connected to the first capacitor and the second capacitor, used to convert the t+1th input analog value V in(t) and the residual voltage V corresponding to the tth time x(t) To overlay;

[0054] The third capacitor C3 is loaded on the negative input terminal and the output terminal of the operational amplifier and is used to maintain the superimposed analog value {V in(t+1) +V x(t)} corresponding to the charge amount, so that the output end of the operational amplifier will be the superimposed analog quantity {V in(t+1) +V x(t)}Sent to the SAR-ADC circuit through the buffer driving circuit for analog-to-digital conversion.

[0055] In one embodiment, the buffer driving circuit is a buffer circuit, which is used to convert the superimposed analog value {V in(t+1) +V x(t)} is transmitted to the SAR-ADC circuit to enhance the driving capability of the switched capacitor circuit.

[0056] In one embodiment, the SAR-ADC circuit comprises:

[0057] The capacitor array is used to sample the superimposed analog quantity {V in(t+1) +V x(t)};

[0058] A comparator is connected to one side of the lower plate of the capacitor array and is used to convert the superimposed analog quantity {Vin(t+1) +V x(t)} and the set voltage V CM The digital code corresponding to the analog quantity is obtained by successive comparison; the residual voltage V corresponding to the t+1 input is inputted by virtual short x(t+1) -V CM The corresponding amount of charge is transferred from the capacitor array to the second capacitor C2 and the fourth capacitor C4 connected in parallel therewith, C4=31C;

[0059] A SAR logic module is connected to the comparator and the lower plate of the capacitor array, and is used to convert the comparison results of the comparator into an N-bit digital code D. (t+1) ; Keep digital code D (t+1) Output, the voltage of the upper plate of the capacitor array is the voltage corresponding to the digital code, and the lower plate of the capacitor array is fed back to V CM According to the charge conservation of the lower plate of the capacitor, the lower plate will transfer a residual charge corresponding to the residual voltage to C2 and C4. Among them, the role of C4 is to distribute the residual voltage charge. Because the size of the capacitor array is 32C, the residual voltage corresponding to its residual voltage charge is V 残量 =Q / (32C). The existence of C4 will make the charge obtained by C2 only Q / 32 (because of the distribution of charge), so the voltage on C2 is also V=(Q / 32) / C, which is the residual voltage.

[0060] According to another aspect of the present invention, a successive approximation digital-to-analog conversion method based on residual accumulated charge is provided, which is used to perform the above method; comprising:

[0061] Step S1: Use the SAR-ADC circuit to convert the tth input analog value V in(t) and the residual voltage V corresponding to the t-1th time x(t-1) Transfer to the capacitor array so that the SAR logic module can transfer the tth recognized analog value V D(t) The analog-to-digital conversion obtains the N-bit D (t) , the corresponding residual voltage for the tth time is V x(t) =V in(t) +V x(t-1) -V D(t) , V in(t) =V in(t+1) , V x(0) =0; t∈[1,M];

[0062] Step S2: Use the switched capacitor circuit to convert the t+1th input analog value V in(t+1) and the residual voltage V corresponding to the tth time x(t) Superposition is performed to obtain the superimposed analog quantity {V in(t+1) +V x(t)};

[0063] Step S3: Using a buffer drive circuit to in(t+1) +V x(t)} is transmitted back to the SAR-ADC circuit to convert the superimposed analog value {V in(t+1) +V x(t)}The corresponding identified analog quantity V D(t+1) Converted into N-bit digital code D (t+1) ;

[0064] Step S4: Using an averaging circuit to average the M digital codes {D (t) , D (t+1) , ..., D (t+M-1)}Average to get N+M 1 / 2 The target digital code of the bit is increased from N to N+M. 1 / 2 Bit.

[0065] The residual value of each conversion is included in the next transformation, so that each residual value participates in the next transformation. The N-bit coarse quantized residual value participates in m changes, and each residual value is 1 / N 2 The value within the step, the total residual value of m times accumulated reaches m / N 2 If statistically distributed noise is not considered, then m transformations can increase the bit length from N to N+M 1 / 2 .

[0066] For example, the residual voltage accumulation SAR-ADC accumulates the residual charge after each conversion for multiple times. Since the signal frequency is low, it is assumed that the signal value remains unchanged within 16 conversion cycles. After the SAR-ADC converts 16 times, the residual charge is accumulated each time until it exceeds 1 LSB, which will affect the conversion result. Assuming that the 16 converted digital quantities are: 10001, 10010, 10001, 10001, 10010, 10001, 10001, 10010, 10001, 10001, 10010, 10001, 10001, 10001, 10001, 10001, 10001, the accumulated digital quantity is: 100010101 divided by 16 (right shift 4 bits): 10001.0101, which generates a 9-bit digital quantity and improves the accuracy by 4 bits, that is, accumulate m times and improve the accuracy by m 1 / 2 Bit.

[0067] For the residual charge accumulation, the residual charge amount is:

[0068] Q 残余 =32C(V in -V CM )-Σ(b i*V ref -V X )*C i ;

[0069] where b i is the digital quantity after conversion.

[0070] In fact, the charge on the lower plate of the capacitor will not escape, that is, the charge is still 32C (V in -V CM ). If the upper plate switch remains unchanged and S7 is closed, the lower plate of the capacitor is virtually shorted from Vx to V due to the virtual short. CM , then due to charge conservation, the lower plate of the capacitor will have (Vx-V CM )*32C charge is transferred to C2 and C4, that is, the residual voltage charge Q 残余 Transfer to C2 and C4. Since C2:C4=1:31, due to the charge sharing principle, the voltage on C2 is the residual voltage Vx-VCM.

[0071] In one embodiment, the residual voltage V corresponding to the tth time is obtained in the successive approximation digital-to-analog conversion method based on the residual accumulated charge. x(t) The method is:

[0072] Get the tth conversion digital code D (t) After that, the upper plate switch of the capacitor array is kept unchanged, and the residual voltage charge in the capacitor array is transferred to the parallel C2 and C4 connected to the switch capacitor circuit and one side of the lower plate of the capacitor array through the virtual short function of the operational amplifier.

[0073] In one embodiment, the step S1 comprises:

[0074] By short-circuiting the output terminal and the negative input terminal of the comparator in the SAR-ADC circuit, the residual voltage charge is transferred to the next sampling process until the charge amount less than 1LSB is accumulated to exceed 1LSB and then recognized by the comparator;

[0075] By virtually shorting the comparator, the residual voltage V corresponding to the t-time input x(t) A corresponding amount of charge is transferred from the capacitor array to the switch capacitor array.

[0076] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A successive approximation digital-to-analog converter based on residual accumulated charge, characterized in that: include: Successive approximation analog-to-digital conversion SAR-ADC circuit is used to convert the tth input analog value V in（t) and the residual voltage V corresponding to the t-1th time x（t-1） Loaded onto the capacitor array, so that the SAR logic module will be identified for the tth time analog value V D（t） The analog-to-digital conversion obtains the N-bit D (t) , the corresponding residual voltage for the tth time is V x（t） =V in（t) +V x（t-1） -V D（t） , V in（t) =V in（t+1) , V x（0） =0; t∈[1,M]; The switched capacitor circuit is connected to one side of the lower plate of the capacitor array and is used to convert the t+1th input analog value V in（t+1） and the residual voltage V corresponding to the tth time x（t） Superposition is performed to obtain the superimposed analog quantity {V in（t+1） +V x（t） }; A buffer driving circuit is connected to the switch capacitor circuit and the upper plate of the capacitor array, and is used to convert the superimposed analog quantity {V in（t+1） +V x（t） } voltage is transmitted to the SAR-ADC circuit to convert the superimposed analog quantity {V in（t+1） +V x（t） }The corresponding identified analog quantity V D（t+1） Converted into N-bit digital code D (t+1) ; An averaging circuit is connected to the SAR-ADC circuit and is used to average the M digital codes {D (t) , D (t+1) , ..., D (t+M-1) }Average to get N+M 1 / 2 The target digital code of the bit is increased from N to N+M. 1 / 2 Bit; The switched capacitor circuit comprises: The first capacitor C1 is used to sample the t+1th input analog value V in（t+1） The corresponding charge; The second capacitor C2 is used to sample the residual voltage V corresponding to the tth time x（t） The corresponding charge; An operational amplifier connected to the first capacitor and the second capacitor, used to convert the t+1th input analog value V in（t） and the residual voltage V corresponding to the tth time x（t） To overlay; The third capacitor C3 is loaded on the negative input terminal and the output terminal of the operational amplifier and is used to maintain the superimposed analog value {V in（t+1） +V x（t） } corresponding to the charge amount, so that the output end of the operational amplifier will be the superimposed analog quantity {V in（t+1） +V x（t） }Sent to the SAR-ADC circuit through the buffer driving circuit for analog-to-digital conversion.

2. The successive approximation digital-to-analog converter based on residual accumulated charge according to claim 1, characterized in that: The buffer driving circuit is a buffer circuit, which is used to convert the superimposed analog quantity {V in（t+1） +V x（t） } is transmitted to the SAR-ADC circuit to enhance the driving capability of the switched capacitor circuit.

3. The successive approximation digital-to-analog converter based on residual accumulated charge according to claim 1, characterized in that: The SAR-ADC circuit comprises: The capacitor array is used to sample the superimposed analog quantity {V in（t+1） +V x（t） }; A comparator is connected to one side of the lower plate of the capacitor array and is used to convert the superimposed analog quantity {V in（t+1） +V x（t） } and the set voltage V CM The digital code corresponding to the analog quantity is obtained by successive comparison; the residual voltage V corresponding to the t+1 input is inputted by virtual short x（t+1） -V CM The corresponding amount of charge is transferred from the capacitor array to the second capacitor C2 and the fourth capacitor C4 connected in parallel therewith; A SAR logic module is connected to the comparator and the lower plate of the capacitor array, and is used to convert the comparison results of the comparator into an N-bit digital code D. （t+1） ; Keep digital code D （t+1） Output, the voltage of the upper plate of the capacitor array is the voltage corresponding to the digital code, and the lower plate of the capacitor array is fed back to V CM According to the charge conservation of the lower plate of the capacitor, the lower plate will transfer a residual charge corresponding to the residual voltage to C2 and C4.

4. A successive approximation digital-to-analog conversion method based on residual accumulated charge, characterized in that: Used to perform the method according to any one of claims 1 to 3; comprising: Step S1: Use the SAR-ADC circuit to convert the tth input analog value V in（t) and the residual voltage V corresponding to the t-1th time x（t-1） Transfer to the capacitor array so that the SAR logic module can transfer the tth recognized analog value V D（t） The analog-to-digital conversion obtains the N-bit D (t) , the corresponding residual voltage for the tth time is V x（t） =V in（t) +V x（t-1） -V D（t） , V in（t) =V in（t+1) , V x（0） =0; t∈[1,M]; Step S2: Use the switched capacitor circuit to convert the t+1th input analog value V in（t+1） and the residual voltage V corresponding to the tth time x（t） Superposition is performed to obtain the superimposed analog quantity {V in（t+1） +V x（t） }; Step S3: Using a buffer drive circuit to in（t+1） +V x（t） } is transmitted back to the SAR-ADC circuit to convert the superimposed analog value {V in（t+1） +V x（t） }The corresponding identified analog quantity V D（t+1） Converted into N-bit digital code D (t+1) ; Step S4: Using an averaging circuit to average the M digital codes {D (t) , D (t+1) , ..., D (t+M-1) }Average to get N+M 1 / 2 The target digital code of the bit is increased from N to N+M. 1 / 2 Bit.

5. The method for successive approximation digital-to-analog conversion based on residual accumulated charge according to claim 4, characterized in that: The residual voltage V corresponding to the tth time is obtained in the successive approximation digital-to-analog conversion method based on the residual accumulated charge. x（t） The method is: Get the tth conversion digital code D (t) After that, the upper plate switch of the capacitor array is kept unchanged, and the residual voltage charge in the capacitor array is transferred to the parallel C2 and C4 connected to the switch capacitor circuit and one side of the lower plate of the capacitor array through the virtual short function of the operational amplifier.

6. The method for successive approximation digital-to-analog conversion based on residual accumulated charge according to claim 4, characterized in that: The step S1 comprises: By short-circuiting the output terminal and the negative input terminal of the comparator in the SAR-ADC circuit, the residual voltage charge is transferred to the next sampling process until the charge amount less than 1LSB is accumulated to exceed 1LSB and then recognized by the comparator; By virtually shorting the comparator, the residual voltage V corresponding to the t-time input x（t） A corresponding amount of charge is transferred from the capacitor array to the switched capacitor circuit.

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