A Serdes Dynamic Threshold Bitstream Synchronization Detection Method and System

Abstract

The present invention discloses a Serdes dynamic threshold bitstream synchronization detection method and system, and the method includes the following steps: (1) Using a shift register structure to generate K-code sampling detection data; (2) Detecting m groups of data according to the data structure of the K-code sampling data; (3) Determining the K-code synchronization state and the unlocked state by a dynamic threshold detection mechanism; (4) Outputting the K-code synchronization data. The structure of the present invention is simple and easy to implement. The circuit implementing the K-code synchronization detection method through the dynamic threshold detection mechanism can quickly lock in a good channel condition; in a poor channel environment, it can effectively avoid false locking and has the characteristics of strong anti-interference ability, etc., meeting the requirements of circuit design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a Serdes dynamic threshold code stream synchronization detection method and system. Background Art

[0002] The high-speed serial data stream on the SerDes needs to be re-serialized and converted into multiple bytes of parallel data at the receiving end, which requires a special sequence, namely the K code. The receiver searches for a specific ratio sequence (K code) in the input data stream. If the sequence is found, the deserializer adjusts the character boundary to match the detected K code character sequence, which is referred to as K code synchronization.

[0003] In SerDes, data is separated by K code sequences, which can be set by the user. The receiving end input scans and searches for a specific bit sequence in the data stream. If the sequence is found, the deserializer adjusts the character boundary to match the detected K code sequence, and at the same time performs synchronization judgment and loss of lock judgment on the synchronization k_flag signal through a dynamic threshold detection mechanism, so as to achieve rapid locking of SerDes K code detection in good channel environments and avoid false locking in poor channel environments. The existing K code detection generally detects synchronization or loss of lock, which means it is in synchronization lock or state, and does not have a dynamic threshold detection judgment mechanism. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide a Serdes dynamic threshold code stream synchronization detection method and system, which has a dynamic threshold detection of the K code synchronization lock signal and a loss of lock judgment mechanism, and has the characteristics of fast locking and avoiding false locking.

[0005] The technical solution of the present invention is: a Serdes dynamic threshold code stream synchronization detection method, comprising the following steps:

[0006] (1) Using a shift register structure to generate K code detection sampling data;

[0007] (2) According to the data structure of K code sampling data, m groups of data are detected;

[0008] (3) Determine the K-code synchronization lock state and unlock state;

[0009] (4) Output K code synchronization data.

[0010] In the step (1), the number of shift registers is 2n, where n is the data bit width of a single channel of the SerDes.

[0011] In the step (2), m≥n.

[0012] The specific process of the step (2) for detecting m groups of data is as follows: two consecutive groups of input data are packaged and combined to generate a sampling synchronization data signal Sample_data[2n-1:0] with a data bit width of 2n-1; then the m groups of data, i.e., Sample_data[0:n-1], Sample_data[1:n], ..., Sample_data[m-2:2n-3], Sample_data[m-1:2n-2], are synchronously aligned and detected with the K code alignment vector in parallel to generate m synchronization indication signals, i.e., k_flag0, k_flag1, ..., k_flag(m-1), wherein the m synchronization indication signals include a real synchronization signal, and the m synchronization indication signals are logically or-operated to generate the synchronization signal k_flag of the SerDes channel data.

[0013] In the step (3), the SerDes K code synchronization k_flag signal is subjected to synchronization lock determination and lock loss determination through a dynamic threshold detection mechanism.

[0014] The specific process of determining the K code synchronization lock state and the unlock state in step (3) is as follows: a dynamic threshold detection mechanism is used to perform threshold determination on the k_flag signal, and an initial threshold L is set; when k_flag=1, each time a clock rising edge arrives, the number of sampled k_flags is accumulated by 1, and the threshold L is reduced by 1; until the number of k_flags is equal to or greater than the dynamic threshold, the SerDes channel data K code is determined to be synchronized, and align_found_int=1; when determining the unlock, in the SerDes channel data K code synchronization state, that is, when align_found_int=1, when k_flag=0, the unlock signal will not be output immediately. If k_flag=0 and is maintained for T clock cycles, the number of k_flags is reduced by 1, and the threshold is increased by 1 at the same time, until the number of k_flags is less than the dynamic threshold, the synchronization is determined to have failed, and the unlock indication signal align_found_int=0 is output.

[0015] A Serdes dynamic threshold code stream synchronization detection system comprises a sampling data establishment module, a detection module, a determination module and an output module; the sampling data establishment module adopts a shift register structure to generate K code detection sampling data; the detection module detects m groups of data according to the data structure of the K code sampling data; the determination module determines the K code synchronization locking state and unlocking state; and the output module outputs the K code synchronization data.

[0016] The specific process of detecting the m groups of data is as follows: two consecutive groups of input data are packaged and combined to generate a sampling synchronization data signal Sample_data[2n-1:0] with a data bit width of 2n-1; then the m groups of data, i.e., Sample_data[0:n-1], Sample_data[1:n], ...Sample_data[m-2:2n-3], Sample_data[m-1:2n-2], are synchronously aligned and detected with the K code alignment vector in parallel to generate m-paths, i.e., k_flag0, k_flag1, ...k_flag(m-1) synchronization indication signals, wherein the m-path synchronization indication signals include a real synchronization signal, and the m-path synchronization indication signals are logically or operated to generate the synchronization signal k_flag of the SerDes channel data.

[0017] The dynamic threshold detection mechanism is used to perform synchronization lock determination and lock loss determination on the SerDes K code synchronization k_flag signal.

[0018] The specific process of determining the K code synchronization lock state and the unlock state is as follows: a dynamic threshold detection mechanism is used to perform threshold determination on the k_flag signal, and an initial threshold L is set; when k_flag=1, each time a clock rising edge arrives, the number of sampled k_flags is accumulated by 1, and the threshold L is reduced by 1; until the number of k_flags is equal to or greater than the dynamic threshold, the SerDes channel data K code is determined to be synchronized, and align_found_int=1; when determining the unlock, in the SerDes channel data K code synchronization state, that is, when align_found_int=1, when k_flag=0, the unlock signal will not be output immediately. If k_flag=0 and is maintained for T clock cycles, the number of k_flags is reduced by 1, and the threshold is increased by 1 at the same time, until the number of k_flags is less than the dynamic threshold, the synchronization is determined to fail, and the unlock indication signal align_found_int=0 is output.

[0019] The beneficial effects of the present invention compared with the prior art are:

[0020] (1) Using a shift register structure to generate sampling detection data, for n-bit channel data, only m groups of data need to be used for synchronization detection to generate m synchronization indication signals. This method can improve synchronization efficiency;

[0021] (2) The SerDes K code synchronization k_flag signal is synchronized and determined through a dynamic threshold detection mechanism. The traditional SerDes K code synchronization adopts a direct determination method. The deserializer finds the sequence, adjusts the character boundary to match the detected K code sequence, and outputs a synchronization lock signal. The k_flag signal is threshold determined by using a dynamic threshold detection mechanism, and the initial threshold L is set; when k_flag = 1, each clock rising edge arrives, the number of sampled k_flags is accumulated by 1, and the threshold L is reduced by 1; until the number of k_flags is equal to or greater than the dynamic threshold, the SerDes channel data K code is determined to be synchronized, and align_found_int = 1; in the case of a good channel environment, it can be locked quickly to improve synchronization efficiency.

[0022] (3) The SerDes K code synchronization k_flag signal is judged to be unlocked through a dynamic threshold detection mechanism. When the SerDes channel data K code is in synchronization state during the unlock judgment, that is, when align_found_int=1, when k_flag=0, the unlock signal will not be output immediately. If k_flag=0 and it is maintained for T clock cycles, the k_flag count is reduced by 1, and the threshold is increased by 1 at the same time, until the k_flag count is less than the dynamic threshold, the synchronization is judged to have failed, and the unlock indication signal align_found_int=0 is output. In the case of a poor channel environment, it can effectively avoid false locking. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Construct a flow chart for the test vector of the present invention;

[0024] Figure 2 Generates module schematics for test vector hardware. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below with reference to the accompanying drawings and specific implementations:

[0026] like Figure 1 As shown, the method of the present invention comprises the following steps:

[0027] (1) A shift register structure is used to generate K code detection sampling data. The number of shift registers is 2n, where n is the single-channel data width of SerDes. During the operation of SerDes, data transmission and reception are performed randomly. Therefore, in order to include a complete set of K codes in a set of sampled detection data, the transmission data of SerDes needs to be packaged. Through the shift register structure, the 2n data method is used to complete the packaging of the detection sampling data.

[0028] (2) Perform synchronous detection on m groups of data according to the K code sampling data structure;

[0029] Two consecutive groups of input data are packaged and combined to generate a sampling synchronization data signal Sample_data[2n-1:0] with a data bit width of 2n-1; then, the m groups of data, namely Sample_data[0:n-1], Sample_data[1:n], ...Sample_data[m-2:2n-3], Sample_data[m-1:2n-2], are synchronously aligned and detected with the K code alignment vector in parallel to generate m synchronization indication signals, namely k_flag0, k_flag1, ...k_flag(m-1), wherein the m synchronization indication signals include one real synchronization signal, and the m synchronization indication signals are logically or-operated to generate the synchronization signal k_flag of the SerDes channel data.

[0030] (3) Determine the K code synchronization state and unlock state through a dynamic threshold detection mechanism;

[0031] A dynamic threshold detection mechanism is used to perform threshold determination on the k_flag signal, and an initial threshold L is set; when k_flag=1, each time a rising edge of the clock arrives, the number of sampled k_flags is accumulated by 1, and the threshold L is reduced by 1; until the number of k_flags is equal to or greater than the dynamic threshold, the SerDes channel data K code is determined to be synchronized, and align_found_int=1; when determining the loss of lock, when the SerDes channel data K code is in the synchronization state, that is, when align_found_int=1, when k_flag=0, the loss of lock signal will not be output immediately. If k_flag=0 and is maintained for T clock cycles, the number of k_flags is reduced by 1, and the threshold is increased by 1 at the same time, until the number of k_flags is less than the dynamic threshold, the synchronization is determined to have failed, and the loss of lock indication signal align_found_int=0 is output.

[0032] The present invention also relates to a Serdes dynamic threshold code stream synchronization detection system, comprising a sampling data establishment module, a detection module, a determination module and an output module; the sampling data establishment module adopts a shift register structure to generate K code detection sampling data; the detection module detects m groups of data according to the data structure of the K code sampling data; the determination module determines the K code synchronization locking state and unlocking state; the output module outputs the K code synchronization data.

[0033] Example:

[0034] Figure 2 Taking the SerDes single channel data bit width of 10 bits as an example, the K code uses K28.5, namely 8'b1011_1100, as the synchronization code.

[0035] Step 1: Use a shift register structure to generate K code detection sampling data. The number of shift registers is 2*10, and 10 is the single-channel data width of SerDes. During the working process of SerDes, the data is sent and received randomly. Therefore, in order to include a complete set of K codes in a set of sampled detection data, the transmission data of SerDes needs to be packaged and processed. The packaging of the detection sampling data is completed through the shift register structure.

[0036] Step 2: Generate sampling synchronization data signal Sample_data[20-1:0] through packaging combination; then perform synchronization alignment detection on 10 groups of data of Sample_data[0:9], Sample_data[1:10], ...Sample_data[9:18] and K code alignment vector (aligment_pattern) in parallel to generate k_flag0, k_flag1, ...k_flag9, a total of 10 synchronization indication signals, perform logic OR processing on the 10 signals, and generate the synchronization signal k_flag of the SerDes channel data.

[0037] Step 3: Use the dynamic threshold detection mechanism to perform threshold determination on the k_flag signal, and set the initial threshold value to 8; when k_flag = 1, each clock rising edge arrives, the sampled k_flag times are accumulated by 1, and the dynamic threshold is reduced by 1; until the k_flag accumulated times are equal to 5, which is greater than the dynamic threshold value 3, the SerDes channel data K code synchronization is determined, and align_found_int = 1; when the loss of lock is determined, the SerDes channel data K code is in the synchronization state (the dynamic threshold is 3, and the k_flag accumulated times are 5), that is, align_found_int = 1, when k_flag = 0, the loss of lock signal will not be output immediately. If k_flag = 0 and is maintained for T clock cycles, the k_flag times are reduced by 1, and the threshold is increased by 1 at the same time, until the k_flag times are 3 less than the dynamic threshold value 5, the synchronization is determined to have failed, and the loss of lock indication signal align_found_int = 0 is output.

[0038] Step 4: Output the K code synchronization data aligned_data[19:0] through the lock indication signal align_found and the K code alignment indication signal sel_reg[9:0] generated by threshold determination.

[0039] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A Serdes dynamic threshold code stream synchronization detection method, characterized in that it includes the following steps: (1) Adopt a shift register structure to generate K-code detection sampling data; (2) Detect m groups of data according to the data structure of the K-code sampling data; (3) Determine the K-code synchronization locked state and unlocked state; (4) Output K-code synchronization data; In the step (1), the number of shift registers is 2n, where n is the data bit width of a single SerDes channel; In the step (2), m ≥ n; The specific process of detecting m groups of data in the step (2) is as follows: Pack and combine two consecutive groups of input data to generate a sampling synchronization data signal Sample_data[2n - 1:0] with a data bit width of 2n - 1; Then, synchronously align and detect m groups of data, namely Sample_data[0:n - 1], Sample_data[1:n], …… Sample_data[m - 2:2n - 3], Sample_data[m - 1:2n - 2], with the K-code alignment vector to generate m-channel synchronization indication signals, namely k_flag0, k_flag1, …… k_flag(m - 1). Among the m-channel synchronization indication signals, there is one true synchronization signal. Perform a logical OR operation on the m-channel synchronization indication signals to generate the synchronization signal k_flag of the SerDes channel data; In the step (3), perform a synchronization lock determination and unlock adjudication on the SerDes K-code synchronization k_flag signal through a dynamic threshold detection mechanism; The specific process of determining the K-code synchronization locked state and unlocked state in the step (3) is as follows: Use a dynamic threshold detection mechanism to perform a threshold determination on the k_flag signal, and set an initial threshold L; When k_flag = 1, each time the rising edge of the clock arrives, increment the number of sampled k_flag by 1, and at the same time subtract 1 from the threshold L; Until the number of k_flag is equal to or greater than the dynamic threshold, determine that the SerDes channel data K-code is synchronized, and align_found_int = 1; In the unlock determination, in the SerDes channel data K-code synchronization state, that is, when align_found_int = 1, when k_flag = 0, the unlock signal will not be immediately output. If k_flag = 0 and it remains for T clock cycles, the number of k_flag is decremented by 1, and the threshold is incremented by 1 at the same time, until the number of k_flag is less than the dynamic threshold, determine that the synchronization fails, and output the unlock indication signal align_found_int = 0.

2. A Serdes dynamic threshold code stream synchronization detection system, characterized in that: It includes a sampling data establishment module, a detection module, a determination module, and an output module; The sampling data establishment module adopts a shift register structure to generate K-code detection sampling data; The detection module detects m groups of data according to the data structure of the K-code sampling data; The determination module determines the K-code synchronization locked state and unlocked state; The output module outputs K-code synchronization data; The specific process of detecting m groups of data is as follows: Pack and combine two consecutive groups of input data to generate a sampled synchronous data signal Sample_data[2n - 1:0] with a data bit width of 2n - 1; then, synchronously align and detect m groups of data, namely Sample_data[0:n - 1], Sample_data[1:n], …… Sample_data[m - 2:2n - 3], Sample_data[m - 1:2n - 2] with the K-code alignment vector in parallel to generate m channels of synchronous indication signals, i.e., k_flag0, k_flag1, …… k_flag(m - 1). One of the m channels of synchronous indication signals contains the true synchronous signal. Perform a logical OR operation on the m channels of synchronous indication signals to generate the synchronous signal k_flag of the SerDes channel data; Perform synchronous locking determination and unlock adjudication on the SerDes K-code synchronous k_flag signal through a dynamic threshold detection mechanism; The specific process of determining the synchronous locking state and unlock state of the K-code is as follows: Use a dynamic threshold detection mechanism to perform threshold determination on the k_flag signal and set the initial threshold L; when k_flag = 1, each time the rising edge of the clock arrives, accumulate the number of times of sampled k_flag by 1, and at the same time subtract 1 from the threshold L; until the number of times of k_flag is equal to or greater than the dynamic threshold, it is determined that the SerDes channel data K-code is synchronized and align_found_int = 1; in the unlock determination, when the SerDes channel data is in the K-code synchronous state, i.e., align_found_int = 1, when k_flag = 0, the unlock signal will not be immediately output. If k_flag = 0 and it remains for T clock cycles, the number of times of k_flag is decremented by 1, and the threshold is incremented by 1 at the same time, until the number of times of k_flag is less than the dynamic threshold, it is determined that the synchronization fails and the unlock indication signal align_found_int = 0 is output.

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