Dynamic vision sensor structure

Abstract

A dynamic vision sensor (DVS), or change detection sensor, reacts to changes in light intensity and, in this way, monitors how a scene changes. The present disclosure encompasses both single-pixel and array architectures. A DVS can comprise a single pixel or a two-dimensional or one-dimensional array of pixels. Changes in intensity registered by the pixels are compared, and pixel addresses where the changes are positive or negative are recorded and processed. By analyzing frames based on only three values for a pixel: increasing, decreasing, or remaining unchanged, the proposed DVS can process visual information much faster than conventional computer vision systems, which associate multi-bit color or grayscale pixel values between consecutive frames.

Description

[0001] This application is a divisional application of the Chinese invention patent with application number "2017800814213" and invention name "Dynamic Vision Sensor Structure".

[0002] Related applications

[0003] This application claims the benefit of Swiss Provisional Patent Application No. CH 20160001764, filed on December 30, 2016, and Swiss Provisional Patent Application No. CH 20160001765, filed on December 30, 2016, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The present invention relates to vision sensors, in particular motion or change detection sensors. These sensors react to changes in light intensity and in this way monitor how a scene changes. Background Art

[0005] Today's machine vision is primarily based on traditional cameras and their associated frame-based image sensors. For some machine vision tasks, such as object recognition, these traditional frame-based cameras are well-suited. However, for other tasks, such as tracking or position and motion estimation, traditional image sensors have drawbacks.

[0006] The main disadvantage is that traditional cameras generate a large amount of redundant and unnecessary data that must be captured, communicated, and processed. This high data load slows reaction time by reducing temporal resolution, leading to increased power consumption and increasing the size and cost of machine vision systems. In addition, most image sensors have limited dynamic range, poor low-light performance, and motion blur.

[0007] These shortcomings arise from the fact that the data is captured as a sequence of still images (frames). In some cases, encoding dynamic scenes as still images is useful for producing beautiful images and movies, but it is not optimal for processing data for machine vision use.

[0008] Conventional computer vision systems using conventional cameras typically compare features between sequential image frames for object recognition. To estimate the position and orientation of a mobile system and infer a three-dimensional map of the surrounding world, two sequential images are compared that partially overlap but were taken at different times and poses. To infer the motion that occurred between the two frames, characteristic visual landmarks (keypoints or other visual features) must be matched across the two images. Finding these pairs of points that correspond to each other in the two images is known as solving the "correspondence problem."

[0009] Solving the correspondence problem requires a significant amount of processing power. To detect landmarks, every pixel in the image may have to be searched for individual features (corners, arcs, edges, etc.). Pixels and their surrounding neighborhoods are then grouped to represent so-called feature descriptors, which are then used to match features between frames and thereby establish corresponding point pairs. This is computationally intensive. Direct methods that directly compare pixel intensities are even more computationally complex.

[0010] On the other hand, so-called dynamic vision sensors (DVS) are sensors that overcome the limitations of frame-based encoding. See U.S. Patent Application Publication No. US 2008 / 0135731 to Lichtsteiner et al., entitled "Light Array for Detecting Time-Dependent Image Data," which is incorporated herein by reference. By using intra-pixel data compression, data redundancy is removed, and high temporal resolution, low latency, low power consumption, and a high dynamic range with minimal motion blur are achieved. Therefore, DVS is particularly suitable for solar- or battery-powered compressed sensing or mobile machine vision applications, where the position of the system must be estimated and processing power is limited due to limited battery capacity.

[0011] DVS pre-processes visual information locally. Instead of producing sharp images, DVS generates intelligent data for computer applications. While traditional image sensors capture movies as a series of still images, DVS detects and transmits only the locations of changes in the scene. It encodes visual information more efficiently than traditional cameras because it compresses the data within the pixels. This means that data can be processed using fewer resources, lower net power, and faster system reaction times. High temporal resolution allows continuous tracking of visual features, overcoming the correspondence problem. Furthermore, the DVS architecture allows for high dynamic range and good low-light performance. Summary of the Invention

[0012] General DVS may have several disadvantages:

[0013] 1. Pixel circuits can be larger because they include an amplifier and two comparators in some cases.

[0014] 2. Asynchronous readout circuits are prone to timing jitter. If a large area of the scene changes in a short period of time, the jitter increases and can delay reading data from parts of the sensor, resulting in motion artifacts.

[0015] 3. Since DVS pixel circuits tend to be self-timed, sensor temporal resolution cannot be imposed, and very fast changes in a small area can saturate the communication bandwidth.

[0016] 4. DVS sensors have the following characteristics: the amount of output data generated depends mainly on the dynamics of the scene. Therefore, the data rate is unpredictable, leading to problems in the processing stage, namely overload (i.e., the processing stage cannot cope with the amount of data).

[0017] 5. In some DVS sensors, the pixels in the array are reset in each row after that row is read out. This means that slow motion will not be detected because small changes from frame to frame cannot be accumulated. In addition, existing pixel circuit designs are prone to motion artifacts due to rolling shutter.

[0018] The present invention relates to DVS (Dynamic Vision Sensor) designs. Various embodiments can be employed to mitigate, eliminate, or obviate at least some of the disadvantages associated with existing solutions. For example, embodiments of the present invention allow for a reduction in the size of pixels used in a pixel array, thereby allowing for a smaller sensor for the same resolution or a higher resolution for the same die size. Furthermore, in some embodiments, the pixels of the pixel array can be operated synchronously (thereby allowing for synchronously operating sensors). Furthermore, the time over which changes in light intensity are evaluated can be controlled, thereby allowing the temporal resolution and event rate to be tailored to the situation and application at hand.

[0019] The pixel circuits can operate synchronously and / or with an external timing reference. This has several advantages, as listed below:

[0020] 1. Control the event rate by varying the temporal resolution of the sensor.

[0021] 2. Frame-based readout allows reading data from pixels with less temporal jitter.

[0022] 3. Having a clocked pixel circuit makes it easier to design the digital communication circuits that interface with the pixel array, allowing the use of standard digital design tools. The design of asynchronous circuits for typical existing DVSs is often more difficult due to the lack of appropriate commercial tools.

[0023] 4. Controlling the timing through the controller enables separation of the change detection and readout phases in time. This reduces the risk of false events due to parasitic coupling from one pixel to another.

[0024] Generally speaking, according to one aspect, the present invention features a sensor. The sensor typically includes an array of pixels. The array can be one-dimensional or two-dimensional. However, single-pixel sensors are possible.

[0025] Each pixel of the sensor comprises several elements. A light sensor detects incident light. A photoreceptor signal is a function of the amount of light received by the light sensor. A storage capacitor is also provided, wherein a first plate of the capacitor carries charge from the photoreceptor signal, and a second plate of the capacitor is connected to a comparator node, the voltage of which varies with changes in the photoreceptor signal. One or more comparators then compare the voltage of the comparator node to one or more reference voltages to assess changes in the photoreceptor signal relative to one or more threshold values.

[0026] Generally speaking, according to another aspect, the present invention features a sensor. The sensor includes a pixel array or a single pixel. Each of the pixels includes a light sensor. The light sensor signal is a function of the amount of light received by the light sensor. Furthermore, a storage capacitor carries charge from the light sensor signal. A single comparator is provided in the pixel. It compares the voltage at the comparator node with one or more reference voltages to assess changes in the light sensor signal relative to one or more threshold values.

[0027] Using only a single comparator in a pixel has the advantage of reducing the size of the pixel. This size reduction can be used to increase the size of the array for the same area of the semiconductor chip. On the other hand, it can also be used to reduce the overall size of the sensor, thereby achieving a low-cost device.

[0028] In general, according to another aspect, the present invention features a sensor. The sensor also includes a pixel array or a single pixel. Each pixel includes a light sensor and a storage capacitor. The pixel also includes a comparator that compares a voltage from the storage capacitor to one or more reference voltages to assess changes in the light sensor signal relative to one or more threshold values. According to the present invention, the comparator also provides a reset voltage to the storage capacitor.

[0029] Using a comparator to provide a reset voltage to the storage capacitor is useful because it resets the storage capacitor in a way that accounts for offsets in the comparator. This is important because each comparator in a pixel array may have a slightly different offset due to manufacturing variability. According to the present invention, any resulting offset is eliminated by using a comparator to provide a reset voltage to the storage capacitor.

[0030] Generally speaking, according to another aspect, the present invention features a sensor. The sensor also includes a pixel array or a single pixel. Each pixel includes a photosensor and a storage capacitor. A comparator is also provided in the pixel. The comparator sequentially compares the voltage from the storage capacitor with two reference voltages to evaluate changes in the photosensor signal relative to an ON threshold or an OFF threshold.

[0031] An advantage of the present invention is that it uses a single comparator to determine both ON and OFF events by comparing the voltage from the storage capacitor to an ON threshold and an OFF threshold in sequence.

[0032] Generally speaking, according to another aspect, the present invention features a sensor. The sensor comprises an array of pixels or a single pixel. Each of these pixels includes a photosensor and a storage capacitor. Furthermore, the pixel comprises one or more comparators that compare the voltage from the storage capacitor to assess changes in the photosensor signal relative to one or more threshold values. Finally, a memory structure is provided in the pixel for storing the output of the one or more comparators.

[0033] Providing a memory structure in the pixel allows the pixel to store the result of the threshold. This allows, for example, the timing of reading out this information from various pixels in the array.

[0034] Generally speaking, according to another aspect, the present invention features an array of pixels or individual pixels. Each of these pixels includes a photosensor and a storage capacitor. According to the present invention, a switch is also provided in each pixel and is controlled by a shutter circuit signal that connects the photosensor to the storage capacitor. This allows a global shutter signal to be provided to all pixels in the array.

[0035] The advantage of using a global shutter is that, for example, a single signal can be used to trigger the entire array, avoiding the problems associated with a rolling shutter.

[0036] In general, according to another aspect, the present invention features a sensor. The sensor includes an array of pixels or a single pixel. Each of these pixels includes a photosensor. The photosensor signal is based on light received by the photosensor in a storage capacitor that carries a charge from the photosensor signal. According to the present invention, one or more comparators are provided in a readout circuit for the array. These comparators compare the voltage of the array's storage capacitor with a reference voltage to assess changes in the photosensor signal relative to one or more threshold values.

[0037] In the present invention, the comparators are moved to the peripheral circuitry surrounding the pixel array. This allows the size of those corresponding pixels to be further reduced. On the other hand, a few comparators can be used to provide the necessary threshold function for the entire array.

[0038] In general, according to another aspect, the invention may also feature a method. Specifically, a method for operating a sensor includes: detecting incident light by a light sensor of a pixel of an array, generating a photoreceptor signal as a function of an amount of light received by the light sensor, using a storage capacitor to store charge corresponding to light previously detected by the light sensor, wherein a first plate of the capacitor carries charge from the photoreceptor signal and a second plate of the capacitor is connected to a comparator node, wherein a voltage at the comparator node varies with changes in the photoreceptor signal, and comparing the voltage at the comparator node to one or more reference voltages to evaluate changes in the photoreceptor signal relative to one or more threshold values.

[0039] The above-mentioned and other features of the present invention, including various novel construction details and combinations of parts, as well as other advantages, will now be described in more detail with reference to the accompanying drawings, and are pointed out in the claims. It should be understood that the specific methods and devices embodying the present invention are shown by way of illustration and not as limitations of the invention. The principles and features of the present invention may be employed in various and numerous embodiments without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In the accompanying drawings, reference numerals refer to the same parts in different views. The drawings are not necessarily to scale; rather, emphasis has been placed on certain areas in order to illustrate the principles of the invention. In the drawings:

[0041] Figure 1 A circuit diagram showing the components and connections of a pixel circuit for a DVS or change detection sensor in accordance with the principles of the present invention.

[0042] Figure 2 A circuit diagram showing an alternative embodiment of a pixel circuit with optional sampling circuitry is shown.

[0043] Figure 3 Schematic diagram showing a sensor layout with pixels arranged in a two-dimensional array of rows and columns.

[0044] Figure 4A Phase timing for a change detection sensor with a fixed frame rate is described, where each phase of processing a frame requires a fixed amount of time.

[0045] Figure 4B Phase timing of a change detection sensor with variable frame rate is described, where the variability is attributed to the time spent in the event readout phase.

[0046] Figure 5 A circuit diagram showing elements of a preferred embodiment of a pixel circuit without sampling.

[0047] Figure 6A timeline of signals is shown; the horizontal time axis corresponds to the duration and occurrence of the phase operations marked at the top.

[0048] Figure 7 A circuit diagram showing components of a preferred embodiment of a pixel circuit with sampling is shown.

[0049] Figure 8 A circuit diagram showing components of a pixel circuit embodiment that is smaller and simpler than previous pixel circuit embodiments.

[0050] Figure 9 Shown is the corresponding Figure 8 Timeline of signals for the pixel circuit embodiment shown in FIG.

[0051] Figure 10 A circuit diagram showing components of a smaller and simpler pixel embodiment in which the storage circuitry is moved from the pixel circuitry to the readout circuitry.

[0052] Figure 11 Shown is the corresponding Figure 10 Timeline of signals for the pixel circuit embodiment shown in FIG.

[0053] Figure 12 A circuit diagram of another pixel embodiment is shown, where each pixel has two comparators, which can be faster than the previous embodiment.

[0054] Figure 13 This circuit diagram shows the smaller pixel size when the comparator function is moved from the pixel circuit to the readout circuit. (Note: The two pixels shown are along the columns of the pixel array.)

[0055] Figure 14 Depicts two pixels arranged in the same Figure 13 In the figure, the pixel circuit includes an amplifier circuit that amplifies the change in pixel output.

[0056] Figure 15 A circuit diagram of an embodiment of a sampling circuit SC is shown.

[0057] Figure 16 A circuit diagram of an embodiment of a 2-stage comparator A1 is shown.

[0058] Figure 17 A circuit diagram of another comparator embodiment based on operating a transconductance amplifier is shown.

[0059] Figure 18 A circuit diagram illustrating one embodiment of a reset circuit is shown.

[0060] Figure 19 A circuit diagram of another reset circuit is shown.

[0061] Figure 20 A circuit diagram showing a third embodiment of a reset circuit is shown.

[0062] Figure 21 Shown Figure 8 A circuit diagram of a first embodiment of a reset circuit of a pixel embodiment.

[0063] Figure 22 Shown Figure 8 FIG. 1 is a circuit diagram of another reset circuit of a pixel embodiment.

[0064] Figure 23 Shown Figure 8 A circuit diagram of a third embodiment of a reset circuit of a pixel embodiment.

[0065] Figure 24 Shown Figure 10 . Circuit diagram of the reset circuit of the pixel embodiment shown in FIG.

[0066] Figure 25 Shown Figure 10 A circuit diagram of an embodiment of a reset circuit of a pixel embodiment is shown in FIG.

[0067] Figure 26 This is a schematic diagram of the photoreceptor circuit.

[0068] Figure 27 A circuit diagram showing a preferred embodiment of a pixel photoreceptor and circuitry.

[0069] Figure 28 A circuit diagram of an embodiment of a photoreceptor having two NMOS feedback transistors is shown.

[0070] Figure 29 A circuit diagram of an embodiment of a photoreceptor having a PMOS feedback transistor is shown.

[0071] Figure 30 A schematic diagram showing an embodiment of a basic readout circuit in a pixel array.

[0072] Figure 31 A schematic diagram showing an embodiment of an event-based readout circuit is shown.

[0073] Figure 32 Shown Figure 5 、 7 and a circuit diagram of a preferred embodiment of the column logic circuit of the pixel circuit in 12.

[0074] Figure 33 Shown for Figure 8 Circuit diagram of an embodiment of a column logic circuit for a pixel circuit in FIG.

[0075] Figure 34 Shown for Figure 10 Circuit diagram of an embodiment of a column logic circuit for a pixel circuit in FIG.

[0076] Figure 35 Shown for Figure 13 Circuit diagram of an embodiment of a column logic circuit for a pixel circuit in FIG.

[0077] Figure 36 Shown for Figure 13 The pixel circuit shown in Figure 35 Signal timeline for the implementation of column logic circuits.

[0078] Figure 37 Shown for Figure 14 The column logic circuit implementation of the pixel circuit shown in . DETAILED DESCRIPTION

[0079] The present invention will now be described in more detail with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, the present invention can be embodied in many different forms and should not be construed as limited to the embodiments described herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0080] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Furthermore, unless expressly stated otherwise, the singular forms and articles "a," "an," and "the" also include the plural forms. It should be further understood that when used in this specification, the terms "include," "comprises," and / or "includes" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, it should be understood that when an element comprising a component or subsystem is referred to and / or shown as connected or coupled to another element, it may be directly connected or coupled to the other element or to an intermediate element.

[0081] It should be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, an element discussed below could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the teachings of the present invention.

[0082] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or exaggerated sense unless expressly defined herein.

[0083] Many technical terms are used throughout the application. For the convenience and accurate description of the present invention, they are defined below.

[0084] A closed switch is a conducting switch, ie, the two terminals are electrically connected.

[0085] Electronic connection: A connection between two nodes in an electrical circuit, either direct (electrical, so that current can flow between the two nodes) or via a buffer.

[0086] Event: An increase or decrease in light intensity at a given pixel.

[0087] Event frame: One iteration of applying threshold voltage, operating memory, reading out and resetting memory contents.

[0088] Event rate: The number of events per second generated and transmitted by the pixel circuitry. The event rate depends on the pixel circuitry configuration, threshold settings, and temporal resolution, as well as the sensor motion and observed scene.

[0089] Frame rate: The number of times per second that each pixel is read. This is equivalent to the rate at which a complete event frame is scanned. The frame rate can be fixed or depend on the number of events generated.

[0090] Motion Artifacts: If the camera or subject moves quickly across the frame, rolling shutter can show up as noticeable slanted lines in the image where vertical lines might otherwise be. If there is rapid motion in the frame, the entire image will appear distorted.

[0091] OFF event: A discrete decrease in light intensity at a given pixel.

[0092] ON event: A discrete increase in light intensity at a given pixel.

[0093] Open Switch: A switch that does not conduct, i.e. provides an open circuit between its two terminals.

[0094] Pixel address: A number or pair of numbers that describes the location of a pixel in an array. Usually a row and column number.

[0095] Power rail: Ground (Vss) or power (Vdd).

[0096] Generally speaking, Figure 1Components of a pixel circuit assembled and connected according to the principles of the invention are represented.Later, reference will be made to a two-dimensional pixel array having rows and columns of pixels, each of which has electronics as described in this or an alternative embodiment.

[0097] In this document, a "pixel" refers to a sensing element that records the intensity of light striking it; a "pixel circuit" or "pixel electronics" refers to the electronic components and circuitry of a pixel. In this document, the term "pixel circuit" will be used to focus on the electronics of the pixel, while the term "pixel" will be used to refer to the sensing element as a whole. In general, a sensor (see Figure 3 ) will consist of a two-dimensional array of pixels 100 and additional peripheral circuitry. However, not all applications require a two-dimensional array. The sensor may also contain a single pixel (an array of one pixel) or a one-dimensional array of pixels (a line sensor).

[0098] The main components of the pixel circuit 100 are listed below.

[0099] 1. Photoreceptor Module. As shown in the figure, the pixel circuit includes a photodiode PD or other photosensor to measure impinging light 9 and convert the light intensity into a current Iphoto; a photoreceptor signal circuit PRC to generate a photoreceptor signal Vpr that depends on the light intensity; and a storage capacitor C1 to store past photoreceptor signals. The photosensor PD and the photoreceptor circuit PRC constitute the photoreceptor module PR.

[0100] 2. Storage capacitor C1 receives the photoreceptor signal Vpr, causing the first plate of the capacitor to carry a charge responsive to the photoreceptor signal Vpr, and thus responsive to light received by the photosensor PD. The second plate of storage capacitor C1 is connected to the comparator node (inverting input) of A1. Thus, the voltage at comparator node Vdiff varies with changes in the photoreceptor signal Vpr.

[0101] 3. Comparator A1: This is the device that compares the difference between the current photoreceptor signal Vpr and the past photoreceptor signal to a threshold. This comparator A1 can be in each pixel, or shared between a subset of pixels (e.g., a column). In a preferred embodiment, the comparator will be integrated with the pixel, with each pixel having a dedicated comparator A1.

[0102] 4. Memory: Memory 50 stores the comparator output based on the sampling signal from controller 60. The memory can be a sampling circuit (such as a switch and parasitic or explicit capacitors) or a digital memory circuit (latch or flip-flop). In one embodiment, the memory will be a sampling circuit, and each pixel will have two memories.

[0103] 5. Conditional reset circuit R1: The reset condition is a combination of the state of the stored comparator output and the reset signal applied by the controller.

[0104] 6. The comparator A1 and the memory 50 may be located in the pixel or in a peripheral circuit (outside the pixel circuit).

[0105] The peripheral circuit includes a controller 60 that applies a threshold signal to the comparator A1, sends a control signal to the memory 50, and selects the time when the conditional reset circuit R1 is activated.

[0106] The peripheral circuitry may also include a readout circuit RO which reads the contents of the memory 50, determines whether the light intensity of a given pixel has increased, decreased or remained unchanged, and sends an output (calculated based on the current memory value) to the processor.

[0107] More specifically, the comparator indicates whether the light has increased or decreased. For an OFF event: If Vdiff is below the threshold Voff (on Vb), the comparator output is high, and this level is stored in memory. This indicates a drop has been detected. If Vdiff is not below the threshold, the comparator output is low: no drop has been detected.

[0108] The only difficulty is that for an On event, a low comparator output means an increase, while a high comparator output means no change; but for an OFF event, a high comparator output means a decrease, while a low comparator output means no change.

[0109] Therefore, the readout must know the memory content and the threshold value applied. Alternatively, as a preferred embodiment described later, there is an inverter for turning on, so that the polarity of the memory used for switching on and off is the same.

[0110] In a preferred embodiment of the pixel circuit 100 of the present invention, each pixel circuit 100 includes only one comparator, which is sequentially used first as a comparator for ON events and then as a comparator for OFF events (or vice versa).

[0111] The pixel circuit 100 and the controller 60 operate as follows.

[0112] Changes in the light intensity received by photosensor PD will be converted into changes in the photoreceptor signal Vpr. When reset circuit R1 is non-conductive, changes in Vpr will also be reflected in the voltage Vdiff at the comparator node at the inverting input terminal (-) of comparator A1. This is because the voltage on storage capacitor C1 remains constant.

[0113] At times selected by controller 60, comparator A1 compares the voltage at the comparator node at the second end of storage capacitor C1 (Vdiff) with a threshold voltage Vb (from the controller) applied to the non-inverting input (+) of comparator A1.

[0114] The controller 60 operates the memory 50 to store the comparator output Vcomp. The memory 50 is typically implemented as part of the pixel circuit 100, as shown. However, in other embodiments, the memory 50 is implemented as part of the column logic circuit (peripheral circuit, one pixel array per column).

[0115] If the state of the comparator output stored in memory 50 indicates a change in light intensity and the global reset signal GlobalReset from controller 60 is active, the conditional reset circuit R1 is conducting. Here, "AND" represents a logical AND operator. When the conditional reset circuit R1 is in the conducting state, the voltage at the comparator node at the inverting input of comparator A1 (Vdiff) is reset to a known level. As a result, it stores the current photosensitive signal Vpr on the storage capacitor C1.

[0116] Figure 2 A pixel circuit 100 according to another embodiment is shown, comprising an optional sampling circuit SC between the light sensing circuit PRC and the storage capacitor C1. The sampling circuit SC allows selective electronic connection or disconnection of the output Vpr of the light sensing circuit PRC and the storage capacitor C1.

[0117] Sampling circuit SC is operated by sampling signal 25 from controller 60 to globally sample the photoreceptor outputs of all pixels at the same time to avoid motion artifacts. In general, sampling circuit SC may include sampling switch 150, parasitic or explicit sampling capacitor C2, and buffer amplifier A2. (Note that buffer amplifier A2 is not used in all implementations.)

[0118] The pixel circuit 100 and the controller 60 operate as follows.

[0119] As in Figure 1 As in the previous embodiment, changes in light intensity will be converted into changes in the photoreceptor signal Vpr.

[0120] At the same time, the controller 60 operates the sampling circuit SC by electrically connecting the photoreceptor output voltage Vpr from the photoreceptor circuit PRC to the sampling capacitor C2. The controller 60 then further operates the sampling circuit SC by opening the switch 150 via the control signal 25 to disconnect the photoreceptor output voltage Vpr from the capacitor C2.

[0121] At a time specified by the controller 60, the comparator A1 compares Vdiff at the comparator node with the threshold Vb applied to its non-inverting input. Simultaneously, the controller 60 operates the memory 50 to store the comparator output Vcomp. As previously described, the memory 50 is located in the pixel circuit 100 or in the column logic circuit 44 of the peripheral RO circuit 42, as described later.

[0122] If the state of the stored comparator output indicates a change in light intensity and the global reset signal GlobalRset (controlled by the controller) is active, the conditional reset circuit R1 is conducting and Vdiff is reset to a known level, the voltage on sample C2 is stored in memory C1.

[0123] As mentioned above, a pixel or pixel array can be used as a sensor for machine vision applications. In machine vision applications, the output of the sensor will flow directly or indirectly to a data processor, where an algorithm can calculate the position and motion of the sensor or the object being analyzed by the sensor.

[0124] Conventional sensors output an image containing pixel values representing the intensity of light striking the pixel. Instead, the sensor here outputs the addresses of those pixels where a change in light intensity has been detected (where the address of a pixel corresponds to its row and column number). This change in light intensity at a given pixel is called an event. More specifically, the term "event" means that the photoreceptor signal, as a function of the light intensity at a pixel, has changed by an amount greater than or equal to a threshold applied by the controller. To signal an event, the address of the corresponding pixel is sent, along with a bit indicating whether the change in light intensity was positive or negative.

[0125] In order to detect light intensity changes between the current and previous instances in time, each pixel needs to store a representation of the light intensity of the previous instance in time.

[0126] More specifically, each pixel stores a voltage Vdiff that represents the difference between the photoreceptor signal at the last event emitted at that pixel and the current photoreceptor signal at that pixel.

[0127] To detect an event in a preferred embodiment, the Vdiff at the comparator node is first compared to a threshold to detect an increase in light intensity (ON event), and the comparator output is sampled on a (explicit or parasitic) capacitor or stored in a flip-flop. The Vdiff at the comparator node is then compared to a second threshold to detect a decrease in light intensity (OFF event), and the comparator output is sampled on a (explicit or parasitic) capacitor or stored in a flip-flop. A global reset signal is sent to all pixels, and in each pixel, the global reset signal is logically ANDed with the sampled comparator output to reset only those pixels where an event was detected. The sampled comparator output voltage is then read out, and the corresponding pixel address is sent to the receiver.

[0128] Figure 3 A sensor 8 is shown comprising a two-dimensional array of pixels 100-1 through 100-6. The illustrated sensor shows only two rows and three columns to avoid cluttering the diagram. In practice, the sensor 8 will comprise m rows (typically much greater than 2) and n columns (typically much greater than 3) of pixels. A pixel in the two-dimensional array can be identified by its address, which is the row and column number of the pixel. For example, pixel 103-6 has row 2 (counting from the top) and column 3 (counting from the left) as its address.

[0129] Controller 60 controls pixels 100 and other components such as row selection circuitry 40 , readout circuitry 42 , and transfers data from the array to processor 46 .

[0130] In the illustrated example, row selection circuitry 40 is shown as part of controller 60. The row selection circuitry 40 selects one or more subsets of rows. When a row of pixels 100 is selected, the comparator outputs of the pixels in the selected row are passed to readout circuitry 42.

[0131] Readout circuitry 42 reads the data (stored comparator outputs) from the pixel array. Typically, readout circuitry 42 will further encode this data into a more efficient representation before transmitting it to some receiver (typically in the form of a processor), such as processor 46, which may be external to the sensor chip.

[0132] The readout circuit 42 is divided into a number of column logic circuits 44-1 to 44-n, where there are n columns, and determines from the readout comparator output whether the light intensity of the corresponding pixel has increased, decreased, or remained unchanged.

[0133] The controller 60 preferably operates the sensor 8 in multiple stages ( Figure 4A and 4B ) is as follows:

[0134] 1. Illumination Change Integration: In this embodiment, the integration of changes continues during the other phases without additional dedicated time requirements.

[0135] 2. Comparison of ON event phases ( Figure 4A and 4B 218 ): In each pixel, comparator A1 is used to compare the integrated illumination change with the ON threshold; the result is stored in memory 50 .

[0136] 3. Comparison of OFF event phases ( Figure 4A and 4B 220 ): In each pixel, comparator A1 is used to compare the integrated illumination change with the OFF threshold; the result is stored in memory 50 .

[0137] 4. Reset phase ( Figure 4A and 4B 222): Each pixel circuit 100, wherein the state of the stored comparator output indicates a change in light intensity, is reset by turning on the respective reset circuit R1.

[0138] 5. Readout phase ( Figure 4A and 4B 224): Under the control of the row selection circuit 40, the comparison result stored in the memory 50 is read out from the pixel array.

[0139] In general, the first phase (integration of lighting changes) does not need to have an explicit duration, since the continuous time integration of the changes does not stop during the other phases. Therefore, the explicit time allocation of this phase can be omitted.

[0140] Of course, the order in which the ON and OFF events are compared can be reversed.Furthermore, depending on the pixel embodiment, the readout phase can occur before the reset phase.

[0141] A controller 60 preferably controls the relative timing of the phases and generates the necessary signals to control the pixels. As shown in Figures 4A and 4B, several modes of pixel operation are possible.

[0142] Fixed readout time: Figure 4A A timing diagram of a fixed time mode is shown in which each operating phase has a fixed time duration. Therefore, the frame rate is fixed. In the example shown, each Evt frame is 100 microseconds long.

[0143] Therefore, the readout phase also has a fixed duration, but the number of events to be read out is likely to vary from event frame to event frame. In order to maintain a reasonable duration limit for the readout phase, the number of events that can be read in a single event frame must be limited 214. If the number of events to be read out is less than the maximum possible number, there will be an idle phase.

[0144] If the number of events is greater than can be read out during the readout phase, there are three options: 1) notify the processor 46 and discard the additional events; 2) notify the processor 46 and amplify the readout phase for the current frame only (after the stretched frame, the sensor, i.e., the pixel array, immediately starts the next event frame); or 3) notify the processor 46 and amplify the readout phase for the current frame, and after the stretched frame, wait for the "official" frame start time to be synchronized with the previous event frame start time.

[0145] Figure 4A An exemplary operating timeline is shown having a frame rate of 10k event frames per second or 100 microseconds per frame.

[0146] More specifically, in each event frame 212, the comparison of ON events 218 takes 10 μs, and the comparison of OFF events 220 also takes 10 μs. The pixels are then reset during a 20 μs phase 222. Finally, in a readout phase 224, the events are read out of pixel array 210 and accumulated in readout circuitry 42. The readout phase lasts 60 μs. Therefore, in this specific example, the sum of the phase durations is 10 + 10 + 20 + 60 = 100 μs.

[0147] As shown in successive event frames 212-1, 212-2, and 212-3, the actual readout 214 in phase 224 consumes varying amounts of time, despite the 60 μs allotted for that phase 224. For example, for the first event frame 212-1, the readout of event 214-1 in phase 224-1 consumes less than half of the 60 μs allotted to 214-1. Conversely, for the third event frame 224-3, the readout of event 214-3 consumes two-thirds of the 60 μs allotted to 224-3.

[0148] Variable readout time: In variable readout time mode, as Figure 4B As shown, the duration of the readout phase 224 depends on the number of events to be transmitted. Thus, the total length of a frame and therefore the frame rate is variable and depends on the number of events per frame.

[0149] More specifically, as in the previous example, each event frame 212 is divided into a comparison of an ON event 218, which takes 10 μs, and a comparison of an OFF event 220, which takes 10 μs. The event reset phase 222 takes 20 μs in each event frame 212. On the other hand, the event readout phase 224 of each event frame 212 is variable in length. Therefore, this phase has a duration dictated by the number of events 214 that need to be read out from the pixel array 210.

[0150] Figure 5A pixel circuit 100 constructed according to the principles of the present invention is shown, which is a preferred embodiment without sampling.

[0151] A light sensor PD, such as a photodiode or phototransistor or photoactive region, is used to convert the impinging light 9 into an electrical signal (i.e., a current or charge designated as Iphoto). Iphoto is then converted into a voltage Vpr by a photosensitive circuit PRC. In this and all other pixel embodiments, the relationship between Vpr and light intensity is typically logarithmic, but can also be linear.

[0152] Preferably, the photoreceptor module PR in each of the one or more pixels of any sensor embodiment is a logarithmic photoreceptor module. A logarithmic photoreceptor module is a photoreceptor configured to convert a current Iphoto, which is proportional to the intensity of light impinging on the sensing surface of the photosensor PD, into a signal that is a logarithmic function of the detected light. Note that while Vpr is selected to be logarithmic with respect to Iphoto, it can be selected to be proportional to Iphoto and other functions.

[0153] The logarithmic conversion of the current (Iphoto) generated by the photodiode to the output voltage is very powerful because it allows a wide range of input currents to be mapped to a limited voltage range. Comparing differences in the logarithmic intensity domain also has the advantage that it is mathematically similar to comparing normalized differences; most definitions of contrast are based on normalized differences (e.g., luminance ratio, Weber contrast, or Michelson contrast). Comparing differences in the logarithmic intensity domain also allows observation of differences in the reflectivity of objects independent of background illumination.

[0154] Storage capacitor C1 receives the photoreceptor signal Vpr, causing the first plate of the capacitor to carry a charge responsive to the photoreceptor signal Vpr. The second plate of storage capacitor C1 is connected to comparator node A1. In the illustrated embodiment, the second plate is connected to the inverting input of event comparator A1. Therefore, the voltage at comparator node Vdiff varies with changes in the photoreceptor signal Vpr, and thus with the light received by photosensor PD.

[0155] During the comparison phase (see, for example, Figure 4A and 4B ), the reset switch RS of the reset circuit R1 is not conducting, so the voltage Vdiff at the comparator node is floating. Therefore, changes in the photoreceptor signal Vpr change the voltage of the floating comparator node Vdiff because the voltage on the storage capacitor C1 remains constant from the time the pixel 100 is reset.

[0156] To compare ON events, the threshold voltage Vb is set by the controller 60 to a value Von (see Figure 6). Consequently, event comparator A1 compares threshold voltage Vb with Vdiff. Controller 60 also pulses OnSel (for on-select), which closes ON-event sampling switch S2. Consequently, the comparator output is inverted by inverter I1 and sampled on a capacitor. In the illustrated embodiment, this capacitor is the parasitic gate capacitance of ON-event output transistor NM2 of output circuit OUT.

[0157] To compare the OFF event, the bias voltage Vb is set to the value Voff (see Figure 6 ). Therefore, event comparator A1 compares the new threshold voltage Vb with Vdiff. Controller 60 also pulses output OffSel, which closes OFF event sampling switch S1. Therefore, the comparator output is sampled on a capacitor. In the illustrated embodiment, this capacitor is the parasitic gate capacitance of OFF event output transistor NM1 of output circuit OUT.

[0158] During the reset phase, the threshold voltage Vb is set to a voltage level Vreset (a value between Von and Voff, preferably a value midway between Von and Voff), and the GlobalReset signal is activated by the controller 60. Therefore, if an ON event or an OFF event (using an OR gate) is detected and GlobalReset is activated, the reset circuit R1 will close the reset switch RS.

[0159] Thus, only those pixels for which an event has been detected are reset.The reset function advantageously allows slow motion to be detected, since small changes from frame to frame can accumulate.

[0160] The example circuit shown also compensates for any offset in the event comparator A1, thereby helping to make the response of the pixels 100 in the pixel array 8 ( Figure 3 ) is consistent across the array. Typically, in those pixels 100 within pixel array 8 where a high voltage level is stored on either the OFF-event output transistor NM1 or the ON-event output transistor NM2, reset switch RS is closed. As a result, the Vdiff at the second terminal of storage capacitor C1, configured as a voltage follower, will be resolved at Vreset plus any offset in the comparator. Thus, the correction applied to the threshold is now compensated for the offset in event comparator A1.

[0161] During the readout phase, the pixel array is read out row by row.Thus, each pixel circuit 100 waits for the controller 60 to activate its RowSelect signal one row at a time.

[0162] Next, we discuss the pixel control signals and their changes over time (timeline diagram).

[0163] Figure 6A timeline showing global pixel control signals and local pixel signals. Vb, OnSel, OffSel, and GlobalReset are global signals for all pixels in the pixel array, while RowSelect is a row (local) signal.

[0164] In more detail, two event frames are shown with ON and OFF comparison phases. Specifically, during comparison phase 218-1 and OFF comparison phase 220-1, threshold voltage Vb changes between Von and Voff levels. Since photoreceptor signal Vpr is constant, no event is detected.

[0165] During the ON comparison phase 218-2, the threshold voltage Vb is changed to Von. Since the photoreceptor signal Vpr is now at a higher level, indicating that the amount of light received by the light sensor PD has increased, the voltage at the second terminal of the storage capacitor C1 (Vdiff) also increases (to a level above Von if the change is large enough). Therefore, when the controller 60 also pulses OnSel, the ON event sampling switch S2 is closed and the ON signal is stored on the capacitance of the ON event output transistor NM2 ( Figure 5 ). When the RowSelect signal is active, the nRxOn line is pulled low.

[0166] Due to the detected event, the reset phase also resets the voltage on the storage capacitor C1. Specifically, in the reset phase 222-2, the threshold voltage Vb is set to the intermediate level Vreset. Because PixReset is high due to the logic in the reset circuit R1, Vdiff is reset to Vreset and the new voltage is stored on the storage capacitor C1.

[0167] Figure 7 Another pixel circuit 100 ( Figure 5 ) has a sampling circuit SC between the photoreceptor PR and the storage capacitor C1.

[0168] This enables the photoreceptor signal Vpr to be sampled before comparison.This configuration ensures that the same photoreceptor voltage value is used for comparison of ON and OFF events, avoiding possible motion artifacts due to variations in Vpr in the comparison of ON and OFF events.

[0169] More specifically, before each ON comparison phase 218, the sampling line from controller 60 is activated for a short period of time to close sampling switch 150. This transfers the photoreceptor signal voltage Vpr to the plates of storage capacitor C1. The sampling signal line from controller 60 is then deactivated, causing sampling switch 150 to open again. Consequently, the charge on the left plate of storage capacitor C1 is static and does not change with subsequent changes in photoreceptor signal Vpr. Such changes typically result from a change in the scene or movement between the sensor and the scene.

[0170] Then, both the ON comparison phase 218 and the OFF comparison phase 220 are performed.The corresponding comparisons for the different threshold voltages Vb will then occur relative to the same voltage sampled from the photoreceptor signal Vpr.

[0171] Figure 8 1 shows another pixel circuit 100. This design results in a smaller pixel.

[0172] More specifically, it has only one output line nRX, which replaces the two output lines nRXon and nRXoff used in the previous example ( Figure 5 and 7 This change also allows the OR gate to be removed from the reset circuit R1 (see Figure 5 and 7 ), and the removal of NM2, one of the output transistors (see Figure 5 and 7 ) in the output circuit OUT. For both event polarities, the output signal nRx is active low. The reset circuit R1 uses the GlobalReset signal and the sampled comparator output to determine whether it is conducting.

[0173] In this embodiment, it is preferred to have a separate reset phase for each event polarity (ie, one reset phase for OFF events and another reset phase for ON events).

[0174] In more detail, similar to the previous embodiment, changes in the photoreceptor output voltage Vpr change the voltage of the floating node Vdiff.

[0175] For comparison due to the ON event, the bias voltage Vb is set to the voltage level Von. The comparator compares Vb with Vdiff. By the pulse OnSel, the comparator output is sampled at the parasitic capacitance of transistor NM1.

[0176] For a reset caused by an ON event, Vb is set to a voltage level Vreset (midway between Von and Voff) and the GlobalReset signal is activated. In those pixels storing a high voltage level on output transistor NM1, the reset switch RS is closed, so Vdiff will settle at Vreset plus the offset of the comparator.

[0177] For row-by-row readout, the RowSelect signal is activated one row at a time. If the gate capacitance of output transistor NM1 stores a high voltage level, output transistor NM1 turns on and the corresponding request line nRx is pulled down. This active-low request is latched in the peripheral readout circuit 42.

[0178] For comparison of the OFF event, the controller 60 sets the bias voltage Vb to the level Voff. By means of the pulse OffSel, this new comparator output is sampled on the parasitic capacitance of the output transistor NM1.

[0179] For the reset OFF event, Vb is set to the voltage level Vreset (midway between Von and Voff) and the global reset signal is activated. In those pixels that store a high voltage level on the gate of output transistor NM1, the reset switch RS is closed, so Vdiff will settle at Vreset plus the offset of the comparator.

[0180] For readout of OFF events performed row by row, the RowSelect signal is activated for each row at a time. If the gate capacitance of output transistor NM1 maintains a high voltage level, it turns on and the output line nRx is pulled down. This active-low request is latched in the peripheral readout circuit 42.

[0181] Figure 9 A timeline showing global pixel control signals and local pixel signals. Vb, OnSel, OffSel, and GlobalReset are global signals; RowSelect is a row (local) signal.

[0182] In this example, the ON compare phase is combined with the readout phase 218. During this period, the threshold voltage Vb increases to Von, and RowSelect is activated. However, in the illustrated example phase 218-1, no ON event is detected. Similarly, the OFF compare phase is combined with the readout phase 220. During the ON reset phase 219 and the OFF reset phase 221, the GlobalReset signal is active.

[0183] Prior to the ON compare and readout phase 218-2, Vpr increases due to the increased light on photosensor PD, and thus Vdiff increases to a value greater than Von. Consequently, event comparator A1 registers an ON event, which is stored in memory when OnSel goes high and low again, causing PixEvt to go high. When the row select signal RowSelect is activated, the ON event is transmitted to the peripheral circuitry on output line nRx. During the ON reset phase 219-2, when PixEvt and global reset are simultaneously high, PixReset goes high, causing the pixel to be reset during the reset phase 219-2.

[0184] Figure 10 1 shows another pixel circuit 100. This design results in a smaller pixel, where the storage functionality is not located in the pixel circuit 100, but is part of the readout circuit 42.

[0185] In more detail, reset circuit R1 uses the RowSelect signal and the output confirmation signal ColAck from the readout circuit 42 to determine whether to close the reset switch RS and reset the storage capacitor C1. The logical AND of ColAck and RowSelect is used to set the latch to store the PixReset signal, and a global signal (ResetPixReset) from the controller is used to reset the latch during the reset phase. The reason for storing the AND of ColAck and RowSelect and not using it directly to control switch RS is to allow all pixels in the array to be reset simultaneously. Without the latch, a reset would need to be performed row by row during the readout phase.

[0186] The ColAck signal from the readout circuit 42 is shared among all pixels in a column. Therefore, pixel reset must be activated row by row. In operation, the row select circuit selects a row of pixels by activating the corresponding RowSelect, and transmits the corresponding comparator output to the readout circuit through the output transistor NM1. The controller 60 then operates the memory in the readout circuit 42 to store the transmitted comparator output; the column logic circuit of the readout circuit 42 determines whether there is an increase or decrease in light intensity. In the column where the column logic circuit detects a change in light intensity, the ColAck signal is activated. The controller then applies a reset voltage Vreset to the positive input of the event comparator A1 of the array 210. Together with the still activated RowSelect signal, the activated ColAck signal resets the corresponding pixel.

[0187] Furthermore, in this pixel circuit, the polarity of the comparator output differs between an ON event (rising light level) and an OFF event (falling light level). Therefore, the polarity difference of the comparator output for ON and OFF events is accounted for in the readout circuit 42. This means that the output signal nRx is active high for an ON event and active low for an OFF event.

[0188] Figure 11 The timeline shows the global pixel control signals and local pixel signals. Vb, OnSel, OffSel, and ResetPixReset are global signals, while RowSelect is a row-direction local signal and ColAck is a column-direction local signal.

[0189] In this example, the ON compare phase is combined with the readout phase 218. During this period, the threshold voltage Vb increases to Von, and RowSelect is activated. However, in the illustrated example phase 218-1, no ON event is detected. Similarly, the OFF compare phase is combined with the readout phase 220. After both the compare and readout phases, there is a reset phase 224.

[0190] Prior to the ON comparison and readout phase 218-2, Vpr increases due to the increased light on photosensor PD, and thus Vdiff increases to a value greater than Von. Consequently, when row select signal RowSelect becomes active, event comparator A1 registers an ON event, which is transmitted to the peripheral circuitry on output line nRx. Since the corresponding column logic registers an event, it activates the ColAck signal. In all pixels where both ColAck and RowSelect are active, the PixReset signal goes high, shorting the comparator input and output. During reset phase 224-2, the controller applies Vreset to Vb, and since PixReset is still high, the pixel is reset. The controller then sets ResetPixReset high for a period of time to reset all PixReset signals back to a low value.

[0191] Figure 12 Another pixel circuit 100 is shown. This design allows for faster operation. It includes two event comparators per pixel, which enables simultaneous ON and OFF event comparisons. In addition, the memory is located in the pixel circuit and is implemented by two sampling circuits at the corresponding comparator outputs. Figure 5 As shown, the memory is a combination of switches with parasitic capacitances, here the parasitic gate capacitances of S4 and NM2, and also the parasitic gate capacitances of S5 and NM1. The comparator output is sampled and stored on the parasitic gate capacitances of the two output transistors NM1 and NM2.

[0192] In more detail, the OFF event comparator A1 receives a Voff threshold voltage provided to the entire pixel array 210. Similarly, the ON event comparator A2 receives a Von threshold voltage provided to the entire pixel array 210.

[0193] When the sample comparison signal SampleComp from the controller 60 is activated, the outputs of the comparators A1 and A2 are transmitted to the gate capacitances of the OFF-event output transistor NM1 and the ON-event output transistor NM2, respectively. Then, when RowSelect is active (i.e., NM3 is on), their states are read through the output lines nRXon and nRXoff.

[0194] In response to an ON event or an OFF event, the reset circuit resets the voltage at the second terminal of the storage capacitor C1 (Vdiff), which is provided to the inverting input of the OFF event comparator A1 and the non-inverting input of the ON event comparator A2. In this case, Vdiff is reset to the common voltage across the array 210.

[0195] Figure 13 Two representative pixels 100 along the columns from array 210 are shown. The ellipses (dots) along the ResetLevel, ColAck and VSF lines represent that there are other pixels along the columns. They are omitted from the figure to avoid clutter. The pixel circuit embodiment of the figure results in smaller pixels. The reason is that the comparator function is not located in the pixel circuit 100, but becomes part of the readout circuit 42 (shown at the bottom in the figure).

[0196] The pixel circuit 100 includes a sampling switch 150 between the photoreceptor circuit PRC and the storage capacitor C1, the output of which is Vpr. This allows for selective electronic connection of the outputs of the photoreceptor circuit PRC and the storage capacitor C1. The sampling switch 150 is operated by a sampling signal sample on line 25 from the controller 60. The sampling signal is activated by the controller 60 to globally sample the photoreceptor outputs of all pixels 100 in the array 210 at the same time. This avoids motion artifacts.

[0197] Specifically, the photoreceptor signal Vpr is transmitted as VPRS to the storage capacitor C1. Buffer 27 then maintains the voltage at the second terminal of the storage capacitor C1 (Vdiff). Typically, buffer 27 transmits the voltage (Vdiff) at the second terminal of the storage capacitor C1 to peripheral circuits. The buffer is activated by the RowSelect signal from the row select circuit 60.

[0198] Pixel circuit 100 uses a source follower as buffer 27. This transmits the voltage on the second terminal of storage capacitor C1 to readout circuit 42 for the pixel column in array 210. Voltage Vdiff is provided to the readout circuit of readout circuit 42 on line Vout to terminal VSF. Here, event comparator circuit A1 compares Vdiff with the Von level and the Voff level. This column comparator A1 is located in readout circuit 42.

[0199] In buffer 27, transistor M1 acts as a unity gain source follower input transistor (the current source of the source follower is part of the readout circuit 42), while M2 is a switch used to enable the source follower. The readout circuit 42 is implemented so that each pixel column has a separate ColAck signal. The ColAck signal is only active in the column where an event is detected ( Figure 37 denoting the readout circuit 42).

[0200] Reset transistor N1 is controlled by the RowSelect signal. Reset transistor N2 is controlled by the output confirmation signal ColAck. Therefore, when both signals are activated, reset transistors N1 and N2 are turned on, and the voltage at the second terminal of storage capacitor C1 (Vdiff) is reset to the reset voltage provided to pixel column 210 on the reset line from readout circuit 42. Therefore, the series connection of transistors N1 and N2 forms a logical AND function for signals RowSelect and ColAck.

[0201] It should be understood that this embodiment can also be implemented without the sampling switch 150 between the photosensitive circuit PRC and the storage capacitor C1.

[0202] Figure 14 Two representative pixels 100 are shown along a column from array 210. Figure 13 As shown, the ellipses (dots) along the ResetLevel, ColAck, and VSF lines indicate the presence of other pixels, which are omitted to avoid cluttering the diagram. This design also focuses on a small pixel area. As with the previous embodiment, the comparator function is not located in the pixel circuit 100, but becomes part of the readout circuit 42. However, unlike Figure 13 This embodiment uses a capacitive amplifier in the buffer 27 to amplify the voltage Vdiff at the second terminal of the storage capacitor C1, specifically, to amplify the voltage change since the pixel was last reset.

[0203] As mentioned before, Vdiff is obtained from VPRS before amplification ( Figure 13). Amplifying changes in Vdiff helps detect small changes in the photoreceptor signal Vpr. The gain of buffer 27 is given by the ratio of the capacitance of C1 divided by C2. It should be noted that capacitor C2 can be explicit or parasitic. In addition to this ratio multiplied by the capacitance, Figure 14 The embodiments and functions of the pixels shown in Figure 13 same.

[0204] In buffer 27, transistor M1 is a PFET input transistor, so the buffer is an amplifier, and M2 is a switch that enables the amplifier. Readout circuit 42 is implemented so that each pixel column has a separate ColAck signal. The ColAck signal is only valid in the column where the event is detected. Figure 37 Such a readout circuit 42 is shown.

[0205] The resetting of the node Vdiff is controlled by the row select switch RS (controlled by the RowSelect signal) and the column reset switch CS (controlled by the output confirmation signal ColAck).

[0206] exist Figure 13 (together with Figure 35 ), the reset level is determined by the source follower and A1 in the readout circuit. The actual reset level will contain the offset of the source follower and the offset of A1, so these two offsets will be compensated.

[0207] exist Figure 14 (together with Figure 37 ), A1 is implemented as two comparators (one for ON and one for OFF), so it is not possible to include both in the reset level. But because Figure 14 The buffer in has a much larger gain than the monomer, the offset of the comparator is not actually important, so it can be left uncompensated.

[0208] Again similar to Figure 13 , Figure 14 It can also be implemented between the photosensitive circuit PRC and the storage capacitor C1 without the sampling switch 150 .

[0209] The discussion will now turn to possible example implementations covering aspects / portions of the above-described pixel circuit embodiments. It should be understood that in most cases, any of the above-described circuits may have any one or more of the features described below.

[0210] Figure 15 A compact embodiment of a sampling circuit SC is shown, as might be used in a pixel embodiment ( Figure 2 、 7, 13, and 14). Sampling circuit SC uses nFET transistor T10 as a switch. The source follower is implemented by two pFET transistors T11 and T12, where T11 is the current source of the source follower and T12 is the source follower input transistor. The gate capacitance of pFET transistor T12 forms the sampling capacitor.

[0211] Figure 16 and 17 Various embodiments of comparators A1 for detecting small changes in illumination are shown. Small changes in voltage on the order of a few millivolts must be detected. This means that a comparator such as Figure 1-3 The circuits shown in Figures 5, 7, 8, 10, 12-14 will require considerable gain (preferably greater than 10dB or 20dB, and most preferably about 40dB or more).

[0212] Figure 16 A two-stage comparator is shown which will provide the necessary gain.A reset switch RS is also shown which in this embodiment does not connect the input and output of the comparator; instead, it connects the input to the output of the first stage of the comparator.

[0213] Figure 17 An alternative implementation of comparator A1 based on an operational transconductance amplifier is shown. It uses five transistors with a two-transistor output stage as a comparator. The advantage is that the comparator's speed is independent of the reference voltage, thus allowing greater freedom in the threshold range. Furthermore, offset compensation can be improved compared to the previous example using a two-transistor, two-stage comparator.

[0214] The reset switch and reset circuit are part of the pixel circuit in all embodiments, and their embodiments are as follows.

[0215] The reset switch can be implemented as an NMOS transistor, a PMOS transistor, or a complete transmission gate that includes both NMOS and PMOS transistors. Depending on the type of switch used, the polarity of the reset signal is active high for NMOS transistors, active low for PMOS transistors, and high and low polarity for the transmission gate. If the reset signal is called PixReset, it is considered active high, and if it is called nPixReset, it is considered active low.

[0216] Figure 18 express Figure 5 、 7 The reset circuit of the pixel circuit in 12 is realized. The AND-OR combination used to generate the reset signal is used Figure 5 、 7 and the circuit shown in 12. Figure 18The AND-OR combination circuit shown in Figure 1 can implement an NMOS transistor used as a reset switch. ON and OFF are sampled comparator outputs. If ON is at a high voltage level, for example, switch S1 conducts and S3 does not. Therefore, in this case, the voltage on PixReset will track the voltage on GlobalReset. If the controller sets GlobalReset to a high voltage level, the reset NMOS transistor conducts, and the comparator is reset.

[0217] If both ON and OFF are low, then S1 and S2 are not conducting, but S3 and S4 are conducting. Therefore, PixReset is connected to ground, and the reset transistor is not conducting.

[0218] Figure 19 An alternative embodiment of a reset using a PMOS reset transistor is shown. For example, if the voltage level ON is high, NM1 is turned on. If the controller 60 sets GlobalReset to a high voltage level, NM3 is also turned on, and the voltage on nPixReset will be pulled to ground, so the PMOS reset transistor is turned on. When the controller 60 sets GlobalReset to a low voltage level, there is no longer a current path between nPixReset and ground. The bias current in PM1 (controlled by the bias voltage on the gate of PM1) will then slowly pull nPixReset to the power supply. If neither ON nor OFF is a high voltage level, the bias current in PM1 will keep nPixReset at the power supply, so the reset transistor is not turned on.

[0219] Figure 20 Figure 6 shows another implementation of the reset circuit. This version integrates the logic function into the actual reset switch. This allows for a more compact implementation. If either ON or OFF is a high voltage level and GlobalReset (controlled by controller 60) is high, the path between the comparator inputs is conductive.

[0220] Figure 21 Shown for Figure 8 Implementation of the reset circuit for a pixel embodiment. Here, an NMOS transistor acts as the reset switch. PixEvt is the sampled comparator output. If PixEvt is at a high voltage level, switch S1 conducts and switch S2 does not. Therefore, in this case, the voltage on PixReset will track the voltage on GlobalReset. If the controller sets GlobalReset to a high voltage level, the reset NMOS transistor conducts, and the comparator is reset.

[0221] If PixEvt is low, S1 is not conducting, but S2 is conducting. Therefore, PixReset is connected to ground, so the reset transistor is not conducting.

[0222] Figure 22 Figure 2 shows the implementation of a reset circuit. This circuit uses a PMOS reset transistor. If the voltage level PixEvt is high, NM1 turns on. If the controller sets GlobalReset to a high voltage level, NM2 also turns on, and the voltage on nPixReset is pulled to ground, turning on the PMOS reset transistor. When the controller sets GlobalReset to a low voltage level, there is no longer a current path between nPixReset and ground. The bias current in PM1 (controlled by the bias voltage on PM1's gate) then slowly pulls nPixReset to the power supply. If PixEvt is low, the bias current in PM1 keeps nPixReset at the power supply, so the reset transistor does not turn on.

[0223] Figure 23 Represents a reset circuit that integrates the logic functionality into the actual reset switch. This allows for a more compact implementation. If PixEvt is a high voltage level and GlobalReset (controlled by the controller) is high, the path between the comparator input and output is conductive.

[0224] Figure 24 Another implementation of the reset circuit compatible with the pixel circuit shown in the figure is shown. 10.

[0225] Here, when RowSelect and ColAck (ColAck is from the column logic circuit to Figure 10 When the signals of the pixels in the array are simultaneously high, node nPixReset is pulled to ground and this low voltage level is stored on the (explicit or parasitic) capacitor CR, and the switch connecting the input and output of the comparator is turned on. After the readout is completed in the entire array, all pixels that have generated an event will have nPixReset on ground and are therefore reset. The controller then sets the signal ResetPixReset to a low voltage level, and MP1 turns on, pulling nPixReset to the power supply. By controlling the level of the reset pixel reset during the reset phase, the rising slope of the pixel reset can be controlled.

[0226] exist Figure 24 In the embodiment shown in , a capacitor is used to implement a latch for the PixReset signal (the node is not always driven). Alternatively, two cross-coupled inverters can be used as a latch, as shown in Figure 25 shown.

[0227] In a preferred embodiment, the pixel uses a logarithmic front end to allow high dynamic range and sensitivity to temporal contrast rather than temporal difference. If a negative feedback circuit is employed, a fast response to illumination changes can be achieved.

[0228] Figure 26 Figure 1 shows a basic logarithmic photoreceptor PR with feedback. It uses a photodiode PD as a light sensor. Photoreceptor circuit PRC includes an inverting amplifier and circuit element M1 with a logarithmic current-voltage relationship connected between the input and output of the inverting amplifier. The inverting amplifier ensures that the voltage across the photodiode PD remains nearly constant.

[0229] Figure 27 A preferred embodiment of the photoreceptor PR is shown. An NMOS transistor serves as the feedback element, and a common source amplifier acts as an inverting amplifier. Between the logarithmic photoreceptor and the capacitor, a source follower can be used to isolate the front end from voltage transients during pixel reset. The source follower also allows low-pass filtering of the input signal, thereby reducing integrated noise.

[0230] Figure 28 and 29 Two other options using two NMOS feedback transistors are shown ( Figure 28 ) or PMOS feedback transistor ( Figure 29 ).

[0231] exist Figure 5 In the pixel readout circuit RO shown in FIG12 , the column request lines nRxOn and nRxOff are shared among all pixels in the same column. If RowSelect is active and a high voltage is stored on the parasitic capacitor of NM2, nRxOn is pulled low to signal an ON event to the data readout circuit. If a low voltage is stored on NM2, NM2 is not conducting, so nRxOn remains high.

[0232] for Figure 8 and 10 In the pixel circuit shown in FIG, the column request line nRx of the readout circuit RO is shared among all pixels in the same column. If RowSelect is valid and a high voltage is stored on the parasitic capacitor of NM1, nRx is pulled low to signal the event to the data readout circuit. If a low voltage is stored on NM1, NM1 is not conductive, so nRx remains high.

[0233] The controller 60 generates the necessary waveforms for the control signals to the pixels and controls the voltage Vb at the input of the comparator and generates the necessary waveforms for controlling the column logic circuits. In many cases, the controller 60 also synchronizes these waveforms to an external timing reference.

[0234] The controller 60 may be integrated on the same sensor integrated circuit (IC) as the pixel circuit, or in a separate IC using, for example, a microcontroller or field programmable gate array (FPGA). The controller may be implemented as a finite state machine or using a microcontroller core.

[0235] Part of the controller 60 is the row select circuit. The row select circuit selects and enables OUT in each pixel in a row via a set of RowSelect signals. The row select circuit has a clock input that allows movement from one row to the next. The output of the row select circuit is a set of RowSelect signals, one for each row of pixels. Selecting a row means that the RowSelect signal for that row is active (high voltage level) while the RowSelect signals for all other rows are inactive (low voltage level). The active RowSelect signal enables those pixels that have sampled the "high" comparator output to generate a column request by changing the state of a signal line shared between all pixels in the column.

[0236] The row selection circuit includes a circuit that encodes the address of the currently selected row and outputs the address to the data readout circuit.

[0237] The row selection circuitry may include the possibility to be configured in such a way that rows are skipped during scanning. This feature is used to implement so-called region of interest (ROI) readout.

[0238] The controller 60 is implemented using software or hardware, such as a finite state machine, which first sets Vb (the first comparator input) to a first threshold voltage (Von) and then sets the signal OnSel to a logic high after a short delay to electrically connect the inverting comparator output to the ON node. Then, after another delay, the controller (hardware or software) is set to a low logic to disconnect the inverting comparator output from the ON node. It then sets Vb to a second threshold voltage (Voff). After a small pause, the software sets the signal output to a logic high to electrically connect the comparator output to the OFF node. After a short delay, it again sets the bias to a logic low to disconnect the comparator output from the OFF node. It then sets Vb to a reset voltage Vreset. After a delay, it sets the signal Global Reset to a logic high to electrically connect the second terminal of the capacitor to the reset level. After another delay, the software sets GlobalReset to a low logic to disconnect the second terminal of the capacitor from the reset level.

[0239] The controller then sets the first RowSelect line to logic high to connect the storage comparator outputs of the pixels in the first row to the readout circuit and signals the readout circuit to begin sending events from row 1. When the readout circuit is complete, the controller sets the first RowSelect line to logic low and the second RowSelect line to logic high.

[0240] All rows are processed until exhausted, ie the controller has read the stored comparator outputs of all rows.

[0241] When the controller has finished reading all stored comparator outputs, it can restart the sequence after a short delay by setting Vb to the first threshold voltage again. This process is repeated during DVS data acquisition.

[0242] Alternatively, the controller may wait for an external timing reference signal rather than restarting the sequence directly. This external timing reference signal may come from the processor.

[0243] The readout circuit is described below.

[0244] In its most basic form, the readout circuitry reads the comparator outputs of all pixels 100 in the array 210 and sends a three-valued (incremented, decremented, or unchanged) image to the receiver once for each frame.

[0245] Figure 30 Readout circuitry for pixel array 210 is shown.

[0246] To read the comparator outputs for the entire pixel array 210, the array 210 is scanned row by row. This means that the row select circuit 40 (part of the controller 60) selects a row of pixels, which means that the outputs of the comparators in those pixels (or the stored outputs of the comparators, depending on the pixel embodiment) are connected to a column row of corresponding column logic circuits 44 that are fed into the readout circuit 42. The column logic circuits 44 determine whether a change has occurred in the corresponding pixel, and then the outputs of the corresponding column logic circuits 44 are scanned using the column scan circuit 48. The column scan circuit 48 sequentially connects the column logic circuit outputs to the output data lines that go to the processor 46.

[0247] Next, event-based readout is described.

[0248] The data readout circuitry may encode the data more efficiently to allow for more efficient readout and processing in processor 46. In this type of pixel circuitry, the data is expected to be sparse, meaning that only a small percentage of pixels in each event frame will have registered changes.

[0249] Sparse digital signals can be easily further compressed. A common method for compressing multidimensional digital data is to encode the coordinates / addresses of the digital signals in the data. This encoding of digital events is also called event-based readout. A common encoding scheme in event-based visual sensors is to encode digital signals as a tuple of row and column coordinates of pixels in an array and a timestamp, thereby encoding the location and time of the occurrence of the digital event. This means that, in one embodiment, only the addresses of those pixels that have detected a change in light intensity (an event that has occurred) are transmitted.

[0250] Figure 31 A readout circuit is shown which allows reading out the addresses of those pixels in which an event has occurred. To this end, the address of the corresponding row is output row by row, as well as the addresses of all columns in which an event has been detected by the column logic circuit.

[0251] The implementation uses a shift register 70. Each pixel column has a corresponding shift register stage 72-1, 72-2, 72-3.

[0252] Each shift register stage 72-1, 72-2, 72-3 can be bypassed. Bypassing is controlled by the EventDetect output of the corresponding column logic circuit 44-1, 44-2, 44-3. If the EventDetect output is low, the corresponding shift register stage 72-1, 72-2, 72-3 is bypassed. If the EventDetect output is high, the shift register stage 72-1, 72-2, 72-3 is not bypassed.

[0253] Controller 60 initiates the reading of events by setting StartPulse high and pulsing Clock. This is received at the input multiplexer 74-1 of the first stage 72-1. The input multiplexer provides the Q input to the D-latch 78-1. The Q output of D-latch 78-1 is provided to the output multiplexer 76-1. The Clock input is received at the Clock input of D-latch 78-1.

[0254] The controller then sets StartPulse low again. The first shift register stage that is not bypassed (e.g., where the corresponding EventDetect is high) will store a high voltage level at its output. This connects the address + event polarity of the corresponding column logic circuit to the communication bus. The receiver can now read this address. At the next clock pulse, the high level moves to the next shift register stage 72, which is not bypassed and the corresponding address + event polarity is connected to the communication bus. This continues until the high level moves to the last shift register stage 72 that is not bypassed. The output of this stage tells the controller 60 using line 80 that the readout of the row is complete. The controller 60 then activates the RowSelect signal for the next row, connects the row address encoder 40 to the communication bus and restarts the shift register.

[0255] Next, the column logic circuit is described.

[0256] refer to Figure 32 , used for pixel output nRxOn and nRxOff (see Figure 5 or 7 or 12) or only nRx (see Figure 10 According to an embodiment of the pixel circuit, column logic circuit 44 determines whether the light intensity at the corresponding pixel is unchanged, increasing, or decreasing by checking whether the state of the pixel output (logical low or logical high) corresponds to a value indicating an increase or decrease. If column logic circuit 44 detects an increase or decrease, it notifies the data readout circuit.

[0257] The outputs of the column logic circuit are a signal (EventDetect) that is asserted when an event is detected, a signal corresponding to the polarity of the event, and a number encoding the column address of the corresponding column. (High polarization means increased light intensity.) Since the column address is just a fixed number for each column, its implementation is not shown in the figure.

[0258] Part of the column logic implementation is the bias transistor for each request line ( Figure 32 92, 94 in ). These bias transistors hold the request lines (nRxOn and nRxOff) at a logic high level as long as no pixel is pulling them.

[0259] When one of the two request lines (nRxOff or nRxOn) is at a low voltage, an event is signaled. The column logic stores the NAND of the two request lines in flip-flop 96 and the state of nRxOff in flip-flop 98 at a time provided by the latch clock signal from controller 60.

[0260] Figure 33 Shown for Figure 8 The pixel circuit is implemented by the column logic circuit.

[0261] Here, an event is detected when Von is applied to the pixel comparator, or when Voff is applied to the pixel comparator, when the request line nRx is low, or when the request line is low. Under the command of the controller, the inverted state of the request line is stored in the Flip-Flop. EventDetect is the logical OR of the flip-flop outputs.

[0262] Figure 34 Shown for Figure 10 The column logic circuit implementation of the pixel circuit diagram.

[0263] In addition to the output signals EventDetect and EventPolity, Figure 10 The column logic circuit of the pixel embodiment must generate a signal to the pixel to reset the pixel together with the RowSelect signal after detecting an event. In the proposed implementation, this ColAck signal is equivalent to the EventDetect signal.

[0264] An event is detected when the request line nRx is high when Von is applied to the pixel comparator, or when the request line is low when Voff is applied to the pixel comparator.

[0265] because Figure 10 The pixel circuit embodiment 10 does not include a storage unit in the pixel, and the column logic circuit includes the storage unit.

[0266] Figure 35 Shown for Figure 13 The column logic circuit of the pixel of the circuit shown in is implemented.

[0267] Here, the column logic circuit includes a comparator A1. The pixel outputs a signal representing Vdiff, and a comparison is performed in the column logic circuit 44 to detect the event.

[0268] Pixel reset is accomplished using comparator / amplifier Comp1. When a pixel should be reset, the EventDetect signal in the corresponding column is high. Controller 60 sets Vb to Vreset and sets DoReset high, causing ColAck to be high. In rows where RowSelect_m is high, voltage Vdiff is then shorted to Vcomp because both transistors in R1 are turned on. The feedback circuit formed by amplifier Comp1 (A1) and the source follower will then ensure that Vdiff settles to a voltage that makes VSF equal to Vreset.

[0269] Figure 36 Shown for Figure 13 The signal timing line of the pixel circuit shown in Figure 35 Implementation of column logic circuit.

[0270] Figure 37 Shown for Figure 14 The pixel circuit is implemented by the column logic circuit.

[0271] The column logic circuit includes two comparators, A1-1 and A1-2. These two comparators allow Vout to be compared to two thresholds simultaneously. The comparator outputs are stored in flip-flops 112 and 114 at a signal latch controlled by controller 60. The logical OR of the comparator outputs, along with the signal DoReset from controller 60, determines whether the pixel has been reset via the signal ColAck.

Claims

1. A sensor comprising: A pixel array, where each pixel consists of: a light sensor that detects incident light; a photoreceptor circuit coupled to the light sensor, a photoreceptor signal from the photoreceptor circuit being a function of an amount of light received by the light sensor; a storage capacitor, wherein a first plate of the storage capacitor carries charge from the photoreceptor signal and a second plate of the storage capacitor is connected to a comparator node having a voltage that varies with changes in the photoreceptor signal; one or more comparators that compare the voltage of the comparator node with one or more reference voltages, wherein the comparator includes a first terminal that receives the voltage from the storage capacitor and a second terminal that selectively receives two reference voltages; and A reset circuit resets the storage capacitor based on an output from the comparator and a global reset signal.

2. The sensor of claim 1, wherein the photosensor circuit is between the light sensor and the storage capacitor.

3. The sensor of claim 2, wherein the photosensor circuit provides a logarithmic response to the current from the light sensor. The sensor of claim 1 , wherein the second plate of the storage capacitor is directly connected to the comparator. The sensor according to claim 1 , wherein the reset circuit is configured to reset the voltage of the comparator node.

6. A sensor comprising: A pixel array, where each pixel consists of: Light sensor; a photosensor circuit coupled to the light sensor, a photosensor signal from the photosensor circuit being indicative of an amount of light received by the light sensor; a storage capacitor that carries charge from the photoreceptor signal; only one comparator that compares the voltage of the comparator node with one or more reference voltages, wherein the comparator includes a first terminal that receives the voltage from the storage capacitor and a second terminal that selectively receives two reference voltages; and A reset circuit resets the storage capacitor based on an output from the comparator and a global reset signal.

7. A sensor comprising: A pixel array, where each pixel consists of: Light sensor; a photoreceptor circuit coupled to the light sensor, a photoreceptor signal from the photoreceptor circuit being a function of an amount of light received by the light sensor; a storage capacitor that carries charge from the photoreceptor signal; a comparator that compares the voltage from the storage capacitor to one or more reference voltages, wherein the comparator includes a first terminal that receives the voltage from the storage capacitor and a second terminal that selectively receives two reference voltages; and A reset circuit resets the storage capacitor based on an output from the comparator and a global reset signal.

8. A sensor comprising: A pixel array, where each pixel consists of: Light sensor; a photoreceptor circuit coupled to the light sensor, a photoreceptor signal from the photoreceptor circuit being a function of an amount of light received by the light sensor; a storage capacitor that carries charge from the photoreceptor signal; a comparator that compares the voltage of the storage capacitor with two reference voltages, wherein the comparator includes a first terminal that receives the voltage from the storage capacitor and a second terminal that selectively receives the two reference voltages; and A reset circuit resets the storage capacitor based on an output from the comparator and a global reset signal.

9. A sensor comprising: A pixel array, where each pixel consists of: Light sensor; a photoreceptor circuit coupled to the light sensor, a photoreceptor signal from the photoreceptor circuit being a function of an amount of light received by the light sensor; a storage capacitor that carries charge from the photoreceptor signal; one or more comparators that compare the voltage from the storage capacitor, wherein the comparator includes a first terminal that receives the voltage from the storage capacitor and a second terminal that selectively receives two reference voltages; at least one memory structure for storing outputs of the one or more comparators; and A reset circuit resets the storage capacitor based on an output from the comparator and a global reset signal.

10. The sensor of claim 9, wherein the memory structure is a switch and a parasitic capacitance.

11. The sensor according to any one of claims 9-10, further comprising a switch for connecting the light sensor to the storage capacitor.

12. The sensor of any one of claims 9-10, wherein the light sensor comprises a photodiode, a phototransistor, or a photoactive region.

13. A sensor comprising: A pixel array, where each pixel consists of: Light sensor; a photosensor circuit coupled to the light sensor, a photosensor signal from the photosensor circuit being a function of the amount of light received by the light sensor, a storage capacitor that carries charge from the photoreceptor signal; and a switch controlled by a shutter signal that connects the light sensor to the storage capacitor; one or more comparators that compare the voltage of the storage capacitor to one or more reference voltages, wherein the comparator includes a first terminal that receives the voltage from the storage capacitor and a second terminal that selectively receives two reference voltages; and A reset circuit resets the storage capacitor based on an output from the comparator and a global reset signal.

14. The sensor of claim 13, wherein the one or more comparators are located in circuitry peripheral to the pixel array. The sensor of claim 13 , wherein the one or more comparators are assigned to columns of the pixels.

16. A sensor comprising: A pixel array, where each pixel consists of: Light sensor; a photosensor circuit coupled to the light sensor, a photosensor signal from the photosensor circuit being a function of an amount of light received by the light sensor; and a storage capacitor that carries charge from the photoreceptor signal; and one or more comparators in a readout circuit that compares the voltage of the storage capacitor of the pixel with a reference voltage, wherein the comparator includes a first terminal that receives the voltage from the storage capacitor and a second terminal that selectively receives two reference voltages; and A reset circuit resets the storage capacitor based on an output from the comparator and a global reset signal.

17. A sensor comprising: One or more pixels, each of the one or more pixels comprising: a photodiode capable of converting light incident on the photodiode into an electric current, wherein the magnitude of the electric current is proportional to the intensity of the light; a photosensor circuit connected to the photodiode such that the photosensor circuit can receive the current from the photodiode, and wherein the photosensor circuit is configured such that the photosensor circuit can convert the current it receives from the photodiode into a voltage and output the voltage as an output of the photosensor circuit; and storage capacitors; at least one comparator having first and second inputs, wherein the first input is settable to a threshold voltage, and wherein the storage capacitor is electronically connected to the second input such that the capacitor is between the output of the photoreceptor circuit and the second input of the comparator; at least one memory electronically connected to the output of the comparator so that the value output by the comparator can be assigned and stored in the memory; and a reset circuit component configured such that it is selectively operable to set the voltage at the second input of the comparator to a predefined reference voltage; and a controller configured to apply one or more threshold voltages to the first input of the comparator, and after the one or more threshold voltages have been applied to the first input of the comparator, enable the memory to store the one or more values output by the comparator, and after the memory has stored the values output by the comparator, enable the reset circuit to set the voltage at the second input of the comparator to a predetermined reference voltage; Wherein the reset circuit component resets the memory based on an output from the comparator and a global reset signal.

18. A method for operating a sensor, the method comprising: Light sensors of the pixels of the array detect incident light; generating a photoreceptor signal, the photoreceptor signal being a function of an amount of light received by the photoreceptor; using a storage capacitor to store charge corresponding to light previously detected by the light sensor, wherein a first plate of the storage capacitor carries charge from the photoreceptor signal and a second plate of the storage capacitor is connected to a comparator node whose voltage varies with changes in the photoreceptor signal; comparing the voltage at the comparator node to one or more reference voltages to evaluate changes in the photoreceptor signal relative to one or more threshold values; resetting the storage capacitor based on an output from the comparator and a global reset signal; The comparator includes a first terminal receiving the voltage from the storage capacitor and a second terminal selectively receiving two reference voltages.

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