Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes: a respective first anode electrically connected to a respective first light emitting element in each first sub-pixel; a respective second anode electrically connected to a respective second light emitting element in each second sub-pixel; a respective third anode electrically connected to a respective third light emitting element in each third sub-pixel; and a respective fourth anode electrically connected to a respective fourth light emitting element in each fourth sub-pixel. A normal projection of the respective third anode on a base substrate substantially covers a normal projection of the first initialization connection line on the base substrate, and covers a normal projection of at least a portion of the respective third voltage supply line on the base substrate.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illuminance. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. This drives the OLED device to emit light of a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate, comprising: a plurality of gate lines, a plurality of first reset control signal lines, and a plurality of first reset signal lines extending along a first direction; a plurality of data lines and a plurality of voltage supply lines extending along a second direction; and a pixel driving circuit; wherein the pixel driving circuit includes a driving transistor; a first transistor and a storage capacitor; and the first transistor includes a gate connected to a corresponding one of the plurality of first reset control signal lines, a source connected to a corresponding one of the plurality of first reset signal lines, and a drain connected to the gate of the driving transistor and a first capacitor electrode of the storage capacitor; wherein the array substrate includes a first initialization connection line, the first initialization connection line connecting a corresponding one of the plurality of first reset signal lines and the source of the first transistor in a corresponding one of a plurality of sub-pixels, the corresponding one of the plurality of first reset signal lines being configured to provide a reset signal to the first one of the plurality of sub-pixels via the first initialization connection line. The array substrate further includes: a source of a transistor; and the plurality of sub-pixels including each first sub-pixel, each second sub-pixel, each third sub-pixel, and each fourth sub-pixel; the array substrate further includes: a corresponding first voltage supply line in each first sub-pixel; a corresponding second voltage supply line in each second sub-pixel; a corresponding third voltage supply line in each third sub-pixel; a corresponding fourth voltage supply line in each fourth sub-pixel; a corresponding first anode electrically connected to a corresponding first light-emitting element in each first sub-pixel; a corresponding second anode electrically connected to a corresponding second light-emitting element in each second sub-pixel; a corresponding third anode electrically connected to a corresponding third light-emitting element in each third sub-pixel; and a corresponding fourth anode electrically connected to a corresponding fourth light-emitting element in each fourth sub-pixel; wherein the orthographic projection of the corresponding third anode on the substrate substantially covers the orthographic projection of the first initialization connection line on the substrate, and covers at least a portion of the orthographic projection of the corresponding third voltage supply line on the substrate.

[0004] Optionally, the first initialization connection line is in the same layer as the plurality of data lines; the first initialization connection line is connected to a corresponding one of the plurality of first reset signal lines through a via extending through the interlayer dielectric layer; the first initialization connection line is connected to the source of the first transistor through a via extending through the interlayer dielectric layer, the insulating layer and the gate insulating layer; and the first initialization connection line passes through a corresponding one of the plurality of first reset control signal lines.

[0005] Optionally, the active layer and drain of the first transistor are part of the overall structure of a corresponding one of the plurality of sub-pixels; at least a portion of the source of the first transistor passes through a corresponding one of the plurality of data lines; and the orthographic projection of the first initialization connection line on the substrate and the orthographic projection of at least a portion of the active layer and at least a portion of the drain of the first transistor on the substrate are separated by the orthographic projection of a corresponding one of the plurality of data lines on the substrate.

[0006] Optionally, the array substrate further includes: a plurality of second reset control signal lines and a plurality of second reset signal lines extending along the first direction; wherein, the pixel driving circuit further includes a second transistor; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the sixth transistor includes a gate connected to a corresponding one of the plurality of second reset control signal lines, a source connected to a corresponding one of the plurality of second reset signal lines, and a drain connected to the drain of the fifth transistor and the anode of the light-emitting element; wherein, the array substrate includes a second initialization connection line, the second initialization connection line connecting the plurality of second reset signal lines. The source of a sixth transistor in a corresponding line and a corresponding sub-pixel of the plurality of second reset signal lines, wherein a corresponding line of the plurality of second reset signal lines is configured to provide a reset signal to the source of the sixth transistor via a second initialization connection line; the second initialization connection line is connected to a corresponding line of the plurality of second reset signal lines via a via extending through the interlayer dielectric layer; the second initialization connection line is connected to the source of the sixth transistor via a via extending through the interlayer dielectric layer, the insulating layer and the gate insulating layer; and the second initialization connection line passes through a corresponding line of the plurality of second reset control signal lines.

[0007] Optionally, the active layer and drain of the sixth transistor are part of the overall structure of a corresponding one of the plurality of sub-pixels; the source of the sixth transistor passes through a corresponding one of the plurality of data lines; and the orthographic projection of the second initialization connection line on the substrate and the orthographic projection of the active layer and drain of the sixth transistor on the substrate are separated by the orthographic projection of a corresponding one of the plurality of data lines on the substrate.

[0008] Optionally, the storage capacitor includes a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding one of the plurality of voltage supply lines, and an insulating layer between the first capacitor electrode and the second capacitor electrode; wherein the array substrate includes: a semiconductor material layer on a substrate; a node connection line in the same layer as a corresponding one of the plurality of voltage supply lines, the node connection line being connected to the first capacitor electrode through a first via and to the semiconductor material layer through a second via; and an anti-interference block in the same layer as the second capacitor electrode, the corresponding one of the plurality of voltage supply lines being connected to the anti-interference block through a third via.

[0009] Optionally, at least a portion of the drain of the first transistor and a portion of the semiconductor material layer at the location connected to the node connection line are arranged in a direction substantially parallel to the second direction.

[0010] Optionally, the pixel driving circuit further includes a second transistor and a third transistor; the second transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to a corresponding one of the plurality of data lines, and a drain connected to the source of the driving transistor; the gate of the third transistor is connected to a corresponding one of the plurality of gate lines, its source is connected to the first capacitor electrode and the gate of the driving transistor, and its drain is connected to the drain of the driving transistor; the portion of the semiconductor material layer at the location connected to the node connection line includes at least a portion of the source of the third transistor; the source of the third transistor and the drain of the first transistor are part of an integral structure in a corresponding one of the plurality of sub-pixels; and a portion of the integral structure extends along a direction substantially parallel to the second direction.

[0011] Optionally, the orthographic projection of the anti-interference block on the substrate substantially covers at least 80% of the orthographic projection of the drain of the first transistor on the substrate.

[0012] Optionally, the anti-interference block includes a handle, a first arm, and a second arm; a corresponding one of the plurality of voltage supply lines is connected to the handle through the third through-hole; the first arm includes an L-shaped portion and a first end portion; the second arm includes a base, a second end portion, and a connecting portion connecting the base and the second end portion; the base connects the L-shaped portion and the handle; and along the first direction, a portion of the node connection line at the location where it is connected to the semiconductor material layer through the second through-hole is spaced apart from the first adjacent data line by the first arm, and spaced apart from the second adjacent data line by the second arm.

[0013] Optionally, the combination of the orthographic projection of the base of the second arm on the substrate and the orthographic projection of the shank on the substrate substantially covers at least 80% of the orthographic projection of the drain of the first transistor on the substrate.

[0014] Optionally, the pixel driving circuit further includes a second transistor and a third transistor; the second transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to a corresponding one of the plurality of data lines, and a drain connected to the source of the driving transistor; the gate of the third transistor is connected to a corresponding one of the plurality of gate lines, its source is connected to the first capacitor electrode and the gate of the driving transistor, and its drain is connected to the drain of the driving transistor; at least a portion of the drain of the first transistor and the portion of the semiconductor material layer at the location connected to the node connection line are arranged in a direction substantially parallel to the direction in which the shank and the base are arranged; and / or at least a portion of the source of the third transistor and at least a portion of the drain of the first transistor are arranged in a direction substantially parallel to the direction in which the shank and the base are arranged.

[0015] Optionally, the corresponding third voltage supply line includes a main body portion and a loop portion connected to the main body portion; and the orthographic projection of the corresponding third anode on the substrate at least partially overlaps with the orthographic projection of the first initialization connection on the substrate, and at least partially overlaps with the orthographic projection of the loop portion on the substrate.

[0016] Optionally, the orthographic projection of a corresponding one of the plurality of data lines on the corresponding third anode lies between the orthographic projection of the first initialization connection line on the corresponding third anode and the orthographic projection of the loop portion on the corresponding third anode.

[0017] Optionally, the loop portion includes a first loop sub-portion along a direction substantially parallel to the second direction, a second loop sub-portion substantially parallel to the first direction, and a third loop sub-portion substantially parallel to the first direction; the second loop sub-portion and the third loop sub-portion respectively connect the first loop sub-portion to the main body portion of the corresponding third voltage supply line; the array substrate further includes a loop hole extending through the corresponding third voltage supply line; and the periphery of the loop hole is surrounded by a combination of the first loop sub-portion, the second loop sub-portion, the third loop sub-portion, and the main body portion.

[0018] Optionally, the orthographic projection of the corresponding third anode on the substrate at least partially overlaps with the orthographic projection of the first loop sub-part on the substrate; and the orthographic projection of the corresponding one of the plurality of data lines on the corresponding third anode lies between the orthographic projection of the first initialization connection line on the corresponding third anode and the orthographic projection of the first loop sub-part on the corresponding third anode.

[0019] Optionally, the signal lines are distributed below the corresponding third anode by placing the first initialization connection line along the first edge of the corresponding third anode on the first side below the corresponding third anode, and placing the loop portion along the second edge of the corresponding third anode on the second side below the corresponding third anode; and the first side and the second side are opposite to each other.

[0020] Optionally, the first initialization connection line is configured to provide the reset signal to the source of the first transistor; and the loop portion is configured to provide a high voltage signal that is transmitted to the second capacitor electrode of the storage capacitor in each of the third sub-pixels.

[0021] Optionally, the source and active layer of the third transistor are part of an overall structure of a corresponding one of the plurality of sub-pixels; the node connection line is connected to the source of the third transistor through the second via; and the orthographic projection of a corresponding one of the plurality of voltage power supply lines on the substrate at least partially overlaps with the orthographic projection of the second arm on the substrate.

[0022] Optionally, one of the plurality of voltage supply lines includes a first parallel portion, a second parallel portion, and a first inclined portion, the first inclined portion connecting the first parallel portion and the second parallel portion along an inclined direction; the first parallel portion and the second parallel portion extending in directions substantially parallel to the second direction; the first inclined portion extending along an inclined angle relative to the first direction; the handle and the base arranged in directions substantially parallel to the second direction; and the connecting portion extending in a direction substantially parallel to the inclined direction.

[0023] Optionally, the orthographic projection of the first inclined portion on the substrate at least partially overlaps with the orthographic projection of the connecting portion on the substrate; the orthographic projection of the first parallel portion on the substrate at least partially overlaps with the orthographic projection of the handle on the substrate; and the orthographic projection of the second parallel portion on the substrate at least partially overlaps with the orthographic projection of the second end portion on the substrate; wherein the corresponding third voltage supply line further includes a second inclined portion connected to the second parallel portion and a third parallel portion connected to the second inclined portion; the third parallel portion extends along a direction substantially parallel to the second direction; the second inclined portion extends along a second inclination angle relative to the first direction; the inclination angle is complementary to the second inclination angle; and the orthographic projection of the second inclined portion on the substrate does not overlap with the orthographic projection of the connecting portion on the substrate.

[0024] Optionally, the pixel driving circuit further includes a second transistor and a third transistor; the second transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to a corresponding one of the plurality of data lines, and a drain connected to the source of the driving transistor; the gate of the third transistor is connected to a corresponding one of the plurality of gate lines, its source is connected to the first capacitor electrode and the gate of the driving transistor, and its drain is connected to the drain of the driving transistor; the drain of the first transistor and the source of the third transistor are part of an integral structure of a corresponding one of the plurality of sub-pixels, at least a portion of the drain of the first transistor is directly connected to at least a portion of the source of the third transistor; the node connection line is connected to the source of the third transistor through the second via; and the orthographic projection of at least a portion of the drain of the first transistor on the substrate at least partially overlaps with the orthographic projection of the stalk on the substrate, at least partially overlaps with the orthographic projection of the first parallel portion on the substrate, and at least partially overlaps with the orthographic projection of the base on the substrate.

[0025] Optionally, the array substrate further includes: a gate insulating layer located on the side of the semiconductor material layer away from the substrate, the first capacitor electrode being located on the side of the gate insulating layer away from the substrate; and an interlayer dielectric layer located on the side of the second capacitor electrode away from the insulating layer, the node connection line and the plurality of voltage supply lines being located on the side of the interlayer dielectric layer away from the second capacitor electrode; wherein the first via extends through the interlayer dielectric layer and the insulating layer in a hole region in which the second capacitor electrode is not present, wherein, except for the hole region, the orthographic projection of the second capacitor electrode on the substrate completely covers the orthographic projection of the first capacitor electrode on the substrate with a margin; and the second via extends through the interlayer dielectric layer, the insulating layer and the gate insulating layer.

[0026] Optionally, the corresponding first voltage supply line, the corresponding second voltage supply line, the corresponding third voltage supply line, and the corresponding fourth voltage supply line are arranged sequentially and continuously along the row direction; the corresponding first voltage supply line, the corresponding second voltage supply line, and the corresponding fourth voltage supply line have substantially the same shape; the shape of the corresponding third voltage supply line is different from the shape of the corresponding first voltage supply line, the corresponding second voltage supply line, and the corresponding fourth voltage supply line; the plurality of voltage supply lines includes a plurality of repeating groups along the row direction; and one of the plurality of repeating groups includes the corresponding first voltage supply line, the corresponding second voltage supply line, the corresponding third voltage supply line, and the corresponding fourth voltage supply line.

[0027] In another aspect, this disclosure provides a display device including an array substrate manufactured as described herein or by the methods described herein, and an integrated circuit connected to the array substrate. Attached Figure Description

[0028] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0029] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0030] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0031] FIG. 2B Mechanisms for preventing crosstalk in an array substrate according to some embodiments of the present disclosure are illustrated.

[0032] FIG. 2CThis is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0033] FIG. 3A This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0034] FIG. 3B It is shown FIG. 3A A diagram showing the structure of the semiconductor material layers in multiple sub-pixels of the array substrate.

[0035] FIG. 3C It is shown FIG. 3A A diagram showing the structure of the first conductive layer in multiple sub-pixels of the array substrate.

[0036] FIG. 3D It is shown FIG. 3A A diagram showing the structure of the second conductive layer in multiple sub-pixels of the array substrate.

[0037] FIG. 3E It is shown FIG. 3A A diagram showing the structure of the signal line layer in multiple sub-pixels of the array substrate.

[0038] FIG. 4A It is along FIG. 3A A cross-sectional view of line A-A' in the diagram.

[0039] FIG. 4B It is along FIG. 3A A cross-sectional view of line B-B' in the diagram.

[0040] FIG. 4C It is along FIG. 3A A cross-sectional view of the C-C' line in the diagram.

[0041] FIG. 4D It is along FIG. 3A A cross-sectional view of the D-D' line in the diagram.

[0042] FIG. 5A yes FIG. 3A A partial view of the subpixels of the array substrate shown.

[0043] FIG. 5B It shows FIG. 5A Certain selected components.

[0044] FIG. 5C The structure of an anti-interference block according to some embodiments of the present disclosure is shown.

[0045] FIG. 5D This is an enlarged view of a region of an array substrate having a first transistor and a third transistor according to some embodiments of the present disclosure.

[0046] FIG. 5E This is another enlarged view of a region of an array substrate having a third transistor according to some embodiments of the present disclosure.

[0047] FIG. 5F The detailed structure of an anti-interference block according to some embodiments of the present disclosure is shown.

[0048] FIG. 5G A partial structure of one of a plurality of voltage supply lines according to some embodiments of the present disclosure is shown.

[0049] FIG. 5H The structural relationship between the anti-interference block and surrounding components is shown in some embodiments of the present disclosure.

[0050] FIG. 6A yes FIG. 3A A partial view of the subpixels of the array substrate shown.

[0051] FIG. 6B It is along FIG. 6A A cross-sectional view of the E-E' line in the diagram.

[0052] FIG. 7A yes FIG. 3A A partial view of the subpixels of the array substrate shown.

[0053] FIG. 7B It is along FIG. 7A A cross-sectional view of line F-F' in the diagram.

[0054] FIG. 8A for FIG. 5A A partial view of the anti-interference block, semiconductor material layer, and one of the multiple voltage supply lines shown.

[0055] FIG. 8B It is along FIG. 8A A cross-sectional view of the G-G' line in the diagram.

[0056] FIG. 9A This is a cross-sectional image of the array substrate.

[0057] FIG. 9B This is a schematic diagram showing a cross-sectional image of the array substrate.

[0058] FIG. 9C This is a schematic diagram showing a cross-sectional image of the array substrate.

[0059] FIG. 10A This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0060] FIG. 10B It is shown FIG. 10A A diagram showing the structure of the signal line layer in multiple sub-pixels of the array substrate.

[0061] FIG. 10C It is shown FIG. 10A A diagram showing the structure of the anode and pixel-defining layer of the light-emitting elements in multiple sub-pixels of the array substrate.

[0062] FIG. 10D It is shown FIG. 10A A diagram showing the structure of the anode and signal line layers of the light-emitting elements in multiple sub-pixels of the array substrate.

[0063] FIG. 11A This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0064] FIG. 11B It is shown FIG. 11A A diagram showing the structure of the signal line layer in multiple sub-pixels of the array substrate.

[0065] FIG. 11C It is shown FIG. 11A A diagram showing the structure of the anode and pixel-defining layer of the light-emitting elements in multiple sub-pixels of the array substrate.

[0066] FIG. 11D It is shown FIG. 11A A diagram showing the structure of the anode and signal line layers of the light-emitting elements in multiple sub-pixels of the array substrate.

[0067] FIG. 12 This is a diagram illustrating the structure of a third voltage supply line according to some embodiments of the present disclosure. Detailed Implementation

[0068] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0069] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by limitations and disadvantages of related technologies. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes: a plurality of gate lines, a plurality of first reset control signal lines, and a plurality of first reset signal lines extending along a first direction; a plurality of data lines and a plurality of voltage supply lines extending along a second direction; and a pixel driving circuit. Optionally, the pixel driving circuit includes a driving transistor; a first transistor; and a storage capacitor. Optionally, the first transistor includes a gate connected to a corresponding one of the plurality of first reset control signal lines, a source connected to a corresponding one of the plurality of first reset control signal lines, and a drain connected to the gate of the driving transistor and a first capacitor electrode of the storage capacitor. Optionally, the array substrate includes a first initialization connection line connecting a corresponding one of the plurality of first reset signal lines to the source of the first transistor in a corresponding one of a plurality of sub-pixels, the corresponding one of the plurality of first reset signal lines being configured to provide a reset signal to the source of the first transistor via the first initialization connection line. Optionally, the plurality of sub-pixels includes each first sub-pixel, each second sub-pixel, each third sub-pixel, and each fourth sub-pixel. Optionally, the array substrate further includes: a corresponding first voltage supply line in each first sub-pixel; a corresponding second voltage supply line in each second sub-pixel; a corresponding third voltage supply line in each third sub-pixel; a corresponding fourth voltage supply line in each fourth sub-pixel; a corresponding first anode electrically connected to a corresponding first light-emitting element in each first sub-pixel; a corresponding second anode electrically connected to a corresponding second light-emitting element in each second sub-pixel; a corresponding third anode electrically connected to a corresponding third light-emitting element in each third sub-pixel; and a corresponding fourth anode electrically connected to a corresponding fourth light-emitting element in each fourth sub-pixel. Optionally, the orthographic projection of the corresponding third anode onto the substrate at least partially overlaps with the orthographic projection of the first initialization connection line onto the substrate, and covers at least a portion of the orthographic projection of the corresponding third voltage supply line onto the substrate.

[0070] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 1The array substrate comprises an array of subpixels Sp. Each subpixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, multiple voltage supply lines Vdd (e.g., high-voltage supply lines), and multiple low-voltage supply lines (e.g., low-voltage supply lines Vss). The emission of light from each subpixel in the subpixel Sp is driven by the pixel driving circuit PDC. In one example, a high-voltage signal (e.g., a VDD signal) is input to the pixel driving circuit PDC connected to the anode of the light-emitting element through a corresponding one of the multiple voltage supply lines Vdd; a low-voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element through a corresponding one of the multiple low-voltage supply lines (e.g., low-voltage supply line Vss). The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0071] Various suitable pixel driving circuits can be used in this array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, and 8T2C. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro OLEDs. Optionally, the light-emitting element is a micro OLED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0072] FIG. 2AThis is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. Referring to FIG2, in some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding one of a plurality of first reset control signal lines rst1, a source connected to a corresponding one of a plurality of first reset signal lines Vint1, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a gate line GL, a source connected to a data line DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to the gate line GL and a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the first capacitor electrode Ce2 of the driving transistor Td. The gate and drain of a transistor are connected to the drain of a driving transistor Td; a fourth transistor T4 has its gate connected to a corresponding one of a plurality of light-emitting control signal lines em, its source connected to a voltage supply line Vdd, and its drain connected to the source of the driving transistor Td and the drain of the second transistor T2; a fifth transistor T5 has a gate connected to a corresponding one of a plurality of light-emitting control signal lines em, a source connected to the drain of the driving transistor Td and the drain of the third transistor T3, and a drain connected to the anode of the light-emitting element LE; and a sixth transistor T6 has a gate connected to a corresponding one of a plurality of second reset control signal lines rst2, a source connected to a corresponding one of a plurality of second reset signal lines Vint2, and a drain connected to the drain of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the voltage supply line Vdd and the source of the fourth transistor T4.

[0073] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the source of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the drain of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0074] FIG. 2B Mechanisms for preventing crosstalk in an array substrate according to some embodiments of this disclosure are illustrated. Reference FIG. 2B The inventors of this disclosure discovered that the presence of crosstalk between the N1 node and adjacent data lines affects display quality. Crosstalk between the N1 node and adjacent data lines... FIG. 2BThese are denoted as parasitic capacitances Cp1 and Cp2. The inventors of this disclosure have discovered, unexpectedly and surprisingly, that the anti-interference block (which will be described in detail in this disclosure) can effectively reduce crosstalk, particularly vertical crosstalk between the N1 node and adjacent data lines.

[0075] FIG. 3A This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 3A In some embodiments, the array substrate includes a plurality of sub-pixels (e.g., red sub-pixels, green sub-pixels, and blue sub-pixels). In some embodiments, the array substrate includes a plurality of gate lines GL extending along a first direction DR1, a plurality of data lines DL extending along a second direction DR2, and a plurality of voltage supply lines Vdd extending along the second direction DR2. Optionally, the array substrate further includes a plurality of first reset control signal lines rst1 extending along the first direction DR1; a plurality of second reset control signal lines rst2 extending along the first direction DR1; a plurality of first reset signal lines Vint1 extending along the first direction DR1; a plurality of second reset signal lines Vint2 extending along the first direction DR1; and a plurality of light emission control signal lines em extending along the first direction DR1. FIG. 3A The diagram depicts the corresponding positions of multiple transistors in the pixel driving circuit. The pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0076] FIG. 3B It is shown FIG. 3A A diagram showing the structure of the semiconductor material layers in multiple sub-pixels of the array substrate. FIG. 3C It is shown FIG. 3A A diagram showing the structure of the first conductive layer in multiple sub-pixels of the array substrate. FIG. 3D It is shown FIG. 3A A diagram showing the structure of the second conductive layer in multiple sub-pixels of the array substrate. FIG. 3E It is shown FIG. 3A A diagram showing the structure of the signal line layer in multiple sub-pixels of the array substrate. FIG. 4A It is along FIG. 3A A cross-sectional view of line A-A' in the diagram. FIG. 4B It is along FIG. 3A Cross-sectional view of line B-B' in the diagram. (Refer to...) FIG. 3A to FIG. 3E as well as FIG. 4A to FIG. 4BIn some embodiments, the array substrate includes a substrate BS, a semiconductor material layer SML on the substrate BS, a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS, a first conductive layer located on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on the side of the first conductive layer away from the gate insulating layer GI, a second conductive layer located on the side of the insulating layer IN away from the first conductive layer, an interlayer dielectric layer ILD located on the side of the second conductive layer away from the insulating layer IN, a first signal line layer located on the side of the interlayer dielectric layer ILD away from the second conductive layer, and a first planarization layer PLN1 located on the side of the signal line layer away from the interlayer dielectric layer ILD.

[0077] Reference FIG. 2A , FIG. 3A and FIG. 3B In some embodiments, the semiconductor material layer has an integral structure in each sub-pixel. FIG. 3B In the image, the first sub-pixel on the left is marked, indicating the area corresponding to multiple transistors in the pixel driving circuit. These transistors include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor Td. FIG. 3B In the diagram, the sub-pixels on the right are labeled with markers indicating the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The sixth transistor T6 includes an active layer ACT6, a source S6, and a drain D6. The driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, S6, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each sub-pixel are part of the overall structure in that sub-pixel. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, S6, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are in the same layer.

[0078] Reference FIG. 2A , FIG. 3A , FIG. 3C , FIG. 4A as well as FIG. 4B In some embodiments, the first conductive layer includes multiple gate lines GL, multiple first reset control signal lines rst1, multiple light emission control signal lines em, multiple second reset control signal lines rst2, and a first capacitor electrode Ce1 for a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the multiple gate lines GL, multiple first reset control signal lines rst1, multiple light emission control signal lines em, multiple second reset control signal lines rst2, and the first capacitor electrode Ce1 are located in the same layer.

[0079] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same steps. In one example, multiple gate lines GL and the first capacitor electrode Ce1 are located in the same layer when they are formed by one or more steps of the same patterning process performed on the same material layer. In another example, multiple gate lines GL and the first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple gate lines GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0080] Reference FIG. 2A , FIG. 3A and FIG. 3D In some embodiments, the second conductive layer includes multiple first reset signal lines Vint1, a second capacitor electrode Ce2 of a storage capacitor Cst, an anti-interference block IPB, and multiple second reset signal lines Vint2. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the multiple first reset signal lines Vint1, the multiple second reset signal lines Vint2, the anti-interference block IPB, and the second capacitor electrode Ce2 are located in the same layer.

[0081] Reference FIG. 2A , FIG. 3A , FIG. 3B and FIG. 3E In some embodiments, the signal line layer includes multiple voltage supply lines Vdd, multiple data lines DL, node connection lines Cln, a first initialization connection line Cli1, and a second initialization connection line Cli2. The node connection line Cln connects a first capacitor electrode Ce1 to the source of a third transistor T3 in a corresponding sub-pixel. The first initialization connection line Cli1 connects a corresponding one of a plurality of first reset signal lines Vint1 to the source of a first transistor T1 in a corresponding sub-pixel. The second initialization connection line Cli2 connects a corresponding one of a plurality of second reset signal lines Vint2 to the source of a sixth transistor T6 in a corresponding sub-pixel. In some embodiments, the first signal line layer also includes an anode contact pad ACP in a corresponding sub-pixel sp. The anode contact pad ACP connects the source of a fifth transistor T5 in a corresponding sub-pixel sp to the anode in the corresponding sub-pixel sp. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple voltage supply lines Vdd, multiple data lines DL, node connection lines Cln, first initialization connection line Cli1, and second initialization connection line Cli2 are in the same layer.

[0082] FIG. 4C It is along FIG. 3A A cross-sectional view of line C-C' in the diagram. (Refer to...) FIG. 2A , FIG. 3A , FIG. 3E and FIG. 4C In some embodiments, the second initialization connection line Cli2 connects a corresponding one of the plurality of second reset signal lines Vint2 to the source S6 of the sixth transistor T6 in the corresponding sub-pixel. The corresponding one of the plurality of second reset signal lines Vint2 is configured to provide a reset signal to the source S6 of the sixth transistor T6 in the corresponding sub-pixel via the second initialization connection line Cli2. Optionally, the second initialization connection line Cli2 is connected to the corresponding one of the plurality of second reset signal lines Vint2 via a fifth via v5 extending through the interlayer dielectric layer ILD. Optionally, the second initialization connection line Cli2 is connected to the source S6 of the sixth transistor T6 in the corresponding sub-pixel via a sixth via v6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0083] FIG. 4D It is along FIG. 3A A cross-sectional view of line D-D' in the diagram. (Refer to...) FIG. 2A , FIG. 3A , FIG. 3E and FIG. 4D In some embodiments, a first initialization connection line Cli1 connects a corresponding one of a plurality of first reset signal lines Vint1 to the source S1 of a first transistor T1 in the corresponding sub-pixel. The corresponding one of the plurality of first reset signal lines Vint1 is configured to provide a reset signal to the source S1 of the first transistor T1 in the corresponding sub-pixel via the first initialization connection line Cli1. Optionally, the first initialization connection line Cli1 is connected to the corresponding one of the plurality of first reset signal lines Vint1 via a seventh via v7 extending through the interlayer dielectric layer ILD. Optionally, the first initialization connection line Cli1 is connected to the source S1 of the first transistor T1 in the corresponding sub-pixel via an eighth via v8 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0084] Reference FIG. 2A , FIG. 3A , FIG. 3C , FIG. 3D and FIG. 4A In some embodiments, except for the via region H, the orthogonal projection of the second capacitor electrode Ce2 on the substrate BS completely covers the orthogonal projection of the first capacitor electrode Ce1 on the substrate BS with a margin, and no part of the second capacitor electrode Ce2 exists in the via region H. In some embodiments, the signal line layer includes a node connection line Cln, which is located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is in the same layer as multiple voltage supply lines Vdd and multiple data lines DL. Optionally, the array substrate also includes a first via v1 in the via region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1. In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer IN away from the substrate BS. Optionally, the array substrate also includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1 and to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the source S3 of the third transistor, such as... FIG. 4A As shown.

[0085] refer to FIG. 2A , FIG. 3A , FIG. 3D and FIG. 4B In some embodiments, the anti-interference block IPB is in the same layer as the second capacitor electrode Ce2. A corresponding one of the plurality of voltage supply lines Vdd is connected to the anti-interference block IPB through a third via v3. Optionally, the third via v3 extends through the interlayer dielectric layer ILD.

[0086] refer to FIG. 2A , FIG. 3A , FIG. 3D and FIG. 4B In some embodiments, multiple data lines DL and multiple voltage supply lines Vdd are located in the same layer. A corresponding data line DL is connected to the source S2 of the second transistor via a fourth via v4. Optionally, the fourth via v4 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0087] FIG. 5A yes FIG. 3A A partial view of the subpixels of the array substrate shown. FIG. 5B It shows FIG. 5A Certain selected components. FIG. 5C The structure of an anti-interference block according to some embodiments of this disclosure is shown. Reference FIG. 3A , FIG. 5A , FIG. 5B and FIG. 5C In some embodiments, the anti-interference block IPB includes a first arm AM1 and a second arm AM2. For example... FIG. 4A and FIG. 5B As shown, a portion of the node connection line Cln at the location where it connects to the semiconductor material layer SML through the second via v2 can be represented as node N1. (Refer to...) FIG. 3A , FIG. 5A and FIG. 5B Along the first direction DR1, the portion of the node connection line Cln at the location where it is connected to the semiconductor material layer SML through the second via v2 (e.g., node N1) is spaced apart from the first adjacent data line ADL1 by the first arm AM1, and spaced apart from the second adjacent data line ADL2 by the second arm AM2.

[0088] The inventors of this disclosure have discovered, unexpectedly and surprisingly, that crosstalk between the N1 node and adjacent data lines can be significantly reduced by setting an anti-interference block (IPB) as described in this disclosure. Table 1 below shows the unexpected and surprising reduction in crosstalk in the array substrate according to this disclosure compared to a control array substrate.

[0089] Table 1. Reduction of crosstalk between N1 node and adjacent data lines in the array substrate.

[0090]

[0091] In Table 1, “N1 node ~ DL” represents the parasitic capacitance between the N1 node and the adjacent data line; “Cst” represents the storage capacitance; “Vdd ~ DL” represents the parasitic capacitance between the corresponding one of the multiple voltage supply lines Vdd and the adjacent data line; and “DL ~ N2 node” represents the parasitic capacitance between the N2 node and the adjacent data line. Crosstalk data was measured under a black data voltage of 6.5V supplied to multiple data lines. As shown in Table 1, although Vdd ~ DL increases with the anti-interference block IPB, crosstalk (especially vertical crosstalk) can be significantly reduced, thereby greatly improving the display quality of the display panel with this array substrate. Optionally, vertical crosstalk is reduced by at least 50% compared to a control array substrate, for example, at least 52%, at least 54%, at least 56%, at least 58%, or at least 60%. Optionally, the parasitic capacitance between the N1 node and the adjacent data line is reduced by at least 50%, for example, at least 52%, at least 54%, at least 56%, at least 58%, or at least 60%. The slight increase in Vdd~DL can be easily compensated for by a compensation integrated circuit.

[0092] Reference FIG. 3A and FIG. 3B In some embodiments, the source S3 of the third transistor T3 and the active layer ACT3 are part of an overall structure in one of a plurality of sub-pixels. (Refer to...) FIG. 3A and FIG. 4A In some embodiments, the node connection line Cln is connected to the source S3 of the third transistor T3 through the second via v2. (See reference...) FIG. 3A , FIG. 4A , FIG. 5A to FIG. 5C and FIG. 5F In some embodiments, the orthographic projection of the first arm AM1 on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0093] As used herein, an active layer refers to an assembly of a transistor comprising at least a portion of a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. As used herein, a source refers to an assembly of a transistor connected to one side of the active layer, and a drain refers to an assembly of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), an active layer refers to an assembly of a transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the case of a dual-gate transistor, a source refers to an assembly of a transistor connected to the side of the first portion away from the third portion, and a drain refers to an assembly of a transistor connected to the side of the second portion away from the third portion.

[0094] FIG. 3A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) FIG. 4B , FIG. 5A to FIG. 5E , FIG. 5G and FIG. 5G In some embodiments, the third transistor T3 is a "dual-gate" transistor and the first transistor T1 is a "dual-gate" transistor. FIG. 5F This is an enlarged view of a region of an array substrate having a first transistor and a third transistor according to some embodiments of the present disclosure. Reference FIG. 5A to FIG. 5G In some embodiments, the active layer ACT1 of the first transistor T1 passes through a corresponding one of the plurality of first reset control signal lines rst1 twice (alternatively, a corresponding one of the plurality of first reset control signal lines rst1 passes through the active layer ACT1 of the first transistor T1 twice). Similarly, in some embodiments, the active layer ACT3 of the third transistor T3 passes through a corresponding one of the plurality of gate lines GL twice (alternatively, a corresponding one of the plurality of gate lines GL passes through the active layer ACT3 of the third transistor T3 twice). FIG. 2A This is another enlarged view of a region of an array substrate having a third transistor according to some embodiments of the present disclosure. (Refer to...) FIG. 3A In some embodiments, a corresponding one of the plurality of gate lines GL includes a body MB extending along a first direction DR1 and a protrusion GP projecting from the body MB along a second direction DR2. For example... FIG. 3BAs shown, the active layer ACT3 of the third transistor T3 passes through the body MB once and through the protrusion GP once. The active layer ACT3 of the third transistor T3 includes a first portion passing through the protrusion GP, ​​a second portion passing through the body MB, and a third portion connecting the first and second portions. The third portion does not pass through any portion of the corresponding gate line GL. FIG. 4A As shown, the orthographic projection of the first arm AM1 onto the substrate at least partially overlaps with the orthographic projection of the third portion of the active layer ACT3 of the third transistor T3 onto the substrate. Optionally, the third portion has an L-shaped profile.

[0095] refer to FIG. 3A , FIG. 4A , FIG. 5A to FIG. 5G and FIG. 3A In some embodiments, the orthographic projection of the second arm AM2 on the substrate BS at least partially overlaps with the orthographic projection of a corresponding one of the plurality of voltage supply lines Vdd on the substrate BS. Optionally, the orthographic projection of a corresponding one of the plurality of voltage supply lines Vdd on the substrate BS at least partially overlaps with the orthographic projection of the second arm AM2 on the substrate BS (e.g., the orthographic projection of a corresponding one of the plurality of voltage supply lines Vdd substantially covers the orthographic projection of the second arm AM2 on the substrate BS). As used herein, the term "substantially covers" means that one orthographic projection is covered by another orthographic projection by at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%.

[0096] FIG. 4A The detailed structure of an anti-interference block according to some embodiments of this disclosure is shown. (Refer to...) FIG. 5A to FIG. 5G , FIG. 5B , FIG. 5B In some embodiments, the anti-interference block IPB further includes a handle H. A corresponding one of the plurality of voltage supply lines Vdd is connected to the handle H via a third through-hole v3. Optionally, the first arm AM1 includes an L-shaped portion LP and a first end portion TP1. Optionally, the second arm AM2 includes a base BP, a second end portion TP2, and a connecting portion CP connecting the base BP and the second end portion TP2. Optionally, the base BP connects the L-shaped portion LP and the handle H.

[0097] Optionally, the shank H has a basically rectangular shape. Optionally, the base BP has a basically rectangular shape. Optionally, the L-shaped portion has an L-shaped shape. Optionally, the first end portion TP1 has a rectangular shape.

[0098] Optionally, the orthographic projection of the first end portion TP1 on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS, while the orthographic projection of the L-shaped portion LP does not overlap with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0099] As used herein, an active layer refers to an assembly of a transistor comprising at least a portion of a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. As used herein, a source refers to an assembly of a transistor connected to one side of the active layer, and a drain refers to an assembly of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), an active layer refers to an assembly of a transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of which onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the case of a dual-gate transistor, a source refers to an assembly of a transistor connected to the side of the first portion away from the third portion, and a drain refers to an assembly of a transistor connected to the side of the second portion away from the third portion.

[0100] FIG. 5B A partial structure of one of a plurality of voltage supply lines according to some embodiments of the present disclosure is shown. (Refer to...) FIG. 5B to FIG. 5G In some embodiments, a corresponding voltage supply line Vdd of a plurality of voltage supply lines Vdd includes a first parallel portion PA1, a second parallel portion PA2, and a first inclined portion INP, the first inclined portion INP connecting the first parallel portion PA1 and the second parallel portion PA2 along an inclined direction IDR. The first parallel portion PA1 and the second parallel portion PA2 each extend along a direction substantially parallel to a second direction DR2. The first inclined portion INP extends along an inclined angle α relative to the first direction DR1. The connecting portion INP extends along a direction substantially parallel to the inclined direction IDR. (Reference) FIG. 5H In some embodiments, the handle H and the base BP are arranged along a direction substantially parallel to the second direction DR2. As used herein, the term "substantially parallel" means an angle ranging from 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0101] Reference FIG. 5HIn some embodiments, the orthographic projection of the first inclined portion INP on the substrate BS at least partially overlaps with the orthographic projection of the connecting portion CP on the substrate BS (e.g., the orthographic projection of the first inclined portion INP on the substrate BS substantially covers the orthographic projection of the connecting portion CP on the substrate BS). Optionally, the orthographic projection of the first parallel portion PA1 on the substrate BS at least partially overlaps with the orthographic projection of the handle H on the substrate BS. Optionally, the orthographic projection of the second parallel portion PA2 on the substrate BS at least partially overlaps with the orthographic projection of the second end portion TP2 on the substrate BS (e.g., the orthographic projection of the second parallel portion PA2 on the substrate BS substantially covers the orthographic projection of the second end portion TP2 on the substrate BS).

[0102] Reference FIG. 5B , FIG. 5H and FIG. 5B In some embodiments, the drain D1 of the first transistor T1 and the source S3 of the third transistor T3 are part of the overall structure of a corresponding sub-pixel sp among a plurality of sub-pixels sp. The drain D1 of the first transistor T1 is directly connected to the source S3 of the third transistor T3. (Refer to...) FIG. 5H In some embodiments, the node connection line Cln is connected to the source S3 of the third transistor T3 through the second via v2. (Refer to...) FIG. 6A , FIG. 3A , FIG. 6A In some embodiments, the orthographic projection of the drain D1 of the first transistor T1 onto the substrate BS at least partially overlaps with the orthographic projection of the shank H onto the substrate BS, at least partially overlaps with the orthographic projection of the first parallel portion PA1 onto the substrate BS, and at least partially overlaps with the orthographic projection of the base BP onto the substrate BS.

[0103] Reference FIG. 6B , FIG. 6A , FIG. 6A In some embodiments, the portion of the node connection line Cln at the location where it is connected to the semiconductor material layer SML through the second via v2 (e.g.) FIG. 6BThe orthographic projection of the N1 node shown on the substrate BS is substantially surrounded by a combination of the orthographic projection of the anti-interference block IPB on the substrate BS and the orthographic projection of a corresponding one of the plurality of gate lines GL on the substrate BS. Alternatively, the orthographic projection of the anti-interference block IPB on the substrate BS is surrounded by a combination of the orthographic projections of the first adjacent data line ADL1, the second adjacent data line ADL2, a corresponding one of the plurality of first reset control signal lines rst1, and a corresponding one of the plurality of gate lines GL on the substrate BS. As used herein, the term "substantially surrounded" means that at least 50% (e.g., at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, and 100%) of the perimeter of the area is surrounded.

[0104] refer to FIG. 3A The virtual line VL passes through the portion of the node connection line Cln at the location where it is connected to the semiconductor material layer through the second via (e.g.) FIG. 3B The N1 node shown is substantially parallel to the first direction DR1 and also passes through the anti-interference block IPB, the first adjacent data line ADL1, and the second adjacent data line ADL2. (See reference...) FIG. 6A In some embodiments, the virtual line VL passes through the active layer ACT3 of the third transistor T3, the anti-interference block IPB, the first adjacent data line ADL1, and the second adjacent data line ADL2. Optionally, the virtual line VL passes through the first end portion TP1, the second end portion TP2, the first adjacent data line ADL1, and the second adjacent data line ADL2.

[0105] FIG. 6B The structural relationship between the anti-interference block and surrounding components is shown in some embodiments of the present disclosure. FIG. 6B The diagram shows a portion of the node connection line Cln along the virtual line VL at the location where it connects to the semiconductor material layer via the second via (e.g., FIG. 7A The first shortest distance d1 between node N1 (shown) and the first center line ml1 of the first adjacent data line ADL1 along the second direction DR2. FIG. 3A Also shown is a portion of the node connection line Cln along the virtual line VL at the location where it is connected to the semiconductor material layer through the second via (e.g.) FIG. 7A The second shortest distance d2 between node N1 (shown) and the edge of the second parallel portion PA2 on the side closest to the second adjacent data line ADL2. FIG. 7B The third shortest distance d3 between the second center line ml2 of the second adjacent data line ADL2 along the second direction DR2 and the third center line ml3 of the handle H along the second direction DR2 is also shown.

[0106] Optionally, the first shortest distance d1 is in the range of 14.5 μm to 16.5 μm, for example, 14.5 μm to 15.0 μm, 15.0 μm to 15.5 μm, 15.5 μm to 16.0 μm, or 16.0 μm to 16.5 μm. Optionally, the second shortest distance d2 is in the range of 12.5 μm to 14.5 μm, for example, 12.5 μm to 13.0 μm, 13.0 μm to 13.5 μm, 13.5 μm to 14.0 μm, or 14.0 μm to 14.5 μm. Optionally, the third shortest distance d3 is in the range of 16.0 μm to 18.0 μm, for example, 16.0 μm to 16.5 μm, 16.5 μm to 17.0 μm, 17.0 μm to 17.5 μm, or 17.5 μm to 18.0 μm. Optionally, the first shortest distance d1 is 15.53 μm, the second shortest distance d2 is 13.65 μm, and the third shortest distance d3 is 16.87 μm.

[0107] Optionally, the ratio between the first shortest distance, the second shortest distance, and the third shortest distance is in the range of (14.5 to 16.5):(13.5 to 14.5):(16.0 to 18.0).

[0108] The inventors of this disclosure have discovered, unexpectedly and surprisingly, that the structure of each layer of the array substrate results in a significant increase in light transmittance. FIG. 7A yes FIG. 7A A partial view of the subpixels of the array substrate shown. See also FIG. 7B The first initialization connection line Cli1 connects a corresponding one of the plurality of first reset signal lines Vint1 to the source S1 of the first transistor T1 in the corresponding sub-pixel. The corresponding one of the plurality of first reset signal lines Vint1 is configured to provide a reset signal to the source S1 of the first transistor T1 in the corresponding sub-pixel through the first initialization connection line Cli1. FIG. 3A It is along FIG. 3B A cross-sectional view of line E-E' in the diagram. (Refer to...) FIG. 7A and FIG. 7B The first initialization connection line Cli1 is connected to a corresponding one of the plurality of first reset signal lines Vint1 via a seventh via v7 extending through the interlayer dielectric layer ILD. The first initialization connection line Cli1 is also connected to the source S1 of the first transistor T1 in the corresponding sub-pixel via an eighth via v8 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The first initialization connection line Cli1 passes through a corresponding one of the plurality of first reset control signal lines rst1.

[0109] Reference FIG. 7B , FIG. 5A , FIG. 5A to FIG. 5F andFIG. 8A In some embodiments, the source S1, active layer ACT1, and drain D1 of the first transistor T1 are part of the overall structure of a corresponding one of the plurality of sub-pixels. (Refer to...) FIG. 5A In some embodiments, the source S1 of the first transistor T1 passes through a corresponding one of the plurality of data lines DL. Optionally, the first initialization connection line Cli1 is separated from the active layer ACT1 and drain D1 of the first transistor T1 by a corresponding one of the plurality of data lines DL. Optionally, the orthographic projection of the first initialization connection line Cli1 on the substrate is separated from the orthographic projection of the active layer ACT1 and drain D1 of the first transistor T1 on the substrate by the orthographic projection of a corresponding one of the plurality of data lines DL on the substrate.

[0110] In some embodiments, the first initialization connection line Cli1 extends in a direction substantially parallel to the second direction DR2. Optionally, the source S1 of the first transistor T1 extends in a direction substantially parallel to the first direction DR1. Optionally, the source S1 of the first transistor T1 and the active layer ACT1 are arranged in a direction substantially parallel to the first direction DR1.

[0111] FIG. 8B yes FIG. 8A A partial view of the subpixels of the array substrate shown. (Refer to...) FIG. 8A The second initialization connection line Cli2 connects a corresponding one of the plurality of second reset signal lines Vint2 to the source of the sixth transistor T6 in the corresponding sub-pixel. The corresponding one of the plurality of second reset signal lines Vint2 is configured to provide a reset signal to the source S6 of the sixth transistor T6 in the corresponding sub-pixel via the second initialization connection line Cli2. FIG. 8B It is along FIG. 9A The cross-sectional view of line F-F' in the diagram. (Refer to...) FIG. 9A and FIG. 9B The second initialization connection line Cli2 is connected to a corresponding one of the plurality of second reset signal lines Vint2 via a fifth via v5 extending through the interlayer dielectric layer ILD. The second initialization connection line Cli2 is also connected to the source S6 of the sixth transistor T6 in the corresponding sub-pixel via a sixth via v6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second initialization connection line Cli2 passes through a corresponding one of the plurality of second reset control signal lines rst2.

[0112] Reference FIG. 9B , FIG. 9C , FIG. 9C and FIG. 10A In some embodiments, the source S6, active layer ACT6, and drain D6 of the sixth transistor T6 are part of the overall structure in a corresponding sub-pixel among a plurality of sub-pixels. (Refer to...)FIG. 10B In some embodiments, the source S6 of the sixth transistor T6 passes through a corresponding one of the plurality of data lines DL. Optionally, the second initialization connection line Cli2 is separated from the active layer ACT6 and drain D6 of the sixth transistor T6 by a corresponding one of the plurality of data lines DL. Optionally, the orthographic projection of the second initialization connection line Cli2 on the substrate is separated from the orthographic projection of the active layer ACT6 and drain D6 of the sixth transistor T6 on the substrate by the orthographic projection of a corresponding one of the plurality of data lines DL on the substrate.

[0113] In some embodiments, the second initialization connection line Cli2 extends in a direction substantially parallel to the second direction DR2. Optionally, the source S6 of the sixth transistor T6 extends in a direction substantially parallel to the first direction DR1. Optionally, the source S6 of the sixth transistor T6 and the active layer ACT6 are arranged in a direction substantially parallel to the first direction DR1.

[0114] The inventors of this disclosure have discovered, unexpectedly and surprisingly, that the storage capacitor Cst can be further increased by setting up an anti-interference block IPB. See also... FIG. 10A In some embodiments, the drain D1 of the first transistor T1 and a portion of the semiconductor material layer SML at the location connected to the node connection line Cln are arranged along a direction substantially parallel to the second direction DR2. Optionally, the portion of the semiconductor material layer SML at the location connected to the node connection line Cln is the source S3 of the third transistor T3. Optionally, the source S3 of the third transistor T3 and the drain D1 of the first transistor T1 are part of an overall structure in a corresponding one of a plurality of sub-pixels. Optionally, the source S3 of the third transistor T3 and the drain D1 of the first transistor T1 are arranged along a direction substantially parallel to the second direction DR2.

[0115] Reference FIG. 10C In some embodiments, the drain D1 of the first transistor T1 and the portion of the semiconductor material layer SML at the location connected to the node connection line Cln are arranged in a direction substantially parallel to the arrangement direction of the shank H and the base BP. Optionally, the source S3 of the third transistor T3 and the drain D1 of the first transistor T1 are arranged in a direction substantially parallel to the arrangement direction of the shank H and the base BP.

[0116] FIG. 10A for FIG. 10D A partial view of the anti-interference block, semiconductor material layer, and one of the multiple voltage supply lines shown. FIG. 10A It is along FIG. 10A A cross-sectional view of the G-G' line. (Refer to...) FIG. 10B and FIG. 10A to FIG. 10CIn some embodiments, the orthographic projection of the anti-interference block IPB on the substrate BS at least partially overlaps with the orthographic projection of the drain D1 of the first transistor T1 on the substrate BS (e.g., the orthographic projection of the anti-interference block IPB on the substrate BS substantially covers the orthographic projection of the drain D1 of the first transistor T1 on the substrate BS). Optionally, the combination of the orthographic projection of the base BP of the second arm AM2 on the substrate BS and the orthographic projection of the shank H on the substrate BS at least partially overlaps with the orthographic projection of the drain D1 of the first transistor T1 on the substrate BS (e.g., the combination of the orthographic projection of the base BP of the second arm AM2 on the substrate BS and the orthographic projection of the shank H on the substrate BS substantially covers the orthographic projection of the drain D1 of the first transistor T1 on the substrate BS).

[0117] As used herein, an active layer refers to an assembly of a transistor comprising at least a portion of a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. As used herein, a source refers to an assembly of a transistor connected to one side of the active layer, and a drain refers to an assembly of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), an active layer refers to an assembly of a transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of which onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the case of a dual-gate transistor, a source refers to an assembly of a transistor connected to the side of the first portion away from the third portion, and a drain refers to an assembly of a transistor connected to the side of the second portion away from the third portion.

[0118] The inventors of this disclosure have discovered that the uniformity of the anode in a display panel can adversely affect image display. For example, color shift can be caused by anode tilt. This disclosure also reveals that the signal lines beneath the anode can significantly influence the degree of anode tilt. In one example, signal lines are positioned on one side beneath the anode, while no signal lines are present on the other side. This results in surface inhomogeneity of the planarization layer on top of the signal lines. This surface inhomogeneity of the planarization layer, in turn, causes anode tilt on top of the planarization layer. FIG. 10B This is a cross-sectional image of the array substrate. (Example) FIG. 10DAs shown, the presence of signal line 1 beneath the left portion of planarization layer 2 causes unevenness in the planarized surface, which in turn causes the anode 3 on top of planarization layer 2 to tilt to the right. The tilted anode reflects more light towards the right side of the display panel. In the display panel, the anodes associated with sub-pixels of different colors have different tilt angles, so the light reflected by the anodes in sub-pixels of different colors is reflected at different angles to reflect different colors of light. The cumulative effect of this problem leads to color shift at wide viewing angles.

[0119] FIG. 10B This is a schematic diagram showing a cross-sectional image of the array substrate. (Example) FIG. 10D As shown, there is no signal line 1 below the untilted third anode 3-3. Signal line 1 is located below anodes 3-1 and 3-2. However, the signal line is only located below the right side of anode 3-1 and only below the left side of anode 3-2, which causes these two anodes to be tilted. Anodes 3-1, 3-2, and 3-3 are the anodes of the red, green, and blue sub-pixels, respectively. Because the tilt angles of the anodes in the three sub-pixels of different colors are different from each other, color shift occurs at large viewing angles.

[0120] FIG. 9A to FIG. 9C This is a schematic diagram showing a cross-sectional image of the array substrate. (Example) FIG. 10D As shown, the signal lines are located below the left and right portions of anode 3-1, and below the left and right portions of anode 3-2. All anodes are essentially flat, thus mitigating the color shift problem.

[0121] FIG. 11A This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. FIG. 11B It is shown FIG. 11A A diagram showing the structure of the signal line layer in multiple sub-pixels of the array substrate. FIG. 11C It is shown FIG. 11A A diagram showing the structure of the anode and pixel-defining layer of the light-emitting elements in multiple sub-pixels of the array substrate. FIG. 11D It is shown FIG. 11A A diagram showing the structure of the anode and signal line layers of the light-emitting elements in multiple sub-pixels of the array substrate. (Refer to...) FIG. 11A to FIG. 11D and FIG. 10BThe image depicts first sub-pixels sp1, second sub-pixels sp2, third sub-pixels sp3, and fourth sub-pixels sp4. In some embodiments, the signal line layer includes a first anode contact pad ACP1 in each first sub-pixel sp1, a second anode contact pad ACP2 in each second sub-pixel sp2, a third anode contact pad ACP3 in each third sub-pixel sp3, and a fourth anode contact pad ACP4 in each fourth sub-pixel sp4. These anode contact pads connect the sources of fifth transistors in each first sub-pixel sp1, second sub-pixel sp2, third sub-pixel sp3, and fourth sub-pixel sp4 to the anodes in the respective first sub-pixel sp1, second sub-pixel sp2, third sub-pixel sp3, and fourth sub-pixel sp4. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the first anode contact pad ACP1, the second anode contact pad ACP2, the third anode contact pad ACP3, and the fourth anode contact pad ACP4 are in the same layer.

[0122] refer to FIG. 11B In some embodiments, the array substrate includes a corresponding first anode AD1 in each first sub-pixel sp1, a corresponding second anode AD2 in each second sub-pixel sp2, a corresponding third anode AD3 in each third sub-pixel sp3, and a corresponding fourth anode AD4 in each fourth sub-pixel sp4. Each first anode AD1, each second anode AD2, each third anode AD3, and each fourth anode AD4 are respectively the anodes of a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element in each first sub-pixel sp1, each second sub-pixel sp2, each third sub-pixel sp3, and each fourth sub-pixel sp4. In some embodiments, the array substrate further includes a pixel defining layer PDL located on the side of each first anode AD1, each second anode AD2, each third anode AD3, and each fourth anode AD4 away from the first planarization layer PLN1. The array substrate also includes a first sub-pixel opening SA1, a second sub-pixel opening SA2, a third sub-pixel opening SA3, and a fourth sub-pixel opening SA4, which extend through the pixel definition layer PDL and expose portions of the corresponding first anode AD1, the corresponding second anode AD2, the corresponding third anode AD3, and the corresponding fourth anode AD4, respectively.

[0123] Reference FIG. 11B and FIG. 11D In some embodiments, the plurality of voltage supply lines Vdd includes a corresponding first voltage supply line Vdd1 in each first sub-pixel sp1, a corresponding second voltage supply line Vdd2 in each second sub-pixel sp2, a corresponding third voltage supply line Vdd3 in each third sub-pixel sp3, and a corresponding fourth voltage supply line Vdd4 in each fourth sub-pixel sp4. In some embodiments, such as FIG. 11D As shown, the corresponding first voltage supply line Vdd1, the corresponding second voltage supply line Vdd2, the corresponding third voltage supply line Vdd3, and the corresponding fourth voltage supply line Vdd4 have essentially the same structure. For example, the corresponding portions of the corresponding first voltage supply line Vdd1, the corresponding second voltage supply line Vdd2, the corresponding third voltage supply line Vdd3, and the corresponding fourth voltage supply line Vdd4 in each first sub-pixel sp1, each second sub-pixel sp2, each third sub-pixel sp3, and each fourth sub-pixel sp4 have the same shape and size.

[0124] refer to FIG. 11D The signal lines under the corresponding first anode AD1 are distributed in a relatively uniform and balanced manner relative to the corresponding first anode AD1. Similarly, the signal lines under the corresponding second anode AD2 are distributed in a relatively uniform and balanced manner relative to the corresponding second anode AD2. The signal lines under the corresponding fourth anode AD4 are distributed in a relatively uniform and balanced manner relative to the corresponding fourth anode AD4. (As in combination...) FIG. 12 As discussed, when the signal lines are uniformly distributed below the anode, the anode is unlikely to tilt. However, the signal lines below the corresponding third anode AD3 are not distributed in a uniform and balanced manner. For example, in FIG. 12 In the area UBA shown, the first initialization connection line Cli1 is positioned below the left portion of the corresponding third anode AD3. However, there is no signal line below the right portion of the corresponding third anode AD3. Without compensation, the unbalanced distribution of signal lines below the corresponding third anode AD3 will cause anode tilt and color shift in the display panel, resulting in color shift, especially at wide viewing angles.

[0125] FIG. 11D This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. FIG. 12 It is shown FIG. 5G A diagram showing the structure of the signal line layer in multiple sub-pixels of the array substrate. FIG. 12 It is shown FIG. 11C A diagram showing the structure of the anode and pixel-defining layer of the light-emitting elements in multiple sub-pixels of the array substrate. FIG. 11D It is shown FIG. 12A diagram showing the structure of the anode and signal line layers of the light-emitting elements in multiple sub-pixels of the array substrate. (Refer to...) ​ In some embodiments, the plurality of voltage supply lines Vdd includes a corresponding first voltage supply line Vdd1 in each first sub-pixel sp1, a corresponding second voltage supply line Vdd2 in each second sub-pixel sp2, a corresponding third voltage supply line Vdd3 in each third sub-pixel sp3, and a corresponding fourth voltage supply line Vdd4 in each fourth sub-pixel sp4. In some embodiments, such as ​ As shown, the corresponding first voltage supply line Vdd1, the corresponding second voltage supply line Vdd2, and the corresponding fourth voltage supply line Vdd4 have substantially the same structure. For example, the corresponding portions of the corresponding first voltage supply line Vdd1, the corresponding second voltage supply line Vdd2, and the corresponding fourth voltage supply line Vdd4 in each first sub-pixel sp1, each second sub-pixel sp2, and each fourth sub-pixel sp4 have the same shape and size.

[0126] The inventors of this disclosure have discovered, unexpectedly and surprisingly, that color shift problems associated with the third anode (AD) can be significantly reduced or eliminated by making the shape of the corresponding third voltage supply line Vdd3 different from the shapes of the corresponding first voltage supply line Vdd1, the corresponding second voltage supply line Vdd2, and the corresponding fourth voltage supply line Vdd4. (Reference) ​ In some embodiments, compared to the corresponding first voltage supply line Vdd1, the corresponding second voltage supply line Vdd2, and the corresponding fourth voltage supply line Vdd4, the corresponding third voltage supply line Vdd3 includes a main body portion MP and a loop portion LO connected to the main body portion MP. (See reference...) ​ and ​ ,exist ​ In the area UBA shown, the first initialization connection line Cli1 is positioned below the left portion of the corresponding third anode AD3; and the loop portion LO is positioned below the right portion of the corresponding third anode AD3. By positioning the loop portion LO below the right portion of the corresponding third anode AD3, the signal lines (the first initialization connection line Cli1 and the loop portion LO) are more evenly distributed below the corresponding third anode AD3, thereby preventing the corresponding third anode AD3 from tilting. Therefore, color shift problems can be mitigated.

[0127] like ​As shown, the orthographic projection of the corresponding third anode AD3 on the substrate at least partially overlaps with the orthographic projection of the first initialization connection line Cli1 on the substrate (e.g., the orthographic projection of the corresponding third anode AD3 on the substrate substantially covers the orthographic projection of the first initialization connection line Cli1 on the substrate), and at least partially overlaps with the orthographic projection of the loop portion LO on the substrate (e.g., the orthographic projection of the corresponding third anode AD3 on the substrate substantially covers the orthographic projection of the loop portion LO on the substrate). Furthermore, the orthographic projection of a corresponding one of the plurality of data lines DL on the corresponding third anode AD3 is between the orthographic projection of the first initialization connection line Cli1 on the corresponding third anode AD3 and the orthographic projection of the loop portion LO on the corresponding third anode AD3, thereby achieving a balanced distribution of signal lines under the corresponding third anode AD3.

[0128] ​ This is a diagram illustrating the structure of a third voltage supply line according to some embodiments of the present disclosure. Reference ​ In some embodiments, the loop portion PO includes a first loop sub-portion LO1, a second loop sub-portion LO2, and a third loop sub-portion LO3, which is substantially parallel to the second direction DR2, a direction substantially parallel to the first direction DR1, and a direction substantially parallel to the first direction DR1. The second loop sub-portion LO2 and the third loop sub-portion LO3 respectively connect the first loop sub-portion LO1 to the body portion of the corresponding third voltage supply line Vdd3. The array substrate also includes a loop hole LH extending through the corresponding third voltage supply line Vdd3. The periphery of the loop hole LH is surrounded by a combination of the first loop sub-portion LO1, the second loop sub-portion LO2, the third loop sub-portion LO3, and the body portion MP.

[0129] like ​ and ​ As shown, in some embodiments, the orthographic projection of the corresponding third anode AD3 on the substrate at least partially overlaps with the orthographic projection of the first initialization connection line Cli1 on the substrate (e.g., the orthographic projection of the corresponding third anode AD3 on the substrate substantially covers the orthographic projection of the first initialization connection line Cli1 on the substrate), and at least partially overlaps with the orthographic projection of the first loop sub-part LO1 on the substrate (e.g., the orthographic projection of the corresponding third anode AD3 on the substrate substantially covers the orthographic projection of the first loop sub-part LO1 on the substrate). Furthermore, the orthographic projection of a corresponding one of the plurality of data lines DL on the corresponding third anode AD3 is between the orthographic projection of the first initialization connection line Cli1 on the corresponding third anode AD3 and the orthographic projection of the first loop sub-part LO1 on the corresponding third anode AD3, thereby achieving a balanced distribution of signal lines under the corresponding third anode AD3.

[0130] See​ and ​ As described above, in some embodiments, the corresponding third voltage supply line Vdd3 includes a first parallel portion PA1, a second parallel portion PA2, and a first inclined portion INP connecting the first parallel portion PA1 and the second parallel portion PA2 along the inclined direction IDR. The first parallel portion PA1 and the second parallel portion PA2 extend in directions substantially parallel to the second direction DR2. The first inclined portion INP extends along an angle α relative to the first direction DR1. The connecting portion INP extends in a direction substantially parallel to the inclined direction IDR. In some embodiments, the second loop sub-portion LO2 and the third loop sub-portion LO3 respectively connect the first loop sub-portion LO1 to the first parallel portion PA1 of the body portion MP. The periphery of the loop hole LH is surrounded by a combination of the first loop sub-portion LO1, the second loop sub-portion LO2, the third loop sub-portion LO3, and the first parallel portion PA1. Optionally, the corresponding third voltage supply line Vdd3 also includes a second inclined portion INP2 connected to the second parallel portion PA2 and a third parallel portion PA3 connected to the second inclined portion INP2. The third parallel portion PA3 extends in a direction substantially parallel to the second direction DR2. The second inclined portion INP2 extends along a second inclined angle β relative to the first direction DR1. The inclined angle α and the second inclined angle β are complementary angles. The orthographic projection of the second inclined portion INP2 on the substrate BS does not overlap with the orthographic projection of the connecting portion CP on the substrate BS.

[0131] refer to ​ , ​ , ​ By positioning the first initialization connection line Cli1 along the first edge E1 of the corresponding third anode AD3 on the first side SD1 below the corresponding third anode AD3, and positioning the loop portion LP along the second edge E2 of the corresponding third anode AD3 on the second side SD2 below the corresponding third anode AD3, the signal lines are distributed below the corresponding third anode AD3. Optionally, the first edge E1 and the second edge E2 are substantially parallel to each other. Optionally, the first side SD1 and the second side SD2 are opposite to each other.

[0132] In another aspect, this disclosure provides a display panel comprising an array substrate manufactured as described herein or by the methods described herein, and a counter substrate facing the array substrate. Optionally, the display panel is an organic light-emitting diode (OLED) display panel. Optionally, the display panel is a micro-LED display panel.

[0133] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate.

[0134] In another aspect, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of gate lines, a plurality of first reset control signal lines, and a plurality of first reset signal lines extending along a first direction; forming a plurality of data lines extending along a second direction; and forming a pixel driving circuit. Optionally, forming the pixel driving circuit includes forming a driving transistor; forming a first transistor; and forming a storage capacitor. Optionally, forming the first transistor includes forming a gate connected to a corresponding one of the plurality of first reset control signal lines, forming a source connected to a corresponding one of the plurality of first reset signal lines, and forming a drain connected to the gate of the driving transistor and a first capacitor electrode of the storage capacitor. Optionally, forming the array substrate includes forming a first initialization connection line connecting a corresponding one of the plurality of first reset signal lines to the source of the first transistor in a corresponding sub-pixel of a plurality of sub-pixels, wherein the corresponding one of the plurality of first reset signal lines is configured to provide a reset signal to the source of the first transistor via the first initialization connection line. Optionally, the first initialization connection line and the plurality of data lines are formed in the same layer. Optionally, the method further includes forming a via extending through the interlayer dielectric layer; the first initialization connection line is formed to be connected to a corresponding one of the plurality of first reset signal lines through the via extending through the interlayer dielectric layer. Optionally, the method further includes forming a via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer; the first initialization connection line is formed to be connected to the source of the first transistor through the via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. Optionally, the first initialization connection line is formed to pass through a corresponding one of the plurality of first reset control signal lines.

[0135] In some embodiments, the active layer and drain of the first transistor are formed as part of an integral structure in a corresponding sub-pixel of a plurality of sub-pixels. Optionally, at least a portion of the source of the first transistor is formed to pass through a corresponding one of a plurality of data lines. Optionally, the orthographic projection of the first initialization connection line on the substrate is spaced apart from the orthographic projections of at least a portion of the active layer and at least a portion of the drain of the first transistor on the substrate by means of the orthographic projections of a corresponding one of the plurality of data lines on the substrate.

[0136] In some embodiments, the method further includes forming a plurality of second reset control signal lines and a plurality of second reset signal lines extending respectively along a first direction. Optionally, forming the pixel driving circuit further includes forming a second transistor; forming a third transistor, forming a fourth transistor, forming a fifth transistor, and forming a sixth transistor. Optionally, forming the sixth transistor includes forming a gate connected to a corresponding one of the plurality of second reset control signal lines, forming a source connected to a corresponding one of the plurality of second reset signal lines, and forming a drain connected to the drain of the fifth transistor and the anode of the light-emitting element. Optionally, forming the array substrate includes forming a second initialization connection line, the second initialization connection line connecting a corresponding one of the plurality of second reset signal lines and the source of the sixth transistor in a corresponding one of the plurality of sub-pixels, the corresponding one of the plurality of second reset signal lines being configured to provide a reset signal to the source of the sixth transistor through the second initialization connection line. Optionally, the method further includes forming a via extending through an interlayer dielectric layer; the second initialization connection line is connected to a corresponding one of the plurality of second reset signal lines through the via extending through the interlayer dielectric layer. Optionally, the method further includes forming a via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer; the second initialization connection line is connected to the source of the sixth transistor through the via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. Optionally, the second initialization connection line is formed to pass through a corresponding one of a plurality of second reset control signal lines.

[0137] In some embodiments, the active layer and drain of the sixth transistor are formed as part of an integral structure in a corresponding sub-pixel of a plurality of sub-pixels. Optionally, the source of the sixth transistor is formed to pass through a corresponding one of a plurality of data lines. Optionally, the orthographic projection of the second initialization connection line on the substrate and the orthographic projection of the active layer and drain of the sixth transistor on the substrate are spaced apart by the orthographic projection of a corresponding one of the plurality of data lines on the substrate.

[0138] In some embodiments, the method further includes forming a plurality of voltage supply lines extending respectively along a second direction. Optionally, forming a storage capacitor includes forming a first capacitor electrode, forming a second capacitor electrode electrically connected to a corresponding one of the plurality of voltage supply lines, and forming an insulating layer between the first capacitor electrode and the second capacitor electrode. Optionally, forming an array substrate includes forming a semiconductor material layer on a substrate; forming a node connection line in the same layer as a corresponding one of the plurality of voltage supply lines, the node connection line being connected to the first capacitor electrode through a first via and to the semiconductor material layer through a second via; and forming an anti-interference block in the same layer as the second capacitor electrode, the corresponding one of the plurality of voltage supply lines being connected to the anti-interference block through a third via.

[0139] In some embodiments, forming an array substrate includes forming a semiconductor material layer on a substrate. Optionally, at least a portion of the drain of the first transistor and a portion of the semiconductor material layer at the location connected to the node connection line are arranged along a direction substantially parallel to the second direction.

[0140] In some embodiments, forming a pixel driving circuit further includes forming a second transistor and forming a third transistor. Optionally, forming the second transistor includes forming a gate connected to a corresponding one of a plurality of gate lines, forming a source connected to a corresponding one of a plurality of data lines, and forming a drain connected to the source of a driving transistor. Optionally, forming the third transistor includes forming a gate connected to a corresponding one of a plurality of gate lines, forming a source connected to a first capacitor electrode and the gate of the driving transistor, and forming a drain connected to the drain of the driving transistor. Optionally, a portion of the semiconductor material layer at a location connected to the node connection line includes at least a portion of the source of the third transistor. Optionally, the source of the third transistor and the drain of the first transistor are formed as part of an integral structure in a corresponding one of a plurality of sub-pixels. Optionally, at least a portion of the source of the third transistor and at least a portion of the drain of the first transistor are arranged along a direction substantially parallel to the second direction.

[0141] In some embodiments, the orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of the drain of the first transistor on the substrate (e.g., the orthographic projection of the anti-interference block on the substrate substantially covers the orthographic projection of the drain of the first transistor on the substrate).

[0142] In some embodiments, forming the anti-interference block includes forming a handle, forming a first arm, and forming a second arm. Optionally, a corresponding voltage supply line among the plurality of voltage supply lines is formed to be connected to the handle through the third via. Optionally, forming the first arm includes forming an L-shaped portion and forming a first end portion. Optionally, forming the second arm includes forming a base, forming a second end portion, and forming a connecting portion connecting the base and the second end portion. Optionally, the base is formed to connect the L-shaped portion and the handle. Optionally, along the first direction, the portion of the node connection line at the location where it is connected to the semiconductor material layer through the second via is separated from a first adjacent data line by the first arm and from a second adjacent data line by the second arm.

[0143] In some embodiments, the combination of the orthographic projection of the base of the second arm onto the substrate and the orthographic projection of the shank onto the substrate at least partially overlaps with the orthographic projection of the drain of the first transistor onto the substrate (e.g., the combination of the orthographic projection of the base of the second arm onto the substrate and the orthographic projection of the shank onto the substrate substantially covers the orthographic projection of the drain of the first transistor onto the substrate).

[0144] As used herein, an active layer refers to an assembly of a transistor comprising at least a portion of a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. As used herein, a source refers to an assembly of a transistor connected to one side of the active layer, and a drain refers to an assembly of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), an active layer refers to an assembly of a transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of which onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the case of a dual-gate transistor, a source refers to an assembly of a transistor connected to the side of the first portion away from the third portion, and a drain refers to an assembly of a transistor connected to the side of the second portion away from the third portion.

[0145] In some embodiments, forming the pixel driving circuit further includes forming a second transistor and a third transistor. Optionally, forming the second transistor includes forming a gate connected to a corresponding one of a plurality of gate lines, forming a source connected to a corresponding one of a plurality of data lines, and forming a drain connected to the source of the driving transistor. Optionally, forming the third transistor includes forming a gate connected to a corresponding one of the plurality of gate lines, forming a source connected to the first capacitor electrode and the gate of the driving transistor, and forming a drain connected to the drain of the driving transistor. Optionally, at least a portion of the drain of the first transistor and a portion of the semiconductor material layer located at the connection point with the node connection line are arranged in a direction substantially parallel to the arrangement direction of the shank and the base. Optionally, at least a portion of the source of the third transistor and at least a portion of the drain of the first transistor are arranged in a direction substantially parallel to the arrangement direction of the shank and the base.

[0146] In some embodiments, forming a plurality of sub-pixels includes forming a corresponding first sub-pixel, forming a corresponding second sub-pixel, forming a corresponding third sub-pixel, and forming a corresponding fourth sub-pixel. Optionally, forming an array substrate further includes forming a corresponding first voltage supply line in each first sub-pixel; forming a corresponding second voltage supply line in each second sub-pixel; forming a corresponding third voltage supply line in each third sub-pixel; forming a corresponding fourth voltage supply line in each fourth sub-pixel; forming a corresponding first anode electrically connected to a corresponding first light-emitting element in each first sub-pixel; forming a corresponding second anode electrically connected to a corresponding second light-emitting element in each second sub-pixel; forming a corresponding third anode electrically connected to a corresponding third light-emitting element in each third sub-pixel; and forming a corresponding fourth anode electrically connected to a corresponding fourth light-emitting element in each fourth sub-pixel. Optionally, forming a corresponding third voltage supply line includes forming a main body portion and forming a loop portion connected to the main body portion. Optionally, the orthographic projection of the corresponding third anode on the substrate at least partially overlaps with the orthographic projection of the first initialization connection line on the substrate (e.g., the orthographic projection of the corresponding third anode on the substrate substantially covers the orthographic projection of the first initialization connection line on the substrate), and at least partially overlaps with the orthographic projection of the loop portion on the substrate (e.g., the orthographic projection of the corresponding third anode on the substrate substantially covers the orthographic projection of the loop portion on the substrate).

[0147] In some embodiments, the orthographic projection of a corresponding one of the plurality of data lines onto the corresponding third anode lies between the orthographic projection of the first initialization connection line onto the corresponding third anode and the orthographic projection of the loop portion onto the corresponding third anode.

[0148] In some embodiments, the loop portion includes a first loop sub-portion along a direction substantially parallel to the second direction, a second loop sub-portion substantially parallel to the first direction, and a third loop sub-portion substantially parallel to the first direction. Optionally, the second loop sub-portion and the third loop sub-portion respectively connect the first loop sub-portion to the body portion of a corresponding third voltage supply line. Optionally, forming the array substrate further includes forming a loop hole extending through the corresponding third voltage supply line. Optionally, the periphery of the loop hole is surrounded by a combination of the first loop sub-portion, the second loop sub-portion, the third loop sub-portion, and the body portion.

[0149] In some embodiments, the orthographic projection of the corresponding third anode on the substrate at least partially overlaps with the orthographic projection of the first initialization connection line on the substrate (e.g., the orthographic projection of the corresponding third anode on the substrate substantially covers the orthographic projection of the first initialization connection line on the substrate), and at least partially overlaps with the orthographic projection of the first loop sub-portion on the substrate (e.g., the orthographic projection of the corresponding third anode on the substrate substantially covers the orthographic projection of the first loop sub-portion on the substrate). Optionally, the orthographic projection of a corresponding one of the plurality of data lines on the corresponding third anode lies between the orthographic projection of the first initialization connection line on the corresponding third anode and the orthographic projection of the first loop sub-portion on the corresponding third anode.

[0150] In some embodiments, the source and active layer of the third transistor are formed as part of an integral structure in a corresponding sub-pixel of a plurality of sub-pixels. Optionally, the node connection line is formed to be connected to the source of the third transistor through the second via. Optionally, the orthographic projection of the first arm on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate. Optionally, the orthographic projection of a corresponding voltage supply line among the plurality of voltage supply lines on the substrate at least partially overlaps with the orthographic projection of the second arm on the substrate (e.g., the orthographic projection of a corresponding voltage supply line among the plurality of voltage supply lines substantially covers the orthographic projection of the second arm on the substrate). Optionally, the orthographic projection of the first end portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate. Optionally, the orthographic projection of the first end portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate.

[0151] As used herein, an active layer refers to an assembly of a transistor comprising at least a portion of a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. As used herein, a source refers to an assembly of a transistor connected to one side of the active layer, and a drain refers to an assembly of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), an active layer refers to an assembly of a transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of which onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the case of a dual-gate transistor, a source refers to an assembly of a transistor connected to the side of the first portion away from the third portion, and a drain refers to an assembly of a transistor connected to the side of the second portion away from the third portion.

[0152] In some embodiments, forming a corresponding line among a plurality of voltage supply lines includes forming a first parallel portion, forming a second parallel portion, and forming a first inclined portion connecting the first and second parallel portions along an inclined direction. Optionally, the first and second parallel portions extend in directions substantially parallel to the second direction. Optionally, the first inclined portion extends along an angle of inclination relative to the first direction. Optionally, the handle and the base are arranged in directions substantially parallel to the second direction. Optionally, the connecting portion extends in a direction substantially parallel to the inclined direction.

[0153] In some embodiments, the orthographic projection of the first inclined portion onto the substrate substantially overlaps the orthographic projection of the connecting portion onto the substrate. Optionally, the orthographic projection of the first parallel portion onto the substrate at least partially overlaps the orthographic projection of the handle onto the substrate. Optionally, the orthographic projection of the second parallel portion onto the substrate substantially overlaps the orthographic projection of the second end portion onto the substrate.

[0154] In some embodiments, forming a pixel driving circuit further includes forming a second transistor and forming a third transistor. Optionally, forming the second transistor includes forming a gate connected to a corresponding one of a plurality of gate lines, forming a source connected to a corresponding one of a plurality of data lines, and forming a drain connected to the source of a driving transistor. Optionally, forming the third transistor includes forming a gate connected to a corresponding one of a plurality of gate lines, forming a source connected to a first capacitor electrode and the gate of the driving transistor, and forming a drain connected to the drain of the driving transistor. Optionally, the drain of the first transistor and the source of the third transistor are formed as part of an integral structure in a corresponding sub-pixel among a plurality of sub-pixels, and at least a portion of the drain of the first transistor is directly connected to at least a portion of the source of the third transistor. Optionally, the node connection line is formed to be connected to the source of the third transistor through the second via. Optionally, the orthographic projection of at least a portion of the drain of the first transistor on the substrate at least partially overlaps with the orthographic projection of the stalk on the substrate, at least partially overlaps with the orthographic projection of the first parallel portion on the substrate, and at least partially overlaps with the orthographic projection of the base on the substrate.

[0155] In some embodiments, forming the array substrate further includes forming a gate insulating layer on the side of the semiconductor material layer away from the substrate, with a first capacitor electrode located on the side of the gate insulating layer away from the substrate; and forming an interlayer dielectric layer on the side of the second capacitor electrode away from the insulating layer, with node connection lines and multiple voltage supply lines located on the side of the interlayer dielectric layer away from the second capacitor electrode. Optionally, the first via is formed in a hole region that does not include a portion of the second capacitor electrode and extends through the interlayer dielectric layer and the insulating layer, wherein, except for the hole region, the orthographic projection of the second capacitor electrode on the substrate completely covers the orthographic projection of the first capacitor electrode on the substrate with a margin. Optionally, the second via extends through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

[0156] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: The first transistor in the first pixel driving circuit of the current stage; The sixth transistor in the second pixel driving circuit of the previous stage, wherein the first transistor and the sixth transistor are jointly controlled by the same reset control signal line; Multiple first reset signal lines; and A first initialization connection line connects a corresponding one of the plurality of first reset signal lines to the source of the first transistor, wherein the corresponding one of the plurality of first reset signal lines is configured to provide a reset signal to the source of the first transistor via the first initialization connection line. The first initialization connection line is located on the same side along the row direction of the active layer or gate of the first transistor and the sixth transistor.

2. The array substrate according to claim 1, wherein, The first initialization connection line is located on the side of the active layer or gate of the first transistor and the sixth transistor away from the drain of the driving transistor in the first pixel driving circuit. as well as The drain of the driving transistor is located on the side of the gate of the driving transistor away from the data line connected to the first pixel driving circuit along the row direction.

3. The array substrate according to claim 1 further includes multiple voltage supply lines; in, The orthographic projection of the corresponding third anode on the substrate substantially covers the orthographic projection of the first initialization connection line on the substrate, and covers at least a portion of the orthographic projection of the corresponding third voltage supply line on the substrate.

4. The array substrate according to claim 1 further includes multiple data lines and multiple first reset control signal lines; in, The first initialization connection line is in the same layer as the plurality of data lines; The first initialization connection line is connected to a corresponding one of the plurality of first reset signal lines through a via extending through the interlayer dielectric layer; The first initialization connection line is connected to the source of the first transistor through a via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer; as well as The first initialization connection line passes through a corresponding one of the plurality of first reset control signal lines.

5. The array substrate according to claim 1, wherein, The active layer and drain of the first transistor are part of the overall structure of a corresponding one of the multiple sub-pixels; At least a portion of the source of the first transistor passes through a corresponding one of the plurality of data lines; as well as The orthographic projection of the first initialization connection line on the substrate and the orthographic projection of at least a portion of the active layer and at least a portion of the drain of the first transistor on the substrate are separated by the orthographic projection of a corresponding one of the plurality of data lines on the substrate.

6. The array substrate according to claim 1, further comprising: Multiple second reset control signal lines and multiple second reset signal lines extending along the first direction respectively; The pixel driving circuit further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The sixth transistor includes a gate connected to a corresponding one of the plurality of second reset control signal lines, a source connected to a corresponding one of the plurality of second reset signal lines, and a drain connected to the drain of the fifth transistor and the anode of the light-emitting element; The array substrate includes a second initialization connection line, which connects a corresponding one of the plurality of second reset signal lines to the source of a sixth transistor in a corresponding one of the plurality of sub-pixels. The corresponding one of the plurality of second reset signal lines is configured to provide a reset signal to the source of the sixth transistor through the second initialization connection line. The second initialization connection line is connected to a corresponding one of the plurality of second reset signal lines via a via extending through the interlayer dielectric layer; The second initialization connection line is connected to the source of the sixth transistor via a via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer; and The second initialization connection line passes through a corresponding one of the plurality of second reset control signal lines.

7. The array substrate according to claim 6 further includes multiple data lines; in, The active layer and drain of the sixth transistor are part of the overall structure of a corresponding one of the multiple sub-pixels; The source of the sixth transistor passes through a corresponding one of the plurality of data lines; and The orthographic projection of the second initialization connection line on the substrate and the orthographic projection of the active layer and drain of the sixth transistor on the substrate are separated by the orthographic projection of a corresponding one of the multiple data lines on the substrate.

8. The array substrate according to claim 3, wherein, The pixel driving circuit includes a driving transistor; a first transistor; and a storage capacitor. The first transistor includes a gate connected to a corresponding one of a plurality of first reset control signal lines, a source connected to a corresponding one of the plurality of first reset signal lines, and a drain connected to the gate of the driving transistor and a first capacitor electrode of the storage capacitor; wherein the storage capacitor includes the first capacitor electrode, a second capacitor electrode electrically connected to a corresponding one of a plurality of voltage supply lines, and an insulating layer between the first capacitor electrode and the second capacitor electrode. The array substrate includes: A semiconductor material layer on a substrate; A node connection line, which is in the same layer as a corresponding one of the plurality of voltage supply lines, is connected to the first capacitor electrode through a first via and to the semiconductor material layer through a second via; and An anti-interference block is located in the same layer as the second capacitor electrode, and one of the multiple voltage supply lines is connected to the anti-interference block through a third through-hole.

9. The array substrate according to claim 8, wherein, At least a portion of the drain of the first transistor and a portion of the semiconductor material layer at the location connected to the node connection line are arranged in a direction substantially parallel to the second direction.

10. The array substrate according to claim 9 further includes multiple gate lines and multiple data lines; in, The pixel driving circuit further includes a second transistor and a third transistor; The second transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to a corresponding one of the plurality of data lines, and a drain connected to the source of the driving transistor; The third transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to the first capacitor electrode and the gate of the driving transistor, and a drain connected to the drain of the driving transistor. The portion of the semiconductor material layer at the location connected to the node connection line includes at least a portion of the source of the third transistor; The source of the third transistor and the drain of the first transistor are part of the overall structure of a corresponding one of the multiple sub-pixels. as well as A portion of the overall structure extends along a direction substantially parallel to the second direction.

11. The array substrate according to claim 8, wherein, The orthographic projection of the anti-interference block on the substrate substantially covers at least 80% of the orthographic projection of the drain of the first transistor on the substrate.

12. The array substrate according to claim 8 further includes multiple voltage supply lines; in, The anti-interference block includes a handle, a first arm, and a second arm; One of the multiple voltage supply lines is connected to the handle through the third through hole; The first arm includes an L-shaped portion and a first end portion; The second arm includes a base, a second end portion, and a connecting portion connecting the base and the second end portion; The base connects the L-shaped portion and the handle portion; as well as Along the first direction, a portion of the node connection line at the location where it is connected to the semiconductor material layer via the second via is spaced apart from the first adjacent data line via the first arm, and spaced apart from the second adjacent data line via the second arm.

13. The array substrate according to claim 12, wherein, The combination of the orthographic projection of the base of the second arm on the substrate and the orthographic projection of the shank on the substrate substantially covers at least 80% of the orthographic projection of the drain of the first transistor on the substrate.

14. The array substrate according to claim 12, further comprising a plurality of gate lines and a plurality of data lines; in, The pixel driving circuit further includes a second transistor and a third transistor; The second transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to a corresponding one of the plurality of data lines, and a drain connected to the source of the driving transistor; The third transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to the first capacitor electrode and the gate of the driving transistor, and a drain connected to the drain of the driving transistor. At least a portion of the drain of the first transistor and the portion of the semiconductor material layer at the location connected to the node connection line are arranged in a direction substantially parallel to the arrangement direction of the shank and the base; and / or At least a portion of the source of the third transistor and at least a portion of the drain of the first transistor are arranged in a direction substantially parallel to the arrangement direction of the shank and the base.

15. The array substrate according to claim 3, wherein, The corresponding third voltage supply line includes a main body portion and a loop portion connected to the main body portion; and The orthographic projection of the corresponding third anode on the substrate at least partially overlaps with the orthographic projection of the first initialization connection line on the substrate, and at least partially overlaps with the orthographic projection of the loop portion on the substrate.

16. The array substrate according to claim 15, further comprising a plurality of data lines; in, The orthographic projection of one of the multiple data lines on the corresponding third anode lies between the orthographic projection of the first initialization connection line on the corresponding third anode and the orthographic projection of the loop portion on the corresponding third anode.

17. The array substrate according to claim 15, wherein, The loop portion includes a first loop sub-portion that is substantially parallel to the second direction, a second loop sub-portion that is substantially parallel to the first direction, and a third loop sub-portion that is substantially parallel to the first direction. The second loop sub-section and the third loop sub-section respectively connect the first loop sub-section to the main body of the corresponding third voltage supply line; The array substrate further includes a loop hole extending through the corresponding third voltage supply line; and The periphery of the loop hole is surrounded by a combination of the first loop sub-part, the second loop sub-part, the third loop sub-part, and the main body part.

18. The array substrate according to claim 17, further comprising a plurality of data lines; in, The orthographic projection of the corresponding third anode on the substrate at least partially overlaps with the orthographic projection of the first loop sub-part on the substrate; as well as The orthographic projection of one of the multiple data lines on the corresponding third anode lies between the orthographic projection of the first initialization connection line on the corresponding third anode and the orthographic projection of the first loop sub-part on the corresponding third anode.

19. The array substrate according to claim 15, wherein, By positioning the first initialization connection line along the first edge of the corresponding third anode on the first side below the corresponding third anode, and positioning the loop portion along the second edge of the corresponding third anode on the second side below the corresponding third anode, the signal lines are distributed below the corresponding third anode; and The first side and the second side are opposite to each other.

20. The array substrate according to claim 15, wherein, The pixel driving circuit includes a driving transistor; a first transistor; and a storage capacitor. Wherein, the first initialization connection line is configured to provide the reset signal to the source of the first transistor; and The loop portion is configured to provide a high-voltage signal, which is transmitted to the second capacitor electrode of the storage capacitor in each third sub-pixel.

21. The array substrate according to claim 12, further comprising a plurality of voltage power supply lines; in, The source and active layer of the third transistor are part of the overall structure of the corresponding one of the multiple sub-pixels; The node connection line is connected to the source of the third transistor through the second through hole; as well as The orthographic projection of one of the plurality of voltage power supply lines on the substrate at least partially overlaps with the orthographic projection of the second arm on the substrate.

22. The array substrate according to claim 12 further includes multiple voltage power supply lines; in, One of the multiple voltage supply lines includes a first parallel portion, a second parallel portion, and a first inclined portion, wherein the first inclined portion connects the first parallel portion and the second parallel portion along the inclined direction; The first parallel portion and the second parallel portion extend in directions substantially parallel to the second direction; The first inclined portion extends along an angle of inclination relative to the first direction; The handle and the base are arranged in a direction substantially parallel to the second direction; as well as The connecting portion extends in a direction substantially parallel to the direction of inclination.

23. The array substrate according to claim 22, wherein, The orthographic projection of the first inclined portion on the substrate at least partially overlaps with the orthographic projection of the connecting portion on the substrate. The orthographic projection of the first parallel portion on the substrate at least partially overlaps with the orthographic projection of the handle portion on the substrate. as well as The orthographic projection of the second parallel portion on the substrate at least partially overlaps with the orthographic projection of the second end portion on the substrate. The corresponding third voltage supply line further includes a second inclined portion connected to the second parallel portion and a third parallel portion connected to the second inclined portion; The third parallel portion extends in a direction substantially parallel to the second direction; The second inclined portion extends along a second inclination angle relative to the first direction; The tilt angle is complementary to the second tilt angle; and The orthographic projection of the second inclined portion on the substrate does not overlap with the orthographic projection of the connecting portion on the substrate.

24. The array substrate according to claim 22 further includes multiple gate lines and multiple data lines; in, The pixel driving circuit further includes a second transistor and a third transistor; The second transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to a corresponding one of the plurality of data lines, and a drain connected to the source of the driving transistor; The third transistor includes a gate connected to a corresponding one of the plurality of gate lines, a source connected to the first capacitor electrode and the gate of the driving transistor, and a drain connected to the drain of the driving transistor. The drain of the first transistor and the source of the third transistor are part of an overall structure in a corresponding one of a plurality of sub-pixels, and at least a portion of the drain of the first transistor is directly connected to at least a portion of the source of the third transistor. The node connection line is connected to the source of the third transistor through the second through hole; as well as The orthographic projection of at least a portion of the drain of the first transistor onto the substrate at least partially overlaps with the orthographic projection of the shank onto the substrate, at least partially overlaps with the orthographic projection of the first parallel portion onto the substrate, and at least partially overlaps with the orthographic projection of the base onto the substrate.

25. The array substrate according to claim 1, further comprising: A gate insulating layer located on the side of the semiconductor material layer away from the substrate, and a first capacitor electrode located on the side of the gate insulating layer away from the substrate; as well as An interlayer dielectric layer is located on the side of the second capacitor electrode away from the insulating layer, and node connection lines and multiple voltage supply lines are located on the side of the interlayer dielectric layer away from the second capacitor electrode. The first via extends through the interlayer dielectric layer and the insulating layer in a region where the second capacitor electrode is not located. Except for the via region, the orthographic projection of the second capacitor electrode on the substrate completely covers the orthographic projection of the first capacitor electrode on the substrate with a margin. The second via extends through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

26. The array substrate according to claim 1, further comprising: Each first sub-pixel, each second sub-pixel, each third sub-pixel, and each fourth sub-pixel; The corresponding first voltage supply line in each of the first sub-pixels; The corresponding second voltage supply line in each of the second sub-pixels; The corresponding third voltage supply line in each of the third sub-pixels; The corresponding fourth voltage supply line in each of the fourth sub-pixels; The corresponding first voltage supply line, the corresponding second voltage supply line, the corresponding third voltage supply line, and the corresponding fourth voltage supply line are arranged sequentially and continuously along the row direction; The corresponding first voltage supply line, the corresponding second voltage supply line, and the corresponding fourth voltage supply line have substantially the same shape; The shape of the corresponding third voltage supply line is different from the shape of the corresponding first voltage supply line, the corresponding second voltage supply line, and the corresponding fourth voltage supply line; The multiple voltage supply lines include multiple repeating groups along the row direction; and One of the plurality of repeating groups includes the corresponding first voltage supply line, the corresponding second voltage supply line, the corresponding third voltage supply line, and the corresponding fourth voltage supply line.

27. A display device comprising an array substrate according to claim 1 and an integrated circuit connected to the array substrate.

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