Communication on the I2C bus

Abstract

Embodiments of the present disclosure relate to communications over an I2C bus. The present specification relates to attributing a first address to a first device by a second device over communications over an I2C bus, wherein the second device sends the first address over the I2C bus, and if the second device does not receive acknowledgement data, the first device records the first address.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Patent Application No. 2101921, filed on February 26, 2021, which is hereby incorporated by reference. Technical Field

[0003] The present disclosure generally relates to electronic devices, systems and methods. More specifically, the present disclosure relates to devices and methods for communicating over an I2C bus. Background Art

[0004] A computer bus is a device for transferring data between multiple electronic devices, such as between multiple components of the same electronic system. A bus typically includes one or more lines suitable for transferring different types of signals (e.g., address signals, data signals, clock signals, etc.). Each data bus is implemented by a communication protocol that defines the way logical data is exchanged between devices.

[0005] Among the different existing buses and communication protocols, I2C (Inter-Integrated Circuit) technology is a communication technology that is very widely used in industry today for communication between different devices. A bus suitable for I2C technology is a bidirectional serial bus using two transmission lines, more precisely, a data transmission line and a clock signal transmission line.

[0006] It would be desirable to be able to at least partially improve upon known communication techniques using a bus adapted for I2C communication. Summary of the invention

[0007] More reliable communication technology is needed.

[0008] A more reliable communication technique using a bus suitable for I2C communication is needed.

[0009] What is needed is an I2C bus communication technique that enables a master device to easily assign addresses to slave devices.

[0010] Embodiments overcome all or part of the disadvantages of known communication techniques using a bus adapted for I2C communications.

[0011] One embodiment provides a method of attributing a first address to a first device by a second device over communication via an I2C bus, wherein the second device sends the first address via the I2C bus, and if the second device does not receive confirmation data, the first device records the first address.

[0012] According to an embodiment, if the second device receives the confirmation data, the first device does not record the first address.

[0013] According to one embodiment, the first device records the first address in a non-volatile register.

[0014] According to one embodiment, the first address is not assigned to a device that can communicate with the second device.

[0015] According to one embodiment, the first device is in a home mode in which it expects to be assigned an address, and leaves the home mode when it records the first address.

[0016] According to an embodiment, the first device comprises a first state variable indicating whether it is in home mode.

[0017] According to one embodiment, the first device comprises a second state variable indicating whether it has recorded the address.

[0018] According to one embodiment, the first address includes a device type identifier and a device number.

[0019] According to an embodiment, the first device is a slave device communicating over an I2C bus.

[0020] According to one embodiment, the first device is a memory.

[0021] According to one embodiment, the first device is a non-volatile memory of the EEPROM type.

[0022] According to an embodiment, the second device is a host device of the I2C bus communication.

[0023] According to one embodiment, the second device is a processor.

[0024] An embodiment provides a method of configuring a third device including the described homing method.

[0025] An embodiment provides a device suitable for implementing the described attribution method.

[0026] More reliable communication technology is needed.

[0027] A more reliable communication technique using a bus suitable for I2C communication is needed.

[0028] What is needed is an I2C bus communication technique that enables a master device to easily assign addresses to slave devices.

[0029] Embodiments overcome all or part of the disadvantages of known communication techniques using a bus adapted for I2C communications.

[0030] One embodiment provides a method of attributing a first address to a first device by a second device over communication via an I2C bus, wherein the second device sends the first address via the I2C bus, and if the second device does not receive confirmation data, the first device records the first address.

[0031] According to an embodiment, if the second device receives the confirmation data, the first device does not record the first address.

[0032] According to one embodiment, the first device records the first address in a non-volatile register.

[0033] According to one embodiment, the first address is not assigned to a device that can communicate with the second device.

[0034] According to one embodiment, the first device is in a home mode in which it expects to be assigned an address, and leaves the home mode when it records the first address.

[0035] According to an embodiment, the first device comprises a first state variable indicating whether it is in home mode.

[0036] According to one embodiment, the first device comprises a second state variable indicating whether it has recorded the address.

[0037] According to one embodiment, the first address includes a device type identifier and a device number.

[0038] According to an embodiment, the first device is a slave device communicating over an I2C bus.

[0039] According to one embodiment, the first device is a memory.

[0040] According to one embodiment, the first device is a non-volatile memory of the EEPROM type.

[0041] According to an embodiment, the second device is a host device of the I2C bus communication.

[0042] According to one embodiment, the second device is a processor.

[0043] An embodiment provides a method of configuring a third device including the described homing method.

[0044] An embodiment provides a device suitable for implementing the described attribution method. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The foregoing and other features and advantages will be described in detail in the following detailed description by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0046] Figure 1The communication on the I2C bus is schematically shown in block form;

[0047] Figure 2 The addresses of the electronic devices are schematically shown in the form of blocks;

[0048] Figure 3 Two views (a) and (b) are schematically shown, illustrating a variation of the electronic device;

[0049] Figure 4 The implementation of communication on the I2C bus is schematically shown in the form of modules;

[0050] Figure 5 The implementation mode of the method of assigning addresses to devices via I2C bus communication is schematically shown in block form;

[0051] Figure 6 Another I2C bus communication is schematically shown in module form; and

[0052] Figure 7 The implementation mode of the method for configuring a device is schematically shown in the form of blocks. DETAILED DESCRIPTION

[0053] In the various drawings, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, size and material properties.

[0054] For the sake of clarity, only the steps and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, all the different control signals that can be sent by a master device to a slave device are not described in exhaustive detail.

[0055] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being connected together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0056] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or when referring to relative position qualifiers, such as the terms "upper", "lower", "upper", "lower", etc., or when referring to orientation qualifiers, such as "horizontal", "vertical", etc., it refers to the orientation shown in the figure.

[0057] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "on the order of" mean within 10%, preferably within 5%.

[0058] The signals referred to in the present disclosure are analog signals including a high state and a low state corresponding to logic data "1" (one) and "0" (zero), respectively. Unless otherwise mentioned, the high state represents a high voltage level, such as equal to the power supply voltage. Unless otherwise mentioned, the low state represents a low voltage level, such as equal to a reference voltage, such as ground.

[0059] Figure 1 Communication on an I2C (Inter-Integrated Circuit) bus is shown schematically in block form.

[0060] Figure 1 An I2C bus 101 formed by two transmission lines SCL and SDA is shown. The transmission line SCL is suitable for transmitting a clock signal that can control the rate of data transmission on the bus. The clock signal is an analog signal that periodically changes between a high level and a low level. The transmission line SDA is suitable for transmitting an analog signal representing data and control signals that changes between a high level and a low level.

[0061] The transmission lines SCL and SDA are actually conductors with voltage levels controlled by the electronic devices using the bus 101. In an idle state, i.e., when the lines SCL and SDA are not transmitting signals, the lines SCL and SDA are, for example, Figure 1 A pull-up resistor, not shown, maintains the voltage level at a high level.

[0062] Figure 1 Also shown are electronic devices that communicate together using bus 101 . Figure 1 More precisely, a master electronic device 102 (host) or host device 102 of I2C bus communication and two slave electronic devices 103 (slave 1) and 104 (slave 2) or slave devices 103 and 104 of I2C bus communication are shown.

[0063] In communication on the I2C bus, a host device such as host device 102 is a device that has initiated the I2C bus communication, which gives it tasks dedicated to its host device status. Among these different tasks, the host device is particularly suitable for:

[0064] - the clock frequency of the clock signal transmitted via the line SCL of the I2C bus;

[0065] - By imposing Figure 4 The start condition and stop condition are used to start and stop I2C bus communication; and

[0066] - Send and / or receive control signals and / or data by using the SDA line.

[0067] Slave devices 103 and 104 are electronic devices that do not initiate I2C bus communications. Slave devices 103 and 104 are adapted to send and / or receive control signals and / or data by communicating with host device 102 using the SDA line. Each slave device 103, 104 responds to an address, which will be combined with Figure 2 Give a description.

[0068] According to one example, the host device 102 may be a processor or microprocessor of an electronic system, and the slave devices 103 and 104 may be other components of the electronic system, such as a memory, a data acquisition device, a communication device, etc. Figure 3 An example of a slave device is described.

[0069] Figure 1 An I2C bus communication is shown, including a host device 102 and multiple (here two) slave devices 103 and 104. Obviously, the I2C communication can be suitable for the communication between the host device and a single slave device, or more than two slave devices, or further suitable for the communication between multiple host devices or one or more slave devices. The embodiments described below are applicable to the I2C bus communication between the host device and one or more slave devices.

[0070] Figure 2 The block diagram schematically shows the Figure 1 The types of slave devices 103 and 104 are described by the addresses of the slave devices.

[0071] To initiate I2C bus communication with a slave device, the master device sends the address of the slave device it wishes to initiate communication with via the data transmission line of the I2C bus. There are multiple slave device address formats. The address formats that can be used are as follows.

[0072] The slave device address Add consists of 7 bits B0 to B6. The address is divided into two parts, each part represents specific information.

[0073] The four most significant bits B0 to B3 represent a device type identifier DTI that enables the nature of the slave device to be identified. In practice, each type of electronic device that may use the I2C bus for communication is represented by an identifier encoded on four bits. According to one example, an EEPROM type (electrically erasable programmable read-only memory) non-volatile memory is represented by the identifier "1010".

[0074] The three least significant bits B4 to B6 represent the device's number CI (CI, chip identifier). The number CI enables multiple electronic devices of the same nature used in the same electronic system to be distinguished. According to one example, if the slave device is the only one of its type, its number CI is "000".

[0075] According to one example, if the electronic system includes an EEPROM type non-volatile memory, the addresses of the two memories may be: “1010000” and “1010001”.

[0076] In addition, a slave device may use multiple addresses to implement I2C bus communications. According to one example, a first address or primary address may be used to send a first type of control signal, while a second address or secondary address may be used for a second type of control signal. For example, the primary address may be, for example, in accordance with the Figure 2 The primary address may follow the formation rules of the address Add described in the foregoing, and the secondary address may also follow these rules, or may follow other formation rules. According to a more precise example, if the device is a memory, the primary address may allow receiving read and write control signals, and the secondary address may enable receiving memory configuration control signals.

[0077] Figure 3 The two views (a) and (b) schematically illustrate an electronic device capable of acting as a slave device in I2C bus communication.

[0078] View (a) is a simplified top view of an EEPROM type nonvolatile memory 200. The memory 200 is protected by a rectangular package 201 which, in top view, has eight connection terminals 202 which protrude from the rectangular package 201 in view (a) and have reference numerals 1 to 8. The connection terminals 202 are arranged in groups of four on parallel sides of the package 201.

[0079] The non-volatile memory 200 is suitable for I2C bus communication, and this is an example using eight connection terminals 202. Reference connection terminal 4 receives a low-level reference signal VSS, for example ground. Reference connection terminal 8 receives a high-level reference signal VCC, for example a power supply voltage. Terminals 1 to 3 transmit three bits of the number CI of the memory 200. To this end, each terminal 1 to 3 is coupled to terminal 4 (VSS) if the terminal indicates "0" (zero), or to terminal 8 (VCC) if the terminal indicates "1" (one). Terminal 5 is coupled to, preferably connected to, the transmission line SDA of the I2C bus. Terminal 6 is coupled to, preferably connected to, the transmission line SCL of the I2C bus. Terminal 7 can, for example, receive a signal WC- (write control), which enables configuration of protection or non-protection of data stored in the memory 200.

[0080] View (b) is a simplified top view of another EEPROM type non-volatile memory 250. The memory 250 is protected by a package 251 which is rectangular, or even square, in a top view, with four connection terminals 252 protruding from the package 251, indicated by reference numerals 1 to 4. The connection terminals are arranged at the four corners of the package 251.

[0081] The non-volatile memory 250 is suitable for I2C bus communication, and this is an example using four connection terminals 252. Terminal 1 is coupled to, preferably connected to, the transmission line SDA of the I2C bus. Reference connection terminal 2 receives a low-level reference signal VSS, such as ground. Terminal 3 is coupled to, preferably connected to, the transmission line SCL of the I2C bus. Reference connection terminal 4 receives a high-level reference signal VCC, such as a power supply voltage.

[0082] In the case of the memory 200, part of the address of the memory available for I2C bus communication can be directly accessed on the connection terminal 202 of the package of the memory 200, and the other part is stored in a specific register of the memory 200. More specifically, Figure 2 The bits B4, B5, B6 of the address of the circuit described in are defined by the voltage levels of the terminals E2, E1, E0. In the case of the memory 250, the memory address is stored in a specific register of the memory 250.

[0083] Figure 4 Is to show about Figure 1 The type of device 102 described is a host device M with respect to Figure 1 103 and 104. Devices M and S communicate via the I2C bus. Figure 1 The depicted bus 101 is of an I2C bus type, the I2C bus comprising a data transmission line SDA and a clock signal transmission line SCL.

[0084] Before the I2C communication between devices M and S begins, the signals sent by lines SCL and SDA are not used and are held at a high level.

[0085] According to an example, combined Figure 4 The I2C communication described is based on a control signal comprising eight data bits. In addition, the address format used by the slave device S is combined with Figure 2 As described.

[0086] In an initial step 301 (START), an I2C communication between devices M and S begins. To this end, the master device M transmits a start condition. The I2C communication start condition is defined, for example, by a falling edge of a signal transmitted on line SDA, while the signal on line SCL is at a high level.

[0087] The start condition applied by the master device M has the function of notifying the slave device S to start I2C communication. This interrupt results in notifying the slave device S that I2C bus communication has started. In other words, the interrupt results in "waking up" or "alerting" the slave device S.

[0088] Once the start condition has been passed, the master device M sends a clock signal via the line SCL. Thus, after the start condition, the signal on the line SCL has a first falling edge and switches to a low level.

[0089] In step 302 (Slave Address), the master device M sends a first control signal. The first control signal includes the address of the slave device with which it wishes to communicate, in this case the address of the slave device S. To read the control signal, the slave device S reads the data of the signal SDA at each rising edge of the signal SCL.

[0090] As an example, the first control signal includes seven bits of the address of the slave device S and a bit indicating the nature of the next control signal. The last bit can, for example, indicate the communication direction of the next control signal or response. According to an example, if the last bit represents "0" (zero), communication occurs in the direction from the host device to the slave device, and if the last bit represents "1" (one), communication occurs in the direction from the slave device to the host device. In other words, if the last bit represents "0", the host device is in the transmission position and the slave device is in the receiving position, and if the last bit represents "1" (one), the host device is in the receiving position and the slave device is in the transmission position.

[0091] In step 303 (confirmation?), if the address sent by the host device M at step 302 corresponds to the address or one of the addresses of the slave device S, the device S sends confirmation data to the host device M (output Y). The next step is step 304 (CMD). If the host device M does not receive the confirmation data (output N), the communication stops and the next step is step 305 (stop). The host device M can receive a confirmation from another slave device ( Figure 4 The acknowledgement data is received by the device S (not shown in the case), in which case the communication starts with the other slave device and the slave device S does not follow the communication. The acknowledgement data sent by the device S is, for example, the setting of the low state of the signal SDA.

[0092] In step 304, devices M and S are ready to communicate. The host device M and the slave device S exchange control signals and / or data. Once the control signal and / or data exchange is completed, the next step is step 305. It should be noted that on the I2C bus communication based on 8-bit control signals, the device with the receiving position sends confirmation data to the device with the transmitting position after receiving each group of 8 data bits. If the device with the receiving position does not send confirmation data at the expected time, the device with the transmitting position believes that the device with the receiving position is no longer warned to communicate with it. The host device M stops communicating in the manner described in conjunction with step 305.

[0093] In step 305, the host device M that has not received the confirmation data sends a stop condition that enables communication to be stopped. For example, when the SCL signal is at a high level, the I2C communication stop condition is defined by the rising edge of the SDA signal. The I2C communication between the devices M and S then ends.

[0094] Figure 5 The implementation mode of the method of attributing the address Add1 to the slave device S1 (slave) implemented by the master device M1 (master) on the I2C bus communication is schematically shown in the form of a block.

[0095] The master device M1 and the slave device S1 are connected by Figure 1 Description of the I2C bus 101 type of I2C bus ( Figure 5 ) coupling, the I2C bus 101 includes Figure 1 Describes the transmission line SDA type data line and about Figure 1 The master device M1 can be coupled to the I2C bus via the SCL type clock line. Figure 5 Other slave devices not shown.

[0096] The address Add1 is an idle address not used by a slave device, with which the master device M1 can communicate on the I2C bus. The address Add1 is intended to be assigned to the slave device S1. According to an example, the address Add1 is a 7-bit binary word.

[0097] At step 401 (Home Mode), the slave device S1 has entered an operating mode in which it expects to be assigned an address, referred to as Home Mode. According to an example, the slave device S1 may include a data bit, such as a state variable, indicating that it is in Home Mode.

[0098] According to one example, the slave device S1 may be in this mode directly at the end of its manufacture. According to another example, the master device M1 may have previously sent a control signal to the slave device S1 , asking it to enter the home mode.

[0099] In step 402 (start), similar to combining Figure 5 In step 301 of the description, the host device M1 transmits a start condition to start I2C bus communication.

[0100] In step 403 (idle slave address), following step 402, the master device M1 sends a first control signal via a data line of the bus I2C. The first control signal includes an address Add1 that is not assigned to a slave device with which the master device M1 can communicate via I2C. According to an example, if the first control signal is an eight-bit binary word and the address Add1 is a seven-bit binary word, the last bit of the control signal indicates the nature of the next control signal. According to one embodiment, the last bit represents a default value, such as "0" (zero).

[0101] In step 404 (not confirmed) after step 403, the host device M1 does not receive the confirmation data. Since the address Add1 is not assigned to a device that may communicate with the host device M1 at this time, it is normal that the host device M1 does not receive the confirmation data.

[0102] In step 405 (store address), the slave device S1 follows the control signal exchange occurring on the data line of the I2C bus, and the slave device S1 understands that the address Add1 sent by the master device M1 is a free address. In fact, if the address Add1 is not free, the slave device responding to the address Add1 will send confirmation data in step 404. The slave device S1 then stores the address Add1 in, for example, a volatile register. The slave device S1 can regard the address Add1 as one of its addresses, for example, as a secondary address, and respond to the master device M1 when the master device M1 will start future communication by requesting the device associated with the address Add1. In combination Figure 6 and Figure 7 An example of the steps implemented by the slave device S1 for recording the address Add1 is described.

[0103] The slave device S1 can use the address Add1 in different ways. According to one embodiment, the slave device S1 can modify its primary address to the address Add1. According to another example of the embodiment, the slave device S1 can record the address Add1 as a secondary address, or use the address Add1 to modify one of its secondary addresses. According to another example of the embodiment, the slave device S1 can use the address Add1 as a temporary secondary address, that is, use the address Add1 as a secondary address, but for a limited number of I2C bus communications. By using the address Add1 as a temporary secondary address or a dynamic secondary address, the slave device S1 can, for example, modify one of its secondary addresses to another address other than the address Add1. It will be within the capabilities of those skilled in the art to find other uses for the address Add1.

[0104] In step 406 (Stop), the host device M1 that has not received the confirmation data ends the communication by sending a stop condition on the data line SDA. Figure 4 Step 305 of the description.

[0105] Figure 6 and Figure 7 Shows about Figure 5 A practical example of the steps implemented by the slave device in the implementation of the described home method. More specifically, Figure 6 The I2C bus communication between a master device M2 (master) and a slave device S2 (slave) is schematically shown in block form. Figure 7 is a block diagram illustrating in more detail the steps implemented by slave device S2.

[0106] exist Figure 6 In the embodiment, the host device M2 and the slave device S2 are coupled via the I2C bus 451, which is a combination of Figure 1 The type of I2C bus 101 described includes a data line SDA2 and a clock line SCL2, the data line SDA2 is combined Figure 1 Describes the type of transmission line SDA, clock line SCL2 is combined Figure 1 Describes the type of transmission line SCL.

[0107] The host device M2 is combined with Figure 5 According to one example, the host device M2 is a processor or microprocessor of an electronic system. The host device M2 is suitable for implementing a combination of Figure 5 Describes the address attribution method.

[0108] Slave device S2 is combined Figure 5According to an example, the slave device S2 is a memory of the electronic system, such as a volatile memory or a non-volatile memory. The slave device S2 is suitable for implementing a combination of Figure 5 Describes the address attribution method.

[0109] In addition, the slave device S2 responds to multiple addresses 452 (addresses). According to an example, the slave device S2 responds to the primary address AddP, and further responds to the secondary address AddS. The host device M2 uses the primary address AddP to send conventional control signals to the slave device S2. According to an example, if the slave device S2 is a memory, the host device M2 uses the primary address AddP to send a read control signal and a write control signal to the slave device S2. The secondary address AddS is used by the host device M2 to send a more specific control signal to the slave device S2, such as a configuration control signal. According to one embodiment, the addresses AddS and AddP are stored in a non-volatile register of the slave device S2.

[0110] According to one embodiment, the slave device S2 is a device having one or more configurable addresses. As an example, the secondary address AddS of the slave device S2 can be configured at the end of manufacturing of the device S2. The address AddS is set to a default value, for example, at the end of manufacturing of the slave device S2. A configuration step is necessary at the beginning of use of the slave device S2 to define its secondary address AddS. This configuration step becomes increasingly important as the secondary address AddS can be used to send configuration control signals to the slave device S2. In fact, if the secondary address AddS is defined by a default value at the time of manufacturing, there is no guarantee that the host device M2 can initiate I2C bus communication before another slave device using this address has used it. This configuration step can be performed by the host device M2 by using information about Figure 5 This is achieved using the address attribution method described in .

[0111] According to one embodiment, the addresses AddP and AddS are related to Figure 2 The type of address Add described. Therefore, the addresses AddP and AddS are formed by the identifiers DTIP and DTIS of the device type and the device numbers CIP and CIS, respectively. According to an example, the addresses AddP and AddS are 7-bit binary words, the identifiers DTIP and DTIS are 4-bit binary words, and the numbers CIP and CIS are 3-bit binary words.

[0112] For the practical examples described herein, it is considered that the slave device distinguishes the primary address from its secondary address as they have different identifiers, but have the same number. In other words, according to one embodiment, the addresses AddP and AddS have different DTIP and DTIS identifiers, and the same numbers CIP and CIS. It is within the capabilities of a person skilled in the art to design a set of steps implemented by the slave device S2, wherein the slave device S2 distinguishes its primary address from its secondary address because they have different numbers. It is also within the capabilities of a person skilled in the art to design a set of steps implemented by the slave device S2, wherein the slave device does not consider the composition of its primary address and secondary address to distinguish them.

[0113] The slave device S2 also includes registers 453 (registers) which may be adapted to store data during implementation of I2C bus communications. More specifically, the slave device S2 includes volatile storage registers RV, or volatile registers RV, and non-volatile storage registers RNV, or non-volatile registers RNV.

[0114] The slave device S2 also includes a state variable 454 (state) used during the implementation of the I2C bus communication. More specifically, the slave device S2 includes:

[0115] - a status variable PERSO indicating whether the configuration of the slave device S2 has taken place;

[0116] - a state variable FSAI indicating whether the slave device S2 stores a temporary address; and

[0117] - Status variable FSAD, indicating whether the slave device is in home mode.

[0118] According to one embodiment, when configuration has not yet occurred, the state variable PERSO indicates "0" (zero). When the slave device S2 does not store an address, the state variable FSA1 indicates "0" (zero). The value of the state variable FSAD depends on the values ​​of the state variables PERSO and FSAI. When both the state variables PERSO and FSAI indicate "0" (zero), the state variable FSAD indicates "1" (one) indicating that the belonging mode is activated. Once one of the two variables PERSO or FSAI indicates "1" (one), the belonging mode is deactivated and the state variable FSAD indicates "0" (zero). In other words, the state variable FSAD corresponds to the inverse of the result of applying the logical OR function to the variables PERSO and FSAI.

[0119] Figure 7A practical example of a set of steps implemented by a slave device S2 during a method of implementing a home address AddT by a master device M2 is shown. As mentioned above, the set of steps described below is a practical example of steps, but other sets of steps implemented by a slave device S2 will be provided. Figure 6 Describe the slave device S2 and the master device M2.

[0120] The address AddT is the type of the addresses AddP and AddS of the slave device S2, that is, Figure 2 Describes the type of address Add. Therefore, the address AddT is decomposed into a device type identifier DTIT and a device number CIT. According to an example, the address AddT is a 7-bit binary word, the identifier DTIT is a 4-bit binary word, and the number CIT is a 3-bit binary word.

[0121] More specifically, address AddT is of the type of secondary address AddS of slave device S2 and has the same identifier as secondary address AddS. Thus, according to one embodiment, the identifier DTIT of address AddT is identical to the identifier DTIS of secondary address AddS and is different from the identifier DTIP of primary address AddP.

[0122] At step 501 (START), the slave device S2 is informed of the start of communication by receiving a start condition executed by the master device M2 on the data line SDA2 of the bus I2C. The slave device S2 is thus arranged to receive and read the data sent via the data line SDA2.

[0123] In step 502 (VERIF), slave device S2 verifies its state following step 501. More specifically, slave device S2 verifies its state variable PERSO indicating whether its configuration has been executed, and its state variable FSAI indicating whether slave device S2 stores a temporary address.

[0124] Furthermore, in step 502, following step 501, the slave device S2 may read the default value of its secondary address AddS stored in the non-volatile register. According to a variant, the value of its secondary address may correspond to the value just configured.

[0125] In step 503 (AddT), the master device M2 sends a control signal including the address AddT via the data line SDA2. The slave device S2 reads the address AddT and decomposes it into its identifier DTIT and its number CIT.

[0126] In step 505 (DTIT=DTIP), following step 503, the slave device S2 verifies the value of the identifier DTIT. More specifically, the slave device compares the identifier DTIT with the identifier DTIP of its master address AddP. If the identifiers DTIT and DTIP are equal (output "yes"), the next step is step 506 (standard command). Otherwise (output "no"), the next step is step 507 (other commands).

[0127] In step 506, the slave device S2 expects to receive a normal control signal because the received identifier DTIT is identical to the identifier DTIP of its master address AddP.

[0128] In step 508 (REF=CIS=CIP), after step 506, the slave device S2 defines the number CIP of its master address AddP as the reference number REF.

[0129] In step 509 (CIT=REF), following step 508, the slave device S2 verifies whether the number CIT of the received address AddT is equal to the reference number REF. If they are equal (output "yes"), the next step is step 510 (receive command). Otherwise (output "no"), the next step is step 511 (exit).

[0130] In step 510, consecutive to address 509, the slave device S2 has determined that the received address AddT is identical to its master address AddP, since the identifier DTIT and the number CIT are equal to the identifier DTIP and the number CIP of the master address AddP. Therefore, the slave device S2 reads the last bit of the control signal sent by the master device M2, which indicates whether the slave device is to send or receive in the remainder of the communication.

[0131] At step 512 (confirmation command), following step 510, slave device S2 sends confirmation data via data line SDA2 and executes the command received from master device M2. Communication between devices M2 and S2 can continue like conventional I2C bus communication, i.e., for example, like combined Figure 4 Step 512 further includes receiving and executing the command by the slave device S2.

[0132] In step 511, following step 509, the slave device determines that the received address AddT is different from its master address AddP. The I2C bus communication initiated by the master device M2 has nothing to do with the slave device S2. Therefore, the slave device S2 does not send confirmation data and stops monitoring the data line SDA2.

[0133] In step 507, consecutively to step 505, the slave device has determined that the identifier DTIT is different from the identifier DTIP of its master address AddP. The slave device may therefore expect to receive specific control signals.

[0134] In step 513 (DTIT=DTIS), following step 507, the slave device S2 verifies whether the identifier DTIT of the received address AddT is identical to the identifier DTIS of its secondary address AddT. If the identifiers DTIT and DTIS are different (output "No"), the next step is step 514 (Exit). Otherwise (output "Yes"), the next step is step 515 (FSAD).

[0135] In step 514, following step 513, the slave device S2 has determined that the identifier DTIT of the received address AddT is different from the identifier DTIS of its secondary address AddS. Step 514 is the same as step 511. In other words, the slave device S2 does not send confirmation data and stops monitoring the data line SDA2.

[0136] In step 515, following step 513, slave device S2 queries its state variable FSAD to know which mode it is in. If the state variable FSAD indicates that slave device S2 is not in home mode, for example by representing "0" (zero) (output 0), the next step is step 516 (PERSO). If the state variable FSAD indicates that slave device S2 is in home mode, for example by representing "1" (one) (output 1), the next step is step 517 (receive command).

[0137] In step 516, following step 515, the slave device S2 queries its state variable PERSO to know whether configuration has occurred. If the state variable PERSO indicates that configuration has occurred, for example by representing "1" (one) (output 1), the next step is step 508 (REF = CIS = CIP). If the state variable PERSO indicates that configuration has not occurred, for example by representing "0" (zero), (output 0), the next step is step 519 (REF = CIV).

[0138] In step 519, following step 516, the slave device S2 defines the number CIV stored in the volatile register RV of the slave device S2, such as the reference number REF. The next step is step 509. The number CIV is described in further detail below.

[0139] In step 517, following step 515, the slave device S2 has determined that it is in home mode. The slave device S2 receives the control signal following the address AddT in the control signal sent by the master device M2.

[0140] In step 520 (not confirmed), following step 517, the slave device S2 does not send confirmation data to the master device M2. In fact, the address AddT is not assigned to it, so it does not have to send confirmation data.

[0141] In step 521 (bus acknowledgement), following step 520, the slave device S2 keeps noticing whether acknowledgement data appears on the data line SDA2 after the control signal including the address AddT. If acknowledgement data is received (output "yes"), the next step is step 522 (AddT not idle). If acknowledgement data is not received (output "no"), the next step is step 523 (AddT idle FSAI=1).

[0142] In step 522, after step 521, the slave device has responded to the address AddT, so the address AddT is not idle.

[0143] In step 525 (exit), after step 522, the slave device S2 has determined that the received address AddT is the address of another slave device with which the master device M2 can communicate. Step 525 is the same as steps 511 and 514. In other words, the slave device S2 does not send confirmation data and stops monitoring the data line SDA2.

[0144] In step 523, continuous with step 521, no slave device responds to address AddT, so slave device S2 can store address AddT in volatile register RV and use address AddT as temporary address, for example. More specifically, slave device S2 stores number CIT in its volatile register RV. Number CIV is equal to number CIT here. More generally, volatile register RV can store number CIV of idle temporary address. Therefore, if in step 509 after step 519, number CIT is equal to reference, that is, equal to number CIV, then the slave device responds to idle temporary address. The next step is step 524.

[0145] Furthermore, in step 523, the slave device S2 indicates that it has received the free address AddT by modifying its state variable FSAI. According to one example, the state variable represents the value "1" (one).

[0146] At step 524 (Stop), following step 523, slave device S2 stops participating in the communication, for example, by stopping responding and sending confirmation data.

[0147] The advantage of the implementation mode of the home method described here is that it does not require hardware changes in the host device. It is compatible with the conventional I2C bus communication method.

[0148] Furthermore, another advantage of the implementation is that it enables free addresses to be assigned to slave devices without having to know the free addresses in advance. More specifically, the implementation enables free addresses to be assigned to slave devices that have secondary addresses that may conflict with the addresses of another slave device, and this is after the slave device is installed in a system that includes a master device.

[0149] Another advantage of the implementation mode of the home method is that it can modify the secondary address of the slave device. This is advantageous because the secondary address of the slave device can be, for example, the slave device configuration address.

[0150] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0151] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A method for attributing a first address to a first device by a second device in communication on an inter-integrated circuit I2C bus, the method comprising: receiving, by the first device, the first address from the second device over the I2C bus; After receiving the first address, monitoring, by the first device, confirmation data for the first address on the I2C bus; as well as In response to the second device not receiving confirmation data for the first address, recording the first address by the first device.

2. The method according to claim 1, further comprising: receiving, by the first device, a second address from the second device over the I2C bus; as well as In response to the second device receiving second confirmation data for the second address, the second address is not recorded by the first device.

3. The method according to claim 1, further comprising: The first address is recorded in a non-volatile register by the first device. The method of claim 1 , wherein the first address is not assigned to a device with which the second device can communicate.

5. The method of claim 1, wherein the first device is in a home mode in which the first device expects to be assigned an address, and the first device leaves the home mode in response to recording the first address. The method of claim 5 , wherein the first device comprises a first state variable indicating whether the first device is in the home mode.

7. The method of claim 1, wherein the first device includes a second state variable indicating whether the first device has recorded any addresses. The method of claim 1 , wherein the first address comprises a device type identifier and a device number.

9. The method of claim 1, wherein the first device is a slave device of the I2C bus communication.

10. The method of claim 1, wherein the first device is a memory.

11. The method of claim 10, wherein the first device is a non-volatile electrically erasable programmable read-only memory (EEPROM).

12. The method of claim 1, wherein the second device is a host device of the I2C bus communication.

13. The method of claim 1, wherein the second device is a processor.

14. The method according to claim 1, further comprising: receiving, by a third device, a second address from the second device over the I2C bus; as well as In response to the second device not receiving second confirmation data for the second address, recording the second address by the third device.

15. A slave device, comprising: Non-volatile memory; as well as The I2C bus communication interface between integrated circuits is configured as follows: receiving a first address from a host device over the I2C bus; After receiving the first address, monitoring confirmation data for the first address on the I2C bus; as well as In response to the host device not receiving confirmation data for the first address, the first address is recorded.

16. The slave device according to claim 15, wherein the I2C bus communication interface is further configured as: receiving a second address from the host device over the I2C bus; and In response to the host device receiving second confirmation data for the second address, the second address is not recorded. 17 . The slave device according to claim 15 , wherein the I2C bus communication interface is further configured to record the first address in a non-volatile register.

18. The slave device of claim 15, wherein the first address is not assigned to a device with which the master device can communicate.

19. The slave device according to claim 15, wherein the slave device is configured as: being in a home mode in which the slave device expects to be assigned an address; and The home mode is left in response to recording the first address.

20. The slave device of claim 19, wherein the slave device comprises a first state variable indicating whether the slave device is in the home mode.

21. The slave device of claim 20, wherein the slave device comprises a second state variable indicating whether the slave device has recorded any addresses.

22. The slave device of claim 15, wherein the first address comprises a device type identifier and a device number.

23. The slave device according to claim 15, wherein the non-volatile memory is of the Electrically Erasable Programmable Read Only Memory (EEPROM) type.

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