Drive signal generation circuit, power-off control method, and display device

Abstract

The application provides a driving signal generation circuit, a power-off control method and a display device. The driving signal generation circuit is used for providing a driving signal for a display panel, and comprises a driving signal output end and a power-off control circuit. The power-off control circuit is electrically connected with a power-off control end, a first voltage end and the driving signal output end respectively, and is used for controlling the communication between the first voltage end and the driving signal output end under the control of a power-off control signal provided by the power-off control end in a power-off stage, so that the driving signal output end outputs an effective driving signal. The application can release the residual charge in the pixels in the power-off stage, and avoids display residual image.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving signal generation circuit, a power-off control method and a display device. BACKGROUND

[0002] In the related art, in the power-off stage of the display panel, the circuit unit for turning on the thin film transistor in the pixel is shared with the noise reduction unit in the normal display of the display panel. Since the duty cycle of the control signal accessed by the control electrode of the transistor in the noise reduction unit is large in the normal display, the aging speed of the transistor is fast with reliability test. After the high-temperature reliability test, the residual image problem caused by insufficient pixel discharge is prone to occur. SUMMARY

[0003] The main purpose of the present application is to provide a driving signal generation circuit, a power-off control method and a display device, which solves the residual image problem caused by insufficient pixel discharge in the power-off stage of the existing display panel.

[0004] In one aspect, the embodiment of the present application provides a driving signal generation circuit for providing a driving signal for a display panel, the driving signal generation circuit comprising a driving signal output end and a power-off control circuit;

[0005] The power-off control circuit is electrically connected with a power-off control end, a first voltage end and the driving signal output end respectively, and is used for controlling the communication between the first voltage end and the driving signal output end under the control of the power-off control signal provided by the power-off control end in the power-off stage, so as to make the driving signal output end output effective driving signal.

[0006] Optionally, the duty cycle of the power-off control signal is less than a duty cycle threshold.

[0007] Optionally, the power-off control circuit comprises a power-off control transistor.

[0008] The control electrode of the power-off control transistor is electrically connected with the power-off control end, the first electrode of the power-off control transistor is electrically connected with the driving signal output end, and the second electrode of the power-off control transistor is electrically connected with the first voltage end.

[0009] Optionally, the driving signal generation circuit comprises a frame reset end, and the power-off control end is the frame reset end.

[0010] Optionally, the power-off control end is the first voltage end; the first voltage end is used for providing an effective voltage signal in the power-off stage and an ineffective voltage signal in a normal working stage.

[0011] The normal working stage is a time period included in the working time of the display panel except the power-off stage.

[0012] Optionally, the power-off control circuit is configured to provide a power-off control signal to control the connection between the first voltage terminal and the driving signal output terminal in the power-off stage, and provide a first control signal to control the disconnection between the first voltage terminal and the driving signal output terminal in the normal working stage.

[0013] The normal working stage is a time period other than the power-off stage in the working time of the display panel.

[0014] Optionally, the driving signal generation circuit further comprises a pull-up node control circuit, a pull-down node control circuit and a driving output circuit.

[0015] The pull-up node control circuit is configured to control the potential of the pull-up node.

[0016] The pull-down node control circuit is configured to control the potential of the pull-down node.

[0017] The driving output circuit is electrically connected with the pull-up node, the pull-down node, the driving signal output terminal, the output clock signal terminal and the second voltage terminal respectively, and is configured to control the connection between the driving signal output terminal and the output clock signal terminal under the control of the potential of the pull-up node, and control the connection between the driving signal output terminal and the second voltage terminal under the control of the potential of the pull-down node.

[0018] The second voltage terminal is configured to provide an invalid voltage signal in the normal working stage and provide a valid voltage signal in the power-off stage; the normal working stage is a time period other than the power-off stage in the working time of the display panel.

[0019] The second voltage terminal is the same as the first voltage terminal.

[0020] Optionally, the pull-up node control circuit is electrically connected with a frame reset terminal, a pull-up node and a third voltage terminal respectively, and is configured to control the electrical connection between the pull-up node and the third voltage terminal under the control of a frame reset signal provided by the frame reset terminal.

[0021] Optionally, the driving signal generation circuit further comprises a carry output circuit and a carry signal output terminal.

[0022] The carry output circuit is electrically connected with the pull-up node, the pull-down node, the carry signal output terminal, the output clock signal terminal and the second voltage terminal respectively, and is configured to control the connection between the carry signal output terminal and the output clock signal terminal under the control of the potential of the pull-up node, and control the connection between the carry signal output terminal and the second voltage terminal under the control of the potential of the pull-down node.

[0023] Optionally, the driving signal generation circuit comprises a first pull-down node and a second pull-down node.

[0024] The pull-up node control circuit is electrically connected with the input terminal, the reset terminal, the first pull-down node and the second pull-down node respectively, and is configured to control the potential of the pull-up node under the control of the input signal provided by the input terminal, control the communication between the pull-up node and the third voltage terminal under the control of the potential of the first pull-down node, control the communication between the pull-up node and the third voltage terminal under the control of the potential of the second pull-down node, and control the communication between the pull-up node and the third voltage terminal under the control of the reset signal provided by the reset terminal.

[0025] Optionally, the pull-down node control circuit comprises a first pull-down control circuit and a second pull-down control circuit.

[0026] The first pull-down control circuit is electrically connected with the input terminal, the first control voltage terminal, the pull-up node, the first pull-down node and the third voltage terminal respectively, and is configured to control the potential of the first pull-down node under the control of the input signal provided by the input terminal, the first control voltage provided by the first control voltage terminal and the potential of the pull-up node.

[0027] The second pull-down control circuit is electrically connected with the input terminal, the second control voltage terminal, the pull-up node, the second pull-down node and the third voltage terminal respectively, and is configured to control the potential of the second pull-down node under the control of the input signal, the second control voltage provided by the second control voltage terminal and the potential of the pull-up node.

[0028] In a second aspect, an embodiment of the present application provides a shutdown control method applied to the driving signal generation circuit, and the shutdown control method comprises the following steps.

[0029] In the shutdown stage, the shutdown control circuit controls the communication between the first voltage terminal and the driving signal output terminal under the control of the shutdown control signal, so that the driving signal output terminal outputs a valid driving signal.

[0030] Optionally, the duty cycle of the shutdown control signal is less than a duty cycle threshold.

[0031] In a third aspect, an embodiment of the present application further provides a display device comprising the driving signal generation circuit.

[0032] The driving signal generation circuit, the shutdown control method and the display device provided by the embodiments of the present application can release the residual charges in the pixels in the shutdown stage, and avoid display residual image. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural diagram of the driving signal generation circuit according to an embodiment of the present application;

[0034] Figure 2 is a structural diagram of the driving signal generation circuit according to at least one embodiment of the present application;

[0035] Figure 3 is a structural diagram of the driving signal generation circuit according to at least one embodiment of the present application;

[0036] Figure 4 is a structural diagram of the driving signal generation circuit according to at least one embodiment of the present application;

[0037] Figure 5 is a circuit diagram of the driving signal generation circuit according to at least one embodiment of the present application;

[0038] Figure 6 is a timing diagram of at least one embodiment of the driving signal generation circuit according to the present application; Figure 5

[0039] Figure 7 is a timing diagram of the driving signal generation circuit according to at least one embodiment of the present application;

[0040] Figure 8 is a circuit diagram of the driving signal generation circuit according to at least one embodiment of the present application;

[0041] Figure 9 is a curve diagram of the threshold voltage of each transistor changing with time at a high temperature of 85 degrees Celsius. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0043] The transistor used in all the embodiments of the present application can be a triode, a thin film transistor, a field effect transistor or other devices with the same characteristics. In the embodiments of the present application, to distinguish the two poles of the transistor except the control pole, one pole is called the first pole and the other pole is called the second pole.

[0044] In actual operation, when the transistor is a triode, the control pole can be a base, the first pole can be a collector, and the second pole can be an emitter; or the control pole can be a base, the first pole can be an emitter, and the second pole can be a collector. ​

[0045] In actual operation, when the transistor is a thin-film transistor or a field effect transistor, the control electrode can be a gate electrode, the first electrode can be a drain electrode, and the second electrode can be a source electrode; or, the control electrode can be a gate electrode, the first electrode can be a source electrode, and the second electrode can be a drain electrode.

[0046] The driving signal generation circuit provided by the embodiment of the present application is used to provide a driving signal for a display panel. Figure 1 As shown in the figure, the driving signal generation circuit comprises a driving signal output end OUT and a shutdown control circuit 11.

[0047] The shutdown control circuit 11 is electrically connected with a shutdown control end S1, a first voltage end V1 and the driving signal output end OUT, respectively, and is used to, in a shutdown stage, control the communication between the first voltage end V1 and the driving signal output end OUT under the control of a shutdown control signal provided by the shutdown control end S1, so as to make the driving signal output end OUT output an effective driving signal.

[0048] In the working process of the driving signal generation circuit provided by the embodiment of the present application, in the shutdown stage, the shutdown control circuit 11 controls the driving signal output end OUT to output an effective driving signal under the control of a shutdown control signal, the driving signal output end OUT is electrically connected with a gate line in a display panel, so as to make a thin-film transistor electrically connected with the gate line conductive, thereby releasing the residual charge in a pixel.

[0049] In at least one embodiment of the present application, the shutdown stage refers to a time period from when the display panel receives a shutdown instruction control signal to when the display panel is completely powered off, but is not limited thereto.

[0050] In the specific implementation, when the thin-film transistor electrically connected with the gate line and included in the pixel is an n-type transistor, the potential of the effective driving signal is a high voltage; when the thin-film transistor electrically connected with the gate line and included in the pixel is a p-type transistor, the potential of the effective driving signal is a low voltage.

[0051] In at least one embodiment of the present application, the potential of the effective driving signal is taken as a high voltage as an example for illustration.

[0052] In at least one embodiment of the present application, the duty cycle of the shutdown control signal is less than a duty cycle threshold.

[0053] For example, the duty cycle threshold can be 10%, but is not limited thereto.

[0054] In a specific implementation, the duty cycle of the shutdown control signal is less than a duty cycle threshold, so as to avoid the transistor included in the shutdown control circuit from aging fast, avoid the threshold voltage of the transistor from drifting seriously, and prevent the threshold voltage of the transistor from being too large to cause insufficient opening of the gate line during shutdown, so that the pixel cannot be discharged sufficiently, and thus display residual image is avoided.

[0055] In at least one embodiment of the present application, when the transistor included in the shutdown control circuit is an n-type transistor, the duty cycle of the shutdown control signal is a ratio between a time during which the potential of the shutdown control signal is maintained as a high voltage in a period and a duration of the period.

[0056] When the transistor included in the shutdown control circuit is a p-type transistor, the duty cycle of the shutdown control signal is a ratio between a time during which the potential of the shutdown control signal is maintained as a low voltage in a period and a duration of the period.

[0057] However, the present application is not limited thereto.

[0058] Optionally, the shutdown control circuit includes a shutdown control transistor.

[0059] The control electrode of the shutdown control transistor is electrically connected to the shutdown control end, the first electrode of the shutdown control transistor is electrically connected to the driving signal output end, and the second electrode of the shutdown control transistor is electrically connected to the first voltage end.

[0060] According to a specific implementation, the driving signal generation circuit includes a frame reset end, and the shutdown control end is the frame reset end.

[0061] In a specific implementation, the shutdown control end can be the frame reset end, which provides an effective voltage signal in a blank time period between two frames to cause the corresponding transistor to open, reset the pull-up node, and provide an effective voltage signal in the shutdown stage to cause the shutdown control transistor included in the shutdown control circuit to open and control the driving signal output end to output an effective driving signal.

[0062] In actual operation, the duty cycle of the frame reset signal provided by the frame reset end is less than 1%, and when the control electrode of the transistor included in the shutdown control circuit is electrically connected to the frame reset end, the threshold voltage of the transistor included in the shutdown control circuit drifts at a relatively small speed, so as to be able to charge the driving signal output end sufficiently in the shutdown stage, cause the pixel to discharge sufficiently, and ensure that there is no residual image problem caused by signal residual.

[0063] According to another specific embodiment, the shutdown control terminal can be the first voltage terminal; the first voltage terminal is configured to provide an effective voltage signal in the shutdown stage and an ineffective voltage signal in a normal working stage.

[0064] The normal working stage is a time period other than the shutdown stage in the working time of the display panel.

[0065] In at least one embodiment of the present application, when the shutdown control terminal is the first voltage terminal, the first voltage terminal only provides an effective shutdown control signal in the shutdown stage, and the transistor included in the shutdown control circuit is turned on only in the shutdown stage.

[0066] In a specific implementation, when the thin film transistor included in the pixel and electrically connected to the driving signal output terminal is an n-type transistor, the effective voltage signal can be a high voltage signal, and the ineffective voltage signal can be a low voltage signal.

[0067] When the thin film transistor included in the pixel and electrically connected to the driving signal output terminal is a p-type transistor, the effective voltage signal can be a low voltage signal, and the ineffective voltage signal can be a high voltage signal.

[0068] However, the present application is not limited thereto.

[0069] In at least one embodiment of the present application, the shutdown control terminal can be configured to provide a shutdown control signal in the shutdown stage to control the communication between the first voltage terminal and the driving signal output terminal, and provide a first control signal in the normal working stage to control the disconnection between the first voltage terminal and the driving signal output terminal.

[0070] The normal working stage is a time period other than the shutdown stage in the working time of the display panel.

[0071] In a specific implementation, the shutdown control terminal can also be a separately arranged control terminal, which provides a first control signal in the normal working stage to control the disconnection between the first voltage terminal and the driving signal output terminal, and provides a shutdown control signal in the shutdown stage to control the communication between the first voltage terminal and the driving signal output terminal.

[0072] The driving signal generation circuit according to at least one embodiment of the present application can further include a pull-up node control circuit, a pull-down node control circuit and a driving output circuit.

[0073] The pull-up node control circuit is configured to control the potential of the pull-up node.

[0074] The pull-down node control circuit is configured to control the potential of the pull-down node.

[0075] The driving output circuit is electrically connected with the pull-up node, the pull-down node, a driving signal output end, an output clock signal end and a second voltage end respectively, and is used for controlling the driving signal output end to be in communication with the output clock signal end under the control of the potential of the pull-up node, and controlling the driving signal output end to be in communication with the second voltage end under the control of the potential of the pull-down node.

[0076] The second voltage end is used for providing an invalid voltage signal in a normal working stage and providing a valid voltage signal in a shutdown stage; the normal working stage is a time period other than the shutdown stage in the working time of the display panel;

[0077] The second voltage end is the same voltage end as the first voltage end.

[0078] In at least one embodiment of the present application, when the thin film transistor electrically connected with the driving signal output end and included in the pixel is an n-type transistor, the valid voltage signal can be a high voltage signal, and the invalid voltage signal can be a low voltage signal.

[0079] When the thin film transistor electrically connected with the driving signal output end and included in the pixel is a p-type transistor, the valid voltage signal can be a low voltage signal, and the invalid voltage signal can be a high voltage signal.

[0080] However, the present application is not limited thereto.

[0081] In at least one embodiment of the present application, the second voltage end and the first voltage end can both be a first low voltage end; in the normal working stage, the first low voltage end provides a first low voltage signal; and in the shutdown stage, the first low voltage signal can provide a high voltage signal.

[0082] As shown in FIG. 1, Figure 2 The driving signal generation circuit in at least one embodiment of the present application includes a driving signal output end OUT, a shutdown control circuit 11, a pull-up node control circuit 21, a pull-down node control circuit 22 and a driving output circuit 23.

[0083] The shutdown control circuit 11 is electrically connected with a shutdown control end S1, a first low voltage end VGL and the driving signal output end OUT respectively, and is used for controlling the first low voltage end VGL to be in communication with the driving signal output end OUT under the control of a shutdown control signal provided by the shutdown control end S1 in the shutdown stage, so that the driving signal output end OUT outputs a valid driving signal.

[0084] The pull-up node control circuit 21 is electrically connected with a pull-up node PU, and is used for controlling the potential of the pull-up node PU.

[0085] The pull-down node control circuit 22 is electrically connected to the pull-down node PD and is used to control the potential of the pull-down node PD;

[0086] The drive output circuit 23 is electrically connected to the pull-up node PU, the pull-down node PD, the drive signal output terminal OUT, the output clock signal terminal CLK, and the first low voltage terminal VGL, respectively. It is used to control the connection between the drive signal output terminal OUT and the output clock signal terminal CLK under the control of the potential of the pull-up node PU, and to control the connection between the drive signal output terminal OUT and the first low voltage terminal VGL under the control of the potential of the pull-down node PD.

[0087] The first low-voltage terminal VGL is used to provide a first low-voltage signal during normal operation and a high-voltage signal during power-off; the normal operation phase is the time period included in the working time of the display panel, excluding the power-off phase.

[0088] exist Figure 2 In at least one embodiment shown, both the first voltage terminal and the second voltage terminal are first low voltage terminals.

[0089] In at least one embodiment of the present invention, the pull-up node control circuit is electrically connected to the frame reset terminal, the pull-up node and the third voltage terminal respectively, and is used to control the pull-up node to be electrically connected to the third voltage terminal under the control of the frame reset signal provided by the frame reset terminal.

[0090] In at least one embodiment of the present invention, the third voltage terminal may be a second low voltage terminal, but is not limited thereto.

[0091] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the drive signal generation circuit shown, the pull-up node control circuit 21 is also electrically connected to the frame reset terminal TRST and the second low voltage terminal LVGL, and is used to control the connection between the pull-up node PU and the second low voltage terminal LVGL under the control of the frame reset signal provided by the frame reset terminal TRST.

[0092] The shutdown control terminal can be the frame reset terminal TRST.

[0093] Optionally, the drive signal generation circuit further includes a carry output circuit and a carry signal output terminal;

[0094] The carry output circuit is electrically connected with the pull-up node, the pull-down node, a carry signal output end, an output clock signal end and a second voltage end respectively, and is used for controlling the carry signal output end to communicate with the output clock signal end under the control of the potential of the pull-up node, and controlling the carry signal output end to communicate with the second voltage end under the control of the potential of the pull-down node.

[0095] In specific implementation, the drive signal generation circuit can further include a carry output circuit and a carry signal output end, the carry output circuit controls the carry signal output end to output a carry signal, and the carry signal is used for cascading.

[0096] The drive signal generation circuit includes a first pull-down node and a second pull-down node according to an embodiment of the present application.

[0097] The pull-up node control circuit is further electrically connected with an input end, a reset end, the first pull-down node and the second pull-down node respectively, and is used for controlling the potential of the pull-up node under the control of an input signal provided by the input end, controlling the pull-up node to communicate with the third voltage end under the control of the potential of the first pull-down node, controlling the pull-up node to communicate with the third voltage end under the control of the potential of the second pull-down node, and controlling the pull-up node to communicate with the third voltage end under the control of a reset signal provided by the reset end.

[0098] In specific implementation, the drive signal generation circuit can adopt two pull-down nodes, and the pull-up node control circuit controls the potential of the pull-up node under the control of an input signal, a reset signal, the potential of the first pull-down node and the potential of the second pull-down node.

[0099] Optionally, the pull-down node control circuit includes a first pull-down control circuit and a second pull-down control circuit.

[0100] The first pull-down control circuit is electrically connected with an input end, a first control voltage end, a pull-up node, a first pull-down node and a third voltage end respectively, and is used for controlling the potential of the first pull-down node under the control of an input signal provided by the input end, a first control voltage provided by the first control voltage end and the potential of the pull-up node.

[0101] The second pull-down control circuit is electrically connected with an input end, a second control voltage end, a pull-up node, a second pull-down node and a third voltage end respectively, and is used for controlling the potential of the second pull-down node under the control of an input signal, a second control voltage provided by the second control voltage end and the potential of the pull-up node.

[0102] In a specific implementation, the pull-down node control circuit can include a first pull-down control circuit and a second pull-down control circuit, the first pull-down control circuit controls the potential of the first pull-down node, and the second pull-down control circuit controls the potential of the second pull-down node.

[0103] Optionally, the pull-up node control circuit can include a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor.

[0104] The control electrode of the first transistor is electrically connected with the first electrode of the first transistor and the input terminal, and the second electrode of the first transistor is electrically connected with the pull-up node.

[0105] The control electrode of the second transistor is electrically connected with the reset terminal, the first electrode of the second transistor is electrically connected with the pull-up node, and the second electrode of the second transistor is electrically connected with the second low-voltage terminal.

[0106] The control electrode of the third transistor is electrically connected with the first pull-down node, the first electrode of the third transistor is electrically connected with the pull-up node, and the second electrode of the third transistor is electrically connected with the second low-voltage terminal.

[0107] The control electrode of the fourth transistor is electrically connected with the second pull-down node, the first electrode of the fourth transistor is electrically connected with the pull-up node, and the second electrode of the fourth transistor is electrically connected with the second low-voltage terminal.

[0108] The control electrode of the fifth transistor is electrically connected with the frame reset terminal, the first electrode of the fifth transistor is electrically connected with the pull-up node, and the second electrode of the fifth transistor is electrically connected with the second low-voltage terminal.

[0109] The first pull-down control circuit includes a sixth transistor, a seventh transistor, and an eighth transistor.

[0110] The control electrode of the sixth transistor and the first electrode of the sixth transistor are electrically connected with the first control voltage terminal, and the second electrode of the sixth transistor is electrically connected with the first pull-down node.

[0111] The control electrode of the seventh transistor is electrically connected with the pull-up node, the first electrode of the seventh transistor is electrically connected with the first pull-down node, and the second electrode of the seventh transistor is electrically connected with the second low-voltage terminal.

[0112] The control electrode of the eighth transistor is electrically connected with the input terminal, the first electrode of the eighth transistor is electrically connected with the first pull-down node, and the second electrode of the eighth transistor is electrically connected with the second low-voltage terminal.

[0113] The second pull-down control circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor.

[0114] The control electrode of the ninth transistor is electrically connected with the second control voltage terminal, and the first electrode of the ninth transistor is electrically connected with the second pull-down node;

[0115] The control electrode of the tenth transistor is electrically connected with the pull-up node, the first electrode of the tenth transistor is electrically connected with the second pull-down node, and the second electrode of the tenth transistor is electrically connected with the second low voltage terminal;

[0116] The control electrode of the eleventh transistor is electrically connected with the input terminal, the first electrode of the eleventh transistor is electrically connected with the second pull-down node, and the second electrode of the eleventh transistor is electrically connected with the second low voltage terminal;

[0117] The drive output circuit comprises a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a first capacitor;

[0118] The control electrode of the twelfth transistor is electrically connected with the pull-up node, the first electrode of the twelfth transistor is electrically connected with the output clock signal terminal, and the second electrode of the twelfth transistor is electrically connected with the drive signal output terminal;

[0119] The control electrode of the thirteenth transistor is electrically connected with the first pull-down node, the first electrode of the thirteenth transistor is electrically connected with the drive signal output terminal, and the second electrode of the thirteenth transistor is electrically connected with the first low voltage terminal;

[0120] The control electrode of the fourteenth transistor is electrically connected with the second pull-down node, the first electrode of the fourteenth transistor is electrically connected with the drive signal output terminal, and the second electrode of the fourteenth transistor is electrically connected with the first low voltage terminal;

[0121] The control electrode of the fifteenth transistor is electrically connected with the output reset terminal, the first electrode of the fifteenth transistor is electrically connected with the drive signal output terminal, and the second electrode of the fifteenth transistor is electrically connected with the first low voltage terminal;

[0122] The first end of the first capacitor is electrically connected with the pull-up node, and the second end of the first capacitor is electrically connected with the drive signal output terminal;

[0123] The carry output circuit comprises a sixteenth transistor, a seventeenth transistor and an eighteenth transistor;

[0124] The control electrode of the sixteenth transistor is electrically connected with the pull-up node, the first electrode of the sixteenth transistor is electrically connected with the output clock signal terminal, and the second electrode of the sixteenth transistor is electrically connected with the carry signal output terminal;

[0125] The control electrode of the seventeenth transistor is electrically connected to the first pull-down node, the first electrode of the seventeenth transistor is electrically connected to the carry signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the first low voltage terminal.

[0126] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the carry signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first low voltage terminal.

[0127] like Figure 4 As shown, the drive signal generation circuit of at least one embodiment of the present invention includes a drive signal output terminal OUT, a carry signal output terminal OUT_C, a power-off control circuit 11, a pull-up node control circuit 21, a pull-down node control circuit, a drive output circuit 23, and a carry output circuit 40.

[0128] The shutdown control circuit 11 is electrically connected to the shutdown control terminal S1, the first low voltage terminal VGL, and the drive signal output terminal OUT, respectively. During the shutdown phase, under the control of the shutdown control signal provided by the shutdown control terminal S1, it controls the connection between the first low voltage terminal VGL and the drive signal output terminal OUT, so that the drive signal output terminal OUT outputs a valid drive signal.

[0129] The pull-up node control circuit 21 is electrically connected to the pull-up node PU, the frame reset terminal TRST, the input terminal INPUT, the reset terminal RST, the first pull-down node PD_A, the second pull-down node PD_B, and the second low-voltage terminal LVGL, respectively. It is used to control the potential of the pull-up node PU under the control of the input signal provided by the input terminal IPUT; to control the connection between the pull-up node PU and the second low-voltage terminal LVGL under the control of the potential of the first pull-down node PD_A; to control the connection between the pull-up node PU and the second low-voltage terminal LVGL under the control of the potential of the second pull-down node PD_B; to control the connection between the pull-up node PU and the second low-voltage terminal LVGL under the control of the reset signal provided by the reset terminal RST; and to control the connection between the pull-up node PU and the second low-voltage terminal LVGL under the control of the frame reset signal provided by the frame reset terminal TRST.

[0130] The pull-down node control circuit includes a first pull-down control circuit 41 and a second pull-down control circuit 42;

[0131] The first pull-down control circuit 41 is electrically connected with the input terminal INPUT, the first control voltage terminal VDD_A, the pull-up node PU, the first pull-down node PD_A and the second low voltage terminal LVGL, for controlling the potential of the first pull-down node PD_A under the control of the input signal, the first control voltage provided by the first control voltage terminal VDD_A and the potential of the pull-up node PU;

[0132] The second pull-down control circuit 42 is electrically connected with the input terminal INPUT, the second control voltage terminal VDD_B, the pull-up node PU, the second pull-down node PD_B and the second low voltage terminal LVGL, for controlling the potential of the second pull-down node PD_B under the control of the input signal, the second control voltage provided by the second control voltage terminal VDD_B and the potential of the pull-up node PU;

[0133] The drive output circuit 23 is electrically connected with the pull-up node PU, the first pull-down node PD_A, the second pull-down node PD_B, the output reset terminal RST_2, the drive signal output terminal OUT, the output clock signal terminal CLK and the first low voltage terminal VGL, for controlling the communication between the drive signal output terminal OUT and the output clock signal terminal CLK under the control of the potential of the pull-up node PU, controlling the communication between the drive signal output terminal OUT and the first low voltage terminal VGL under the control of the potential of the first pull-down node PD_A, controlling the communication between the drive signal output terminal OUT and the first low voltage terminal VGL under the control of the potential of the second pull-down node PD_B, and controlling the communication between the drive signal output terminal OUT and the first low voltage terminal VGL under the control of the output reset signal provided by the output reset terminal RST_2;

[0134] The carry output circuit 40 is electrically connected with the pull-up node PU, the first pull-down node PD_A, the second pull-down node PD_B, the carry signal output terminal OUT_C, the output clock signal terminal CLK and the first low voltage terminal VGL, for controlling the communication between the carry signal output terminal OUT_C and the output clock signal terminal CLK under the control of the potential of the pull-up node PU, controlling the communication between the carry signal output terminal OUT_C and the first low voltage terminal VGL under the control of the potential of the first pull-down node PD_A, and controlling the communication between the carry signal output terminal OUT_C and the first low voltage terminal VGL under the control of the potential of the second pull-down node PD_B;

[0135] The first low-voltage end VGL is configured to provide a first low-voltage signal in a normal working stage and provide a high-voltage signal in a shutdown stage; the normal working stage is a time period other than the shutdown stage in a working time of the display panel;

[0136] The second low-voltage end LVGL is configured to provide a second low-voltage signal.

[0137] As shown in Figure 5 As shown in Figure 4 Based on at least one embodiment of the driving signal generation circuit shown in

[0138] The shutdown control circuit comprises a shutdown control transistor M0.

[0139] The gate of the shutdown control transistor M0 is connected with the frame reset end TRST, the source of the shutdown control transistor M0 is electrically connected with the driving signal output end OUT, and the drain of the shutdown control transistor M0 is electrically connected with the first low-voltage end VGL.

[0140] The pull-up node control circuit 21 can comprise a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5.

[0141] The gate of the first transistor M1 is electrically connected with the source of the first transistor M1 and the input end INPUT, and the drain of the first transistor M1 is electrically connected with the pull-up node PU.

[0142] The gate of the second transistor M2 is electrically connected with the reset end RST, the source of the second transistor M2 is electrically connected with the pull-up node PU, and the drain of the second transistor M2 is electrically connected with the second low-voltage end LVGL.

[0143] The gate of the third transistor M3 is electrically connected with the first pull-down node PD_A, the source of the third transistor M3 is electrically connected with the pull-up node PU, and the drain of the third transistor M3 is electrically connected with the second low-voltage end LVGL.

[0144] The gate of the fourth transistor M4 is electrically connected with the second pull-down node PD_B, the source of the fourth transistor M4 is electrically connected with the pull-up node PU, and the drain of the fourth transistor M4 is electrically connected with the second low-voltage end LVGL.

[0145] The gate of the fifth transistor M5 is electrically connected with the frame reset end TRST, the source of the fifth transistor M5 is electrically connected with the pull-up node PU, and the drain of the fifth transistor M5 is electrically connected with the second low-voltage end LVGL.

[0146] The first pull-down control circuit 41 comprises a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8;

[0147] The gate of the sixth transistor M6 and the source of the sixth transistor M6 are electrically connected with the first control voltage terminal VDD_A, and the drain of the sixth transistor M6 is electrically connected with the first pull-down node PD_A;

[0148] The gate of the seventh transistor M7 is electrically connected with the pull-up node PU, the source of the seventh transistor M7 is electrically connected with the first pull-down node PD_A, and the drain of the seventh transistor M7 is electrically connected with the second low voltage terminal LVGL;

[0149] The gate of the eighth transistor M8 is electrically connected with the input terminal INPUT, the source of the eighth transistor M8 is electrically connected with the first pull-down node PD_A, and the drain of the eighth transistor M8 is electrically connected with the second low voltage terminal LVGL;

[0150] The second pull-down control circuit 42 comprises a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11;

[0151] The gate of the ninth transistor M9 and the source of the ninth transistor M9 are electrically connected with the second control voltage terminal VDD_B, and the drain of the ninth transistor M9 is electrically connected with the second pull-down node PD_B;

[0152] The gate of the tenth transistor M10 is electrically connected with the pull-up node PU, the source of the tenth transistor M10 is electrically connected with the second pull-down node PD_B, and the drain of the tenth transistor M10 is electrically connected with the second low voltage terminal LVGL;

[0153] The gate of the eleventh transistor M11 is electrically connected with the input terminal INPUT, the source of the eleventh transistor M11 is electrically connected with the second pull-down node PD_B, and the drain of the eleventh transistor M11 is electrically connected with the second low voltage terminal LVGL;

[0154] The drive output circuit 23 comprises a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 and a first capacitor C1;

[0155] The gate of the twelfth transistor M12 is electrically connected with the pull-up node PU, the source of the twelfth transistor M12 is electrically connected with the output clock signal terminal CLK, and the drain of the twelfth transistor M12 is electrically connected with the drive signal output terminal OUT;

[0156] The gate of the thirteenth transistor M13 is electrically connected with the first pull-down node PD_A, the source of the thirteenth transistor M13 is electrically connected with the driving signal output terminal OUT, and the drain of the thirteenth transistor M13 is electrically connected with the first low voltage terminal VGL.

[0157] The gate of the fourteenth transistor M14 is electrically connected with the second pull-down node PD_B, the source of the fourteenth transistor M14 is electrically connected with the driving signal output terminal OUT, and the drain of the fourteenth transistor M14 is electrically connected with the first low voltage terminal VGL.

[0158] The gate of the fifteenth transistor M15 is electrically connected with the output reset terminal RST_2, the source of the fifteenth transistor M15 is electrically connected with the driving signal output terminal OUT, and the drain of the fifteenth transistor M15 is electrically connected with the first low voltage terminal VGL.

[0159] The first end of the first capacitor C1 is electrically connected with the pull-up node PU, and the second end of the first capacitor C1 is electrically connected with the driving signal output terminal OUT.

[0160] The carry output circuit 40 includes a sixteenth transistor M16, a seventeenth transistor M17 and an eighteenth transistor M18.

[0161] The gate of the sixteenth transistor M16 is electrically connected with the pull-up node PU, the source of the sixteenth transistor M16 is electrically connected with the output clock signal terminal CLK, and the drain of the sixteenth transistor M16 is electrically connected with the carry signal output terminal OUT_C.

[0162] The gate of the seventeenth transistor M17 is electrically connected with the first pull-down node PD_A, the source of the seventeenth transistor M17 is electrically connected with the carry signal output terminal OUT_C, and the drain of the seventeenth transistor M17 is electrically connected with the first low voltage terminal VGL.

[0163] The gate of the eighteenth transistor M18 is electrically connected with the second pull-down node PD_B, the source of the eighteenth transistor M18 is electrically connected with the carry signal output terminal OUT_C, and the drain of the eighteenth transistor M18 is electrically connected with the first low voltage terminal VGL.

[0164] In Figure 5 In at least one embodiment of the driving signal generation circuit shown in the figure, all the transistors are n-type transistors, but the application is not limited thereto.

[0165] Figure 6 is Figure 5The waveform diagram of the first low voltage signal provided by VGL, the second low voltage signal provided by LVG, the frame reset signal provided by TRST, the first control voltage provided by VDD_A, the second control voltage provided by VDD_B and the output clock signal provided by CLK.

[0166] In Figure 6 , the label SN is the Nth frame display time, the label SN+1 is the N+1th frame display time, the label Xon is the power-off stage, and Vgnd is the ground voltage. Wherein, N is a positive integer.

[0167] As Figure 6 shown, in the power-off stage Xon, the frame reset signal provided by TRST is a high voltage signal to control M0 to open, and VGL provides a high voltage signal to control OUT to output a high voltage signal, to control the thin film transistor in the pixel in the display panel which is electrically connected with OUT to open, to release the residual charge in the pixel. And because the duty cycle of the frame reset signal is small, M0 will not have a large threshold voltage drift phenomenon, and in the power-off stage, M0 can be fully turned on to make the pixel fully discharge, to solve the residual image problem.

[0168] As Figure 7 shown, on the basis of Figure 6 , the timing of the first clock signal CLK1, the timing of the second clock signal CLK2, the timing of the third clock signal CLK3, the timing of the fourth clock signal CLK4, the timing of the fifth clock signal CLK5, the timing of the sixth clock signal CLK6, the timing of the seventh clock signal CLK7, the timing of the eighth clock signal CLK8, the timing of the first start voltage STV1 and the timing of the second start voltage STV2 are added.

[0169] In the related art, the shutdown control transistor M0 is not provided, in the shutdown stage, the potential of the first control voltage provided by VDD_A and the potential of the second control voltage provided by VDD_B are pulled up at the same time, M3, M4, M13 and M14 are opened, the potential of the frame reset signal provided by TRST is pulled up, M5 is opened, M3, M4 and M5 are opened, and the low voltage signal provided by LVGL is low, in the shutdown process, the potential of the pull-up node in all row driving signal generation circuits is low voltage, and the problem of white line during power-on and power-off can be avoided. M13 and M14 are opened, the first low voltage signal provided by VGL is high, the driving signal provided by all row driving signal output ends is high voltage signal, all pixels included in the display panel are discharged, and the related problem of shutdown screen residual is avoided. Since the voltage bias working duty cycle of M3, M4, M13 and M14 is about 50% in the normal display process, the transistor aging is wide, that is, the threshold voltage of each transistor increases rapidly, and the higher the temperature, the faster the threshold voltage drift speed. During the aging test, it is easy to cause the threshold voltage of M3, the threshold voltage of M4, the threshold voltage of M13 and the threshold voltage of M14 to be too large, so that M3, M4, M13 and M14 are insufficiently opened in the shutdown stage, and the pixels cannot be fully discharged, thereby causing the residual image problem. Based on this, the shutdown control transistor controlled by the shutdown control signal with small duty cycle is adopted in the embodiment of the application, so that the potential of the driving signal is high voltage in the shutdown stage, so that the pixels are fully discharged, and the residual image problem is solved.

[0170] Figure 8 At least one embodiment of the driving signal generation circuit shown in the figure is different from Figure 5 At least one embodiment of the driving signal generation circuit shown in the figure is different from

[0171] Figure 8 At least one embodiment of the driving signal generation circuit shown in the figure is different from

[0172] Figure 8 At least one embodiment of the driving signal generation circuit shown in the figure is different from

[0173] Figure 9 M13, Figure 5M0 in M8, wherein L1 is the threshold voltage curve of M13, L2 is the threshold voltage curve of M0 in M8, L3 is the threshold voltage curve of M0 in M8, and L4 is the threshold voltage curve of M0 in M8. Figure 5 M0 in M8, wherein L1 is the threshold voltage curve of M13, L2 is the threshold voltage curve of M0 in M8, L3 is the threshold voltage curve of M0 in M8, and L4 is the threshold voltage curve of M0 in M8. Figure 8 M0 in M8, wherein L1 is the threshold voltage curve of M13, L2 is the threshold voltage curve of M0 in M8, L3 is the threshold voltage curve of M0 in M8, and L4 is the threshold voltage curve of M0 in M8.

[0174] In the above-mentioned figures, the horizontal axis is time t, and the vertical axis is threshold voltage V. Figure 9 In the above-mentioned figures, the horizontal axis is time t, and the vertical axis is threshold voltage V.

[0175] The power-off control method according to an embodiment of the present application is applied to the driving signal generation circuit described above, and the power-off control method comprises the following steps.

[0176] In the power-off stage, the power-off control circuit controls the communication between the first voltage terminal and the driving signal output terminal under the control of the power-off control signal, so that the driving signal output terminal outputs an effective driving signal.

[0177] In at least one embodiment of the present application, the duty cycle of the power-off control signal is less than a duty cycle threshold.

[0178] The display device according to an embodiment of the present application comprises the driving signal generation circuit described above.

[0179] The display device provided by the embodiments of the present application can be any product or component with display function, such as wearable devices, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigation devices, etc.

[0180] The above-mentioned is the preferred embodiment of the present application, and it should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A drive signal generation circuit for providing a drive signal for a display panel, characterized by, The driving signal generation circuit comprises a driving signal output end and a shutdown control circuit; The shutdown control circuit is electrically connected with a shutdown control end, a first voltage end and the driving signal output end respectively, and is configured to, in the shutdown stage, control the communication between the first voltage end and the driving signal output end under the control of a shutdown control signal provided by the shutdown control end, so that the driving signal output end outputs an effective driving signal; The duty cycle of the shutdown control signal is less than a duty cycle threshold; The duty cycle threshold is 10%; The driving signal generation circuit further comprises a pull-down control node control circuit; the pull-down control node control circuit is configured to control the potential of a pull-down node; the pull-down control node control circuit comprises a first pull-down control circuit and a second pull-down control circuit; The first pull-down control circuit is electrically connected with an input end, a first control voltage end, a pull-up node, a first pull-down node and a third voltage end respectively, and is configured to control the potential of the first pull-down node under the control of an input signal provided by the input end, a first control voltage provided by the first control voltage end and the potential of the pull-up node; The second pull-down control circuit is electrically connected with an input end, a second control voltage end, a pull-up node, a second pull-down node and a third voltage end respectively, and is configured to control the potential of the second pull-down node under the control of an input signal, a second control voltage provided by the second control voltage end and the potential of the pull-up node; The first control voltage end is configured to provide an ineffective voltage signal in a part of the time period included in the shutdown stage, and the second control voltage end is configured to provide an ineffective voltage signal in a part of the time period included in the shutdown stage.

2. The drive signal generation circuit of claim 1, wherein, The shutdown control circuit comprises a shutdown control transistor; The control electrode of the shutdown control transistor is electrically connected with a shutdown control end, the first electrode of the shutdown control transistor is electrically connected with the driving signal output end, and the second electrode of the shutdown control transistor is electrically connected with the first voltage end.

3. The drive signal generation circuit of claim 1, wherein, The driving signal generation circuit comprises a frame reset end, and the shutdown control end is the frame reset end.

4. The drive signal generation circuit of claim 1, wherein, The shutdown control end is the first voltage end; the first voltage end is configured to provide an effective voltage signal in the shutdown stage and an ineffective voltage signal in a normal working stage; The normal working stage is a time period included in the working time of the display panel except the shutdown stage.

5. The drive signal generation circuit of claim 1, wherein, The shutdown control circuit is configured to provide a shutdown control signal in the shutdown stage to control the communication between the first voltage end and the driving signal output end, and provide a first control signal in the normal working stage to control the disconnection between the first voltage end and the driving signal output end; The normal working stage is a time period included in the working time of the display panel except the shutdown stage.

6. The drive signal generation circuit of any one of claims 1 to 5, wherein, Further comprising a pull-up node control circuit and a driving output circuit; The pull-up node control circuit is configured to control the potential of a pull-up node; The driving output circuit is electrically connected with the pull-up node, the pull-down node, a driving signal output end, an output clock signal end and a second voltage end respectively, and is used for controlling the driving signal output end to communicate with the output clock signal end under the control of the potential of the pull-up node, and controlling the driving signal output end to communicate with the second voltage end under the control of the potential of the pull-down node. The second voltage end is used for providing an invalid voltage signal in a normal working stage and providing a valid voltage signal in a shutdown stage; the normal working stage is a time period other than the shutdown stage in the working time of the display panel The second voltage end is the same voltage end as the first voltage end.

7. The drive signal generation circuit of claim 6, wherein, The pull-up node control circuit is electrically connected with a frame reset end, a pull-up node and a third voltage end respectively, and is used for controlling the pull-up node to be electrically connected with the third voltage end under the control of a frame reset signal provided by the frame reset end.

8. The drive signal generation circuit of claim 6, wherein, The carry output circuit and a carry signal output end are further included. The carry output circuit is electrically connected with the pull-up node, the pull-down node, the carry signal output end, the output clock signal end and the second voltage end respectively, and is used for controlling the carry signal output end to communicate with the output clock signal end under the control of the potential of the pull-up node, and controlling the carry signal output end to communicate with the second voltage end under the control of the potential of the pull-down node.

9. The drive signal generation circuit of claim 7, wherein, The first pull-down node and the second pull-down node are included. The pull-up node control circuit is further electrically connected with an input end, a reset end, the first pull-down node and the second pull-down node respectively, and is used for controlling the potential of the pull-up node under the control of an input signal provided by the input end, controlling the pull-up node to communicate with the third voltage end under the control of the potential of the first pull-down node, controlling the pull-up node to communicate with the third voltage end under the control of the potential of the second pull-down node, and controlling the pull-up node to communicate with the third voltage end under the control of a reset signal provided by the reset end.

10. A power-off control method applied to the drive signal generation circuit according to any one of claims 1 to 9, characterized by, The shutdown control method comprises: In the shutdown stage, the shutdown control circuit controls the first voltage end to communicate with the driving signal output end under the control of a shutdown control signal, so that the driving signal output end outputs a valid driving signal; The duty cycle of the shutdown control signal is less than a duty cycle threshold; the duty cycle threshold is 10%; and The duty cycle of the shutdown control signal is less than a duty cycle threshold; the duty cycle threshold is 10%; and The driving signal generation circuit further comprises a pull-down control node control circuit; the pull-down control node control circuit comprises a first pull-down control circuit and a second pull-down control circuit; the first pull-down control circuit is electrically connected with an input end, a first control voltage end, a pull-up node, a first pull-down node and a third voltage end respectively, and is used for controlling the potential of the first pull-down node under the control of an input signal provided by the input end, a first control voltage provided by the first control voltage end and the potential of the pull-up node; the second pull-down control circuit is electrically connected with the input end, a second control voltage end, the pull-up node, a second pull-down node and the third voltage end respectively, and is used for controlling the potential of the second pull-down node under the control of the input signal, a second control voltage provided by the second control voltage end and the potential of the pull-up node; The shutdown control method further comprises: In a part of the time period included in the shutdown stage, the first control voltage end provides an invalid voltage signal; In a part of the time period included in the shutdown stage, the second control voltage end provides an invalid voltage signal.

11. A display device comprising: The driving signal generation circuit comprises the driving signal generation circuit according to any one of claims 1 to 9.

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