storage device

Abstract

Embodiments provide a storage device capable of reliably performing a read operation. According to one embodiment, the storage device includes a first interconnection, a second interconnection, a storage cell connected between the first interconnection and the second interconnection and including a variable resistance element and a switching element connected in series to the variable resistance element, and a control circuit configured to perform control of a read operation to read data stored in the storage cell. The control circuit performs the control in such a manner as to set the first interconnection, which has been charged with a first voltage, and the second interconnection, which has been charged with a second voltage, to a floating state, set the switching element to an on state by discharging the second interconnection set to the floating state, thereby increasing a voltage applied to the storage cell, and read the data stored in the storage cell in a state where the switching element is set to the on state.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2021-037466, filed March 9, 2021, and U.S. Patent Application No. 17 / 462449, filed August 31, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to storage devices. Background Technology

[0004] A non-volatile storage device is proposed, comprising storage cells, each storage cell including a series connection of a variable resistive storage element (such as a magnetoresistive element) and a switching element. Summary of the Invention

[0005] The embodiment provides a storage device capable of reliably performing read operations.

[0006] Generally, according to one embodiment, a storage device includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction intersecting the first direction; a storage cell connected between the first interconnect and the second interconnect, and including a variable resistive storage element and a switching element, wherein the switching element and the variable resistive storage element are connected in series between a first end and a second end of the storage cell, the first end and the second end being respectively connected to the first interconnect and the second interconnect; and a control circuit configured to perform control of a read operation to read data stored in the storage cell. The control circuit performs control in such a way that it sets the first interconnect, charged with a first voltage, and the second interconnect, charged with a second voltage, into a floating state; it sets the switching element into a conducting state by discharging the second interconnect, which is set into a floating state, thereby increasing the voltage applied to the storage cell; and it reads data stored in the storage cell while the switching element is set into the conducting state. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the general schematic configuration of a storage device according to an embodiment.

[0008] Figure 2A This is a perspective view schematically illustrating the configuration of the storage cell array section in a storage device according to an embodiment.

[0009] Figure 2B This is a perspective view schematically illustrating a modified configuration of the storage cell array section in a storage device according to an embodiment.

[0010] Figure 3This is a cross-sectional view schematically illustrating the configuration of magnetoresistive elements in a storage device according to an embodiment.

[0011] Figure 4 This is a cross-sectional view schematically illustrating the configuration of a selector in a storage device according to an embodiment.

[0012] Figure 5 This schematically illustrates the relationship between the voltage applied across the two ends of the memory cell and the current flowing through the memory cell.

[0013] Figure 6 This is a circuit diagram illustrating a read operation performed by a storage device according to an embodiment.

[0014] Figures 7A to 7C This is a timing diagram illustrating an example of a read operation performed by a storage device according to an embodiment.

[0015] Figures 8A to 8C This is a timing diagram illustrating another example of a read operation performed by a storage device according to an embodiment. Detailed Implementation

[0016] The embodiments will be described below with reference to the accompanying drawings.

[0017] Figure 1 This is a block diagram illustrating a general schematic configuration of a storage device (e.g., a non-volatile storage device) according to an embodiment. Note that magnetic storage devices will be described below as examples of storage devices.

[0018] The magnetic storage device according to this embodiment includes a storage cell array 100, a control circuit 200, and a detection circuit 300.

[0019] Figure 2A This is a perspective view schematically showing the configuration of the memory cell array section 100.

[0020] The memory cell array 100 includes: a plurality of word lines (also referred to herein as first interconnects) 10 provided on a base region (not shown, which includes a semiconductor substrate not shown) and extending in the X direction; a plurality of bit lines (also referred to herein as second interconnects) 20 extending in the Y direction; and a plurality of memory cells 30 connected between the plurality of word lines 10 and the plurality of bit lines 20.

[0021] Note that the X, Y, and Z directions shown in the attached diagram intersect each other. More specifically, the X, Y, and Z directions are orthogonal to each other.

[0022] When writing data to or reading data from memory cell 30, word line 10 and bit line 20 each provide a predetermined signal to each memory cell 30. Figure 2A In the middle, although the word line 10 is located on the lower layer side and the bit line 20 is located on the upper layer side, the word line 10 can also be located on the upper layer side and the bit line 20 can be located on the lower layer side.

[0023] Each storage cell 30 includes a magnetoresistive element 40 as a variable resistive storage element and a selector, namely a switching element 50 connected in series with the magnetoresistive element 40, for selecting the magnetoresistive element 40.

[0024] exist Figure 2A In this configuration, although the magnetoresistive element 40 is located on the lower layer and the selector 50 is located on the upper layer, as... Figure 2B As shown, the magnetoresistive effect element 40 can also be located on the upper layer side, and the selector 50 can be located on the lower layer side.

[0025] Figure 3 This is a cross-sectional view schematically showing the configuration of the magnetoresistive element 40.

[0026] In this embodiment, a magnetic tunnel junction (MTJ) element is used as a magnetoresistive effect element 40. The magnetoresistive effect element 40 includes a storage layer (i.e., a first magnetic layer 41), a reference layer (i.e., a second magnetic layer 42), and a tunnel barrier layer (i.e., a non-magnetic layer 43).

[0027] Storage layer 41 is a ferromagnetic layer with a variable magnetization direction. A variable magnetization direction means that the magnetization direction changes relative to the write current. Reference layer 42 is a ferromagnetic layer with a fixed magnetization direction. A fixed magnetization direction means that the magnetization direction does not change relative to a predetermined write current. Tunnel barrier layer 43 is an insulating layer provided between storage layer 41 and reference layer 42.

[0028] When the magnetization direction of the storage layer 41 is parallel to the magnetization direction of the reference layer 42, the magnetoresistive element 40 is in a low-resistance state, in which its resistance is relatively low. When the magnetization direction of the storage layer 41 is opposite to the magnetization direction of the reference layer 42, the magnetoresistive element 40 is in a high-resistance state, in which its resistance is relatively high. Therefore, the magnetoresistive element 40 can store binary data in response to its resistance state (low-resistance state or high-resistance state). Furthermore, the low-resistance state or high-resistance state in the magnetoresistive element 40 can be set depending on the direction of the write current.

[0029] although Figure 3 The magnetoresistive effect element 40 shown has a bottomless structure in which the storage layer 41 is located on the lower side and the reference layer 42 is located on the upper side. However, a magnetoresistive effect element with a topless structure in which the storage layer 41 is located on the upper side and the reference layer 42 is located on the lower side is also applicable.

[0030] Figure 4This is a cross-sectional view schematically showing the configuration of selector 50.

[0031] Selector 50 includes a lower electrode 51, an upper electrode 52, and a selector material layer, namely a switching material layer 53 provided between the lower electrode 51 and the upper electrode 52. Selector 50 is a two-terminal switching element exhibiting nonlinear current-voltage characteristics. When the voltage applied to the two terminals is lower than a threshold voltage, selector 50 is set to a high-resistance state, such as a non-conductive state, and when the voltage applied to the two terminals is equal to or higher than the threshold voltage, selector 50 is set to a low-resistance state, such as a conductive state.

[0032] Figure 5 The relationship between the voltage applied across the two ends of the storage cell 30 and the current flowing through the storage cell 30 is illustrated schematically.

[0033] When the voltage applied to memory cell 30 increases to a level equal to or higher than the threshold voltage Vth, selector 50 switches to a low-resistance state (on state), and when the voltage applied to memory cell 30 decreases to a level lower than the holding voltage Vhold, selector 50 switches to a high-resistance state (off state). When the voltage applied to memory cell 30 is equal to the holding voltage Vhold, the holding current Ihold flows through memory cell 30. Applying a voltage equal to or higher than the threshold voltage Vth between a word line 10 and a bit line 20 causes selector 50 to switch to the on state, making it possible to write or read data from the magnetoresistive element 40 connected in series with selector 50.

[0034] Next, we will refer to Figure 6 The circuit diagram shown and Figures 7A to 7C The timing diagram shown describes the read operation of the storage device according to this embodiment.

[0035] Storage devices are mainly in Figure 1 The device operates under the control of the control circuit 200 shown. That is, the write operation of writing data to the magnetoresistive element 40 and the read operation of reading data stored in the magnetoresistive element 40 are mainly performed under the control of the control circuit 200.

[0036] like Figure 6 As shown, one end of switch circuit 61 and one end of switch circuit 62 are connected to each word line 10, global word line 63 is connected to the other end of switch circuit 61, and voltage supply line 64 is connected to the other end of switch circuit 62. One end of switch circuit 71 and one end of switch circuit 72 are connected to each bit line 20, global bit line 73 is connected to the other end of switch circuit 71, and voltage supply line 74 is connected to the other end of switch circuit 72. A fixed voltage Vdd / 2 is applied to each voltage supply line 64 and 74.

[0037] Global word line (GWL) control circuit 210 is connected to global word line 63, and global bit line (GBL) control circuit 220 is connected to global bit line 73. Figure 1 The control circuit 200 shown includes a global word line control circuit 210 and a global bit line control circuit 220.

[0038] The detection circuit 300 includes a constant current source 310 and a sense amplifier (S / A) 320, and a read enable transistor 81 and a clamping transistor 82 are connected between the detection circuit 300 and the global word line 63.

[0039] The following will refer to Figures 7A to 7C Describe the read operation in detail. Figure 7A The voltage VGWL of global word line 63 and the voltage VGBL of global bit line 73 are shown. Figure 7B The read enable signal REN is shown being applied to the gate of transistor 81. Figure 7C The current Icell through the storage cell 30 is shown, which is the current through the series connection of the magnetoresistive element 40 and the selector 50.

[0040] Before the read operation begins, the voltage VGWL on global word line 63 and the voltage VGBL on global bit line 73 are each held at Vdd / 2. Additionally, the read enable signal REN is low, and the current Icell through memory cell 30 is zero.

[0041] When the read operation begins at time t1, the control circuit 200 performs control in such a way that it charges the selected word line 10 connected to the target memory cell (also referred to as the selected memory cell) 30 and the selected bit line 20 connected to the target memory cell 30.

[0042] Specifically, the global word line control circuit 210 charges the global word line 63 with a first voltage, and the global bit line control circuit 220 charges the global bit line 73 with a second voltage. In this embodiment, both the first and second voltages are Vdd, therefore, the first voltage is equal to the second voltage. At this time, the switching circuit 61 connected to the selected word line 10 and the switching circuit 71 connected to the selected bit line 20 are set to the ON state. On the other hand, the switching circuit 62 connected to the selected word line 10 is set to the OFF state, and the switching circuit 72 connected to the selected bit line 20 is set to the OFF state. Therefore, the selected word line 10 and the selected bit line 20 are each charged with voltage Vdd. That is, the voltage used to charge the selected word line 10 is equal to the voltage used to charge the selected bit line 20.

[0043] Furthermore, the switch circuit 61 connected to each unselected word line 10 is set to the off state, and the switch circuit 62 connected to each unselected word line 10 is set to the on state. Similarly, the switch circuit 71 connected to each unselected bit line 20 is set to the off state, and the switch circuit 72 connected to each unselected bit line 20 is set to the on state. Therefore, the voltage of each of the unselected word lines 10 and 20 is Vdd / 2.

[0044] After the selected word line 10 and the selected bit line 20 are charged with voltage Vdd as described above, the control circuit 200 performs control in a manner that sets the selected word line 10 and the selected bit line 20 into a floating state.

[0045] Specifically, at time t2, the global word line control circuit 210 sets the global word line 63 to a floating state, and the global bit line control circuit 220 sets the global bit line 73 to a floating state. Therefore, the selected word line 10 and the selected bit line 20 are set to a floating state.

[0046] After the selected word line 10 and selected bit line 20 are set to a floating state as described above, the control circuit 200 performs control to discharge the selected bit line 20 starting at time t3. As a result, the voltage applied to the selected memory cell 30 increases, and the selector 50 of the selected memory cell 30 switches to the on state.

[0047] Specifically, by discharging the global bit line 73 through the global bit line control circuit 220, the voltage of the selected bit line 20 gradually decreases to Vss (e.g., zero volts).

[0048] Additionally, in this embodiment, at time t3, the control signal from the control circuit 200 sets the read enable signal REN to a high level and the transistor 81 switches to the on state. This enables the constant current source 310 to supply a constant current to the selected memory cell 30. Note that the timing of the read enable signal REN switching to a high level does not need to match the timing of the start of discharge of the selected bit line 20, and the read enable signal REN can switch to a high level before the detection circuit 300 actually detects the data stored in the magnetoresistive element 40.

[0049] When the voltage difference between the global word line 63 and the global bit line 73 reaches the threshold voltage Vth, that is, when the voltage difference between the selected word line 10 and the selected bit line 20 reaches the threshold voltage Vth at time t4, the selector 50 of the selected memory cell 30 switches from the off state to the on state. Therefore, a conduction current is supplied from the constant current source 310 to the series connection between the magnetoresistive element 40 of the selected memory cell 30 and the selector 50, and the voltage of the selected word line 10, i.e., the voltage of the global word line 63, gradually decreases.

[0050] When the voltage of global word line 63 drops, the voltage difference between global word line 63 and global bit line 73 (this difference is equal to the voltage difference between selected word line 10 and selected bit line 20) reaches the holding voltage Vhold. That is, the voltage applied to the selected memory cell 30 reaches the holding voltage Vhold at time t5. At this time, the control signal from the control circuit 200 keeps the read enable signal REN at a high level and the transistor 81 is set to the on state. Therefore, the on-current is continuously supplied from the constant current source 310 to the selector 50 of the selected memory cell 30. For this reason, the selector 50 of the selected memory cell 30 is not set to the off state and is kept in the on state. That is, after the selector 50 is set to the on state at time t4, the on-current continuously flows through the selector 50.

[0051] The control circuit 200 performs control in such a way that when the selector 50 of the selected memory cell 30 is set to the on state and the voltage applied to the selected memory cell 30 (which is equal to the difference between the voltage applied to the selected word line 10 and the voltage applied to the selected bit line 20) is maintained at the holding voltage Vhold, the data (data corresponding to the low resistance state or the high resistance state) stored in the magnetoresistive element 40 of the selected memory cell 30 is read.

[0052] Specifically, the sensing amplifier 320 detects the cell current Icell passing through the selected storage cell 30, thereby determining the data stored in the magnetoresistive element 40. For example... Figure 7C As shown, when the magnetoresistive element 40 is in a low-resistance state, the on-current through the selected memory cell 30 (described as the holding current Ihold1) is higher than the on-current through the selected memory cell 30 (described as the holding current Ihold2) when the magnetoresistive element 40 is in a high-resistance state. Therefore, the detection circuit 300, including the sense amplifier 320, detects the resistance state of the magnetoresistive element 40 based on the on-current through the selector 50 (which is equal to the on-current through the selected memory cell 30), thereby determining the data stored in the magnetoresistive element 40. The detection circuit 300, including the sense amplifier 320, detects the resistance state of the magnetoresistive element 40 when the on-current through the selector 50 is held constant and the voltage applied to the selected memory cell 30 is held at the holding voltage Vhold.

[0053] Note that the method for determining the data stored in the magnetoresistive element 40 is not limited to the method described above, namely, detecting the holding current Ihold through the selected storage cell 30 while the voltage applied to the selected storage cell 30 is held at the holding voltage Vhold. Other determination methods are also applicable.

[0054] As described above, according to this embodiment, the selector 50 is set to the conducting state by charging the selected word line 10 and the selected bit line 20, discharging the selected bit line 20 which is set to a floating state, and increasing the voltage applied to the selected memory cell 30. Therefore, the selector 50 can be reliably set to the conducting state while it is in the conducting state, and the data stored in the magnetoresistive element 40 can be reliably read.

[0055] Furthermore, the constant current source 310 supplies a constant on-state current to the selected memory cell 30 before the voltage applied to the selected memory cell 30 (i.e., the voltage applied between the selected word line 10 and the selected bit line 20) reaches the holding voltage Vhold. Therefore, data stored in the magnetoresistive element 40 can be reliably read while the selector 50 is in the on state without switching the selector 50 to the off state.

[0056] Figures 8A to 8C This is a timing diagram illustrating an example of a read operation performed by a storage device according to this embodiment.

[0057] Figures 8A to 8C The read operation shown is basically similar to that described above. Figures 7A to 7C The read operation shown. However, Figures 8A to 8C The read operation shown is similar to the following aspects: Figures 7A to 7C The read operations shown are different. Figures 7A to 7C In the read operation shown, while global word line 63 and global bit line 73 are each charged with voltage Vdd, global word line 63 and global bit line 73 are switched to a floating state. In contrast, in Figures 8A to 8C In the read operation shown, while global word line 63 is charged with voltage Vdd and global bit line 73 is charged with voltage Vdd / 2, global word line 63 and global bit line 73 are converted to a floating state. That is, in Figures 8A to 8C In the read operation shown, the first voltage and the second voltage are different. Note that the first voltage and the second voltage are not limited to... Figures 7A to 7C The value in the example of the read operation shown is or Figures 8A to 8C The values ​​in the example of the read operation shown are acceptable as long as the difference between the first voltage and the second voltage is less than the threshold voltage Vth.

[0058] exist Figures 8A to 8C In the example of the read operation shown, similar to Figures 7A to 7C The read operation shown can produce similar effects to the embodiments described above, and similarly, data stored in the magnetoresistive element 40 can be reliably read when the selector 50 is set to the on state.

[0059] Although a magnetoresistive element is used as a variable resistance storage element in the embodiments described above, other variable resistance storage elements may also be used.

[0060] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications as falling within the scope and spirit of this disclosure.

[0061] Explanation of the mark

[0062] 10: Word line (first interconnection)

[0063] 20: Bit line (second interconnect)

[0064] 30: Storage unit

[0065] 40: Magnetoresistive element

[0066] 41: Storage layer

[0067] 42: Reference Layer

[0068] 43: Tunnel barrier layer

[0069] 50: Selector (Switching Element)

[0070] 51: Lower electrode

[0071] 52: Upper electrode

[0072] 53: Selector Material Layer

[0073] 61, 62: Switching circuit

[0074] 63: Global Text Line

[0075] 64: Voltage supply line

[0076] 71, 72: Switching circuits

[0077] 73: Global Bitline

[0078] 74: Voltage supply line

[0079] 81, 82: Transistors

[0080] 100: Memory cell array section

[0081] 200: Control circuit

[0082] 210: Global word line control circuit

[0083] 220: Global Bitline Control Circuit

[0084] 300: Detection circuit

[0085] 310: Constant Current Source

[0086] 320: Sensing Amplifier

Claims

1. A storage device, comprising: The first interconnect extends in the first direction; The second interconnect extends in a second direction that intersects the first direction; A storage cell is connected between the first interconnect and the second interconnect, and includes a variable resistance storage element and a switching element, the switching element being connected in series with the variable resistance storage element between a first end and a second end of the storage cell, the first end and the second end being respectively connected to the first interconnect and the second interconnect; as well as A control circuit is configured to control a read operation of reading data stored in the storage unit, wherein... The control circuit performs the control of the read operation in such a manner as follows: The first interconnect, which has been charged with the first voltage, and the second interconnect, which has been charged with the second voltage, are set to a floating state. After the first interconnect and the second interconnect have been set to the floating state, the switching element is set to the conducting state by discharging the second interconnect, thereby increasing the voltage applied to the memory cell, and With the switching element set to the on state and after the voltage applied to the memory cell decreases from the threshold voltage to the holding voltage, data stored in the memory cell is read by sensing a constant holding current through the memory cell, wherein the switching element switches to the on state at the threshold voltage, and the holding voltage is below the threshold voltage and above zero voltage.

2. The storage device according to claim 1, wherein, When the voltage applied to the storage cell is lower than the holding voltage, the switching element switches to the off state.

3. The storage device according to claim 2, wherein, The difference between the first voltage and the second voltage is less than the threshold voltage.

4. The storage device according to claim 2, wherein, When reading data stored in the storage unit, the difference between the voltage applied to the first interconnect and the voltage applied to the second interconnect is equal to the holding voltage.

5. The storage device according to claim 1, wherein, The first voltage is equal to the second voltage.

6. The storage device according to claim 1, wherein, The first voltage is different from the second voltage.

7. The storage device according to claim 1, wherein, The control circuit performs control in such a way that after the switching element is set to the on state, the conduction current continuously passes through the switching element.

8. The storage device according to claim 7, further comprising: A constant current source supplies the conduction current to the switching element.

9. The storage device according to claim 1, further comprising: The detection circuit detects the resistance state of the variable resistance storage element based on the conduction current through the switching element.

10. The storage device according to claim 9, wherein, The detection circuit detects the resistance state of the variable resistance storage element while the conduction current is maintained at a constant value.

11. The storage device according to claim 1, wherein, The variable resistance storage element is a magnetoresistive element.

12. A storage device, comprising: Multiple bit lines, including the first bit line and the second bit line; Multiple character lines, including the first character line and the second character line; In a plurality of memory cells between the bit lines and the word lines, each memory cell includes a variable resistor element and a switching element, the variable resistor element and the switching element being connected in series between a first end and a second end, the first end being connected to one of the bit lines and the second end being connected to one of the word lines; Control circuit; as well as The detection circuit, in which, During a read operation that reads data stored in a target storage unit, wherein the target storage unit is one of the storage units between the first bit line and the first word line. When the first bit line is at a first voltage and the first word line is at a second voltage, the control circuit sets the first bit line and the first word line to a floating state. After setting the first bit line and the first word line to a floating state, the control circuit discharges the first bit line and supplies a constant current to the switching element of the target memory cell to turn on the switching element of the target memory cell. After the voltage difference between the first word line and the first bit line decreases from the threshold voltage to the holding voltage and the holding current flows constantly through the target memory cell having the switching element in the on state, the detection circuit detects the current through the target memory cell and determines the data stored in the target memory cell based on the detected current, wherein the switching element switches to the on state at the threshold voltage and the holding voltage is less than the threshold voltage and greater than zero voltage.

13. The storage device according to claim 12, wherein, When the voltage applied to the storage cell is lower than the holding voltage, the switching element switches to the off state.

14. The storage device according to claim 13, wherein, The difference between the first voltage and the second voltage is less than the threshold voltage.

15. The storage device according to claim 12, wherein, The first voltage is equal to the second voltage.

16. The storage device according to claim 12, wherein, The first voltage is different from the second voltage.

17. The storage device according to claim 12, wherein, After the switching element is turned on, the control circuit continuously supplies the current to the switching element.

18. The storage device according to claim 12, wherein, When the detected current is higher than the reference level, the detection circuit determines that data with a first value is stored in the target storage unit, and when the detected current is lower than the reference level, the detection circuit determines that data with a second value is stored in the target storage unit.

19. The storage device according to claim 12, wherein, During a read operation on the target memory cell, a fixed voltage is applied to the second bit line and the second word line.

20. The storage device according to claim 19, wherein, The fixed voltage is equal to half of the first voltage.

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