Control method of controller, storage medium thereof, controller, and storage device

Abstract

A control method for error handling in a controller, a storage medium thereof, the controller, and a storage device. The controller is used in a first device capable of linking a second device in accordance with an interconnection protocol. The control method includes the steps of: processing, by the controller, first error information by sending a negative acknowledgement control message to the second device in accordance with the interconnection protocol, wherein the first error information indicates a first error that occurred when the controller performs data reception at a protocol layer in accordance with the interconnection protocol; and setting error handling state data to indicate that error handling is declared for the first error information, so that the controller does not handle a sequence number error that occurs after the first error until the error handling state data is set to indicate that the error handling is undecleared.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a control method for error handling in a controller, its storage medium, a controller, and a storage device. Background Technology

[0002] The amount of data generated and processed in today's mobile devices (such as smartphones, tablets, multimedia devices, wearable devices, and other computing devices) is constantly increasing. The chip-to-chip interconnect technology inside mobile devices or the interconnect interface technology affected by mobile devices needs to be further evolved in order to meet the goals of higher transmission speed, low power consumption, scalability, support for multiplexing, and ease of adoption.

[0003] To this end, the Mobile Industry Processor Interface (MIPI) Alliance has developed interconnect interface technologies that meet the above objectives, such as the MIPI M-PHY specification for the physical layer and the MIPI UniPro specification for the Unified Protocol (UniPro). On the other hand, the Joint Electron Device Engineering Council (JEDEC) has used the MIPI M-PHY specification and the MIPI UniPro specification to introduce the next-generation high-performance non-volatile memory standard, called Universal Flash Storage (UFS). UFS enables high-speed data transfer at the billion-bit-per-second level and low-power operation, and possesses the functionality and scalability required for high-end mobile systems, thus facilitating rapid industry adoption.

[0004] When engineers develop chips, electronic modules, or electronic devices based on these interconnect interface technologies, they must ensure that the product's functionality and operation comply with specifications. For example, a system implemented according to the UFS standard includes computing devices and non-volatile memory storage devices, with the computing device acting as the local host and the storage device as the remote device, respectively. A bidirectional link is established between the host and the device. According to the UniPro specification, error handling is required. When either the host or the device detects an error in the received data, the party that detected the error should proactively send a notification signal to the other party, triggering the other party to retransmit the data. Summary of the Invention

[0005] The embodiments provide a control technique for error handling of interconnect interfaces, wherein during the error handling process of the interconnect interface, error handling status information is set, and based on this error handling status information, delays caused by repeatedly sending notification signals indicating that an error has occurred are avoided, thereby helping to improve the performance of error handling of the interconnect interface. Various embodiments based on the control technique are proposed below, such as control methods for error handling in controllers, their storage media, controllers, and storage devices.

[0006] An implementation provides a control method for error handling in a controller, the controller being used in a first device capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: processing a first error message by sending a Negative Acknowledgment Control (NAC) message to the second device according to the interconnection protocol, wherein the first error message represents a first error that occurred when the controller performed data reception according to the protocol layer of the interconnection protocol; and setting error handling status data to indicate asserting error handling for the first error message, such that the controller will not handle sequence number errors occurring after the first error until the error handling status data is set to indicate deasserting the error handling.

[0007] In some embodiments of the control method, the method further includes: discarding second error information indicating a sequence number error based on the error handling status data indicating the declaration of the error handling, so that the controller will not send a negative response control message because of the second error information.

[0008] In some embodiments of the control method, the method further includes: when a data message resolving the first error is received, setting the error handling status data to indicate deassert of the error handling.

[0009] Another embodiment provides a storage medium that records program code for causing a storage device to execute at least one or a combination of the aforementioned control methods for error handling in a controller.

[0010] Another embodiment provides a controller for use in a first device capable of linking a second device according to an interconnection protocol. The controller includes an error handling module and an error suppression module. The error handling module is configured to process first error information by sending a negative acknowledgment control (NAC) message to the second device according to the interconnection protocol, wherein the first error information represents a first error that occurred when the controller performed data reception at the protocol layer of the interconnection protocol. The error suppression module is configured to set error handling status data to indicate assertion error handling for the first error information, such that the controller will not handle sequence number errors occurring after the first error until the error handling status data is set to indicate deassertification of the error handling.

[0011] In some embodiments, the error suppression module is further configured to discard second error information indicating a sequence number error based on the error handling status data indicating that the error handling has been declared, so that the controller will not send a negative response control message because of the second error information.

[0012] In some embodiments, the error suppression module is further configured to, upon receiving a data message resolving the first error, set the error handling status data to indicate a deassert of the error handling.

[0013] Another embodiment provides a storage device capable of linking to a host according to an interconnect protocol, the storage device comprising: non-volatile memory and a memory controller. The memory controller, coupled to the non-volatile memory, is configured to control data access to the non-volatile memory, wherein the memory controller is configured to perform a plurality of operations, the plurality of operations including: processing a first error message by sending a negative acknowledgement control (NAC) message to a second device according to the interconnect protocol, wherein the first error message indicates a first error occurring when the controller performs data reception according to the protocol layer of the interconnect protocol; and setting error handling state data to indicate asserting error handling for the first error message, such that the memory controller does not handle sequence number errors occurring after the first error until the error handling state data is set to indicate deasserting the error handling.

[0014] In some embodiments, the memory controller is configured to further perform: discarding a second error message indicating a sequence number error based on the error handling status data indicating that the error handling has been declared, so that the controller will not send a negative response control message because of the second error message.

[0015] In some embodiments, the memory controller is configured to further perform: upon receiving a data message resolving the first error, setting the error handling status data to indicate a deassert of the error handling.

[0016] In some embodiments, the protocol layer is a Universal Flash Memory Interconnect (UIC) layer.

[0017] In some embodiments, the first device is a storage device based on the Universal Flash Storage (UFS) standard.

[0018] In some embodiments, the first device is configured to communicate with the second device in an asymmetric power mode.

[0019] Therefore, the above provides various embodiments of a control technique for error handling of interconnect interfaces, such as a control method for error handling in a controller, its storage medium, controller, and storage device. The above-described control technique for error handling can reduce or avoid delays caused by repeatedly sending notification signals indicating an error occurring during the error handling process of the interconnect interface, thereby helping to improve the performance of error handling of the interconnect interface. Attached Figure Description

[0020] Figure 1 This is a schematic block diagram of a storage system in which an embodiment of the error handling control technology of the interconnect interface according to the present disclosure can be implemented;

[0021] Figure 2 Based on Figure 1 A schematic diagram of the multi-layered architecture of the storage system;

[0022] Figure 3 for Figure 2 A schematic diagram of the layered architecture of the UFS system;

[0023] Figure 4 This diagram illustrates error handling between the host and the UFS device during data transmission, showing a situation where errors are repeatedly notified.

[0024] Figure 5A A flowchart illustrating one implementation of a control method for error handling in a controller;

[0025] Figure 5B A flowchart illustrating one implementation of a control method for error handling in a controller;

[0026] Figure 5C A flowchart illustrating one implementation of a control method for error handling in a controller;

[0027] Figure 6 This is a schematic diagram of one implementation of a control method for error handling in a controller;

[0028] Figure 7 For implementation Figure 5A A schematic block diagram of one implementation of the controller for the control method; and

[0029] Figure 8 Based on Figure 7 The controller is implemented in the layered architecture of the UFS system.

[0030] Figure Labels

[0031] 1. Storage System

[0032] 2 UFS system

[0033] 10 mainframes

[0034] 11 Application Processors

[0035] 12. Host Buffer Memory

[0036] 13. Host Controller

[0037] 15 Host Interface

[0038] 20 Storage devices

[0039] 20A UFS device

[0040] 21 Memory Controller

[0041] 22 Internal Memory

[0042] 23 Controller

[0043] 24. Device buffer memory

[0044] 25 Device Interfaces

[0045] 29. Non-volatile memory (NVM)

[0046] 110 UFS Application Layer

[0047] 120 UFS Interconnect (UIC) Layer

[0048] 130 MIPI Unified Protocol (UniPro) Layer

[0049] 140 MIPI physical (M-PHY) layers

[0050] 141 Transmitter

[0051] 142 receiver

[0052] 150 Device Management Entities (DME)

[0053] 210 UFS Application Layer

[0054] 220 UFS Interconnect (UIC) Layer

[0055] 230 MIPI Unified Protocol (UniPro) Layer

[0056] 240 MIPI physical (M-PHY) layers

[0057] 241 Transmitter

[0058] 242 receiver

[0059] 250 Device Management Entities (DME)

[0060] 400-413 squares

[0061] 420-440 blocks

[0062] 500 waveform

[0063] 510 Error Handling Module

[0064] 520 Error Suppression Module

[0065] 521 Error handling status setting unit

[0066] 523 Suppressing serial number error unit

[0067] 600 controller

[0068] 610 Error Handling Module

[0069] 620 Error Suppression Module

[0070] 621 Error handling status setting unit

[0071] 623 Suppressing serial number error unit

[0072] Steps S10 to S40

[0073] AP Application

[0074] CLK clock line

[0075] DRV device driver

[0076] Din, Dout data cables

[0077] E1 First Error Message

[0078] E2 Second Error Message

[0079] ERR is the value of the error message entered.

[0080] G1 and G2 time interval

[0081] L1.5 PHY Connector Layer

[0082] L2 Data Link Layer

[0083] L3 network layer

[0084] L4 transport layer

[0085] nac_error_handling control flag

[0086] The value of the NEH control flag nac_error_handling

[0087] OS operating system

[0088] RST Reset Line

[0089] SL1 sub-link

[0090] SL2 sub-link

[0091] t1~t5, t5A time points Detailed Implementation

[0092] To fully understand the purpose, features and effects of the present invention, the present invention will be described in detail below with reference to the following specific embodiments and accompanying drawings.

[0093] The following provides various embodiments of control techniques for error handling of interconnect interfaces based on the present disclosure, such as control methods for error handling in controllers, their storage media, controllers, and storage devices.

[0094] To facilitate understanding of the purpose and function of the control technology, the following is provided: Figures 1-4 Examples will be used to illustrate the various application scenarios to which the control technology is applicable. First, a brief introduction... Figures 1-3 .like Figure 1 This illustration shows an embodiment of a storage system that can be used to implement control techniques for error handling of interconnect interfaces according to the present disclosure.Figure 2 It can be indicated that Figure 1 The storage system is implemented as a storage system conforming to the UFS standard, or simply a UFS system, which illustrates the multi-layered hierarchical architecture of the UFS system. Figure 3 for Figure 2 A schematic diagram of the multi-layered architecture of the UFS system.

[0095] The following is Figures 1-3 Examples are used to illustrate various application scenarios.

[0096] Please refer to Figure 1 This is a schematic block diagram of a storage system. Figure 1 A storage system is illustrated as an embodiment that can be used to implement the control technology described herein (which will be described in detail later). For example... Figure 1 As shown, the storage system 1 may include a host 10 and a storage device 20.

[0097] Host 10 may include application processor 11, host buffer memory 12, host controller 13, and host interface 15. Host 10 can run an operating system (OS) in host buffer memory 12 via application processor 11 and execute device driver (DRV) and various application programs (AP) on the OS. Host buffer memory 12 can be used as main memory or cache memory of host 10. Host buffer memory 12 can temporarily store data to be provided to storage device 20. Host buffer memory 12 can also be used as host memory for temporarily storing the OS, device driver (DRV), and application programs (AP). Host 10 can write data to storage device 20 or read data written to storage device 20. Application processor 11 executes application programs (AP) to send input / output requests for data transfer to storage device 20 or receive data from storage device 20 to device driver (DRV). Input / output requests may be, for example, read requests, write requests, or erase requests. Device driver (DRV) can translate input / output requests generated by application programs (AP) into requests defined in the protocol specification and can send the translated requests to host controller 13. The host controller 13 can control operations on the storage device 20 within the host 10. For example, when a write request is received from the device driver DRV, the host controller 13 can provide data stored in the host buffer memory 12 to the storage device 20 through the host interface 15. For example, when a read request is received from the device driver DRV, the host controller 13 can receive data from the storage device 20 through the host interface 15.

[0098] Host interface 15 can be coupled to device interface 25 via data lines Din and Dout for sending / receiving data, a reset line RST for sending a hardware reset signal, and a clock line CLK for sending data. Data lines Din and Dout can be implemented in multiple pairs, where a pair of data lines Din and Dout can be referred to as a lane. Host interface 15 can communicate with device interface 25 using at least one interface protocol, such as Mobile Industrial Processor Interface (MIPI), Universal Flash Storage (UFS), Small Computer System Interface (SCSI), or Serial Attached SCSI (SAS); however, the implementation of this disclosure is not limited to the examples described above.

[0099] Storage device 20 can write data to or provide data to be written to host 10 under the control of host 10. Storage device 20 can be implemented as a solid-state storage device (SSD), multimedia card (MMC), embedded MMC (eMMC), secure digital card (SD) card, or universal flash storage (UFS) device; however, the implementation of this disclosure is not limited to the above examples.

[0100] Storage device 20 may include a memory controller 21 and non-volatile memory (NVM) 29. The memory controller 21 controls the overall operation of storage device 20. The memory controller 21 may include internal memory 22, a controller 23, a device buffer memory 24, and a device interface 25. The internal memory 22 may store various types of information generated during the operation of the memory controller 21 or controller 23. The controller 23 controls write operations, read operations, or erase operations on the non-volatile memory 29. The controller 23 can exchange data with the non-volatile memory 29 or the device buffer memory 24 via an address bus or a data bus. The device buffer memory 24 can temporarily store data to be stored in or read from the non-volatile memory 29. The device buffer memory 24 may be implemented as either volatile memory or non-volatile memory. Device interface 25 can communicate with host interface 15 using at least one interface protocol, such as Mobile Industrial Processor Interface (MIPI), Universal Flash Storage (UFS), Small Computer System Interface (SCSI), or Serial Attached SCSI (SAS); however, the implementation of this disclosure is not limited to the examples described above. Non-volatile memory 29 can perform data write operations, data read operations, or data erase operations under the control of controller 23. Non-volatile memory 29 may, for example, comprise one or more memory chips.

[0101] Please refer to Figure 2 Based on Figure 1 A schematic diagram of the multi-layered architecture of the storage system. Figure 2 It can be indicated thatFigure 1 Storage system 1 is implemented as a UFS-compliant storage system, or simply UFS system 2, illustrating a multi-tiered architecture of the UFS system. Admittedly, the implementation of this disclosure is not limited to this example and can be applied, where appropriate, to various storage systems with multi-tiered structures. Figure 2 Individual layers can be implemented as hardware, firmware, or software, depending on the circumstances.

[0102] Please refer to Figure 2 UFS system 2 may include host 10 and UFS device 20A. For example, UFS device 20A may utilize, Figure 1 This is achieved through storage device 20.

[0103] Host 10 includes a UFS application layer 110 and a UFS interconnect (UIC) layer 120. The UFS interconnect (UIC) layer 120 includes a MIPI UniPro layer (hereinafter referred to as the UniPro layer) 130 and a MIPI M-PHY layer (hereinafter referred to as the M-PHY layer) 140. The device management entity (DME) 150 is defined to be able to interoperate with the UFS application layer 110, the UniPro layer 130 and the M-PHY layer 140, thereby realizing functions involving the overall UniPro protocol, such as power-on, power-off, reset, power mode change and other control or configuration functions.

[0104] Similarly, UFS device 20A includes a UFS application layer 210 and a UFS interconnect layer 220. The UFS interconnect layer 220 includes a UniPro layer 230 and an M-PHY layer 240. UFS device 20A also defines a corresponding Device Management Entity (DME) 250.

[0105] Each layer of host 10 can perform the same or similar operations as each layer of UFS device 20A.

[0106] The UFS application layer 110 (or 210) can run various types of modules required to operate the host 10 (or UFS device 20A). For example, the UFS application layer 110 may include a UFS command set (UCS) layer, and the UCS layer can manage commands used by the application AP, operating system OS, or driver DRV from the host 10 to issue instructions to the UFS interconnect layer 120 for reading, writing, or erasing data on the UFS device 20A. Corresponding to the host 10, the UFS application layer 110 is composed of, for example... Figure 1The controller 23 in the storage device 20 implements the UFS application layer 210 of the UFS device 20A, and performs read, write or erase operations on the non-volatile memory 29 after receiving instructions from the UFS application layer 110 of the host 10.

[0107] Device Management Entity (DME) 150 (or 250) can be used to control or manage UFS Interconnect (UIC) Layer 120 (or 220).

[0108] The UFS interconnect layer 120 (or 220) can provide services to the UFS application layer 110 (or 210) above it. For example, the UFS interconnect layer 120 (or 220) can generate UFS protocol information units (UPIUs), which are data packets used to send / receive data or requests, or can release received UPIUs.

[0109] The M-PHY layer 140 (or 240) can convert information received from the upper UniPro layer 130 (or 230) according to a predetermined protocol, and can send the converted information to the UFS device 20A (or host 10). Furthermore, the M-PHY layer 140 (or 240) can convert information received from the UFS device 20A (or host 10) according to a predetermined protocol, and can send the converted information to the upper UniPro layer 130 (or 230).

[0110] In one embodiment, both the UFS application layer 210 and the UFS interconnect layer 220 can be implemented using firmware or hardware, and can be executed or implemented by the controller 23, as referenced above. Figure 1 Or as described in 2.

[0111] Please refer to Figure 3 , it is Figure 2 A schematic diagram of the layered architecture of the UFS system. Figure 3 The following explanation uses the case where UniPro layer 130 consists of four layers as an example. The individual layers in UniPro layer 230 of UFS device 20A can be operated and implemented similarly.

[0112] like Figure 3 As shown, UniPro layer 130 (or 230) may include PHY adapter layer L1.5, data link layer L2, network layer L3 and transport layer L4.

[0113] The PHY adapter layer L1.5 couples the M-PHY layer (140 or 240) to the data link layer L2. The PHY adapter layer L1.5 can perform bandwidth control, power management, etc., between the M-PHY layer and the data link layer L2. In implementation, the M-PHY layer 140 of the host 10 includes a transmitter 141 and a receiver 142, and the M-PHY layer 240 of the UFS device 20A includes a transmitter 241 and a receiver 242, thereby enabling full-duplex communication.

[0114] The data link layer L2 can perform flow control for data transmission between host 10 and UFS device 20A. That is, data link layer L2 can monitor data transmission or control the data transmission rate. Furthermore, data link layer L2 can perform error control based on cyclic redundancy check (CRC). Data link layer L2 can generate frames using packets received from network layer L3, or it can generate packets using frames received from PHY adapter layer L1.5.

[0115] Network layer L3 is used for routing functions to select transmission paths for packets received from transport layer L4.

[0116] Transport layer L4 can use commands received from UFS application layer 110 (or 210) to configure data segments suitable for the protocol and send the data segments to network layer L3, or it can extract commands from packets received from network layer L3 and send the commands to UFS application layer 110 (or 210). Transport layer L4 can use sequence-based error control schemes to ensure the validity of data transmission.

[0117] When engineers develop chips, electronic modules, or electronic devices based on interconnect interface technologies such as the UFS standard, they must ensure that the product's functionality and operation comply with specifications. For example, a system implemented according to the UFS standard might include a storage device that includes computing devices and non-volatile memory (as mentioned above). Figure 2The system consists of a host (10) and a UFS device (20A), which act as the local host and the remote device, respectively. A bidirectional link is established between the host (10) and the UFS device (20A). According to the UniPro specification, both the host (10) and the UFS device (20A) need to implement error handling mechanisms, such as frame error handling at the data link layer (L2). Specifically, when either the host or the UFS device (20A) sends a data frame, a timer is started to check if a response is received within a predetermined time; otherwise, error handling is performed. When either the host or the UFS device (20A) receives a data frame, it checks whether the data frame is correct or incorrect. If the data frame is correct, a control frame, such as an Acknowledgment and Flow Control (AFC) frame, is sent to the originating end as a notification signal. When a data frame contains an error, a control frame, such as a Negative Acknowledgment Control (NAC) frame, is sent to the initiating end as a notification signal. Upon receiving the NAC frame, the initiating end triggers a retransmission mechanism, i.e., a replay mechanism. For example, the initiating end might first send AFC1 and AFC0 frames, and then continue transmitting (i.e., continue transmitting) the data frame.

[0118] In a UFS system, UFS transmitters and receivers are allowed to operate in asymmetric power mode (or asymmetric speed). Please refer to [further details needed]. Figure 3 In this scenario, the operating speed of a host transmitter (such as transmitter 141 of host 10) connected to a device receiver (such as receiver 242 of UFS device 20A) may be faster than the operating speed of a device transmitter (such as transmitter 241 of UFS device 20A) connected to a host receiver (such as receiver 142 of host 10). Assume that the sub-link from the host transmitter to the device receiver operates in fast mode, while the sub-link from the device transmitter to the host receiver operates in slow mode, and both sub-links are sending data to each other.

[0119] The inventors discovered that when implementing error handling for the host 10 and UFS device 20A according to the UniPro specification, if the host 10 and UFS device 20A operate in an asymmetric power mode (or asymmetric speed), a situation of continuously repeating error notifications may occur. Please refer to... Figure 4 This is a schematic diagram illustrating error handling between host 10 and UFS device 20A during data transmission. For ease of explanation,Figure 4 The following is a simplified illustration of potential scenarios during data transfer between host 10 and UFS device 20A, based on the UniPro specifications (such as versions 1.4 and 1.8) adopted according to the UFS standard. For example, in... Figure 4 The two squares on the far left represent host 10 and UFS device 20A, respectively. Please refer to... Figure 3 and Figure 4 In this example, host 10 and UFS device 20A are configured to operate in an asymmetric power mode (or asymmetric speed), such that sublink SL1 from transmitter 141 of host 10 to receiver 242 of UFS device 20A operates in fast mode, while sublink SL2 from transmitter 241 of UFS device 20A to receiver 142 of host 10 operates in slow mode. Figure 4 The series of squares 400-413 to the right of host 10 represent the frames sent by host 10 to UFS device 20A via sublink SL1 over time; Figure 4 The series of squares 420-440 to the right of UFS device 20A represent the frames sent by UFS device 20A to host 10 via sublink SL2 over time. Also... Figure 4 The frames shown in the data transmission from UFS device 20A to host 10 via sublink SL2 are helpful in illustrating the situation, such as notification signals sent by UFS device 20A to host 10 (e.g., AFC or NAC frames). Other frames are temporarily ignored as they do not affect understanding. Furthermore, Figure 4 The schematic diagrams showing the frames received by host 10 and UFS device 20A are omitted. Those skilled in the art will understand this invention based on UniPro specifications (such as versions 1.4 and 1.8). Figure 4 The significance of.

[0120] like Figure 4 As shown, at time point t1, host 10 begins sending data link (DL) frames. For example, if the frames start from sequence number 0, then... Figure 4 In this context, square 400 represents "Frame #0". Then, UFS device 20A receives "Frame #0" and, after checking (e.g., based on Cyclic Redundancy Check (CRC) or other suitable criteria), determines that "Frame #0" is correct. Therefore, it sends an AFC frame to host 10. This AFC frame carries the sequence number "#0" of the corresponding frame. Figure 4 The square 420 in the middle represents the AFC frame "AFC#0".

[0121] At time t2, for some reason, frame #1 (as shown in box 401) is corrupted (indicated by a cross symbol below box 401), causing UFS device 20A to encounter a Protocol Data Unit (PDU) error. Afterwards, UFS device 20A begins transmitting NAC frames, such as the NAC frame indicated by box 430, for error handling. Meanwhile, host 10 continues to send multiple frames due to the faster sublink SL1. Because UFS device 20A is performing error handling, frames #2 through #6 (as shown in boxes 402-406) are discarded by UFS device 20A.

[0122] At time t3, host 10 receives the first NAC frame from UFS device 20A and stops sending frames at an appropriate cutpoint. In this case, host 10 stops sending frames after sending "frame #7" (as shown in block 408). After a random time interval (gap) (as shown by arrow G1), host 10 replays the frames, as shown in blocks 410-413, starting transmission from "frame #1" (as shown in block 401) after the "AFC#" frame (as mentioned in the AFC1 and AFC0 frames).

[0123] For the UFS device 20A, the transmission corresponding to the NAC frame is completed after receiving a good AFC frame.

[0124] At time t4, UFS device 20A expects to receive "Frame #1". However, host 10 has already sent "Frame #7", so receiving "Frame #7" will cause a frame "sequence number error" and trigger the transmission of another NAC frame. Similarly, because error handling is in progress, "Frame #1" and "Frame #2" (as shown in blocks 412-412) will be discarded by UFS device 20A.

[0125] At time t5, host 10 receives the second NAC from UFS device 20A and stops sending frames at the appropriate cutoff point. At this time, host 10 stops sending frames after sending "Frame #3" (as illustrated in block 413). When the receiver of UFS device 20A receives "Frame #3", it will cause a sequence number error and trigger the transmission of another NAC frame and another error handling.

[0126] The aforementioned NAC frames and error handling therefore occur repeatedly. Since the time interval for host 10 to replay frames may be random, eventually, the time interval of host 10 and the NAC frame transmission of UFS device 20A may overlap, and both host 10 and UFS device 20A can complete error handling in the manner defined in the specification. However, it takes a considerable amount of latency for host 10 and UFS device 20A to reach the state of completed error handling. In the worst case, this situation will continue until the data link (DL) protection timer expires.

[0127] Therefore, to avoid the situation where the host 10 and UFS device 20A repeatedly send notification signals (such as NAC frames) indicating the occurrence of errors when operating in asymmetric power mode (or asymmetric speed), and to reduce the delay time caused by repeated error handling, a control technique for error handling of interconnect interfaces is proposed. This control technique, based on error handling of an interconnect interface (such as an implementation of error handling in the UniPro specification), further sets additional information not disclosed in the specification of the interconnect interface (such as the UniPro specification), which can be called "error handling status information," to indicate the states of "negative acknowledgment" and "error handling," and avoids repeatedly sending notification signals (such as NAC frames) indicating the occurrence of errors based on this error handling status information. Various implementations of this control technique are proposed below, such as the following control method for error handling in a controller.

[0128] Please refer to Figure 5A This is a flowchart illustrating one implementation of a control method for error handling in a controller. The controller is used in a first device capable of linking a second device according to an interconnect protocol (such as the UFS standard). Taking the UFS standard as an example, the controller can refer to the host controller 13 of host 10 or the memory controller 21 of storage device 20, thereby achieving... Figure 2 The UFS system. The control method includes the following steps:

[0129] As shown in step S10, the controller sends a negative acknowledgment control (NAC) message to the second device in accordance with the interconnection protocol to process the first error information, wherein the first error information indicates a first error that occurred when the controller performed data reception in accordance with the protocol layer of the interconnection protocol.

[0130] As shown in step S20, the controller sets error handling status data to indicate that the first error information assert error handling is performed, so that the controller will not handle sequence number errors that occur after the first error until the error handling status data is set to indicate that the error handling is deasserted.

[0131] like Figure 5B As shown, in some embodiments of the control method, the method further includes: as shown in step S30, discarding second error information indicating a sequence number error based on the error handling status data indicating the declaration of the error handling, so that the controller will not send an NAC message due to the second error information.

[0132] like Figure 5C As shown, in some embodiments of the control method, the method further includes: as shown in step S40, when a data message resolving the first error is received, setting the error handling status data to indicate the cancellation of the error handling declaration.

[0133] For example, in step S20, the error handling status information can be implemented using a control flag, any suitable data structure, or an electrical signal. In the following examples and related diagrams, the error handling status information is illustrated using the control flag and the symbol nac_error_handling.

[0134] According to an example of step S20, whenever either host 10 or UFS device 20A encounters a new error (referred to as the first error), the party that detected the error (e.g., UFS device 20A) sets the control flag nac_error_handling to a first value (e.g., logic 1, other values, or data) to indicate that "negative acknowledgment" and "error handling" are in effect. The party that detected the error (e.g., UFS device 20A) keeps the control flag nac_error_handling at the first value until the party that detected the error (e.g., UFS device 20A) receives a good frame, at which point the control flag nac_error_handling is set to a second value (e.g., logic 0, other values, or data) to indicate that "negative acknowledgment" and "error handling" are not in effect. The good frame, for example, is a Data Link (DL) Traffic Class (TC) frame, where the DL TC frame indicates that the sequence number of the frame is as expected, i.e., a data message that can resolve the error. When the control flag nac_error_handling represents "negative acknowledgment" and "error handling", the party that detects the error (such as UFS device 20A) will no longer transmit additional NAC frames.

[0135] like Figure 6 The diagram shown is an application example of a control method used for error handling in a controller. Figure 6 In the middle, host 10 and UFS device 20A and Figure 4 Similarly, operating in an asymmetric power mode (or asymmetric speed), the frames sent by host 10 are shown in blocks 400-413, which are... Figure 4 The same as shown. Figure 6 and Figure 4 The difference lies in, Figure 6 In this context, host 10 and UFS device 20A implement the following: Figure 5A Control methods.

[0136] like Figure 6 As shown, at time point t1, host 10 begins sending DL frames. For example, the frames start from sequence number 0, therefore... Figure 6 The square 400 represents "frame #0".

[0137] At time t2, for some reason, “Frame #1” (as shown in square 401) is corrupted (as indicated by the cross symbol below square 401), causing the UFS device 20A to encounter a Protocol Data Unit (PDU) error.

[0138] Afterwards, based on Figure 5AIn step S10, the UFS device 20A begins transmitting NAC frames, such as the NAC frame represented by block 430, for error handling. According to... Figure 5A In step S20, the UFS device 20A (e.g., UIC layer 230) declares the control flag nac_error_handling (e.g., set to logic 1), as... Figure 6 The waveform 500 shown below represents a change in the control flag `nac_error_handling`, from logic 0 to logic 1. After this, UFS device 20A (such as UniPro layer 130) ignores sequence number errors based on the asserted control flag `nac_error_handling`, thus suppressing subsequent sequence number errors. Meanwhile, host 10 continues to send multiple frames due to the faster sublink SL1. Because UFS device 20A is performing error handling, frames "#2" through "#6" (as shown in blocks 402-406) will be discarded by UFS device 20A.

[0139] At time t3, host 10 receives the first NAC frame from UFS device 20A and stops sending frames at an appropriate cutoff point. In this case, host 10 stops sending frames after sending "frame #7" (as shown in block 408). After a random time interval (as shown by arrow G2), host 10 replays the frames, as shown in blocks 410-413, starting transmission from "frame #1" (as shown in block 401) after the "AFC#" frame (as mentioned in the AFC1 and AFC0 frames).

[0140] For the UFS device 20A, the transmission corresponding to the NAC frame is completed after receiving a good AFC frame.

[0141] At time t4, UFS device 20A expects to receive "frame #1". Before the current error handling, the last frame UFS device 20A received was "frame #0". If UFS device 20A can receive "frame #1" sent by host 10 due to replay, it means that the correct frame has been received, thus resolving the current error. Therefore, UFS device 20A expects to receive "frame #1".

[0142] Even if host 10 sends "frame #7", UFS device 20A will encounter a "sequence number error" after receiving "frame #7", but because UFS device 20A relies on... Figure 5A Step S20 is implemented to suppress sequence number errors based on the declared control flag nac_error_handling, so that in this case, the sequence number error does not lead to the transmission of another NAC frame. For example, UFS device 20 can, based on Figure 5BStep S20 is implemented by discarding error messages indicating sequence number errors based on the declared control flag nac_error_handling.

[0143] At time t5A, host 10 replays the sent frames, starting with sequence number #1, such as "frame #1", "frame #2", "frame #3", etc. UFS device 20A can correctly receive these frames. After receiving "frame #1", UFS device 20A recognizes it as the expected frame, thus resolving the current error. Therefore, based on... Figure 5C In step S40, the control flag nac_error_handling is set to indicate that the error handling has been deasserted, such as... Figure 6 The waveform 500 shown below indicates a change in the control flag nac_error_handling, from logic 1 to logic 0.

[0144] As mentioned above, using based Figure 5A The control method shown does not involve additional NAC frame transmissions and facilitates error handling within the expected latency, thereby helping to improve the error handling performance of the interconnect interface.

[0145] Based on the aforementioned control method for error handling in a controller, a further controller can be implemented, wherein the controller is used in a first device capable of linking a second device according to an interconnection protocol (such as the UFS standard). Taking the UFS standard as an example, the controller can refer to... Figure 1 The host controller 13 of the host 10 or the memory controller 21 of the storage device 20, thereby realizing Figure 2 The UFS system.

[0146] like Figure 7 As shown, let's take Figure 2 The UFS system is shown in the figure. The controller 600 of the UFS device 20A includes an error handling module 610 and an error suppression module 620. The controller 600 can utilize... Figure 1 This is implemented using memory controller 21 or controller 23.

[0147] Error handling module 610 is configured to process first error information by sending a negative acknowledgment control (NAC) message to the second device (e.g., host 10) in accordance with the interconnection protocol, wherein the first error information indicates a first error that occurred when the controller performed data reception in accordance with the protocol layer of the interconnection protocol.

[0148] Error suppression module 620 is configured to set error handling status data to indicate that error handling is declared for the first error information, such that the controller will not process sequence number errors that occur after the first error until the error handling status data is set to indicate that the error handling is declaring.

[0149] The above Figure 7 The implementation method can also be used to achieve the above-described Figures 5A-5C Or related examples. Correspondingly, the host controller 13 of host 10 can also be based on... Figure 7 And thus achieve the corresponding effect.

[0150] Please refer to Figure 8 Based on Figure 7 The controller is implemented in the layered architecture of the UFS system. (See diagram.) Figure 8 As shown, the aforementioned implementation is carried out in the UFS device 20A (or host 10) according to the UniPro specification. Figure 5A The control method shown.

[0151] For example, in the controller (such as memory controller 21 or controller 23) of UFS device 20A, the error handling module 610 is implemented based on the data link layer L2 in UniPro layer 230 to handle error messages and perform NAC transmission control, and further implements the error suppression module 620.

[0152] Error handling module 610 processes first error information E1 by sending a negative acknowledgment control (NAC) message to the host in accordance with the interconnection protocol, wherein the first error information E1 indicates a first error that occurred when the controller performed data reception in accordance with the protocol layer of the interconnection protocol.

[0153] For example, the error suppression module 620 may further include an error handling state setting unit 621 and a suppression sequence number error unit 623.

[0154] Error handling state setting unit 621 is configured to set error handling state data (such as the declaration control flag nac_error_handling) to indicate that error handling is declared for the first error information E1, so that the controller (such as memory controller 21 or controller 23) will not process the first error (such as... Figure 6 The sequence number error occurs after the Protocol Data Unit (PDU) error shown in the diagram. The error handling state setting unit 621 is configured to, when the controller receives a data message resolving the first error (such as...), Figure 6When the expected frame (#1) is shown in the diagram, the error handling status data is set to indicate that the error handling is declaring (e.g., declaring the control flag nac_error_handling).

[0155] The sequence number error suppression unit 623 is configured to discard the second error message E2 indicating a sequence number error based on the error handling status data indicating the declaration of the error handling, so that the controller will not send an NAC message due to the second error message E2. Figure 8As shown, the sequence number error suppression unit 623 can be implemented to "discard" the second error information E2, which indicates a sequence number error, based on an operation of the input error information (second error information E2) and the error handling status data (control flag nac_error_handling). For example, it can be based on a logical AND operation, such as ERR·NEH', where ERR represents the value (e.g., a logical value) of the input error information (e.g., second error information E2), and ERR is 1 when the input error information is a sequence number error, otherwise ERR is 0; NEH represents the value (e.g., a logical value) of the control flag nac_error_handling, and NEH is 1 when it is declared, otherwise NEH is 0 (note that in another example, the control flag nac_error_handling can also be set to 0 to indicate declaration, and set to 1 to indicate dedeclaration). Therefore, the sequence number error suppression unit 623 can be implemented by performing an operation on ERR·NEH' based on the input error information (second error information E2) and the error handling status data (declared control flag nac_error_handling) to obtain a logic 0 result. Based on this result, the sequence number error suppression unit 623 can set the input error information (such as second error information E2) as invalid to discard the second error information E2, thereby preventing the second error information E2 from being input to the error suppression module 620, thus suppressing the second error information E2. Conversely, when the control flag nac_error_handling is declaring, the operation on ERR·NEH' yields a logic 1 result. Based on this result, the sequence number error suppression unit 623 can set the input error information (such as second error information E2) as valid, thereby allowing the second error information E2 to be input to the error suppression module 620. The error suppression module 620 then processes the second error information E2 according to an interconnection protocol (such as the UFS standard) and transmits the NAC message. Furthermore, in some examples, the sequence number error suppression unit 623 can also be implemented as other logical operations to achieve a similar effect, such as (ERR'+NEH)', or other suitable logical operations such as AND, OR, NOT, NAND, NOR, XOR, or XNOR, or combinations thereof. Therefore, the implementation of the sequence number error suppression unit 623 is not limited to the above examples.

[0156] Correspondingly, in the controller of host 10 (such as host controller 11), the error handling module 510, based on the data link layer L2 implementation in UniPro layer 130, is used to process error messages and perform NAC transmission control, and further implements an error suppression module 520 to achieve the function of the corresponding module in the aforementioned UFS device 20A. For example, the error suppression module 520 may further include an error handling status setting unit 521 and a suppression sequence number error unit 523 to achieve the function of the corresponding unit in the aforementioned UFS device 20A.

[0157] In some embodiments, a storage device (e.g., 20, 20A) is provided, capable of being linked to a host according to an interconnect protocol. The storage device includes: non-volatile memory (e.g., 29) and a memory controller (e.g., 21). The memory controller, coupled to the non-volatile memory, is used to control data access to the non-volatile memory. The memory controller is configured to perform a plurality of operations, including operations corresponding to... Figure 5A The operation of steps S10 to S20 in the control method. In some embodiments, the storage device can also be configured or programmed to implement the above-mentioned control method. Figure 5A The method can be implemented as at least one or a combination thereof in several embodiments. The storage device can be implemented as a solid-state storage device (SSD), universal flash memory (UFS), embedded multimedia card (eMMC), or any other suitable storage device or storage-based product.

[0158] Furthermore, in the above embodiments regarding host and storage devices (such as...) Figure 1 , 2 In the diagrams, embodiments, or related figures, at least one or a combination of the host controller 13, memory controller 21 (or controller 23), UIC layer (or PHY adapter layer L1.5, data link layer L2, network layer L3, and transport layer L4), and MIPI physical layer, can be implemented using one or more circuits, such as microcontrollers, processors, or digital signal processors. Alternatively, they can be designed using techniques based on hardware description languages ​​(HDLs) or any other design method for digital circuits familiar to those skilled in the art, and can be implemented using one or more circuits such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or complex programmable logic devices (CPLDs), or can be implemented using dedicated circuits or modules. However, the implementation of the present invention is not limited to these examples. Furthermore, the foregoing... Figure 5A Steps S10 to S20Figures 5B-5C ,or Figure 8 The examples shown can also be implemented using hardware circuits, such as logic circuits or other suitable digital circuits.

[0159] Furthermore, in some embodiments, a non-transitory storage medium is proposed, which records data for use by computing devices (as described above). Figure 1 Or the storage device shown in Figure 2), by means of a memory controller (or controller) in the storage device, executes program code for a control method for error handling in the controller, wherein the method includes according to Figure 5A Any embodiment of the method or a combination thereof. For example, program code is one or more programs or program modules, such as those used to implement the method. Figures 5B-5C Steps S10 to S20 Figure 8 ,or Figure 5A The example shown illustrates that the code for these modules is cooperative and can be executed in any suitable order or in parallel. When the computing device executes this code, it causes the computing device to perform operations based on... ​ An embodiment of a control method for error handling in a controller. The readable storage medium described above is, for example, firmware, ROM, RAM, memory card, optical information storage medium, magnetic information storage medium, or any other type of storage medium or memory, and the implementation of the present invention is not limited to this example.

[0160] Therefore, the above embodiments provide a control technology for error handling of interconnect interfaces. Various implementations are proposed based on this control technology, such as a control method for error handling in a controller, its storage medium, a controller, and a storage device. In the error handling process of the interconnect interface, error handling status information is set, and this error handling status information is used to avoid delays caused by repeatedly sending notification signals indicating that an error has occurred, thereby helping to improve the performance of error handling of the interconnect interface.

[0161] The present invention has been disclosed above with reference to preferred embodiments. However, those skilled in the art should understand that the embodiments are merely illustrative and should not be construed as limiting the scope of the invention. It should be noted that all variations and substitutions equivalent to the described embodiments should be considered within the scope of the present invention. Therefore, the scope of protection of the present invention is defined by the claims.

Claims

1. A control method for error handling in a controller, characterized in that, The controller is used in a first device capable of linking a second device according to an interconnection protocol, and the control method includes: The first error information is processed by sending a negative acknowledgment control (NAC) message to the second device according to the interconnection protocol, wherein the first error information indicates a first error that occurred when the controller performed data reception according to the protocol layer of the interconnection protocol; and Error handling status data is set to indicate that error handling is declared for the first error information, such that the controller will not handle sequence number errors that occur after the first error until the error handling status data is set to indicate that the error handling is declaring.

2. The control method according to claim 1, characterized in that, The method further includes: Based on the error handling status data indicating the declaration of the error handling, the second error information indicating an incorrect sequence number is discarded so that the controller will not send a negative response control message due to the second error information.

3. The control method according to claim 1, characterized in that, The method further includes: When a data message resolving the first error is received, the error handling status data is set to indicate that the error handling has been lifted.

4. The control method according to claim 1, characterized in that, The protocol layer is the Universal Flash Interconnect (UIC) layer.

5. The control method according to claim 1, characterized in that, The first device is a storage device based on the Universal Flash Storage (UFS) standard.

6. The control method according to claim 5, characterized in that, The first device is configured to communicate with the second device in an asymmetric power mode.

7. A storage medium, characterized in that, The storage medium records program code for causing the storage device to execute the control method for error handling in a controller according to any one of claims 1 to 6.

8. A controller for use in a first device capable of linking a second device according to an interconnection protocol, characterized in that, The controller includes: An error handling module is configured to process first error information by sending a negative acknowledgment control (NAC) message to the second device according to the interconnection protocol, wherein the first error information indicates a first error that occurred when the controller performed data reception according to the protocol layer of the interconnection protocol; and An error suppression module is configured to set error handling status data to indicate that error handling is declared for the first error information, such that the controller will not process sequence number errors that occur after the first error until the error handling status data is set to indicate that the error handling is declaring.

9. The controller according to claim 8, characterized in that, The error suppression module is further configured to discard second error information indicating a sequence number error based on the error handling status data indicating the declaration of the error handling, so that the controller will not send a negative response control message because of the second error information.

10. The controller according to claim 8, characterized in that, The error suppression module is further configured to, when receiving a data message resolving the first error, set the error handling status data to indicate the cancellation of the error handling declaration.

11. The controller according to claim 8, characterized in that, The protocol layer is the Universal Flash Interconnect (UIC) layer.

12. The controller according to claim 8, characterized in that, The first device is a storage device based on the Universal Flash Storage (UFS) standard.

13. The controller according to claim 12, characterized in that, The first device is configured to communicate with the second device in an asymmetric power mode.

14. A storage device capable of connecting to a host according to an interconnection protocol, characterized in that, The storage device includes: Non-volatile memory; and A memory controller, coupled to the non-volatile memory, is configured to control data access to the non-volatile memory, wherein the memory controller is configured to perform a plurality of operations, the plurality of operations including: The first error information is processed by sending a negative acknowledgment control (NAC) message to the second device in accordance with the interconnect protocol, wherein the first error information indicates a first error that occurred when the memory controller performed data reception in accordance with a protocol layer of the interconnect protocol; and Error handling status data is set to indicate that error handling is declared for the first error information, such that the memory controller will not process sequence number errors that occur after the first error until the error handling status data is set to indicate that the error handling is declaring.

15. The storage device according to claim 14, characterized in that, The memory controller is configured to perform further actions: Based on the error handling status data indicating the declaration of the error handling, the second error information indicating an incorrect sequence number is discarded so that the memory controller will not send a negative response control message due to the second error information.

16. The storage device according to claim 14, characterized in that, The memory controller is configured to perform further actions: When a data message resolving the first error is received, the error handling status data is set to indicate that the error handling has been lifted.

17. The storage device according to claim 14, characterized in that, The protocol layer is the Universal Flash Memory Interconnect (UIC) layer.

18. The storage device according to claim 14, characterized in that, The storage device conforms to the Universal Flash Storage (UFS) standard.

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