A high-voltage LDMOS device structure resistant to single event burnout

Abstract

The application provides a high-voltage LDMOS device structure resistant to single event effect, which comprises a P-type substrate, a buried oxygen layer, a gate oxide layer, a slot oxide layer, a field oxide layer, an N-type epitaxial layer, a P-type well region, a P-type buried layer region, a source region P+ implantation, a slot bottom P+ implantation, an N-type well region, a source region N+ implantation, a drain region N+ implantation, polycrystalline silicon, metal and a dielectric slot. The application introduces a new electrode under the P-type well region, provides an additional leakage path for the hole current generated by single particle radiation, and avoids the opening of the internal parasitic transistor of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of semiconductor power devices, and particularly relates to a high-voltage LDMOS device structure resistant to single-event burnout. BACKGROUND

[0002] With the increasingly wide application of power semiconductor devices in electronic systems of aerospace and the like, anti-radiation reinforcement technology for power management systems and gate drive circuits has become the research focus of various companies and colleges and universities. As a core part of analog circuits, the high-voltage LDMOS device is prone to single-event burnout in a space radiation environment, which causes the device to fail and the entire circuit to fail to work normally. Therefore, it is necessary to study a high-voltage LDMOS device resistant to single-event burnout. SUMMARY

[0003] To solve the problem of single-event burnout of the high-voltage LDMOS device and inhibit the opening of the parasitic transistor, the application provides a high-voltage LDMOS device structure resistant to single-event burnout. In a space environment, high-energy particles will be incident into the LDMOS device, and a large number of electron-hole pairs are generated along the incident path through energy deposition. Under the action of an electric field, the electrons and holes move to the drain and source, respectively, to form a transient current. Part of the holes flow into the P well (parasitic transistor base region) and then flow out from the body electrode P+. The hole current generates a voltage drop in the base region, so that the P well / N+ junction (base region / emission junction) is positively biased, and the parasitic transistor is turned on. The electrons from the source N+ enter the drift region through the P well, which causes the device to have Kirk effect ionization of more electron-hole pairs. The holes move to the source under the action of an electric field to provide stable positive feedback current for the base region, and finally cause the device to burn out. The application reduces the hole current flowing through the P-type well region (parasitic transistor base region) to avoid the opening of the parasitic transistor, and effectively improves the ability of the high-voltage LDMOS device to resist single-event burnout.

[0004] To achieve the above-mentioned application purposes, the technical scheme of the application is as follows:

[0005] A high-voltage LDMOS device structure against single event burnout, comprising a first-conductivity-type substrate 8 at the bottom, a buried oxide layer 7 above the first-conductivity-type substrate 8, a second-conductivity-type drift region 5 above the buried oxide layer 7, a second-conductivity-type well region 4 above the right upper part of the second-conductivity-type drift region 5, a second-conductivity-type source region 2 inside the right upper part of the second-conductivity-type well region 4, a first-conductivity-type well region 3 above the left upper part of the second-conductivity-type drift region 5, a second-conductivity-type source region 2 inside the first-conductivity-type well region 3, and a first-conductivity-type body region 1, a slot oxide layer 15 left of the first-conductivity-type well region 3 and a dielectric slot 14 inside the slot oxide layer 15, the first-conductivity-type body region 1 below the dielectric slot 14, and a first-conductivity-type buried layer region 6 below the first-conductivity-type body region 1, a polysilicon gate electrode 12 above the gate oxide layer 9 and the field oxide layer 10, a source electrode 11 above the first-conductivity-type well region 3 and the dielectric slot 14, and a drain electrode 13 above the second-conductivity-type source region 2 inside the right upper part of the second-conductivity-type well region 4.

[0006] As a preferred mode, the first-conductivity-type body region 1 at the bottom of the dielectric slot 14 is completely surrounded by the first-conductivity-type buried layer region 6.

[0007] As a preferred mode, the side of the slot oxide layer 15 is tangent to the first-conductivity-type well region 3, and the dielectric slot 14 is short-circuited to the source electrode 11, thereby providing the first-conductivity-type body region 1 at the bottom of the dielectric slot 14 and the first-conductivity-type buried layer region 6 with an equal potential to the source electrode, and providing a discharge path for the extraction of ionized charges.

[0008] As a preferred mode, a dielectric slot 14 equal in width to the active region is provided along the width direction of the current flow.

[0009] As a preferred mode, a plurality of dielectric slots 14 are provided along the width direction of the current flow, and the adjacent dielectric slots 14 are filled with slot oxide layers 15.

[0010] As a preferred mode, the bottom of the first-conductivity-type buried layer region 6 is tangent to or higher than the buried oxide layer 7.

[0011] As a preferred mode, the material of the dielectric slot 14 is polysilicon or metal.

[0012] As a preferred mode, when the first-conductivity-type doping impurities are acceptor-type and the second-conductivity-type doping impurities are donor-type, the drain electrode is biased at a positive potential relative to the source electrode; when the first-conductivity-type doping impurities are donor-type and the second-conductivity-type doping impurities are acceptor-type, the drain electrode is biased at a negative potential relative to the source electrode.

[0013] The beneficial effect of the present application is that the present application provides a high-voltage LDMOS device structure resistant to single event burnout, a trench oxide layer 15, a dielectric trench 14, and a first-conductivity-type body region 1 below the dielectric trench 14, and a first-conductivity-type buried layer region 6 below the first-conductivity-type body region 1 are added to the left of the first-conductivity-type well region 3, thereby providing an additional radiation current discharge path to avoid the device burnout phenomenon caused by single event effects and improve the single event burnout resistance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 It is a conventional high-voltage LDMOS device structure diagram.

[0015] Figure 2 It is a high-voltage LDMOS device structure diagram of embodiment 1 of the present application.

[0016] Figure 3 It is a high-voltage LDMOS device structure plan view of embodiment 1 of the present application.

[0017] Figure 4 It is a high-voltage LDMOS device front plan view of embodiment 1 of the present application.

[0018] Figure 5 It is a high-voltage LDMOS device structure plan view of embodiment 2 of the present application.

[0019] Figure 6 It is a high-voltage LDMOS device structure front plan view of embodiment 3 of the present application.

[0020] 1 is a first-conductivity-type body region, 2 is a second-conductivity-type source region, 3 is a first-conductivity-type well region, 4 is a second-conductivity-type well region, 5 is a second-conductivity-type drift region, 6 is a first-conductivity-type buried layer region, 7 is a buried oxide layer, 8 is a first-conductivity-type substrate, 9 is a gate oxide layer, 10 is a field oxide layer, 11 is a source electrode, 12 is a polysilicon gate electrode, 13 is a drain electrode, 14 is a dielectric trench, and 15 is a trench oxide layer. DETAILED DESCRIPTION

[0021] The embodiments of the present application will be described in detail by specific examples below, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied by different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0022] Figure 1This is a structural diagram of a conventional high-voltage LDMOS device. When high-energy particles bombard the device, a large number of electron-hole pairs are generated along the incident path through energy deposition. Under the influence of an electric field, electrons and holes move towards the drain and source, respectively, forming a transient current. Some holes flow into the P-well (the base region of the parasitic transistor) and then flow out from the body electrode P+. The hole current generates a voltage drop in the base region, causing the P-well / N+ junction (base / emitter junction) to be forward biased, and the parasitic transistor turns on. Electrons from the source N+ enter the drift region through the P-well, causing the device to undergo the Kirk effect, ionizing more electron-hole pairs at the drain. Holes move towards the source under the influence of the electric field, providing a stable positive feedback current to the base region, ultimately leading to device burnout.

[0023] To prevent the parasitic transistor from turning on, this invention adds a trench oxide layer 15, a dielectric trench 14, a first conductivity type body region 1 below the dielectric trench 14, and a first conductivity type buried layer region 6 below the first conductivity type body region 1 to the left of the first conductivity type well region 3. This provides an additional path for radiated current discharge, avoids device burn-out caused by single-event effects, and improves the device's resistance to single-event burn-out. The device structure is as follows: Figure 2 As shown. The dielectric trench 14 of the high-voltage LDMOS device structure of this invention is fully filled, as shown. Figure 3 As shown, or the medium tank 14 can be filled in segments, such as... Figure 5 As shown, all of these can effectively improve the device's resistance to single-particle burn-out. Also, as a preferred embodiment, the bottom of the first conductivity type buried layer region 6 of the high-voltage LDMOS device structure of this invention is tangent to the buried oxide layer 7, as shown... Figure 4 As shown, or the bottom of the first conductive type buried layer region 6 is slightly higher than the buried oxide layer 7, such as... Figure 6 As shown, all of these methods can effectively improve the device's resistance to single-event burn-out.

[0024] Example 1

[0025] like Figure 2As shown, this embodiment provides a high-voltage LDMOS device structure resistant to single-particle burn-out, including a first conductivity type substrate 8 at the bottom, a buried oxide layer 7 above the first conductivity type substrate 8, a second conductivity type drift region 5 above the buried oxide layer 7, a second conductivity type well region 4 located to the right of the second conductivity type drift region 5, a second conductivity type source region 2 located to the right of the second conductivity type well region 4, a first conductivity type well region 3 located to the left of the second conductivity type drift region 5, a second conductivity type source region 2 and a first conductivity type body region 1 located inside the first conductivity type well region 3, a trench oxide layer 15 located to the left of the first conductivity type well region 3 and a dielectric trench 14 located inside the trench oxide layer 15, a first conductivity type body region 1 located below the dielectric trench 14, a first conductivity type buried layer region 6 located below the first conductivity type body region 1, a polysilicon gate electrode 12 located above the gate oxide layer 9 and the field oxide layer 10, a source electrode 11 located above the first conductivity type well region 3 and the dielectric trench 14, and a drain electrode 13 located above the second conductivity type source region 2 located to the right of the second conductivity type well region 4.

[0026] The medium tank 14 is made of polycrystalline silicon or metal.

[0027] When the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

[0028] The bottom of the first conductive type buried layer region 6 is tangent to the buried oxide layer 7.

[0029] The side of the oxide layer 15 is tangent to the first conductivity type trap region 3, and the dielectric trench 14 is short-circuited with the source electrode 11, thereby providing a potential equal to that of the source electrode for the first conductivity type body region 1 and the first conductivity type buried layer region 6 located at the bottom of the dielectric trench 14, providing a discharge path for the extraction of ionized charges.

[0030] like Figure 3 As shown, a dielectric groove 14 with the same width as the active region is provided along the width direction (i.e., Z direction) through which the device current flows.

[0031] like Figure 4 As shown, the first conductive type body region 1 located at the bottom of the dielectric tank 14 is completely surrounded by the first conductive type buried layer region 6.

[0032] Example 2

[0033] like Figure 5As shown, the difference between this embodiment and embodiment 1 is that: multiple dielectric trenches 14 are provided along the width direction of the device current flow (i.e., the Z direction), and the trench oxide layer 15 is filled between adjacent dielectric trenches 14.

[0034] Example 3

[0035] like Figure 6 As shown, the difference between this embodiment and Embodiment 1 is that the bottom of the first conductive type buried layer region 6 is higher than the buried oxide layer 7.

[0036] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high voltage LDMOS device structure resistant to single event burnout, characterized by: The device comprises a first conductive type substrate (8) at the bottom, a buried oxide layer (7) above the first conductive type substrate (8), a second conductive type drift region (5) above the buried oxide layer (7), a second conductive type well region (4) above the right upper part of the second conductive type drift region (5), a second conductive type source region (2) inside the right upper part of the second conductive type well region (4), a first conductive type well region (3) above the left upper part of the second conductive type drift region (5), a second conductive type source region (2) inside the first conductive type well region (3), a first conductive type body region (1), a trench oxide layer (15) left of the first conductive type well region (3) and a dielectric trench (14) inside the trench oxide layer (15), a first conductive type body region (1) below the dielectric trench (14), and a first conductive type buried layer region (6) below the first conductive type body region (1), a polysilicon gate electrode (12) above the gate oxide layer (9) and the field oxide layer (10), a source electrode (11) above the first conductive type well region (3) and the dielectric trench (14), and a drain electrode (13) above the second conductive type source region (2) inside the right upper part of the second conductive type well region (4). The first conductive type body region (1) at the bottom of the dielectric trench (14) is completely surrounded by the first conductive type buried layer region (6). The side of the trench oxide layer (15) is tangent to the first conductive type well region (3), and the dielectric trench (14) is short-circuited to the source electrode (11), thereby providing the first conductive type body region (1) at the bottom of the dielectric trench (14) and the first conductive type buried layer region (6) with an equal potential to the source electrode and providing a discharge path for the extraction of ionized charges. The material of the dielectric trench (14) is polysilicon or metal. 2.The high-voltage LDMOS device structure against single event burnout of claim 1, wherein: One dielectric trench (14) equal in width to the active region is provided along the width direction of the current flow of the device. 3.The high-voltage LDMOS device structure against single event burnout of claim 1, wherein: A plurality of dielectric trenches (14) are provided along the width direction of the current flow of the device, and the adjacent dielectric trenches (14) are filled with a trench oxide layer (15).

4. The high voltage LDMOS device structure against single event burnout of claim 1, wherein: The bottom of the first conductive type buried layer region (6) is tangent to the buried oxide layer (7) or higher than the buried oxide layer (7).

5. The high voltage LDMOS device structure against single event burnout of claim 1, wherein: When the first conductive type doping impurities are acceptor type and the second conductive type doping impurities are donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductive type doping impurities are donor type and the second conductive type doping impurities are acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

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