A DC-DC converter, its driving circuit and related equipment

Abstract

The present invention provides a DC-DC converter, a drive circuit thereof, and related equipment. The drive circuit includes a differential amplifier circuit, a first dead-zone control circuit, and a second dead-zone control circuit. The differential amplifier circuit is used to amplify a first differential control signal and a second differential control signal. The first dead-zone control circuit is used to delay, level-shift, and amplify the first differential control signal output by the differential amplifier circuit. The second dead-zone control circuit is used to delay, level-shift, and amplify the second differential control signal output by the differential amplifier circuit, so that the first switch and the second switch have dead time during the switching process, thereby preventing the first switch and the second switch from being turned on at the same time. This not only avoids damage to the first switch and the second switch due to instantaneous high current, but also reduces power loss of the DC-DC converter and improves the efficiency of the DC-DC converter.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply systems, and more particularly to a DC-DC converter, a driving circuit thereof, and related equipment. Background Art

[0002] With the rapid development of science and technology, the continuous emergence of miniaturized and intelligent electronic products has not only improved people's living standards, but also put more stringent tests on their power supply systems. Miniaturization, energy saving, low consumption, reliability and low cost have become the development direction of new power supply systems.

[0003] Existing power supply systems include DC-DC converters to convert input voltage to the fixed voltage required by electronic products. Figure 1 As shown, a conventional DC-DC converter includes a power amplifier circuit, a primary coil circuit, a transformer, and a rectifier and filter circuit. The power amplifier circuit includes a first switch K1 and a second switch K2. The first switch K1 is turned on and off by a first differential control signal Vin+, and the second switch K2 is turned on and off by a second differential control signal Vin-. When the first switch K1 is turned on and the second switch K2 is turned off, and when the first switch K1 is turned off, the second switch K2 is turned on. When the first switch K1 is turned on and the second switch K2 is turned off, the DC-DC converter outputs a first voltage. When the first switch K1 is turned off and the second switch K2 is turned on, the DC-DC converter outputs a second voltage. By adjusting the ratio of the first voltage to the second voltage, the desired output voltage can be obtained.

[0004] However, if Figure 2 As shown, since the first differential control signal Vin+ (dashed line) and the second differential control signal Vin- (solid line) are both square wave signals with alternating high and low levels, and the rising edge and falling edge of the first differential control signal Vin+ overlap or almost overlap with the rising edge and falling edge of the second differential control signal Vin-, a momentary large current will flow through the first switch K1 and the second switch K2 during the switching process, causing the first switch K1 and the second switch K2 to be turned on at the same time. This may not only cause the first switch K1 and the second switch K2 to burn out due to the large current, but also result in a large power loss in the DC-DC converter. Summary of the Invention

[0005] In view of this, the present invention provides a DC-DC converter and a driving circuit and related devices thereof to reduce the power consumption of the DC-DC converter.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A driving circuit for driving a first switch and a second switch in a power amplifier circuit in a DC-DC converter, the driving circuit comprising a differential amplifier circuit, a first dead zone control circuit, and a second dead zone control circuit;

[0008] The differential amplifier circuit is used to amplify the first differential control signal and the second differential control signal, and transmit the amplified first differential control signal to the first dead zone control circuit, and transmit the amplified second differential control signal to the second dead zone control circuit;

[0009] The first dead zone control circuit is used to delay, level-shift and amplify the first differential control signal output by the differential amplifier circuit, and transmit the obtained first control signal to the control terminal of the first switch;

[0010] The second dead zone control circuit is used to delay, level shift and amplify the second differential control signal output by the differential amplifier circuit, and transmit the obtained second control signal to the control end of the second switch, so that the first switch and the second switch have dead zone time at the same time during the switch conversion process.

[0011] Optionally, the differential amplifier circuit includes a third switch, a fourth switch, a first resistor and a second resistor;

[0012] A first end of the first resistor is connected to a first voltage terminal, a second end of the first resistor is connected to a first end of the third switch, a second end of the third switch is connected to a second voltage terminal, a control end of the third switch receives the first differential control signal, and a common end of the first resistor and the third switch is connected to the first dead zone control circuit;

[0013] A first end of the second resistor is connected to the third voltage terminal, a second end of the second resistor is connected to the first end of the fourth switch, a second end of the fourth switch is connected to the second voltage terminal, a control end of the fourth switch receives the second differential control signal, and a common end of the second resistor and the fourth switch is connected to the second dead zone control circuit;

[0014] The voltage of the second voltage terminal is lower than the voltage of the first voltage terminal, and the voltage of the second voltage terminal is lower than the voltage of the third voltage terminal.

[0015] Optionally, the first dead zone control circuit includes a first delay circuit, a first level shift circuit, and a first amplifier circuit connected in sequence, and the second dead zone control circuit includes a second delay circuit, a second amplifier circuit, and a second level shift circuit connected in sequence;

[0016] The first delay circuit is used to delay the first differential control signal output by the differential amplifier circuit;

[0017] The first level shift circuit is used to perform level shift processing on the first differential control signal output by the first delay circuit;

[0018] The first amplifier circuit is used to amplify the first differential control signal output by the first level shift circuit and transmit the obtained first control signal to the control end of the first switch;

[0019] The second delay circuit is used to delay the second differential control signal output by the differential amplifier circuit;

[0020] The second amplifier circuit is used to amplify the second differential control signal output by the second delay circuit;

[0021] The second level shift circuit is used to perform level shift processing on the second differential control signal output by the second amplifying circuit, and transmit the obtained second control signal to the control end of the second switch.

[0022] Optionally, the first delay circuit includes a first diode, a third resistor, and a first capacitor, wherein an anode of the first diode is connected to a first end of the third resistor, a cathode of the first diode is connected to a second end of the third resistor, a first end of the first capacitor is connected to a cathode of the first diode, a second end of the first capacitor is grounded, an anode of the first diode is connected to a first output end of the differential amplifier circuit, and the first output end outputs a first differential control signal;

[0023] The first level shifting circuit includes a fifth switch, a second diode, and a sixth switch, wherein a control terminal of the fifth switch is connected to a cathode of the first diode, a first terminal of the fifth switch is connected to a fourth voltage terminal, a second terminal of the fifth switch is connected to an anode of the second diode, a cathode of the second diode is connected to a first terminal of the sixth switch, a control terminal and a second terminal of the sixth switch are connected to a fifth voltage terminal, and a voltage of the fifth voltage terminal is lower than a voltage of the fourth voltage terminal;

[0024] The first amplifying circuit includes a fourth resistor and a seventh switch, wherein a first end of the fourth resistor is connected to the sixth voltage terminal, a second end of the fourth resistor is connected to the first end of the seventh switch, a control end of the seventh switch is connected to the cathode of the second diode, a second end of the seventh switch is connected to the seventh voltage terminal, a voltage of the seventh voltage terminal is lower than a voltage of the sixth voltage terminal, and a control end of the first switch is connected to a common end of the fourth resistor and the seventh switch.

[0025] Optionally, the second delay circuit includes a third diode, a fifth resistor, and a second capacitor, wherein the anode of the third diode is connected to the first end of the fifth resistor, the cathode of the third diode is connected to the second end of the fifth resistor, the first end of the second capacitor is connected to the cathode of the third diode, the second end of the second capacitor is grounded, the anode of the third diode is connected to the second output end of the differential amplifier circuit, and the second output end outputs the second differential control signal;

[0026] The second amplifying circuit includes a sixth resistor and an eighth switch, a first end of the sixth resistor is connected to the eighth voltage terminal, a second end of the sixth resistor is connected to the first end of the eighth switch, a control end of the eighth switch is connected to the cathode of the third diode, and a second end of the eighth switch is connected to a ninth voltage terminal, where a voltage at the ninth voltage terminal is lower than a voltage at the eighth voltage terminal;

[0027] The first level shifting circuit includes a ninth switch, a fourth diode, and a tenth switch. The control end of the ninth switch is connected to the common end of the sixth resistor and the eighth switch. The first end of the ninth switch is connected to the tenth voltage end. The second end of the ninth switch is connected to the anode of the fourth diode. The cathode of the fourth diode is connected to the first end of the tenth switch. The control end and the second end of the tenth switch are connected to the eleventh voltage end. The voltage of the eleventh voltage end is lower than the voltage of the tenth voltage end. The control end of the second switch is connected to the common end of the fourth diode and the tenth switch.

[0028] Optionally, the first switch to the tenth switch are all GaN-based HEMT devices.

[0029] A DC-DC converter, characterized by comprising a drive circuit and a power amplifier circuit, wherein the power amplifier circuit comprises a first switch and a second switch, and the drive circuit is the drive circuit as described in any one of the above items.

[0030] Optionally, the DC-DC converter further includes a fifth diode, a sixth diode, a first inductor, a transformer, a seventh diode, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a second inductor and a seventh resistor;

[0031] The first end of the first switch is connected to the cathode of the fifth diode, the second end of the first switch is connected to the anode of the fifth diode, and the cathode of the fifth diode is connected to the twelfth voltage terminal;

[0032] The first end of the second switch is connected to the cathode of the sixth diode, the second end of the second switch is connected to the anode of the sixth diode, the cathode of the sixth diode is connected to the anode of the fifth diode, and the anode of the sixth diode is grounded;

[0033] A first end of the third capacitor is connected to the cathode of the fifth diode, a second end of the third capacitor is connected to the first end of the fourth capacitor, and a second end of the fourth capacitor is grounded;

[0034] The first end of the first inductor is connected to the cathode of the sixth diode, the second end of the first inductor is connected to the first input end of the transformer, and the second input end of the transformer is connected to the common end of the third capacitor and the fourth capacitor;

[0035] The first output end of the transformer is connected to the anode of the seventh diode, the second output end of the transformer is grounded, the cathode of the seventh diode is connected to the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the first end of the second inductor is connected to the cathode of the seventh diode, the second end of the second inductor is connected to the first end of the sixth capacitor, the second end of the sixth capacitor is grounded, the first end of the seventh resistor is connected to the second end of the second inductor, and the second end of the seventh resistor is grounded.

[0036] A power supply system includes the DC-DC converter described above.

[0037] An electronic device includes the power supply system described above.

[0038] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0039] The DC-DC converter, its driving circuit, and related devices provided by the present invention amplify a first differential control signal and a second differential control signal using a differential amplifier circuit, then delay, level-shift, and amplify the first differential control signal using a first dead-zone control circuit to obtain a first control signal, and delay, amplify, and level-shift the second differential control signal using a second dead-zone control circuit to obtain a second control signal. This allows both a first switch controlled by the first control signal and a second switch controlled by the second control signal to have dead-zone times. Furthermore, after the first and second switches are simultaneously turned off, one of the switches is turned on again, preventing the first and second switches from being simultaneously turned on. This prevents damage to the first and second switches due to instantaneous high current, thereby reducing power loss in the DC-DC converter. Furthermore, when the first and second switches are simultaneously turned off, the current in the transformer of the DC-DC converter is zero, thereby reducing DC loss in the transformer and improving the efficiency of the transformer and the DC-DC converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0041] Figure 1 It is a structural diagram of an existing DC-DC converter;

[0042] Figure 2 for Figure 1 Waveform diagram of the first differential control signal and the second differential control signal in the DC-DC converter shown;

[0043] Figure 3 A schematic structural diagram of a driving circuit of a DC-DC converter provided in one embodiment of the present invention;

[0044] Figure 4 A schematic structural diagram of a driving circuit of a DC-DC converter provided in another embodiment of the present invention;

[0045] Figure 5 A schematic structural diagram of a driving circuit of a DC-DC converter provided in one embodiment of the present invention;

[0046] Figure 6 A schematic structural diagram of a level shifting circuit provided by one embodiment of the present invention;

[0047] Figure 7Waveform diagram of a first control signal and a second control signal of a DC-DC converter provided by one embodiment of the present invention;

[0048] Figure 8 A schematic structural diagram of a transformer in a DC-DC converter provided by one embodiment of the present invention;

[0049] Figure 9 A waveform diagram of the voltage and current of the output signal of a DC-DC converter provided by one embodiment of the present invention;

[0050] Figure 10 This is a voltage waveform diagram of the output signal of a DC-DC converter provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0051] The above is the core idea of ​​the present invention. In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0052] One embodiment of the present invention provides a driving circuit, such as Figure 3 As shown, a first switch M1 and a second switch M2 are used to drive a power amplifier circuit in a DC-DC converter. Optionally, the DC-DC converter is a Buck-type isolated DC-DC converter. In an embodiment of the present invention, the driving circuit includes a differential amplifier circuit 00, a first dead zone control circuit 10, and a second dead zone control circuit 20.

[0053] The differential amplifier circuit 00 is used to amplify the first differential control signal Vin+ and the second differential control signal Vin-, and transmit the amplified first differential control signal Vin+ to the first dead zone control circuit 10, and transmit the amplified second differential control signal Vin- to the second dead zone control circuit 20;

[0054] The first dead zone control circuit 10 is used to delay, level-shift, and amplify the first differential control signal Vin+ output by the differential amplifier circuit 00 to obtain a first control signal V1, and transmit the obtained first control signal V1 to the control terminal of the first switch M1;

[0055] The second dead zone control circuit 20 is used to delay, level-shift and amplify the second differential control signal Vin- output by the differential amplifier circuit 00 to obtain a second control signal V2, and transmit the obtained second control signal V2 to the control end of the second switch M2, so that the first switch M1 and the second switch M2 have dead zones at the same time during the switching process.

[0056] The drive circuit provided in the embodiment of the present invention delays, level-shifts, and amplifies the first differential control signal Vin+ through the first dead-zone control circuit 10, and delays, level-shifts, and amplifies the second differential control signal Vin- through the second dead-zone control circuit 20. This allows both the first switch M1 controlled by the first control signal V1 and the second switch M2 controlled by the second control signal V2 to have dead-zone times. Furthermore, after the first switch M1 and the second switch M2 are simultaneously turned off, one of the switches is turned on again, i.e., the first switch M1 and the second switch M2 are not simultaneously turned on. This not only avoids damage to the first switch M1 and the second switch M2 due to instantaneous high current when they are simultaneously turned on, thereby reducing power loss in the DC-DC converter, but also, when the first switch M1 and the second switch M2 are simultaneously turned off, the current in the transformer T in the DC-DC converter is zero, thereby reducing DC loss in the transformer T and improving the efficiency of the transformer T and the DC-DC converter.

[0057] It should be noted that, in order to obtain the desired delay time or dead time, in the embodiment of the present invention, the first differential control signal Vin+ and the second differential control signal Vin- are first amplified using the differential amplifier circuit 00. Furthermore, because the first dead-zone control circuit 10 delays the first differential control signal Vin+, and the second dead-zone control circuit 20 delays the second differential control signal Vin-, the amplitudes of the first differential control signal Vin+ and the second differential control signal Vin- are reduced. Therefore, to ensure the control effect of the output signals on the first switch M1 and the second switch M2, in the embodiment of the present invention, the first differential control signal Vin+ and the second differential control signal Vin- are level-shifted and amplified. In addition, since the amplitudes of the control signals required by the control ends of the first switch M1 and the second switch M2 are different, in the embodiment of the present invention, the first differential control signal Vin+ is first level-shifted and then amplified, and the second differential control signal Vin- is first amplified and then level-shifted, thereby optimizing the output signals of the first dead-zone control circuit 10 and the second dead-zone control circuit 20, and further enabling better control of the first switch M1 and the second switch M2.

[0058] In some embodiments of the present invention, Figure 4As shown, the first dead zone control circuit 10 includes a first delay circuit 101, a first level shift circuit 102 and a first amplifier circuit 103 connected in sequence, and the second dead zone control circuit 20 includes a second delay circuit 201, a second amplifier circuit 202 and a second level shift circuit 203 connected in sequence.

[0059] Among them, the first delay circuit 101 is used to delay the first differential control signal Vin+ output by the differential amplifier circuit 00; the first level shift circuit 102 is used to perform level shift processing on the first differential control signal Vin+ output by the first delay circuit 101; the first amplifier circuit 103 is used to amplify the first differential control signal Vin+ output by the first level shift circuit 102, and transmit the obtained first control signal V1 to the control end of the first switch M1.

[0060] The second delay circuit 201 is used to delay the second differential control signal Vin- output by the differential amplifier circuit 00; the second amplifier circuit 202 is used to amplify the second differential control signal Vin- output by the second delay circuit 201; the second level shifter circuit 203 is used to level shift the second differential control signal Vin- output by the second amplifier circuit 202, and transmit the obtained second control signal V2 to the control end of the second switch M2.

[0061] In some embodiments of the present invention, Figure 5 As shown, the differential amplifier circuit 00 includes a third switch M3, a fourth switch M4, a first resistor R1 and a second resistor R2.

[0062] Among them, the first end of the first resistor R1 is connected to the first voltage terminal Vdd1, the second end of the first resistor R1 is connected to the first end of the third switch M3, the second end of the third switch M3 is connected to the second voltage terminal Vss1, the control end of the third switch M3 receives the first differential control signal Vin+, and the common end of the first resistor R1 and the third switch M3 is connected to the first dead zone control circuit 10.

[0063] A first end of the second resistor R2 is connected to the third voltage terminal Vdd2, a second end of the second resistor R2 is connected to a first end of the fourth switch M4, a second end of the fourth switch M4 is connected to the second voltage terminal Vss1, a control end of the fourth switch M4 receives the second differential control signal Vin-, and a common end of the second resistor R2 and the fourth switch M4 is connected to the second dead zone control circuit 20.

[0064] The voltage of the second voltage terminal Vss1 is lower than the voltage of the first voltage terminal Vdd1 , and the voltage of the second voltage terminal Vss1 is lower than the voltage of the third voltage terminal Vdd2 .

[0065] On this basis, in some embodiments of the present invention, Figure 5 As shown, the first delay circuit 101 includes a first diode D1, a third resistor R3 and a first capacitor C1. The anode of the first diode D1 is connected to the first end of the third resistor R3, the cathode of the first diode D1 is connected to the second end of the third resistor R3, the first end of the first capacitor C1 is connected to the cathode of the first diode D1, the second end of the first capacitor C1 is grounded, and the anode of the first diode D1 is connected to the first output end of the differential amplifier circuit 00, which outputs the first differential control signal Vin+.

[0066] The first level shifting circuit 102 includes a fifth switch M5, a second diode D2, and a sixth switch M6. The control end of the fifth switch M5 is connected to the cathode of the first diode D1, the first end of the fifth switch M5 is connected to the fourth voltage terminal Vdd3, the second end of the fifth switch M5 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the first end of the sixth switch M6, the control end and the second end of the sixth switch M6 are connected to the fifth voltage terminal Vss2, and the voltage of the fifth voltage terminal Vss2 is lower than the voltage of the fourth voltage terminal Vdd3.

[0067] The first amplifying circuit 103 includes a fourth resistor R4 and a seventh switch M7. A first end of the fourth resistor R4 is connected to the sixth voltage terminal Vdd4. A second end of the fourth resistor R4 is connected to the first end of the seventh switch M7. A control end of the seventh switch M7 is connected to the cathode of the second diode D2. A second end of the seventh switch M7 is connected to the seventh voltage terminal Vss3. The voltage of the seventh voltage terminal Vss3 is lower than the voltage of the sixth voltage terminal Vdd4. The control end of the first switch M1 is connected to a common end of the fourth resistor R4 and the seventh switch M7.

[0068] On this basis, in some embodiments of the present invention, Figure 5 As shown, the second delay circuit 201 includes a third diode D3, a fifth resistor R5 and a second capacitor C2, the anode of the third diode D3 is connected to the first end of the fifth resistor R5, the cathode of the third diode D3 is connected to the second end of the fifth resistor R5, the first end of the second capacitor C2 is connected to the cathode of the third diode D3, the second end of the second capacitor C2 is grounded, and the anode of the third diode D3 is connected to the second output end of the differential amplifier circuit 00, which outputs the second differential control signal Vin-.

[0069] The second amplifying circuit 202 includes a sixth resistor R6 and an eighth switch M8. A first end of the sixth resistor R6 is connected to the eighth voltage terminal Vdd5, a second end of the sixth resistor R6 is connected to the first end of the eighth switch M8, a control end of the eighth switch M8 is connected to the cathode of the third diode D3, and a second end of the eighth switch M8 is connected to the ninth voltage terminal Vss4. The voltage of the ninth voltage terminal Vss4 is lower than the voltage of the eighth voltage terminal Vdd5.

[0070] The first level shifting circuit 203 includes a ninth switch M9, a fourth diode D4, and a tenth switch M10. The control end of the ninth switch M9 is connected to the common end of the sixth resistor R6 and the eighth switch M8. The first end of the ninth switch M9 is connected to the tenth voltage terminal Vdd6. The second end of the ninth switch M9 is connected to the anode of the fourth diode D4. The cathode of the fourth diode D4 is connected to the first end of the tenth switch M10. The control end and the second end of the tenth switch M10 are connected to the eleventh voltage terminal Vss5. The voltage of the eleventh voltage terminal Vss5 is lower than the voltage of the tenth voltage terminal Vdd6. The control end of the second switch M2 is connected to the common end of the fourth diode D4 and the tenth switch M10.

[0071] It should be noted that, in some embodiments of the present invention, the first to tenth switches M1 to M10 are all HEMTs (High Electron Mobility Transistors). Further, optionally, the first to tenth switches M1 to M10 are all GaN (gallium nitride)-based HEMTs. Of course, the present invention is not limited to this. In other embodiments, the switches in the drive circuit, i.e., the first to tenth switches M1 to M10, are all PMOS transistors or NMOS transistors.

[0072] It should be noted that the first resistor R1 and the second resistor R2 in the differential amplifier circuit 00 are important components for implementing the circuit's output function. When Vdd and Vss are fixed, increasing the resistance of the first resistor R1 and the second resistor R2 can reduce the current in the circuit and reduce the DC loss of the differential amplifier circuit 00.

[0073] However, there are limits to how much the resistance of the first resistor R1 and the second resistor R2 can increase. Especially for HEMT devices, the device has an output capacitor Cout. When the signal output is high, there is a time delay RCout. When the resistance reaches a certain level, it can seriously affect the circuit's performance. The output signal may fail to reach the high output level Vdd within the circuit's operating cycle, which can seriously affect the circuit's output characteristics and output signal quality. Therefore, based on the above, the resistance of the first resistor R1 and the second resistor R2 in the differential amplifier circuit 00 cannot be increased indefinitely. They are limited by the circuit delay RCout within the operating frequency. Therefore, the selection of resistors requires a balance of pros and cons.

[0074] In some embodiments of the present invention, Figure 5 As shown, the differential amplifier circuit 00 adopts a differential pair circuit, such as Figure 2As shown, the first differential control signal Vin+ and the second differential control signal Vin- are square wave signals with alternating high and low levels. When the first differential control signal Vin+ is a low-level signal and the second differential control signal Vin- is a high-level signal, the fourth switch M4 is turned on and the third switch M3 is turned off. The voltage of the second voltage terminal Vss1, that is, the low level, is transmitted to the second delay circuit 201, and the voltage of the first voltage terminal Vdd1, that is, the high level, is transmitted to the first delay circuit 101 through the first resistor R1. When the first differential control signal Vin+ is a high-level signal and the second differential control signal Vin- is a low-level signal, the fourth switch M4 is turned off and the third switch M3 is turned on. The voltage of the third voltage terminal Vdd2, that is, the high level, is transmitted to the second delay circuit 201 through the second resistor R2, and the voltage of the second voltage terminal Vss1, that is, the low level, is transmitted to the first delay circuit 101.

[0075] When a high level is transmitted to the first delay circuit 101, a forward voltage is applied across the first diode D1, turning on the first diode D1 and having a very low resistance. The high level is output to the control terminal of the fifth switch M5 through the first diode D1, turning on the fifth switch M5. When a low level is transmitted to the first delay circuit 101, a reverse voltage is applied across the first diode D1, turning off the first diode D1 and having an infinite resistance. At this time, the loop formed by the third resistor R3 and the first capacitor C1 outputs a low level to the control terminal of the fifth switch M5. During this process, the fifth switch M5 remains in the on state. It should be noted that charging the first capacitor C1 through the third resistor R3 can gradually reduce the level of the control terminal of the fifth switch M5, causing the level of the control terminal of the fifth switch M5 to decrease with a delay, thereby achieving signal delay.

[0076] Similarly, when a high level is transmitted to the second delay circuit 201, a forward voltage is applied across the third diode D3, turning on the third diode D3 and having a very low resistance. The high level is then output to the control terminal of the eighth switch M8 via the third diode D3, thereby turning on the eighth switch M8. When a low level is transmitted to the second delay circuit 201, a reverse voltage is applied across the third diode D3, turning off the third diode D3 and having an infinite resistance. At this point, the loop formed by the fifth resistor R5 and the second capacitor C2 outputs a low level to the control terminal of the eighth switch M8. During this process, the eighth switch M8 remains on. Similarly, by charging the second capacitor C2 through the fifth resistor R5, the level at the control terminal of the eighth switch M8 is gradually reduced, thereby causing the level at the control terminal of the eighth switch M8 to decrease with a delay, thereby achieving signal delay, i.e., signal shaping.

[0077] Moreover, since the voltage of the signal output by the first delay circuit 101 and the second delay circuit 201 is determined by the first voltage terminal Vdd1, the third voltage terminal Vdd2 and the second voltage terminal Vss1, the signal can be amplified by presetting the voltages of the first voltage terminal Vdd1, the third voltage terminal Vdd2 and the second voltage terminal Vss1.

[0078] It should be noted that the RC delay network in the first delay circuit 101 and the second delay circuit 201 is a first-order RC network, and the input signal is the amplified differential control signal. If the amplitude of the input signal is V IN , such as the amplitude of the first differential control signal Vin+ is V IN , then at time t, the voltage of the first capacitor C1 is Vc=V IN (1-et / R3*C1). The delay time of the first delay circuit 101 can be calculated based on this formula. The delay time of the second delay circuit 201 can also be calculated in the same way, which will not be repeated here.

[0079] Although the fifth switch M5 is always on, the voltage at the cathode of the second diode D2 varies depending on the level or voltage at the control terminal of the fifth switch M5. Furthermore, the voltage at the cathode of the second diode D2 changes with the voltage at the control terminal of the fifth switch M5. Furthermore, because the sixth switch M6 is a depletion-type P-type transistor, it is always in a saturated on state. Therefore, the level or voltage at the control terminal of the fifth switch M5 decreases by a certain value before being transmitted to the control terminal of the seventh switch M7.

[0080] When the control terminal of the seventh switch M7 is at a high level, the seventh switch M7 is turned on, and the voltage of the seventh voltage terminal Vss3, i.e., a low level, is transmitted to the control terminal of the first switch M1. When the control terminal of the seventh switch M7 is at a low level, the seventh switch M7 is turned off, and the voltage of the sixth voltage terminal Vdd4, i.e., a high level, is transmitted to the control terminal of the first switch M1. Since the voltage of the signal output by the first amplifier circuit 103 is determined by the voltage of the sixth voltage terminal Vdd4 and the voltage of the seventh voltage terminal Vss3, the signal output by the first amplifier circuit 103 can be amplified by setting the voltage of the sixth voltage terminal Vdd4 and the voltage of the seventh voltage terminal Vss3 to drive the high-power first switch M1.

[0081] Similarly, when the control terminal of the eighth switch M8 is at a high level, the eighth switch M8 is turned on, and the voltage of the ninth voltage terminal Vss4, i.e., a low level, is transmitted to the control terminal of the ninth switch M9. When the control terminal of the eighth switch M8 is at a low level, the eighth switch M8 is turned off, and the voltage of the eighth voltage terminal Vdd5, i.e., a high level, is transmitted to the control terminal of the ninth switch M9. Since the voltage of the signal output by the second amplifier circuit 203 is determined by the voltage of the eighth voltage terminal Vdd5 and the voltage of the ninth voltage terminal Vss4, the signal output by the second amplifier circuit 203 can be amplified by setting the voltage of the eighth voltage terminal Vdd5 and the voltage of the ninth voltage terminal Vss4.

[0082] The ninth switch M9 is always in the on state. The voltage at the cathode of the fourth diode D4 changes with the voltage at the control terminal of the ninth switch M9. Furthermore, because the tenth switch M10 is a depletion-type P-type transistor, the tenth switch M10 is always in a saturated on state. Therefore, the voltage at the control terminal of the ninth switch M9 decreases by a certain value before being transmitted to the control terminal of the second switch M2.

[0083] It should be noted that when the sixth switch M6 and the tenth switch M10 are always in the on state, the current in the switch is Where L is the gate length of the switch, W is the gate width of the switch, V TH is the threshold voltage of the switch. After the current in the circuit is determined, the voltage across each second diode D2 or fourth diode D4 is also determined, and the voltage of the diode cathode output signal V = V x -nV b , n is the number of diodes, V b is the voltage across the diode, such as the voltage across the second diode D2 or the fourth diode D4, Figure 6 As shown, Vx is the voltage at the second terminal X of the fifth switch M5 or the ninth switch M9. In the embodiment of the present invention, n is only taken as 1 for illustration, but is not limited thereto. In other embodiments, n may be greater than or equal to 2.

[0084] It should also be noted that in some embodiments of the present invention, the circuit sequence used for two circuits with two different signals is different. For the upper signal, the delay circuit precedes the level shifter circuit and then the amplifier circuit; for the lower signal, the amplifier circuit precedes the level shifter circuit. This is because the amplitudes of the two differential control signals differ after passing through the differential amplifier circuit 00. This also optimizes the dead-zone circuit output signal.

[0085] In some embodiments of the present invention, the input voltage VIN of the DC-DC converter is 48V. Figure 7As shown in the figure, the voltage range of the first control signal (dashed line) of the first switch M1 in the power amplifier circuit is -5V to 48V, and the voltage range of the second control signal (solid line) of the second switch M2 is -5V to 0V. Therefore, different processing orders are adopted for the two different signals. The first signal, due to its larger amplitude, first passes through the level shifter circuit before the amplifier circuit; the second signal, due to its smaller amplitude, first passes through the amplifier circuit before the level shifter circuit.

[0086] like Figure 7 As shown, the time when the first control signal V1 and the second control signal V2 are simultaneously at a low level (the time shown in the dotted box), that is, the dead time simultaneously possessed by the first switch M1 controlled by the first control signal V1 and the second switch M2 controlled by the second control signal V2, can ensure that after the first switch M1 and the second switch M2 are simultaneously turned off, one of the switches is turned on again, that is, the first switch M1 and the second switch M2 will not be turned on at the same time. This not only avoids damage to the first switch M1 and the second switch M2 due to instantaneous high current when they are simultaneously turned on, thereby reducing the power loss of the DC-DC converter, but also, when the first switch M1 and the second switch M2 are simultaneously turned off, the current of the transformer T in the DC-DC converter is zero, thereby reducing the DC loss of the transformer T and improving the efficiency of the transformer T and the DC-DC converter.

[0087] The embodiment of the present invention further provides a DC-DC converter, such as Figure 3 As shown, the embodiment includes a driving circuit and a power amplifier circuit. The power amplifier circuit includes a first switch M1 and a second switch M2. The driving circuit is the driving circuit provided in any of the above embodiments. It should be noted that in the embodiments of the present invention, the DC-DC converter is described as a step-down converter, but the present invention is not limited to this. In other embodiments, the DC-DC converter may also be a step-up converter, etc.

[0088] like Figure 3 As shown, the DC-DC converter in some embodiments of the present invention further includes a primary coil circuit, a transformer T, and a rectifier and filter circuit. The primary coil circuit includes a fifth diode D5, a sixth diode D6, a third capacitor C3, a fourth capacitor C4, and a first inductor L1. The rectifier and filter circuit includes a seventh diode D7, a fifth capacitor C5, a sixth capacitor C6, a second inductor L2, and a seventh resistor R7.

[0089] A first end of the first switch M1 is connected to the cathode of the fifth diode D5, a second end of the first switch M1 is connected to the anode of the fifth diode D5, and the cathode of the fifth diode D5 is connected to the twelfth voltage terminal VIN; a first end of the second switch M2 is connected to the cathode of the sixth diode D6, a second end of the second switch M2 is connected to the anode of the sixth diode D6, the cathode of the sixth diode D6 is connected to the anode of the fifth diode D5, and the anode of the sixth diode D6 is grounded; a first end of the third capacitor C3 is connected to the cathode of the fifth diode D5, a second end of the third capacitor C3 is connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is grounded;

[0090] A first end of the first inductor L1 is connected to the cathode of the sixth diode D6, a second end of the first inductor L1 is connected to the first input end of the transformer T, and the second input end of the transformer T is connected to the common end of the third capacitor C3 and the fourth capacitor C4; a first output end of the transformer T is connected to the anode of the seventh diode D7, a second output end of the transformer T is grounded, a cathode of the seventh diode D7 is connected to the first end of the fifth capacitor C5, and a second end of the fifth capacitor C5 is grounded; a first end of the second inductor L2 is connected to the cathode of the seventh diode D7, a second end of the second inductor L2 is connected to the first end of the sixth capacitor C6, and a second end of the sixth capacitor C6 is grounded; a first end of the seventh resistor R7 is connected to the second end of the second inductor L2, and a second end of the seventh resistor R7 is grounded.

[0091] When the first control signal V1 output by the driving circuit is at a low level and the second control signal V2 is at a high level, the second switch M2 is turned off and the first switch M1 is turned on; when the first control signal V1 output by the driving circuit is at a high level and the second control signal V2 is at a low level, the second switch M2 is turned on and the first switch M1 is turned off.

[0092] In the embodiment of the present invention, the primary coil of the transformer T adopts a half-bridge topology, and a first inductor L1 is connected in series between the power amplifier circuit and the primary coil. At the same time, the other end of the first inductor L1 is connected between the third capacitor C3 and the fourth capacitor C4. At this time, the voltage at the upper port of the primary coil, i.e., the first input terminal of the transformer T, is VIN, and the voltage at the other port of the primary coil, i.e., the second input terminal of the transformer T, is When the first switch M1 and the second switch M2 are turned on and off, the input voltage of the primary coil of the transformer T also changes.

[0093] When the second switch M2 is turned off and the first switch M1 is turned on, the voltage at the upper port of the primary coil, i.e., the first input terminal of the transformer T, is VIN, and the voltage at the other port of the primary coil, i.e., the second input terminal of the transformer T, is Then the input voltage of the primary coil of transformer T is: When the second switch M2 is turned on and the first switch M1 is turned off, the voltage at the upper port of the primary coil, i.e., the first input terminal of the transformer T, is 0V, and the voltage at the other port of the primary coil, i.e., the second input terminal of the transformer T, is Then the input voltage of the primary coil of transformer T is: Combined with the charging and discharging function of the first inductor L1, the output of the transformer T is However, due to the introduction of the dead time, the primary coil will have a third state, where the second switch M2 and the first switch M1 are both in the off state. During the dead time, the second switch M2 and the first switch M1 are both in the off state. At this time, the current in the circuit is approximately 0, which reduces the DC power consumption to a certain extent and also reduces the power consumption of the transformer T, thereby increasing efficiency.

[0094] In some embodiments of the present invention, transformer T utilizes a GaN-based on-chip transformer with four metal layers and SiN as the dielectric. The transformer has a radius of 200 μm, a line width of 30 μm, a line spacing of 5 μm, a metal thickness of 300 nm, and a 20 nm thickness for the isolation material between the upper and lower coils. Based on the input and output voltages, a turns ratio of 9:3 is selected.

[0095] In some embodiments of the present invention, the rectifier and filter circuit utilizes a diode and an improved π-type rectifier and filter circuit. This circuit primarily utilizes the diode's unidirectional conductivity to first convert the AC signal output by transformer T into a DC signal, which is then passed through a π-type C, L, C network to achieve a stable voltage, thereby stabilizing the output voltage at 5V. While filter circuits using capacitors or inductors alone may not provide ideal filtering results, this composite π-type filter circuit offers superior filtering performance, minimizes output voltage ripple, and is suitable for applications with higher currents.

[0096] In some embodiments of the present invention, the driver circuit utilizes 0.25 μm GaN-based p-type HEMT main and auxiliary power amplifier dies, fabricated into an integrated buck-type isolated DC-DC converter. This DC-CDC converter operates with a 48 V DC input, a -10 V to -5 V control differential signal, and a 50 MHz frequency. The output is 5 V.

[0097] In some embodiments of the present invention, the first resistor R1 and the second resistor R2 of the differential amplifier circuit 00 in the driving circuit are 500 ohms, which is the resistance optimized by comprehensively weighing various aspects of the circuit. The DC loss of the circuit is: Ron1 and Ron2 are the on-resistances of the third switch M3 and the fourth switch M4 when they are turned on, respectively.

[0098] In some embodiments of the present invention, the third resistor R3 is 500 ohms, the first capacitor C1 is 2.8 pf, the fifth resistor R5 is 1000 ohms, and the second capacitor C2 is 1.4 pf. The fourth resistor R4 is 500 ohms, and the sixth resistor R6 is 150 ohms. The third and fourth capacitors C3 and C4 are 100 μF, and the first inductor L1 is 0.3 nH. The first inductor L1 is charged and discharged by the switching of the first switch M1 and the second switch M2, thereby converting the DC signal into an AC signal.

[0099] Since the GaN-based p-type transistors used are fully shut off only when the gate-source voltage is less than -5V, and VIN = 48V, to drive the first switch M1 and the second switch M2 in the power amplifier circuit, the input voltage of the first switch M1 must be between -5 and 48V, and the input voltage of the second switch M2 must be between -5 and 0V. Because the first and second switches M1 and M2 need to carry large currents, a trade-off is made. The gate widths of the first and second switches M1 and M2 of the power amplifier circuit are 8x125 transistors, with 2x125 and 6x125 transistors connected in parallel. To prevent reverse breakdown of the first and second switches M1 and M2 of the power amplifier circuit, two reverse diodes are connected in parallel with the first and second switches M1 and M2.

[0100] The on-chip transformer in some embodiments of the present invention uses four layers of metal, and the isolation medium used is SiN. Two layers of metal and three layers of dielectric are added based on the GaN process. When designing the primary coil of the transformer T, a new layer of metal is first added as the lower coil, and then a layer of dielectric is added, and then the metal in the center is led out through photolithography and etching. After the secondary coil is completed, a layer of dielectric is laid, mainly to isolate the upper and lower layers of coils. Then the secondary coil of the transformer T is made. The secondary coil is made in the same way as the primary coil. First, a layer of coil is made of metal, and then a layer of dielectric is covered, and then a hole is opened to lead out the metal wire in the center.

[0101] In some embodiments of the present invention, the radius of transformer T is 200μm, the line width is 30μm, the line spacing is 5μ, the metal thickness is 300nm, and the thickness of the isolation material of the upper and lower coils is 20nm. The parasitic resistance of transformer T is 28Ω, the inductance value is 11nH, the mutual inductance is 0.01nH, the quality factor is 0.11, and the coupling coefficient is 0.868. The various parameters of transformer T are calculated through Z parameter simulation, as follows: imag represents the imaginary part, real represents the real part, f represents the frequency, w represents the angular frequency, L11 represents the parasitic inductance of the primary coil, L21 represents the parasitic inductance of the secondary coil, R1 represents the parasitic resistance of the primary coil, M represents the mutual inductance of the primary and secondary coils, K represents the coupling coefficient, and Q represents the quality factor, such as Figure 8 Shown is a model diagram of a transformer.

[0102] Among them, the parasitic resistance of the transformer is: R1=real(Z 11 );

[0103] The transformer inductance is:

[0104] The mutual inductance of the transformer is:

[0105] The coupling coefficient is:

[0106] The quality factor is:

[0107] In some embodiments of the present invention, transformer T employs an isolated on-chip transformer. This transformer is constructed in a symmetrical manner, resulting in a turns ratio of 1 and a coupling coefficient typically exceeding 0.7. The greatest advantage of an isolated on-chip transformer over other transformers is its isolation capability.

[0108] The DC-DC converter in the embodiment of the present invention provides a dead time between the first switch M1 and the second switch M2 through the driving circuit, thereby avoiding damage to the switches caused by the instantaneous high current when the first switch M1 and the second switch M2 are turned on at the same time. At the same time, the power consumption of the transformer and the DC-DC converter is reduced, and the efficiency of the DC-DC converter is improved. The waveforms of the voltage (solid line) and current (dashed line) of the final output signal VOUT of the DC-DC converter are shown as follows: Figure 9 As shown, the overall voltage waveform of the final output signal VOUT of the DC-DC converter is as follows Figure 10 Optionally, the voltage of VOUT is 4.99V to 5.04V, and the ripple is within 50mV.

[0109] An embodiment of the present invention further provides a power supply system, which includes the DC-DC converter provided in any of the above embodiments.

[0110] An embodiment of the present invention further provides an electronic device including the power supply system provided in any of the above embodiments. The electronic device includes but is not limited to a smartphone, a tablet computer, a television, and the like.

[0111] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. The above description of the disclosed embodiments enables professionals and technicians in this field to implement or use the present invention. Various modifications to these embodiments will be apparent to professionals and technicians in this field, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving circuit for driving a first switch and a second switch in a power amplifier circuit in a DC-DC converter, characterized in that: The driving circuit includes a differential amplifier circuit, a first dead zone control circuit and a second dead zone control circuit; The differential amplifier circuit is used to amplify the first differential control signal and the second differential control signal, and transmit the amplified first differential control signal to the first dead zone control circuit, and transmit the amplified second differential control signal to the second dead zone control circuit; The first dead zone control circuit is used to delay, level-shift and amplify the first differential control signal output by the differential amplifier circuit, and transmit the obtained first control signal to the control terminal of the first switch; The second dead zone control circuit is used to delay, level shift and amplify the second differential control signal output by the differential amplifier circuit, and transmit the obtained second control signal to the control end of the second switch, so that the first switch and the second switch have dead zone time at the same time during the switch conversion process.

2. The driving circuit according to claim 1, wherein: The differential amplifier circuit includes a third switch, a fourth switch, a first resistor and a second resistor; A first end of the first resistor is connected to a first voltage terminal, a second end of the first resistor is connected to a first end of the third switch, a second end of the third switch is connected to a second voltage terminal, a control end of the third switch receives the first differential control signal, and a common end of the first resistor and the third switch is connected to the first dead zone control circuit; A first end of the second resistor is connected to the third voltage terminal, a second end of the second resistor is connected to the first end of the fourth switch, a second end of the fourth switch is connected to the second voltage terminal, a control end of the fourth switch receives the second differential control signal, and a common end of the second resistor and the fourth switch is connected to the second dead zone control circuit; The voltage of the second voltage terminal is lower than the voltage of the first voltage terminal, and the voltage of the second voltage terminal is lower than the voltage of the third voltage terminal.

3. The driving circuit according to claim 1 or 2, characterized in that: The first dead zone control circuit includes a first delay circuit, a first level shift circuit, and a first amplifier circuit connected in sequence, and the second dead zone control circuit includes a second delay circuit, a second amplifier circuit, and a second level shift circuit connected in sequence; The first delay circuit is used to delay the first differential control signal output by the differential amplifier circuit; The first level shift circuit is used to perform level shift processing on the first differential control signal output by the first delay circuit; The first amplifier circuit is used to amplify the first differential control signal output by the first level shift circuit and transmit the obtained first control signal to the control end of the first switch; The second delay circuit is used to delay the second differential control signal output by the differential amplifier circuit; The second amplifier circuit is used to amplify the second differential control signal output by the second delay circuit; The second level shift circuit is used to perform level shift processing on the second differential control signal output by the second amplifying circuit, and transmit the obtained second control signal to the control end of the second switch.

4. The driving circuit according to claim 3, wherein: The first delay circuit includes a first diode, a third resistor, and a first capacitor, wherein an anode of the first diode is connected to a first end of the third resistor, a cathode of the first diode is connected to a second end of the third resistor, a first end of the first capacitor is connected to a cathode of the first diode, a second end of the first capacitor is grounded, an anode of the first diode is connected to a first output end of the differential amplifier circuit, and the first output end outputs a first differential control signal; The first level shifting circuit includes a fifth switch, a second diode, and a sixth switch, wherein a control terminal of the fifth switch is connected to a cathode of the first diode, a first terminal of the fifth switch is connected to a fourth voltage terminal, a second terminal of the fifth switch is connected to an anode of the second diode, a cathode of the second diode is connected to a first terminal of the sixth switch, a control terminal and a second terminal of the sixth switch are connected to a fifth voltage terminal, and a voltage of the fifth voltage terminal is lower than a voltage of the fourth voltage terminal; The first amplifying circuit includes a fourth resistor and a seventh switch, wherein a first end of the fourth resistor is connected to the sixth voltage terminal, a second end of the fourth resistor is connected to the first end of the seventh switch, a control end of the seventh switch is connected to the cathode of the second diode, a second end of the seventh switch is connected to the seventh voltage terminal, a voltage of the seventh voltage terminal is lower than a voltage of the sixth voltage terminal, and a control end of the first switch is connected to a common end of the fourth resistor and the seventh switch.

5. The driving circuit according to claim 4, wherein: The second delay circuit includes a third diode, a fifth resistor, and a second capacitor, wherein an anode of the third diode is connected to a first end of the fifth resistor, a cathode of the third diode is connected to a second end of the fifth resistor, a first end of the second capacitor is connected to a cathode of the third diode, a second end of the second capacitor is grounded, an anode of the third diode is connected to a second output end of the differential amplifier circuit, and the second output end outputs a second differential control signal; The second amplifying circuit includes a sixth resistor and an eighth switch, a first end of the sixth resistor is connected to the eighth voltage terminal, a second end of the sixth resistor is connected to the first end of the eighth switch, a control end of the eighth switch is connected to the cathode of the third diode, and a second end of the eighth switch is connected to a ninth voltage terminal, where a voltage at the ninth voltage terminal is lower than a voltage at the eighth voltage terminal; The first level shifting circuit includes a ninth switch, a fourth diode, and a tenth switch. The control end of the ninth switch is connected to the common end of the sixth resistor and the eighth switch. The first end of the ninth switch is connected to the tenth voltage end. The second end of the ninth switch is connected to the anode of the fourth diode. The cathode of the fourth diode is connected to the first end of the tenth switch. The control end and the second end of the tenth switch are connected to the eleventh voltage end. The voltage of the eleventh voltage end is lower than the voltage of the tenth voltage end. The control end of the second switch is connected to the common end of the fourth diode and the tenth switch.

6. The driving circuit according to claim 5, wherein: The first switch to the tenth switch are all GaN-based HEMT devices.

7. A DC-DC converter, characterized in that: The device comprises a driving circuit and a power amplifier circuit, wherein the power amplifier circuit comprises a first switch and a second switch, and the driving circuit is the driving circuit according to any one of claims 1 to 6.

8. The DC-DC converter according to claim 7, wherein: The DC-DC converter further includes a fifth diode, a sixth diode, a first inductor, a transformer, a seventh diode, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a second inductor and a seventh resistor; The first end of the first switch is connected to the cathode of the fifth diode, the second end of the first switch is connected to the anode of the fifth diode, and the cathode of the fifth diode is connected to the twelfth voltage terminal; The first end of the second switch is connected to the cathode of the sixth diode, the second end of the second switch is connected to the anode of the sixth diode, the cathode of the sixth diode is connected to the anode of the fifth diode, and the anode of the sixth diode is grounded; A first end of the third capacitor is connected to the cathode of the fifth diode, a second end of the third capacitor is connected to the first end of the fourth capacitor, and a second end of the fourth capacitor is grounded; The first end of the first inductor is connected to the cathode of the sixth diode, the second end of the first inductor is connected to the first input end of the transformer, and the second input end of the transformer is connected to the common end of the third capacitor and the fourth capacitor; The first output end of the transformer is connected to the anode of the seventh diode, the second output end of the transformer is grounded, the cathode of the seventh diode is connected to the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the first end of the second inductor is connected to the cathode of the seventh diode, the second end of the second inductor is connected to the first end of the sixth capacitor, the second end of the sixth capacitor is grounded, the first end of the seventh resistor is connected to the second end of the second inductor, and the second end of the seventh resistor is grounded.

9. A power supply system, characterized in that: Includes the DC-DC converter according to claim 7 or 8.

10. An electronic device, characterized in that: Includes the power supply system according to claim 9.

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