A task distribution method, device, equipment and medium based on data aggregation

Abstract

The present invention relates to the field of computer technologies, and in particular, to a task dispatching method, apparatus, device, and medium based on data aggregation. The method includes: receiving bus width data and corresponding addresses from an AXI Slave bus by beat; combining the successively received bus width data according to a preset aggregation rule based on the addresses corresponding to each bus width data to form a number of aggregation tasks, and all the bus width data belonging to the same aggregation task correspond to the same scheduling unit; respectively obtaining configuration parameters corresponding to all the bus width data in each aggregation task from an AHB Slave bus to generate configuration information corresponding to each aggregation task; and dispatching read DDR tasks corresponding to each aggregation task based on the configuration information corresponding to each aggregation task. The solution of the present invention reduces the number of tasks for reading DDR, improves the execution efficiency of the system, significantly increases the running speed of the system, and reduces the consumption of hardware resources of the system.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a task dispatching method, device, equipment, and medium based on data aggregation. Background Art

[0002] In computer science, the AXI bus is an on-chip bus oriented to high performance, high bandwidth, and low latency. The bus address and data phases are separated, supporting unaligned data transmission. Also, in burst transmission, the host only needs to provide the starting address. The bus has separate read and write data channels, and supports outstanding transmission access and out-of-order access, and it is easy to achieve timing convergence by adding registers. AXI is a new high-performance protocol in AMBA. AXI technology enriches the existing AMBA standard content and can meet the requirements of ultra-high performance and complex on-chip system designs. The bus issues data in units of the minimum scheduling unit. However, considering the transmission characteristics of the bus, multiple concurrent bus data transmissions may scatter the data belonging to the same scheduling unit. That is to say, the data actually issued by the bus may be composed of interleaved and serially arranged data smaller than the scheduling unit.

[0003] Currently, the traditional AXI bus task dispatching method is as Figure 1 shown. Its processing flow is as follows: A task is formed according to each bus bit-width data, the corresponding configuration is read, and a task for reading DDR data is dispatched. Since it takes a certain delay to read DDR and obtain the corresponding data, the traditional method of dispatching tasks often requires task caching and cannot be carried out in a pipeline manner. The traditional task dispatching method will occupy a large amount of system cache resources and frequently read DDR, which will seriously affect the execution efficiency of the system. Summary of the Invention

[0004] In view of this, aiming at the deficiencies of the traditional task dispatching method, such as frequently reading DDR, occupying a large amount of bus resources and cache resources, the present invention provides a task dispatching method, device, equipment, and medium based on data aggregation.

[0005] According to a first aspect of the present invention, a task dispatching method based on data aggregation is provided. The method includes:

[0006] Receiving bus bit-width data and corresponding addresses from the AXI Slave bus by beat;

[0007] Combining the sequentially received bus bit-width data based on the addresses corresponding to each bus bit-width data according to a preset aggregation rule to form several aggregation tasks, where each bus bit-width data belonging to the same aggregation task corresponds to the same scheduling unit;

[0008] Obtain the configuration parameters corresponding to all bus bit-width data in each aggregation task from the AHB Slave bus respectively to generate configuration information corresponding to each aggregation task;

[0009] Dispatch the DDR reading tasks corresponding to each aggregation task respectively based on the configuration information corresponding to each aggregation task.

[0010] In some embodiments, the combining the sequentially received bus bit-width data according to a preset aggregation rule based on the address corresponding to each bus bit-width data to form several aggregation tasks includes:

[0011] Compare the address corresponding to the bus bit-width data received in the current cycle with the address corresponding to the bus bit-width data received in the previous cycle;

[0012] In response to the address corresponding to the bus bit-width data received in the current cycle having the same high bits as the address corresponding to the bus bit-width data received in the previous cycle and the difference between the two being equal to a preset value, confirm that the bus bit-width data received in the current cycle and the bus bit-width data received in the previous cycle correspond to the same scheduling unit and are consecutive;

[0013] Otherwise, use the data corresponding to the unaggregated group cycles received in the previous cycle and before as a group to generate an aggregation task;

[0014] In response to receiving a new cycle of bus bit-width data, return to execute the step of comparing the address corresponding to the bus bit-width data received in the current cycle with the address corresponding to the bus bit-width data received in the previous cycle.

[0015] In some embodiments, the combining the sequentially received bus bit-width data according to a preset aggregation rule based on the address corresponding to each bus bit-width data to form several aggregation tasks further includes:

[0016] Statistically count the number of received bus bit-width data in units of the same high bits;

[0017] In response to the bus bit-width data received in the current cycle having a certain high bit and the current total number of data of the certain high bit being equal to a preset quantity, directly use the bus bit-width data received in the current cycle and the data corresponding to the unaggregated group cycles received before as a group to generate an aggregation task.

[0018] In some embodiments, the method further includes:

[0019] Execute the DDR reading tasks corresponding to several aggregation tasks in a pipeline manner.

[0020] According to the second aspect of the present invention, there is provided a task dispatching device based on data aggregation, and the device includes:

[0021] A receiving module, configured to receive bus-width data and corresponding addresses from an AXI Slave bus by beat

[0022] An aggregation module, configured to combine the successively received bus-width data into several aggregation tasks based on the addresses corresponding to each bus-width data according to a preset aggregation rule, wherein all the bus-width data belonging to the same aggregation task correspond to the same scheduling unit;

[0023] A configuration information generation module, configured to obtain configuration parameters corresponding to all the bus-width data in each aggregation task from an AHB Slave bus respectively to generate configuration information corresponding to each aggregation task;

[0024] A dispatching module, configured to dispatch read DDR tasks corresponding to each aggregation task respectively based on the configuration information corresponding to each aggregation task.

[0025] In some embodiments, the aggregation module is further configured to:

[0026] Compare the address corresponding to the bus-width data received in the current beat with the address corresponding to the bus-width data received in the previous beat;

[0027] In response to the address corresponding to the bus-width data received in the current beat and the address corresponding to the bus-width data received in the previous beat having the same high bits and the difference between the two being equal to a preset value, confirm that the bus-width data received in the current beat and the bus-width data received in the previous beat correspond to the same scheduling unit and are continuous;

[0028] Otherwise, use the data corresponding to the unaggregated beats received in the previous beat and before as a group to generate an aggregation task;

[0029] In response to receiving new bus-width data in a beat, return to execute the step of comparing the address corresponding to the bus-width data received in the current beat with the address corresponding to the bus-width data received in the previous beat.

[0030] In some embodiments, the aggregation module is further configured to:

[0031] Count the number of received bus-width data in units of the same high bits;

[0032] In response to the bus-width data received in the current beat being a certain high bit and the current total number of data of the certain high bit being equal to a preset quantity, directly use the bus-width data received in the current beat and the data corresponding to the unaggregated beats received before as a group to generate an aggregation task.

[0033] In some embodiments, the device further includes a module configured to execute the following steps:

[0034] Execute the read DDR tasks corresponding to several aggregation tasks in a pipelined manner.

[0035] According to the third aspect of the present invention, there is also provided a computer device, which includes:

[0036] At least one processor; and

[0037] A memory, where the memory stores a computer program that can run on the processor, and when the processor executes the program, it executes the aforementioned task dispatching method based on data aggregation.

[0038] According to the fourth aspect of the present invention, there is also provided a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, it executes the aforementioned task dispatching method based on data aggregation.

[0039] In the above-mentioned task dispatching method based on data aggregation, by aggregating the data belonging to the same scheduling unit, reading the corresponding configuration after the aggregation is completed, and dispatching the task of reading DDR data, the number of tasks of reading DDR is significantly reduced, and the execution efficiency of the system is improved; at the same time, the data aggregation process does not overlap with the previous task of reading DDR data in terms of time, and pipelining processing can be achieved without task caching, which can significantly improve the running speed of the system and reduce the usage of hardware resources of the system.

[0040] In addition, the present invention also provides a task dispatching device based on data aggregation, a computer device, and a computer-readable storage medium, which can also achieve the above technical effects and will not be elaborated here. Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained based on these drawings without creative efforts.

[0042] Figure 1 Schematic diagram of the task dispatching principle of the traditional AXI Slave bus;

[0043] Figure 2 Schematic diagram of the process of a task dispatching method based on data aggregation provided by an embodiment of the present invention

[0044] Figure 3 Schematic diagram of the task dispatching principle of the AXI Slave bus based on data aggregation provided by an embodiment of the present invention;

[0045] Figure 4 Hardware architecture diagram of the task distribution scheme based on data aggregation mode provided by an embodiment of the present invention;

[0046] Figure 5A Schematic diagram of the overall process of forming all aggregation tasks in a certain scenario;

[0047] Figure 5B For Figure 5A Schematic diagram of generating the corresponding aggregation task 1;

[0048] Figure 5C For Figure 5A Schematic diagram of generating the corresponding aggregation task 2;

[0049] Figure 5D For Figure 5A Schematic diagram of generating the corresponding aggregation task 3;

[0050] Figure 5E For Figure 5A Schematic diagram of generating the corresponding aggregation task 4;

[0051] Figure 5F For Figure 5A Schematic diagram of generating the corresponding aggregation task n;

[0052] Figure 6 Schematic diagram of the structure of a task distribution device based on data aggregation provided by another embodiment of the present invention;

[0053] Figure 7 Internal structure diagram of a computer device in another embodiment of the present invention. Detailed implementation manners

[0054] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0055] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different, so it can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0056] To facilitate the understanding of the solution of the present invention, the following first explains the technical terms that appear in each embodiment:

[0057] DDR (Double Data Rate): DDR is a memory name, which means double data rate synchronous dynamic random access memory, and it is one of the memories.

[0058] AXI (Advanced Extensible Interface): AXI is a bus protocol and an on-chip bus oriented to high performance, high bandwidth, and low latency.

[0059] AHB (Advanced High Performance Bus): AHB is an advanced high performance bus and a bus interface.

[0060] AMBA (Advanced Microcontroller Bus Architecture): AMBA is an advanced microcontroller bus architecture developed by ARM.

[0061] In one embodiment, please refer to Figure 2 and Figure 3 As shown, the present invention provides a task dispatching method 100 based on data aggregation. Specifically, the method includes the following steps:

[0062] Step 101, receive bus bit-width data and corresponding addresses from the AXI Slave bus by beat.

[0063] Step 102, combine the sequentially received bus bit-width data based on the addresses corresponding to each bus bit-width data according to a preset aggregation rule to form several aggregation tasks, where all bus bit-width data belonging to the same aggregation task correspond to the same scheduling unit.

[0064] Step 103, obtain the configuration parameters corresponding to all bus bit-width data in each aggregation task from the AHB Slave bus respectively to generate configuration information corresponding to each aggregation task.

[0065] Step 104, dispatch read DDR tasks corresponding to each aggregation task based on the configuration information corresponding to each aggregation task.

[0066] The above-mentioned task dispatching method based on data aggregation aggregates the data belonging to the same scheduling unit, reads the corresponding configuration after aggregation, and dispatches tasks to read DDR data, thereby significantly reducing the number of tasks to read DDR and improving the execution efficiency of the system; at the same time, the data aggregation process will not overlap with the previous task of reading DDR data in time, enabling pipelining processing without task caching, which can significantly improve the running speed of the system and reduce the usage of system hardware resources.

[0067] In some embodiments, the aforementioned step 102, combining the sequentially received bus bit-width data based on the addresses corresponding to each bus bit-width data according to a preset aggregation rule to form several aggregation tasks includes:

[0068] Compare the address corresponding to the bus width data received in the current beat with the address corresponding to the bus width data received in the previous beat;

[0069] In response to the address corresponding to the bus width data received in the current beat and the address corresponding to the bus width data received in the previous beat having the same high bits and the difference between the two being equal to a preset value, confirm that the bus width data received in the current beat and the bus width data received in the previous beat correspond to the same scheduling unit and are consecutive;

[0070] Otherwise, use the data corresponding to the unaggregated beat counts received in the previous beat and before as a group to generate an aggregation task;

[0071] In response to receiving the bus width data of a new beat, return to execute the step of comparing the address corresponding to the bus width data received in the current beat with the address corresponding to the bus width data received in the previous beat.

[0072] In some embodiments, the aforementioned step 102 of combining the sequentially received bus width data into several aggregation tasks based on the addresses corresponding to each bus width data according to a preset aggregation rule further includes:

[0073] Count the number of received bus width data in units of the same high bits;

[0074] In response to the bus width data received in the current beat being a certain high bit and the current total number of data of the certain high bit being equal to a preset quantity, directly use the bus width data received in the current beat and the data corresponding to the unaggregated beat counts received before as a group to generate an aggregation task.

[0075] In some embodiments, the method further includes:

[0076] Execute the read DDR tasks corresponding to several aggregation tasks in a pipelined manner.

[0077] In yet another embodiment, please refer to Figure 4 as shown Figure 4 is a hardware architecture for implementing a task dispatching method based on data aggregation, mainly including a data aggregation control module and an aggregation task dispatching module. The following will elaborate on these two parts in detail.

[0078] The first part: Data aggregation control module

[0079] The data aggregation control module is responsible for aggregating multiple bus-width data according to the aggregation rule to form a larger aggregation task, then obtaining the corresponding configuration parameters, dispatching the DDR reading task, and reading the corresponding data. Compared with the traditional task dispatching method (each bus-width data will obtain the configuration parameters and dispatch the DDR reading task), the improved data aggregation control can significantly reduce the number of task dispatches, significantly improve the system efficiency, and enable pipelined processing of the read data. The specific implementation method of the data aggregation control module is as follows: Aggregation rule: The serial data of the bus width belongs to the same scheduling unit and the addresses are continuous, or the current bus-width data is the last data of the corresponding scheduling unit.

[0080] Aggregation implementation method: Mark the data and its corresponding address sent by the bus as the "current state". We delay the data and its corresponding address in the current state and mark them as the "previous state". The implementation of aggregation is to determine whether aggregation occurs by comparing the addresses of the current state and the previous state. The judgment condition is: If the high bits of the addresses of the current state and the previous state are equal (specifically depending on the bus address width and the size of the scheduling unit), it means that the data in the current state and the previous state belong to the same scheduling unit; if the address of the current state minus the address of the previous state is equal to the size of the corresponding address of the bus data, it means that the addresses of the data in the current state and the previous state are continuous. If both of the above conditions are met, aggregation occurs, and the data in the current state and the previous state are grouped into the same aggregation task; if not, an aggregation task is generated (the aggregation task is the result of data aggregation). In addition, if the data in the previous state is the last data of the scheduling unit, an aggregation task is directly generated without waiting for the subsequent data addresses for aggregation judgment.

[0081] The second part: Aggregation task dispatching module

[0082] The aggregation task dispatching module reads the corresponding configuration information according to the aggregation tasks formed by data aggregation and dispatches them to each execution agency. Each execution agency reads the data at the corresponding address in the DDR through the pipelined processing method according to the configuration parameters included in the dispatched tasks for data processing by other modules.

[0083] To facilitate the understanding of the solution of the present invention, please combine the following Figure 5A The following scenario is used to illustrate the data aggregation process in detail. It should be noted that Figure 5A The numbers that belong to the same scheduling unit and are consecutive in the address indicate two consecutive addresses, for example: address 1 of scheduling unit 0, address 2 of scheduling unit 0, which belong to the same scheduling unit 0 and the addresses are continuous, and it is assumed that each scheduling unit contains n bus-width data.

[0084] (1) Please combine the following Figure 5BAs shown in the figure, the process of the data aggregation control module generating aggregation task 1 is as follows:

[0085] The previous state address 1 is consecutive with the current state address 2, and both belong to scheduling unit 0, so aggregation occurs;

[0086] The previous state address 2 is consecutive with the current state address 3, and both belong to scheduling unit 0, so aggregation occurs;

[0087] The previous state address 3 is not consecutive with the current state address 8, so no aggregation occurs. The aggregation ends and aggregation task 1 is generated.

[0088] The finally generated aggregation task 1 contains 3 data (scheduling unit 0: data 1, data 2, data 3).

[0089] (2) Please combine with Figure 5C As shown in the figure, the process of the data aggregation control module generating aggregation task 2 is as follows:

[0090] The previous state address 8 is consecutive with the current state address 9, and both belong to scheduling unit 0, so aggregation occurs;

[0091] The previous state address 9 and the current state address 1 do not belong to the same scheduling unit, so no aggregation occurs. The aggregation ends and aggregation task 2 is generated.

[0092] The finally generated aggregation task 2 contains 2 data (scheduling unit 0: data 8, data 9).

[0093] (3) Please combine with Figure 5D As shown in the figure, the process of the data aggregation control module generating aggregation task 3 is as follows:

[0094] The previous state address 1 is consecutive with the current state address 2, and both belong to scheduling unit 1, so aggregation occurs;

[0095] The previous state address 2 is consecutive with the current state address 3, and both belong to scheduling unit 1, so aggregation occurs;

[0096] The previous state address 3 is consecutive with the current state address 4, and both belong to scheduling unit 1, so aggregation occurs;

[0097] The previous state address 4 and the current state address 1 do not belong to the same scheduling unit, so no aggregation occurs. The aggregation ends and aggregation task 3 is generated.

[0098] The finally generated aggregation task 3 contains 4 data (scheduling unit 1: data 1, data 2, data 3, data 4).

[0099] (4) Please combine with Figure 5E As shown in the figure, the process of the data aggregation control module generating aggregation task 4 is as follows:

[0100] The previous beat status address 1 is consecutive with the current status address 2, and both belong to the scheduling unit 5, resulting in aggregation;

[0101] The previous beat status address 2 is consecutive with the current status address 3, and both belong to the scheduling unit 5, resulting in aggregation;

[0102] The previous beat status address 3 and the current status address 1 do not belong to the same scheduling unit, so no aggregation occurs. The aggregation ends and generates the aggregation task 4.

[0103] The finally generated aggregation task 4 contains 3 pieces of data (scheduling unit 5: data 1, data 2, data 3).

[0104] (5) Please combine Figure 5F As shown, the process by which the data aggregation control module generates the aggregation task n is as follows:

[0105] The previous beat status address n - 2 is consecutive with the current status address n - 1, and both belong to the scheduling unit 0, resulting in aggregation;

[0106] The previous beat status address n - 1 is consecutive with the current status address n, and both belong to the scheduling unit 0, resulting in aggregation;

[0107] The previous beat status address n directly generates aggregation for the last data of this scheduling unit. The aggregation ends and generates the aggregation task n.

[0108] The aggregation task n contains 3 pieces of data (scheduling unit 0: data n - 2, data n - 1, data n).

[0109] From the implementation process of generating the aggregation task through the data aggregation control module in this embodiment, it can be seen that compared with the traditional task dispatching method where each bus bit-width data forms a task dispatch, the data aggregation method can aggregate the data belonging to the same scheduling unit to form a larger task, and then notify the aggregation task dispatching module to obtain the configuration information corresponding to the task. This improved method can effectively reduce the amount of tasks and "lighten the burden" on the system and the bus.

[0110] The aggregation task dispatching module processes the n aggregation tasks formed in the above process as follows:

[0111] (1) Read the corresponding configuration according to the aggregation task 1 information and dispatch 1 read DDR task (this aggregation task contains 3 pieces of data). There is no need to cache this task, and the data in DDR is read in a pipelined manner. The traditional method requires reading the configuration 3 times and dispatching 3 read DDR tasks, and at the same time, it is necessary to cache these 3 tasks.

[0112] (2) Read the corresponding configuration according to the aggregation task 2 information, and dispatch 1 DDR reading task (there are 2 data in this aggregation task). There is no need to cache this task, and the data in the DDR is read in a pipeline manner. The traditional method requires reading the configuration 2 times, dispatching 2 DDR reading tasks, and caching these 2 tasks at the same time.

[0113] (3) Read the corresponding configuration according to the aggregation task 3 information, and dispatch 1 DDR reading task (there are 4 data in this aggregation task). There is no need to cache this task, and the data in the DDR is read in a pipeline manner. The traditional method requires reading the configuration 4 times, dispatching 4 DDR reading tasks, and caching these 4 tasks at the same time.

[0114] (4) Read the corresponding configuration according to the aggregation task 4 information, and dispatch 1 DDR reading task (there are 3 data in this aggregation task). There is no need to cache this task, and the data in the DDR is read in a pipeline manner. The traditional method requires reading the configuration 3 times, dispatching 3 DDR reading tasks, and caching these 3 tasks at the same time.

[0115] (5) Read the corresponding configuration according to the aggregation task n information, and dispatch 1 DDR reading task (there are 3 data in this aggregation task). There is no need to cache this task, and the data in the DDR is read in a pipeline manner. The traditional method requires reading the configuration 3 times, dispatching 3 DDR reading tasks, and caching these 3 tasks at the same time.

[0116] Through the above detailed description of the processing process of the aggregation task dispatching module, it can be analyzed that the method of the present invention has the following advantages: Since the data belonging to the same scheduling space is aggregated according to the aggregation rule, the number of task dispatches for reading the DDR is reduced, the number of external DDR accesses is reduced, and the bus occupancy rate is significantly reduced. Since the data aggregation process does not overlap with the previous task of reading DDR data in time, the pipeline processing of reading data can be realized without task caching. This method can significantly improve the running speed and efficiency of the system and save the cache resources of the system.

[0117] In another embodiment, please refer to Figure 6 As shown, the present invention also provides a task dispatching device 200 based on data aggregation. The device includes:

[0118] A receiving module 201, configured to receive the bus width data and the corresponding address from the AXI Slave bus by beat.

[0119] An aggregation module 202, configured to combine the sequentially received bus width data according to a preset aggregation rule based on the address corresponding to each bus width data to form several aggregation tasks, where each bus width data belonging to the same aggregation task corresponds to the same scheduling unit;

[0120] The configuration information generation module 203 is configured to respectively obtain configuration parameters corresponding to all bus bit-width data in each aggregation task from the AHB Slave bus to generate configuration information corresponding to each aggregation task.

[0121] The dispatching module 204 is configured to respectively dispatch read DDR tasks corresponding to each aggregation task based on the configuration information corresponding to each aggregation task.

[0122] In the above task dispatching device based on data aggregation, by aggregating data belonging to the same scheduling unit, reading the corresponding configuration after aggregation is completed, and dispatching tasks for reading DDR data, the number of tasks for reading DDR is significantly reduced, and the execution efficiency of the system is improved. At the same time, the data aggregation process does not overlap with the previous task of reading DDR data in terms of time, enabling pipelining processing without task caching, which can significantly improve the running speed of the system and reduce the usage of hardware resources of the system.

[0123] In some embodiments, the aggregation module 202 is further configured to:

[0124] Compare the address corresponding to the bus bit-width data received in the current beat with the address corresponding to the bus bit-width data received in the previous beat.

[0125] In response to the address corresponding to the bus bit-width data received in the current beat and the address corresponding to the bus bit-width data received in the previous beat having the same high bits and the difference between the two being equal to a preset value, it is confirmed that the bus bit-width data received in the current beat and the bus bit-width data received in the previous beat correspond to the same scheduling unit and are consecutive.

[0126] Otherwise, the data corresponding to the unaggregated beats received in the previous beat and before is used as a group to generate an aggregation task.

[0127] In response to receiving new bus bit-width data in a beat, return to execute the step of comparing the address corresponding to the bus bit-width data received in the current beat with the address corresponding to the bus bit-width data received in the previous beat.

[0128] In some embodiments, the aggregation module 202 is further configured to:

[0129] Count the number of received bus bit-width data in units of the same high bits.

[0130] In response to the bus bit-width data received in the current beat being a certain high bit and the current total number of data of the certain high bit being equal to a preset quantity, directly use the bus bit-width data received in the current beat and the data corresponding to the unaggregated beats received before as a group to generate an aggregation task.

[0131] In some embodiments, the device further includes a module configured to perform the following steps:

[0132] Execute the read DDR tasks corresponding to a number of aggregation tasks in a pipelined manner.

[0133] It should be noted that the specific limitations on the task dispatching device based on data aggregation can be referred to the limitations on the task dispatching method based on data aggregation in the above text, and will not be elaborated here. Each module in the above task dispatching device based on data aggregation can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0134] According to another aspect of the present invention, a computer device is provided. The computer device can be a server, and its internal structure diagram is shown in Figure 7 as follows. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the task dispatching method based on data aggregation described above is implemented. Specifically, the method includes the following steps:

[0135] Receive bus width data and corresponding addresses from the AXI Slave bus by beat number;

[0136] Based on the addresses corresponding to each bus width data, combine the sequentially received bus width data according to a preset aggregation rule to form a number of aggregation tasks, where all bus width data belonging to the same aggregation task correspond to the same scheduling unit;

[0137] Obtain the configuration parameters corresponding to all bus width data in each aggregation task from the AHB Slave bus respectively to generate configuration information corresponding to each aggregation task;

[0138] Dispatch the read DDR tasks corresponding to each aggregation task based on the configuration information corresponding to each aggregation task.

[0139] In some embodiments, the combining the sequentially received bus width data according to a preset aggregation rule based on the addresses corresponding to each bus width data to form a number of aggregation tasks includes:

[0140] Compare the address corresponding to the bus width data received in the current beat with the address corresponding to the bus width data received in the previous beat;

[0141] In response to the address corresponding to the bus width data received in the current beat having the same high bits as the address corresponding to the bus width data received in the previous beat and the difference between the two being equal to a preset value, it is confirmed that the bus width data received in the current beat and the bus width data received in the previous beat correspond to the same scheduling unit and are consecutive;

[0142] Otherwise, use the data corresponding to the unaggregated beats received in the previous beat and before as a group to generate an aggregation task;

[0143] In response to receiving the bus width data of a new beat, return to execute the step of comparing the address corresponding to the bus width data received in the current beat with the address corresponding to the bus width data received in the previous beat.

[0144] In some embodiments, the combining the successively received bus width data according to a preset aggregation rule based on the address corresponding to each bus width data to form a number of aggregation tasks further includes:

[0145] Count the number of received bus width data in units of the same high bits;

[0146] In response to the bus width data received in the current beat being a certain high bit and the current total number of data of the certain high bit being equal to a preset quantity, directly use the bus width data received in the current beat and the data corresponding to the unaggregated beats received before as a group to generate an aggregation task.

[0147] In some embodiments, the method further includes:

[0148] Execute the read DDR tasks corresponding to a number of aggregation tasks in a pipeline manner.

[0149] According to another aspect of the present invention, there is provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the above-mentioned task dispatching method based on data aggregation. Specifically, it includes performing the following steps:

[0150] Receive bus width data and corresponding addresses from the AXI Slave bus by beat;

[0151] Combine the successively received bus width data according to a preset aggregation rule based on the address corresponding to each bus width data to form a number of aggregation tasks, wherein each bus width data belonging to the same aggregation task corresponds to the same scheduling unit;

[0152] Obtain the configuration parameters corresponding to all bus bit-width data in each aggregation task from the AHB Slave bus respectively to generate configuration information corresponding to each aggregation task;

[0153] Dispatch the read DDR tasks corresponding to each aggregation task respectively based on the configuration information corresponding to each aggregation task.

[0154] In some embodiments, the combining the sequentially received bus bit-width data according to a preset aggregation rule based on the address corresponding to each bus bit-width data to form several aggregation tasks includes:

[0155] Compare the address corresponding to the bus bit-width data received in the current cycle with the address corresponding to the bus bit-width data received in the previous cycle;

[0156] In response to the address corresponding to the bus bit-width data received in the current cycle and the address corresponding to the bus bit-width data received in the previous cycle having the same high bits and the difference between the two being equal to a preset value, confirm that the bus bit-width data received in the current cycle and the bus bit-width data received in the previous cycle correspond to the same scheduling unit and are consecutive;

[0157] Otherwise, use the data corresponding to the non-aggregated previous cycles and the previous received data as a group to generate an aggregation task;

[0158] In response to receiving the bus bit-width data of a new cycle, return to execute the step of comparing the address corresponding to the bus bit-width data received in the current cycle with the address corresponding to the bus bit-width data received in the previous cycle.

[0159] In some embodiments, the combining the sequentially received bus bit-width data according to a preset aggregation rule based on the address corresponding to each bus bit-width data to form several aggregation tasks further includes:

[0160] Count the number of received bus bit-width data in units of the same high bits;

[0161] In response to the bus bit-width data received in the current cycle having a certain high bit and the current total number of data of the certain high bit being equal to a preset quantity, directly use the bus bit-width data received in the current cycle and the data corresponding to the non-aggregated previous received cycles as a group to generate an aggregation task.

[0162] In some embodiments, the method further includes:

[0163] Execute the read DDR tasks corresponding to several aggregation tasks in a pipelined manner.

[0164] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0165] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0166] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A task dispatching method based on data aggregation, characterized in that The method includes: Receiving bus bit-width data and corresponding addresses from the AXI Slave bus by beat; Combining the sequentially received bus bit-width data based on the addresses corresponding to each bus bit-width data according to a preset aggregation rule to form a number of aggregation tasks, where all bus bit-width data belonging to the same aggregation task correspond to the same scheduling unit; Obtaining the configuration parameters corresponding to all bus bit-width data in each aggregation task from the AHB Slave bus respectively to generate configuration information corresponding to each aggregation task; Dispatching read DDR tasks corresponding to each aggregation task based on the configuration information corresponding to each aggregation task; The combining the sequentially received bus bit-width data based on the addresses corresponding to each bus bit-width data according to a preset aggregation rule to form a number of aggregation tasks includes: Comparing the address corresponding to the bus bit-width data received in the current beat with the address corresponding to the bus bit-width data received in the previous beat; In response to the address corresponding to the bus bit-width data received in the current beat having the same high bits as the address corresponding to the bus bit-width data received in the previous beat and the difference between the two being equal to a preset value, it is confirmed that the bus bit-width data received in the current beat and the bus bit-width data received in the previous beat correspond to the same scheduling unit and are consecutive; Otherwise, taking the data corresponding to the previous beat and the non-aggregated beats received before as a group to generate an aggregation task; In response to receiving new beat bus bit-width data, returning to execute the step of comparing the address corresponding to the bus bit-width data received in the current beat with the address corresponding to the bus bit-width data received in the previous beat.

2. The task dispatching method based on data aggregation according to claim 1, wherein The combining the sequentially received bus bit-width data based on the addresses corresponding to each bus bit-width data according to a preset aggregation rule to form a number of aggregation tasks further includes: Counting the number of received bus bit-width data in units of the same high bits; In response to the bus bit-width data received in the current beat being a certain high bit and the current total number of data of the certain high bit being equal to a preset quantity, directly taking the bus bit-width data received in the current beat and the data corresponding to the non-aggregated beats received before as a group to generate an aggregation task.

3. The task dispatching method based on data aggregation according to claim 1, wherein The method further includes: Executing the read DDR tasks corresponding to a number of aggregation tasks in a pipelined manner.

4. A task dispatching device based on data aggregation, characterized in that, The apparatus includes: A receiving module configured to receive bus bit-width data and corresponding addresses from the AXI Slave bus by beat; An aggregation module configured to combine the sequentially received bus bit-width data based on the addresses corresponding to each bus bit-width data according to a preset aggregation rule to form a number of aggregation tasks, where all bus bit-width data belonging to the same aggregation task correspond to the same scheduling unit; A configuration information generation module configured to obtain the configuration parameters corresponding to all bus bit-width data in each aggregation task from the AHB Slave bus respectively to generate configuration information corresponding to each aggregation task; A dispatching module configured to dispatch read DDR tasks corresponding to each aggregation task based on the configuration information corresponding to each aggregation task; The aggregation module is further configured to: Compare the address corresponding to the bus bit-width data received in the current beat with the address corresponding to the bus bit-width data received in the previous beat; In response to the address corresponding to the bus bit-width data received in the current beat and the address corresponding to the bus bit-width data received in the previous beat having the same high bits and the difference between the two being equal to a preset value, confirm that the bus bit-width data received in the current beat and the bus bit-width data received in the previous beat correspond to the same scheduling unit and are consecutive; Otherwise, use the data corresponding to the unaggregated beats received in the previous beat and before as a group to generate an aggregation task; In response to receiving the bus bit-width data of a new beat, return to execute the step of comparing the address corresponding to the bus bit-width data received in the current beat with the address corresponding to the bus bit-width data received in the previous beat.

5. The task dispatching device based on data aggregation according to claim 4, wherein, The aggregation module is further configured to: Count the number of bus bit-width data received in units of the same high bits; In response to the bus bit-width data received in the current beat being a certain high bit and the current total number of data of the certain high bit being equal to a preset quantity, directly use the bus bit-width data received in the current beat and the data corresponding to the unaggregated beats received before as a group to generate an aggregation task.

6. The task dispatching device based on data aggregation according to claim 4, wherein The device further includes a module configured to execute the following steps: Execute the read DDR tasks corresponding to a number of aggregation tasks in a pipelined manner.

7. A computer device, characterized in that, Comprising: At least one processor; And A memory, the memory stores a computer program that can run in the processor, and when the processor executes the program, it executes the method according to any one of claims 1-3.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it executes the method according to any one of claims 1-3.

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