A driving control circuit, a control method thereof, and a display device

Abstract

The present disclosure discloses a driving control circuit, a control method thereof, and a display device. By providing a first control circuit and a level conversion circuit, a discharge enable signal can be output by the first control circuit when a data transmission control signal is abnormal or during shutdown. After receiving the discharge enable signal, the level conversion circuit can control the sub-pixels in the display panel to release charges according to the discharge enable signal. In this way, when the data transmission control signal is abnormal, the sub-pixels in the display panel can be timely controlled to release charges, so that the display panel can be timely turned off, which is equivalent to displaying a black screen, thereby comparing the display anomaly. Moreover, during shutdown, the sub-pixels in the display panel can also be timely controlled to release charges, avoiding display anomalies when powering on again.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a drive control circuit, a control method thereof, and a display device. Background Art

[0002] In displays such as liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), etc., generally multiple pixel units are included. Each pixel unit may include: a red sub-pixel, a green sub-pixel, and a blue sub-pixel. By controlling the brightness corresponding to each sub-pixel, the desired displayed color is mixed to display a color image. Summary of the Invention

[0003] The drive control circuit provided by an embodiment of the present disclosure includes:

[0004] A first control circuit configured to output a discharge enable signal when a data transmission control signal is abnormal and during shutdown;

[0005] A level conversion circuit configured to receive the discharge enable signal and control the sub-pixels in the display panel to release charges according to the discharge enable signal;

[0006] Wherein, the first control circuit includes: a timing controller and a discharge trigger circuit; wherein, a first pin of the timing controller is coupled to the discharge trigger circuit, and the timing controller is configured to output a discharge trigger signal through the first pin when the data transmission control signal is abnormal and during the shutdown; the discharge trigger circuit is respectively coupled to a first power supply terminal, a second power supply terminal, and the level conversion circuit, and the discharge trigger circuit is configured to receive the discharge trigger signal when the data transmission control signal is abnormal, and output the discharge enable signal according to the discharge trigger signal and the signal of the first power supply terminal; and during the shutdown, output the discharge enable signal according to the signals of the first power supply terminal and the second power supply terminal;

[0007] Alternatively, the first control circuit includes: a power conversion circuit; wherein, a reset pin of the power conversion circuit is coupled to the level conversion circuit; the power conversion circuit is configured to output the discharge enable signal through the reset pin when the data transmission control signal is abnormal and during shutdown.

[0008] In some examples, the discharge trigger circuit includes a first transistor, a second transistor, a first resistor, and a second resistor;

[0009] The control terminal of the first transistor is coupled to the first pin of the timing controller, the first terminal of the first transistor is coupled to the ground terminal, and the second terminal of the first transistor is coupled to the control terminal of the second transistor and the first terminal of the first resistor respectively;

[0010] The second terminal of the first resistor is coupled to the first power supply terminal;

[0011] The first terminal of the second transistor is coupled to the ground terminal, and the second terminal of the second transistor is coupled to the first terminal of the second resistor and the level conversion circuit respectively;

[0012] The second terminal of the second resistor is coupled to the second power supply terminal.

[0013] In some examples, the level conversion circuit is further configured to send the signal of the first effective level reference signal terminal to the gate driving circuit in the display panel according to the discharge enable signal, and control the gate driving circuit to output an effective level to each coupled gate line, so as to control the sub-pixels in the display panel to release charges;

[0014] The level conversion circuit is further configured to generate a clock signal according to the signals of the second effective level reference signal terminal and the invalid level reference signal terminal, and send the generated clock signal to the gate driving circuit in the display panel to control the gate driving circuit to drive the gate line.

[0015] In some examples, the first effective level reference signal terminal and the second effective level reference signal terminal are the same signal terminal.

[0016] In some examples, the drive control circuit further includes: a voltage stabilizing capacitor; the first terminal of the voltage stabilizing capacitor is coupled to the first effective level reference signal terminal, and the second terminal of the voltage stabilizing capacitor is coupled to the fixed voltage terminal.

[0017] In some examples, the voltage stabilizing capacitor is integrally provided with the level conversion circuit.

[0018] In some examples, the first effective level reference signal terminal and the second effective level reference signal terminal are different signal terminals.

[0019] In some examples, the voltage discharge rate of the first effective level reference signal terminal is less than the voltage discharge rate of the second effective level reference signal terminal.

[0020] The display device provided by the embodiments of the present disclosure includes a display panel and the above drive control circuit.

[0021] The control method of the above drive control circuit provided by the embodiments of the present disclosure includes:

[0022] When the data transmission control signal is abnormal, the first control circuit outputs a discharge enable signal; the level conversion circuit receives the discharge enable signal and controls the sub-pixels in the display panel to release charges according to the discharge enable signal.

[0023] When powering off, the first control circuit outputs a discharge enable signal; the level conversion circuit receives the discharge enable signal and controls the sub-pixels in the display panel to release charges according to the discharge enable signal. Description of the Drawings

[0024] Figure 1 Some structural schematic diagrams of the display device in the embodiments of the present disclosure;

[0025] Figure 2 Some structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0026] Figure 3 Some other structural schematic diagrams of the display device in the embodiments of the present disclosure;

[0027] Figure 4 Some signal timing diagrams in the embodiments of the present disclosure;

[0028] Figure 5 Some structural schematic diagrams of the shift register in the embodiments of the present disclosure;

[0029] Figure 6 Some other signal timing diagrams in the embodiments of the present disclosure;

[0030] Figure 7 Some other structural schematic diagrams of the display device in the embodiments of the present disclosure;

[0031] Figure 8 Some other signal timing diagrams in the embodiments of the present disclosure;

[0032] Figure 9 Some other signal timing diagrams in the embodiments of the present disclosure;

[0033] Figure 10 Some other structural schematic diagrams of the display device in the embodiments of the present disclosure;

[0034] Figure 11 Some other structural schematic diagrams of the display device in the embodiments of the present disclosure;

[0035] Figure 12 Some other structural schematic diagrams of the display device in the embodiments of the present disclosure. Detailed Description of the Embodiments

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. And, without conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0038] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure. And, the same or similar reference numerals throughout denote the same or similar elements or elements having the same or similar functions.

[0039] As Figure 1 shown in Figure 2 the display device provided by the embodiments of the present disclosure includes a display panel 100 and a driving and control circuit 200. Among them, the display panel 100 may include: a plurality of pixel units arranged in an array, a plurality of gate lines (for example, GA1, GA2, GA3, GA4), a plurality of data lines (for example, DA1, DA2, DA3), a gate driving circuit 110, and a source driving circuit 120. The gate driving circuit 110 is respectively coupled to the gate lines GA1, GA2, GA3, GA4, and the source driving circuit 120 is respectively coupled to the data lines DA1, DA2, DA3. Exemplarily, each pixel unit includes a plurality of sub-pixels SPX. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed through red, green, and blue to achieve color display. Or, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed through red, green, blue, and white to achieve color display. Of course, in actual applications, the emission colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0040] As Figure 2 , each sub-pixel SPX may include a transistor 01 and a pixel electrode 02. Among them, a row of sub-pixels SPX corresponds to a gate line, and a column of sub-pixels SPX corresponds to a data line. The gate of the transistor 01 is electrically connected to the corresponding gate line, the source of the transistor 01 is electrically connected to the corresponding data line, and the drain of the transistor 01 is electrically connected to the pixel electrode 02. It should be noted that the pixel array structure of the present disclosure may also be a double-gate structure, that is, two gate lines are provided between adjacent rows of sub-pixels. This arrangement can reduce the number of data lines by half, that is, some adjacent columns of sub-pixels include data lines, and some adjacent columns of sub-pixels do not include data lines. The specific arrangement structure of sub-pixels and the arrangement mode of data lines and scan lines are not limited.

[0041] In the embodiments of the present disclosure, the display panel in the embodiments of the present disclosure may be a liquid crystal display panel. Exemplarily, a liquid crystal display panel generally includes an upper substrate and a lower substrate that are opposed to each other, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate. When displaying a picture, since there is a voltage difference between the data voltage applied to the pixel electrode of each sub-pixel SPX and the common electrode voltage VCOM on the common electrode, this voltage difference can form an electric field, so that the liquid crystal molecules are deflected under the action of this electric field. Since different intensities of the electric field cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixel SPX is different, so that the light emitted by the backlight module passes through the sub-pixels SPX with different transmittances to achieve different gray-scale brightnesses, and then the picture display is realized.

[0042] The applicant has found that: in practical applications, the system circuit obtains the display data of one frame, generates a data transmission control signal according to the display data, then sequentially sends out the display data according to the data transmission control signal, and also sends out the generated data transmission control signal. However, due to the existence of certain adverse factors, the output data transmission control signal will be abnormal, which will cause the display panel to display an abnormal picture. For example, due to the abnormality of the data transmission control signal, the sub-pixels in the display panel cannot release charges in time, resulting in the phenomenon of tidal black screen.

[0043] Based on this, as Figure 1 shown, the embodiments of the present disclosure provide a driving control circuit 200, including:

[0044] A first control circuit 210, configured to output a discharge enable signal when the data transmission control signal is abnormal and during shutdown;

[0045] A level conversion circuit 220, configured to receive the discharge enable signal and control the sub-pixels in the display panel to release charges according to the discharge enable signal.

[0046] The driving control circuit provided by the embodiments of the present disclosure can output a discharge enable signal through the first control circuit when the data transmission control signal is abnormal and during shutdown by setting the first control circuit and the level conversion circuit. After receiving the discharge enable signal, the level conversion circuit can control the sub-pixels in the display panel to release charges according to the discharge enable signal. In this way, when the data transmission control signal is abnormal, the sub-pixels in the display panel can be timely controlled to release charges, so that the display panel is timely turned off, which is equivalent to displaying a black screen, thereby comparing the display abnormality. Moreover, during shutdown, the sub-pixels in the display panel can also be timely controlled to release charges to avoid display abnormality when powering on again.

[0047] In some embodiments of the present disclosure, as Figure 3 shown in Figure 4 FIG. 7, the driving control circuit 200 may further include: a system circuit 230 and a power conversion circuit 240. Among them, the system circuit 230 is configured to output a power supply voltage VCC1 to the power conversion circuit 240, obtain display data of the picture to be displayed, generate a data transmission control signal according to the display data, then sequentially send the display data to the timing controller 211 according to the data transmission control signal, and also send the generated data transmission control signal to the timing controller 211. The timing controller 211 generates reference clock control signals cks1-cks12 according to the received data transmission control signal, and sends the generated reference clock control signals cks1-cks12 to the level conversion circuit 220. The level conversion circuit 220 generates clock signals ck1-ck12 according to the reference clock control signals cks1-cks12, a first reference voltage VREF1, and a second reference voltage VREF2, and sends the generated clock signals ck1-ck12 to the gate driving circuit in the display panel to control the gate driving circuit to drive the gate lines to control the transistors in the sub-pixels to conduct. The timing controller 211 also sends the display data to the source driving circuit 120, and the source driving circuit 120 loads a data voltage on the data lines in the display panel 100 according to the received display data. In this way, when the transistors in the sub-pixels are conducting, the data voltage on the data lines can be input into the pixel electrodes, so that the sub-pixels can achieve their brightness, thereby realizing the function of picture display.

[0048] In some embodiments of the present disclosure, the gate driving circuit 110 includes a plurality of cascaded shift registers, and the driving output terminal Output of one shift register is coupled to one gate line. Moreover, the signal input terminal Input of the first-stage shift register is coupled to the frame trigger signal terminal, and in each adjacent two-stage shift register, the signal input terminal Input of the next-stage shift register is coupled to the driving output terminal Output of the previous-stage shift register. Exemplarily, as Figure 5As shown, the shift register includes transistors M1 to M4 and capacitor C1. Moreover, the shift register is coupled to an input signal terminal Input, a reset signal terminal Reset, a clock signal terminal CLK, a low-level reference signal terminal VGL, and a driving output terminal Output. And, the reset signal terminal Reset is used to receive a frame reset signal. It should be noted that the working process of this shift register can be the same as that in the related art and will not be elaborated here.

[0049] In some embodiments of the present disclosure, as Figures 4 to 6 shown, clock signals ck1 to ck12 can be input to the clock signal terminal CLK of the shift register, so that the driving output terminal Output of the shift register outputs gate scanning signals ga1 to ga12 to the gate lines. The gate scanning signals ga1 to ga12 respectively represent the signals on the gate lines GA1 to GA12. Also, a first reference voltage VREF1 is used to generate the high-level voltage of the clock signals ck1 to ck12, that is, the high-level voltage of the clock signals ck1 to ck12 is the first reference voltage VREF1. A second reference voltage VREF2 is used to generate the low-level voltage of the clock signals ck1 to ck12, that is, the low-level voltage of the clock signals ck1 to ck12 is the second reference voltage VREF2. This makes the high-level voltage of the gate scanning signals ga1 to ga12 also be the first reference voltage VREF1, and the low-level voltage also be the second reference voltage VREF2.

[0050] In some embodiments of the present disclosure, the level conversion circuit 220 is configured to generate a clock signal according to the signals of the second valid level reference signal terminal and the invalid level reference signal terminal VL, and send the generated clock signal to the gate driving circuit in the display panel to control the gate driving circuit to drive the gate lines. Exemplarily, the signal of the second valid level reference signal terminal is a signal having the first reference voltage VREF1, and the signal of the invalid level reference signal terminal VL is a signal having the second reference voltage VREF2.

[0051] In some embodiments of the present disclosure, as Figure 3 shown, the power conversion circuit 240 is configured to receive the power supply voltage VCC1, supply power to itself, and output a timing power supply voltage VTCON to the timing controller 211 and a second power supply voltage V to the second power supply terminal VDD2 according to the power supply voltage VCC1 VDD2, output the first reference voltage VREF1 to the second active-level reference signal terminal, and output the second reference voltage VREF2 to the inactive-level reference signal terminal VL. That is to say, the level conversion circuit 220 is configured to generate a clock signal according to the signals of the second active-level reference signal terminal and the inactive-level reference signal terminal VL and the reference clock control signal, and send the generated clock signal to the gate driving circuit in the display panel to control the gate driving circuit to drive the gate lines. Moreover, the timing controller 211 receives the timing power supply voltage VTCON to supply power to itself to implement the functions of the timing controller 211 itself.

[0052] In some embodiments of the present disclosure, as Figure 3 shown, the first control circuit 210 may include: a timing controller 211 and a discharge trigger circuit 212; wherein, the first pin PIN1 of the timing controller 211 is coupled to the discharge trigger circuit 212, and the timing controller 211 is configured to output a discharge trigger signal through the first pin PIN1 when the data transmission control signal is abnormal and during shutdown. The discharge trigger circuit 212 is respectively coupled to the first power supply terminal VDD1, the second power supply terminal VDD2, and the level conversion circuit 220, and the discharge trigger circuit 212 is configured to receive the discharge trigger signal when the data transmission control signal is abnormal, and output a discharge enable signal according to the discharge trigger signal and the signal of the first power supply terminal VDD1; and during shutdown, output a discharge enable signal according to the signals of the first power supply terminal VDD1 and the second power supply terminal VDD2. Exemplarily, the system circuit 230 outputs the first power supply voltage V VDD1 .

[0053] In some embodiments of the present disclosure, as Figure 7 shown, the discharge trigger circuit 212 includes a first transistor T1, a second transistor T2, a first resistor R1, and a second resistor R2. Among them, the control end of the first transistor T1 is coupled to the first pin PIN1 of the timing controller 211, the first end of the first transistor T1 is coupled to the ground terminal, and the second end of the first transistor T1 is respectively coupled to the control end of the second transistor T2 and the first end of the first resistor R1; the second end of the first resistor R1 is coupled to the first power supply terminal VDD1; the first end of the second transistor T2 is coupled to the ground terminal, and the second end of the second transistor T2 is respectively coupled to the first end of the second resistor R2 and the level conversion circuit 220; the second end of the second resistor R2 is coupled to the second power supply terminal VDD2.

[0054] Exemplarily, the resistance values of the first resistor R1 and the second resistor R2 may be the same or different, and their specific values can be determined according to the requirements of actual applications and are not limited herein.

[0055] Exemplarily, the first transistor T1 and the second transistor T2 may be Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Its control terminal may be a gate, the first terminal may be a source, and the second terminal may be a drain. Alternatively, its control terminal is a gate, the first terminal is a drain, and the second terminal is a source, which is not limited herein.

[0056] Exemplarily, as Figure 7 shown, the first transistor T1 and the second transistor T2 are N-type transistors. Of course, the first transistor T1 and the second transistor T2 may also be P-type transistors, which is not limited herein.

[0057] Exemplarily, the first pin PIN1 of the timing controller 211 may be a General-purpose input / output (GPIO) interface. Of course, in practical applications, the first pin PIN1 of the timing controller 211 may also be an interface in other forms, which is not limited herein.

[0058] In the embodiments of the present disclosure, the level conversion circuit 220 is further configured to send the signal of the first effective level reference signal terminal VGH1 to the gate driving circuit 110 in the display panel according to the discharge enable signal, and control the gate driving circuit 110 to output an effective level to each coupled gate line, so as to control the sub-pixels in the display panel to release charges. In some embodiments of the present disclosure, the first effective level reference signal terminal VGH1 and the second effective level reference signal terminal may be set as the same signal terminal. For example, Figure 7 shown, only the first effective level reference signal terminal VGH1 is schematically shown. This can reduce the number of signal lines and the wiring difficulty.

[0059] In some embodiments of the present disclosure, as Figure 7 shown, the drive control circuit 200 further includes: a voltage stabilizing capacitor Cs; the first end of the voltage stabilizing capacitor Cs is coupled to the first effective level reference signal terminal VGH1, and the second end of the voltage stabilizing capacitor Cs is coupled to the fixed voltage terminal VGN. Exemplarily, the fixed voltage terminal VGN may be a ground terminal. Optionally, the voltage stabilizing capacitor is integrally provided with the level conversion circuit 220 to improve the integration degree. By providing the voltage stabilizing capacitor coupled to the first effective level reference signal terminal VGH1, the voltage drop rate of the first effective level reference signal terminal VGH1 can be reduced, the charge release time of the sub-pixels can be further increased, and the discharge can be further ensured to be complete.

[0060] The embodiments of the present disclosure also provide a control method for a driving control circuit, including: when a data transmission control signal is abnormal, a first control circuit outputs a discharge enable signal; a level conversion circuit receives the discharge enable signal and controls sub-pixels in a display panel to release charges according to the discharge enable signal.

[0061] The following combines Figure 3 , Figure 7 and Figure 8 , to illustrate the working process of the driving control circuit provided by the embodiments of the present disclosure. Among them, Fm_1 is a display frame during normal display. Among them, the T11 stage in Fm_1 is the data refresh stage, and the T12 stage is the frame reset stage. Fm_a + 1 is a display frame when the data transmission control signal is abnormal. There may be a normal display frames between the display frames Fm_1 and Fm_a + 1, or there may be no interval. It is only illustrated by taking the example of an interval of a normal display frames. And, taking a clock signal ck1 as an example, stv represents the signal at the frame trigger signal terminal, and res represents the frame reset signal received by the reset signal terminal Reset. And, the first power supply voltage V VDD1 of the first power supply terminal VDD1 is at a high level, and the second power supply voltage V VDD2 of the second power supply terminal VDD2 is at a high level.

[0062] In the T11 stage of the display frame Fm_1, the system circuit 230 outputs the power supply voltage VCC1 to the power conversion circuit 240 and obtains the display data of the to-be-displayed picture, and generates a data transmission control signal according to the display data, and then sequentially sends the display data to the timing controller 211 according to the data transmission control signal, and also sends the generated data transmission control signal to the timing controller 211. The power conversion circuit 240 receives the power supply voltage VCC1, powers itself and outputs the timing power supply voltage VTCON to the timing controller 211 according to the power supply voltage VCC1, and outputs the second power supply voltage V VDD2, output the first reference voltage VREF1 to the second valid level reference signal terminal, and output the second reference voltage VREF2 to the invalid level reference signal terminal VL. The timing controller 211 receives the timing power supply voltage VTCON to supply power to itself, and receives the data transmission control signal, and detects the received data transmission control signal. If it is determined that the data transmission control signal is normal, the first pin PIN1 is pulled high to set the level of the first pin PIN1 to a high level, then the first transistor T1 is turned on, thereby pulling down the level of the control terminal of the second transistor T2 to control the second transistor T2 to turn off. Since the level of the second power supply terminal VDD2 is high, the second end of the second transistor T2 is pulled high by the voltage of the second power supply terminal VDD2, that is, the level of the second end of the second transistor T2 is high. When the level of the second end of the second transistor T2 is high, the level conversion circuit 220 does not turn on the discharge function. The timing controller 211 also generates a reference clock control signal according to the data transmission control signal, and sends the generated reference clock control signal to the level conversion circuit 220. The level conversion circuit 220 does not turn on the discharge function, and generates a clock signal ck1 according to the reference clock control signal, the first reference voltage VREF1, and the second reference voltage VREF2, and sends the generated clock signal ck1 to the gate driving circuit in the display panel to control the gate driving circuit to drive the gate lines to control the transistors in the sub-pixels to turn on. The timing controller 211 also sends the display data to the source driving circuit 120, and the source driving circuit 120 loads the data voltage on the data lines in the display panel 100 according to the received display data. In this way, when the transistor in the sub-pixel is turned on, the data voltage on the data line can be input into the pixel electrode, so that the sub-pixel can achieve its brightness, thereby realizing the function of picture display.

[0063] In the T12 stage of the display frame Fm_1, the frame reset signal controls all the PU nodes and the driving output terminals of the shift registers to be pulled low for reset.

[0064] In the display frame Fm_a+1, the system circuit 230 outputs the power supply voltage VCC1 to the power conversion circuit 240, obtains the display data of the picture to be displayed, generates a data transmission control signal according to the display data, then sequentially sends the display data to the timing controller 211 according to the data transmission control signal, and also sends the generated data transmission control signal to the timing controller 211. Due to the abnormality of the data transmission control signal, the power management circuit 240 stops outputting voltage based on the protection mechanism. However, due to the function of the capacitors in each component, the voltages at each signal terminal do not immediately drop to 0V, but slowly drop to 0V. That is to say, the timing controller 211 can still supply power to itself for a period of time according to the timing power supply voltage VTCON, receive the data transmission control signal, detect the received data transmission control signal, determine that the data transmission control signal is abnormal, and then pull down the first pin PIN1 to set the level of the first pin PIN1 to a low level, so that the first transistor T1 is turned off. Due to the abnormality of the data transmission control signal, the power management circuit 240 stops outputting voltage based on the protection mechanism. Therefore, there is no voltage input to the second power supply terminal VDD2, that is, the level of the second power supply terminal VDD2 is a low level. Although the power management circuit 240 stops outputting voltage, the system circuit 230 still continues to work. Therefore, there is still voltage input to the first power supply terminal VDD1, that is, the level of the first power supply terminal VDD1 is a high level. Thus, the level of the control terminal of the second transistor T2 is pulled up to control the second transistor T2 to conduct, so that the second terminal of the second transistor T2 is pulled down by the voltage of the ground terminal, that is, the level of the second terminal of the second transistor T2 is a low level. When the level of the second terminal of the second transistor T2 is a low level, the level conversion circuit 220 turns on the discharge function to send the signal of the first effective level reference signal terminal VGH1 to the gate driving circuit in the display panel, that is, all the clock signals are high levels, and controls the gate driving circuit to output a high level as the effective level to each coupled gate line to control all the transistors in all the sub-pixels in the display panel to conduct, so as to release the charge. And when the timing controller 211 determines that the data transmission control signal is abnormal, it can not send the display data to the source driving circuit, and the source driving circuit can pause working to reduce the power consumption.

[0065] It should be noted that by setting the voltage stabilizing capacitor coupled to the first effective level reference signal terminal VGH1, the falling speed of the voltage of the first effective level reference signal terminal VGH1 can be reduced, the charge release time of the sub-pixel can be further increased, and the complete discharge can be further ensured.

[0066] The embodiments of the present disclosure also provide a control method for a driving control circuit, including: when shutting down, the first control circuit 210 outputs a discharge enable signal; the level conversion circuit 220 receives the discharge enable signal and controls the sub-pixels in the display panel to release charges according to the discharge enable signal.

[0067] The following combines Figure 3 , Figure 7 and Figure 9 , to illustrate the working process of the driving control circuit provided by the embodiments of the present disclosure. Among them, Fm_1 is a display frame during normal display. Among them, the T11 stage in Fm_1 is the data refresh stage, and the T12 stage is the frame reset stage. Fm_b + 1 is the display frame when shutting down. There may be b normal display frames between the display frames Fm_1 and Fm_b + 1, or there may be no interval. It is only illustrated by taking the example of an interval of b normal display frames. And, taking a clock signal ck1 as an example, stv represents the signal at the frame trigger signal terminal, and res represents the frame reset signal received by the reset signal terminal Reset. And, the first power supply voltage V VDD1 of the first power supply terminal VDD1 is at a high level, and the second power supply voltage V VDD2 of the second power supply terminal VDD2 is at a high level.

[0068] For the working processes of the T11 stage and the T12 stage in the display frame Fm_1, reference can be made to the working processes of the above-mentioned T11 stage and T12 stage, which will not be elaborated here.

[0069] In the display frame Fm_b + 1, the system circuit 230 shuts down, and the voltages at each signal terminal drop normally. Then, the first pin PIN1 of the timing controller 211 is pulled low to set the level of the first pin PIN1 to a low level, so that the first transistor T1 is turned off. Since the voltages at each signal terminal drop normally, the power management circuit 240 stops outputting voltage, so there is no voltage input to the second power supply terminal VDD2, that is, the levels of the second power supply terminal VDD2 and the first power supply terminal VDD1 are at a low level. Then, the second end of the second transistor T2 is pulled low by the voltage of the ground terminal, that is, the level of the second end of the second transistor T2 is at a low level. When the level of the second end of the second transistor T2 is at a low level, the level conversion circuit 220 enables the discharge function to send the signal of the first effective level reference signal terminal VGH1 to the gate driving circuit in the display panel, that is, all clock signals are at a high level, and controls the gate driving circuit to output a high level as the effective level to each coupled gate line to control all the transistors in all the sub-pixels in the display panel to conduct, so as to release charges. And, the source driving circuit also stops working.

[0070] It should be noted that by setting a voltage stabilizing capacitor coupled to the first effective level reference signal terminal VGH1, the falling speed of the voltage of the first effective level reference signal terminal VGH1 can be reduced, the time for the sub-pixel to release charges can be further increased, and the complete discharge can be further ensured.

[0071] Some embodiments of the present disclosure provide another structural schematic diagram of a driving control circuit, as Figure 10 shown, which is a modification of the implementation manner in the above embodiment. Only the differences between this embodiment and the above embodiment will be described below, and the same parts will not be elaborated here.

[0072] In some embodiments of the present disclosure, the first effective level reference signal terminal VGH1 and the second effective level reference signal terminal VGH2 can also be set as different signal terminals. And, the voltage discharge rate of the first effective level reference signal terminal VGH1 is less than the voltage discharge rate of the second effective level reference signal terminal VGH2. Exemplarily, as Figure 10 shown, the level conversion circuit 220 is respectively coupled to the first effective level reference signal terminal VGH1 and the second effective level reference signal terminal VGH2.

[0073] In some embodiments of the present disclosure, the level conversion circuit 220 is configured to generate a clock signal according to the signals of the second effective level reference signal terminal VGH2 and the invalid level reference signal terminal VL and the reference clock control signal, and send the generated clock signal to the gate driving circuit 110 in the display panel to control the gate driving circuit 110 to drive the gate lines. It should be noted that the process of the level conversion circuit 220 generating the clock signal can refer to the description in the above embodiment and will not be elaborated here.

[0074] In some embodiments of the present disclosure, the level conversion circuit 220 is configured to send the signal of the first effective level reference signal terminal VGH1 to the gate driving circuit 110 in the display panel according to the discharge enable signal, and control the gate driving circuit 110 to output an effective level to each coupled gate line to control the sub-pixels in the display panel to release charges. Since the voltage discharge rate of the first effective level reference signal terminal VGH1 is less than the voltage discharge rate of the second effective level reference signal terminal VGH2, the time for the sub-pixels to release charges can be further increased, and the complete discharge can be further ensured.

[0075] In some embodiments of the present disclosure, the power conversion circuit 240 is further configured to output a third reference voltage VREF3 to the first active-level reference signal terminal VGH1 according to the supply power voltage VCC1. Moreover, the third reference voltage VREF3 is a high level, and the voltage discharge rate (i.e., the falling rate) of its voltage is less than the voltage discharge rate (i.e., the falling rate) of the first reference voltage VREF1. Exemplarily, a capacitor can be provided at the port of the power conversion circuit 240 that outputs the third reference voltage VREF3, so that the voltage discharge rate (i.e., the falling rate) of the output third reference voltage VREF3 is less than the voltage discharge rate (i.e., the falling rate) of the first reference voltage VREF1.

[0076] The following Figure 3 , Figure 8 and Figure 10 are used to illustrate the working process of the drive control circuit provided in the embodiments of the present disclosure. Among them, for the working processes of the T11 stage and the T12 stage in the display frame Fm_1, reference can be made to the above-mentioned working processes of the T11 stage and the T12 stage, which will not be elaborated here.

[0077] In display frame Fm_a+1, the system circuit 230 outputs the power supply voltage VCC1 to the power conversion circuit 240, obtains the display data of the picture to be displayed, generates a data transmission control signal according to the display data, then sequentially sends the display data to the timing controller 211 according to the data transmission control signal, and also sends the generated data transmission control signal to the timing controller 211. Due to the abnormality of the data transmission control signal, the power management circuit 240 stops outputting voltage based on the protection mechanism. However, due to the function of the capacitors in each component, the voltages at each signal terminal cannot immediately drop to 0V, but slowly drop to 0V. That is to say, the timing controller 211 can still supply power to itself for a period of time according to the timing power supply voltage VTCON, receive the data transmission control signal, detect the received data transmission control signal, determine that the data transmission control signal is abnormal, then pull down the first pin PIN1 to set the level of the first pin PIN1 to a low level, and the first transistor T1 is turned off. Due to the abnormality of the data transmission control signal, the power management circuit 240 stops outputting voltage based on the protection mechanism, so there is no voltage input to the second power supply terminal VDD2, that is, the level of the second power supply terminal VDD2 is a low level. Although the power management circuit 240 stops outputting voltage, the system circuit 230 still continues to work, so there is still voltage input to the first power supply terminal VDD1, that is, the level of the first power supply terminal VDD1 is a high level. Thus, the level of the control terminal of the second transistor T2 is pulled up to control the second transistor T2 to conduct, so that the second terminal of the second transistor T2 is pulled down by the voltage of the ground terminal, that is, the level of the second terminal of the second transistor T2 is a low level. When the level of the second terminal of the second transistor T2 is a low level, the level conversion circuit 220 turns on the discharge function to send the signal of the first effective level reference signal terminal VGH1 to the gate driving circuit in the display panel, that is, all the clock signals are high levels, and controls the gate driving circuit to output a high level as the effective level to each coupled gate line to control all the transistors in all the sub-pixels in the display panel to conduct, thereby releasing the charge. And, when the timing controller 211 determines that the data transmission control signal is abnormal, it can not output the display data to the source driving circuit, and the source driving circuit can pause to work to reduce the power consumption.

[0078] It should be noted that by making the voltage discharge rate of the first effective level reference signal terminal VGH1 less than the voltage discharge rate of the second effective level reference signal terminal, the falling speed of the voltage of the first effective level reference signal terminal VGH1 can be reduced, the time for the sub-pixels to release the charge can be further increased, and the complete discharge can be further ensured.

[0079] The following is combined with Figure 3 、 Figure 9 and Figure 10, the working process of the driving control circuit provided in the embodiments of the present disclosure will be described. For the working processes of the T11 stage and the T12 stage in the display frame Fm_1, reference may be made to the above T11 stage and T12 stage working processes, which will not be elaborated here.

[0080] In the display frame Fm_b + 1, the system circuit 230 shuts down, and the voltages at each signal terminal drop normally. Then, the first pin PIN1 of the timing controller 211 is pulled low to set the level of the first pin PIN1 to a low level, and the first transistor T1 is turned off. Since the voltages at each signal terminal drop normally, the power management circuit 240 stops outputting voltage, and there is no voltage input to the second power supply terminal VDD2, that is, the levels of the second power supply terminal VDD2 and the first power supply terminal VDD1 are low levels. Then, the second end of the second transistor T2 is pulled low by the voltage of the ground terminal, that is, the level of the second end of the second transistor T2 is a low level. When the level of the second end of the second transistor T2 is a low level, the level conversion circuit 220 enables the discharge function to send the signal of the first effective level reference signal terminal VGH1 to the gate driving circuit in the display panel, that is, all clock signals are high levels, and the gate driving circuit is controlled to output a high level as the effective level to each coupled gate line to control all transistors in all sub-pixels in the display panel to conduct, thereby discharging the charge. Also, the source driving circuit stops working.

[0081] It should be noted that by making the voltage discharge rate of the first effective level reference signal terminal VGH1 less than the voltage discharge rate of the second effective level reference signal terminal, the falling speed of the voltage of the first effective level reference signal terminal VGH1 can be reduced, the charge discharge time of the sub-pixels can be further increased, and the complete discharge can be further ensured.

[0082] The embodiments of the present disclosure provide some structural schematic diagrams of the driving control circuit, as Figure 11 shown, which are variations of the implementation manners in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0083] In some embodiments of the present disclosure, as Figure 11 and Figure 12 shown, the first control circuit 210 may also include: a power conversion circuit 240; wherein, the reset pin PIN2 of the power conversion circuit 240 is coupled to the discharge enable pin XON of the level conversion circuit 220. And the power conversion circuit 240 is configured to output a discharge enable signal through the reset pin PIN2 when the data transmission control signal is abnormal and during shutdown. The level conversion circuit 220 is configured to receive the discharge enable signal and control the sub-pixels in the display panel to discharge the charge according to the discharge enable signal.

[0084] In some embodiments of the present disclosure, asFigure 11 As shown, the drive control circuit 200 may further include: a system circuit 230 and a timing controller 211. Among them, the system circuit 230 is configured to output a power supply voltage VCC1 to the power conversion circuit 240 and obtain display data of a to-be-displayed picture, generate a data transmission control signal according to the display data, then sequentially send the display data to the timing controller 211 according to the data transmission control signal, and also send the generated data transmission control signal to the timing controller 211. The timing controller 211 generates reference clock control signals cks1 to cks12 according to the received data transmission control signal, and sends the generated reference clock control signals cks1 to cks12 to the level conversion circuit 220. The level conversion circuit 220 generates clock signals ck1 to ck12 according to the reference clock control signals cks1 to cks12, a first reference voltage VREF1, and a second reference voltage VREF2, and sends the generated clock signals ck1 to ck12 to the gate driving circuit in the display panel to control the gate driving circuit to drive the gate lines to control the transistors in the sub-pixels to conduct. The timing controller 211 also sends the display data to the source driving circuit 120, and the source driving circuit 120 loads a data voltage on the data lines in the display panel 100 according to the received display data. In this way, when the transistors in the sub-pixels conduct, the data voltage on the data lines can be input into the pixel electrodes, so that the sub-pixels can achieve their brightness, thereby realizing the function of picture display.

[0085] It should be noted that other functions of the system circuit 230, the timing controller 211, the power management circuit 240, and the level conversion circuit 220 can be referred to the above description and will not be elaborated here.

[0086] When the data transmission control signal is abnormal, the power management circuit 240 stops outputting voltage based on the protection mechanism, then its reset pin PIN2 is pulled low so that the level of its reset pin PIN2 is low. When the level of the reset pin PIN2 of the level conversion circuit 220 is low, the discharge function is turned on to send the signal of the first effective level reference signal terminal VGH1 to the gate driving circuit in the display panel, that is, all the clock signals are high level, and the gate driving circuit is controlled to output a high level as the effective level to each coupled gate line to control all the transistors in the sub-pixels in the display panel to conduct, thereby releasing charges. And when the timing controller 211 determines that the data transmission control signal is abnormal, it may not send display data to the source driving circuit, and the source driving circuit can pause working to reduce power consumption.

[0087] When the device is turned off, the voltages at all signal terminals drop to zero normally, and the power management circuit 240 stops outputting voltage. Then its reset pin PIN2 is pulled low so that the level of its reset pin PIN2 is at a low level. When the level of the reset pin PIN2 is at a low level, the level conversion circuit 220 enables the discharging function to send the signal of the first effective level reference signal terminal VGH1 to the gate driving circuit in the display panel. Even if the clock signals are all at a high level, it controls the gate driving circuit to output a high level as the effective level to each coupled gate line, so as to control all the transistors in the sub-pixels in the display panel to conduct, thereby releasing the charges. Moreover, when the timing controller 211 determines that the data transmission control signal is abnormal, it may not output display data to the source driving circuit, and the source driving circuit may suspend operation to reduce power consumption.

[0088] It should be noted that the implementation manner of the signal of the first effective level reference signal terminal VGH1 may refer to the above description and will not be elaborated here.

[0089] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, including the above-mentioned display panel and the driving and control circuit provided by the embodiments of the present disclosure. The principle of the display device for solving the problem is similar to that of the foregoing driving and control circuit. Therefore, the implementation of the display device may refer to the implementation of the foregoing driving and control circuit, and the repeated parts will not be elaborated here.

[0090] In specific implementation, in the embodiments of the present disclosure, the display device may be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be elaborated here, nor should it be regarded as a limitation to the present disclosure.

[0091] The driving and control circuit, its control method and the display device provided by the embodiments of the present disclosure can output a discharge enable signal through the first control circuit when the data transmission control signal is abnormal and when the device is turned off by setting the first control circuit and the level conversion circuit. After receiving the discharge enable signal, the level conversion circuit can control the sub-pixels in the display panel to release charges according to the discharge enable signal. In this way, when the data transmission control signal is abnormal, the sub-pixels in the display panel can be timely controlled to release charges, so that the display panel is timely turned off, which is equivalent to displaying a black screen, thereby comparing the display abnormality. Moreover, when the device is turned off, the sub-pixels in the display panel can also be timely controlled to release charges to avoid display abnormality when the device is turned on again.

[0092] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. A drive control circuit, characterized in that, Comprising: A first control circuit configured to output a discharge enable signal when a data transmission control signal is abnormal and during shutdown; A level conversion circuit configured to receive the discharge enable signal and control sub-pixels in a display panel to release charges according to the discharge enable signal; Wherein, the first control circuit includes: a timing controller and a discharge trigger circuit; wherein, a first pin of the timing controller is coupled to the discharge trigger circuit, and the timing controller is configured to output a discharge trigger signal through the first pin when the data transmission control signal is abnormal and during the shutdown; the discharge trigger circuit is respectively coupled to a first power supply terminal, a second power supply terminal, and the level conversion circuit, and the discharge trigger circuit is configured to receive the discharge trigger signal when the data transmission control signal is abnormal and output the discharge enable signal according to the discharge trigger signal and the signal of the first power supply terminal; and during the shutdown, output the discharge enable signal according to the signals of the first power supply terminal and the second power supply terminal; Alternatively, the first control circuit includes: a power conversion circuit; wherein, a reset pin of the power conversion circuit is coupled to the level conversion circuit; the power conversion circuit is configured to output the discharge enable signal through the reset pin when the data transmission control signal is abnormal and during shutdown; Wherein, the level conversion circuit is further configured to send the signal of a first effective level reference signal terminal to a gate driving circuit in the display panel according to the discharge enable signal, and control the gate driving circuit to output an effective level to each coupled gate line to control the sub-pixels in the display panel to release charges; The level conversion circuit is further configured to generate a clock signal according to the signals of a second effective level reference signal terminal and an invalid level reference signal terminal, and send the generated clock signal to the gate driving circuit in the display panel to control the gate driving circuit to drive the gate lines.

2. The drive control circuit according to claim 1, wherein The discharge trigger circuit includes a first transistor, a second transistor, a first resistor, and a second resistor; A control end of the first transistor is coupled to the first pin of the timing controller, a first end of the first transistor is coupled to a ground terminal, and a second end of the first transistor is respectively coupled to a control end of the second transistor and a first end of the first resistor; A second end of the first resistor is coupled to the first power supply terminal; A first end of the second transistor is coupled to the ground terminal, and a second end of the second transistor is respectively coupled to a first end of the second resistor and the level conversion circuit; A second end of the second resistor is coupled to the second power supply terminal.

3. The drive control circuit according to claim 1, wherein The first effective level reference signal terminal and the second effective level reference signal terminal are the same signal terminal.

4. The drive control circuit according to claim 3, characterized in that, The drive control circuit further includes: a voltage stabilizing capacitor; a first end of the voltage stabilizing capacitor is coupled to the first effective level reference signal terminal, and a second end of the voltage stabilizing capacitor is coupled to a fixed voltage terminal.

5. The drive control circuit according to claim 4, wherein The voltage stabilizing capacitor is integrally provided with the level conversion circuit.

6. The drive control circuit according to claim 1, wherein The first effective level reference signal terminal and the second effective level reference signal terminal are different signal terminals.

7. The drive control circuit according to claim 6, wherein The voltage discharge rate of the first effective level reference signal terminal is less than that of the second effective level reference signal terminal.

8. A display device, characterized in that, It includes a display panel and the drive control circuit according to any one of claims 1-7.

9. A control method for a drive control circuit according to any one of claims 1-7, characterized in that, It includes: When the data transmission control signal is abnormal, the first control circuit outputs a discharge enable signal; The level conversion circuit receives the discharge enable signal and controls the sub-pixels in the display panel to release charges according to the discharge enable signal; When shutting down, the first control circuit outputs a discharge enable signal; The level conversion circuit receives the discharge enable signal and controls the sub-pixels in the display panel to release charges according to the discharge enable signal.

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