Semiconductor device and method of detecting, manufacturing and storing system thereof

Abstract

The embodiment of the present application discloses a kind of semiconductor devices and its detection method, manufacturing method, storage system.The semiconductor device includes core area and non-core area, the semiconductor device includes crystalline layer, and the non-core area of the crystalline layer has detection part;The method comprises: detecting the optical parameter of the detection part;The optical parameter of the detection part is compared with the standard optical parameter of pre-set;According to the comparison result, the crystallization degree of the crystalline layer of the core area is detected.The embodiment of the present application does not need to damage semiconductor device, and improves detection efficiency, reduces detection cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its detection method, fabrication method and storage system. Background Technology

[0002] The main method for detecting the crystallinity of polysilicon layers in semiconductor devices involves slicing the polysilicon layer, analyzing the depth and grain size of the crystals, and then performing electrical tests on the polysilicon layer to determine its crystallinity. However, slicing can cause irreversible damage to semiconductor devices, while electrical tests have long feedback cycles and high testing costs. Summary of the Invention

[0003] This invention provides a semiconductor device and its detection method, fabrication method, and storage system, which do not damage the semiconductor device, improve detection efficiency, and reduce detection costs.

[0004] This invention provides a method for detecting a semiconductor device, the semiconductor device including a core region and a non-core region, the semiconductor device including a crystal layer, and the non-core region of the crystal layer having a detection unit;

[0005] The method includes:

[0006] Detect the optical parameters of the detection unit;

[0007] The optical parameters of the detection unit are compared with preset standard optical parameters;

[0008] The degree of crystallization of the crystallized layer in the core area was detected based on the comparison results.

[0009] Furthermore, the semiconductor device also includes a stacked structure and a substrate;

[0010] The substrate is located on one side of the stacked structure and covers the stacked structure of the non-core area. The crystalline layer is located on the side of the substrate opposite to the stacked structure and covers the stacked structure of the substrate and the core area. The detection part of the crystalline layer penetrates the substrate.

[0011] Furthermore, the method also includes:

[0012] The standard optical parameters are set; the standard optical parameters are the optical parameters of the target crystal test layer that meets the preset electrical performance among multiple crystal test layers, and the multiple crystal test layers are formed by irradiating each other with lasers of multiple energies in a one-to-one correspondence.

[0013] Furthermore, the step of detecting the degree of crystallization of the crystallized layer in the core region based on the comparison results includes:

[0014] If the comparison result shows that the optical parameters of the detection unit are greater than the standard optical parameters, then it is determined that the degree of crystallization of the crystal layer in the core region does not meet the preset crystallization requirements;

[0015] If the comparison result shows that the optical parameters of the detection unit are less than or equal to the standard optical parameters, then it is determined that the crystallization degree of the crystallization layer in the core region meets the preset crystallization requirements.

[0016] Furthermore, the crystalline layer is formed by laser irradiation with a preset standard energy;

[0017] The method further includes:

[0018] The energy of the laser is tested to determine whether it is stable based on the comparison results.

[0019] Further, the step of detecting whether the energy of the laser is stable based on the comparison result includes:

[0020] If the comparison result shows that the optical parameters of the detection unit are consistent with the standard optical parameters, then the energy of the laser is determined to be stable.

[0021] If the comparison result shows that the optical parameters of the detection unit are inconsistent with the standard optical parameters, then the energy of the laser is determined to be unstable.

[0022] Furthermore, the non-core area includes a non-functional area, and the detection unit is located in the non-functional area.

[0023] Furthermore, the optical parameters include at least one of refractive index and extinction coefficient.

[0024] Furthermore, the crystalline layer is a polycrystalline silicon layer.

[0025] Furthermore, the semiconductor device is a memory.

[0026] Accordingly, embodiments of the present invention also provide a detection device for a semiconductor device, the semiconductor device including a core region and a non-core region, the semiconductor device including a crystal layer, and the non-core region of the crystal layer having a detection unit;

[0027] The device includes:

[0028] An optical detection module is used to detect the optical parameters of the detection unit;

[0029] The comparison module is used to compare the optical parameters of the detection unit with preset standard optical parameters;

[0030] The crystallinity detection module is used to detect the crystallinity of the crystallization layer in the core area based on the comparison results.

[0031] Furthermore, the device also includes:

[0032] The setting module is used to set the standard optical parameters; the standard optical parameters are the optical parameters of the target crystal test layer that meets the preset electrical performance among multiple crystal test layers, and the multiple crystal test layers are formed by irradiating with lasers of multiple energies one by one.

[0033] Furthermore, the crystallinity detection module is specifically used for:

[0034] If the comparison result shows that the optical parameters of the detection unit are greater than the standard optical parameters, then it is determined that the degree of crystallization of the crystal layer in the core region does not meet the preset crystallization requirements;

[0035] If the comparison result shows that the optical parameters of the detection unit are less than or equal to the standard optical parameters, then it is determined that the crystallization degree of the crystallization layer in the core region meets the preset crystallization requirements.

[0036] Furthermore, the crystalline layer is formed by irradiating the amorphous layer with a laser of preset standard energy;

[0037] The device further includes:

[0038] The stability detection module is used to detect whether the energy of the laser is stable based on the comparison results.

[0039] Furthermore, the stability detection module is specifically used for:

[0040] If the comparison result shows that the optical parameters of the detection unit are consistent with the standard optical parameters, then the energy of the laser is determined to be stable.

[0041] If the comparison result shows that the optical parameters of the detection unit are inconsistent with the standard optical parameters, then the energy of the laser is determined to be unstable.

[0042] Furthermore, the optical parameters include at least one of refractive index and extinction coefficient.

[0043] Accordingly, embodiments of the present invention also provide a semiconductor device, including a core region and a non-core region;

[0044] The semiconductor device includes:

[0045] A crystalline layer, wherein a non-core region of the crystalline layer has a detection section, the thickness of which is the same as the thickness of the crystalline layer in the core region.

[0046] Furthermore, the semiconductor device further includes:

[0047] Stacked structure;

[0048] A substrate, located on one side of the stacked structure and covering the substrate and the stacked structure of the non-core area;

[0049] The crystalline layer is located on the side of the substrate opposite to the stacked structure and covers the stacked structure of the core area, and the detection unit penetrates the substrate.

[0050] Furthermore, the non-core area includes a stepped area and a non-functional area located in the stepped area away from the core area, and the detection unit is located in the non-functional area.

[0051] Furthermore, the semiconductor device is a memory.

[0052] Accordingly, embodiments of the present invention also provide a manufacturing method, wherein the semiconductor device includes a core region and a non-core region;

[0053] The method includes:

[0054] A crystalline layer is formed, and a detection section is formed in the non-core area of ​​the crystalline layer, the thickness of which is the same as the thickness of the crystalline layer in the core area.

[0055] Further, the step of forming a crystalline layer, such that the non-core region of the crystalline layer has a detection section, includes:

[0056] Provides a substrate located in a non-core area and a stacked structure located on one side of the substrate;

[0057] Through holes are formed in the substrate;

[0058] An amorphous layer is formed on the side of the substrate opposite to the stacked structure, such that the amorphous layer covers the stacked structure of the substrate and the core region and fills the through-hole;

[0059] The amorphous layer is converted into a crystalline layer, and the crystalline layer corresponding to the through hole constitutes the detection unit.

[0060] Furthermore, the non-core area includes a cutting channel, and the detection unit is located on the cutting channel;

[0061] The method further includes:

[0062] Remove the cutting path and the detection section.

[0063] Accordingly, embodiments of the present invention also provide a semiconductor device formed using the above-described semiconductor device fabrication method.

[0064] Accordingly, embodiments of the present invention also provide a storage system, including the above-described semiconductor device and a controller connected to the semiconductor device.

[0065] The beneficial effects of this invention are as follows: a detection unit is set in the non-core area of ​​the crystal layer to detect the optical parameters of the detection unit, and the optical parameters of the detection unit are compared with preset standard optical parameters to detect the degree of crystallization of the crystal layer in the core area based on the comparison results. This does not require damage to the crystal layer in the core area, thereby ensuring that the semiconductor device is not damaged. Moreover, there is no need to perform electrical testing on the crystal layer, which improves detection efficiency and reduces detection costs. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 These are schematic diagrams of the semiconductor devices in some embodiments;

[0068] Figure 2 A schematic diagram of the structure of a semiconductor device before crystallization provided in an embodiment of the present invention;

[0069] Figure 3 A schematic diagram of the structure of a semiconductor device after crystallization, provided in an embodiment of the present invention;

[0070] Figure 4 A schematic flowchart of a semiconductor device detection method provided in an embodiment of the present invention;

[0071] Figure 5 A schematic diagram illustrating the relationship between laser energy and optical parameters in the semiconductor device detection method provided in this embodiment of the invention;

[0072] Figure 6 A schematic diagram illustrating the relationship between doping concentration and optical parameters in the semiconductor device detection method provided in this embodiment of the invention;

[0073] Figure 7 A schematic diagram of a semiconductor device detection apparatus provided in an embodiment of the present invention;

[0074] Figure 8 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0075] Figure 9 This is a schematic diagram of a storage system provided in an embodiment of the present invention. Detailed Implementation

[0076] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0077] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0078] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0080] like Figure 1As shown, in some embodiments, the semiconductor device includes a stacked structure 100a, a substrate 200a, and a polysilicon layer 300a. The substrate 200a is located in the non-core region 402a and is situated on one side of the stacked structure 100a. The polysilicon layer 300a is located on the side of the substrate 200a facing away from the stacked structure 100a and covers the stacked structure 100a in the core region 401a. When detecting the crystallinity of the polysilicon layer 300a in the core region 401a, the polysilicon layer 300a in the core region 401a is sliced, and the crystal depth and grain size of the polysilicon layer 300a in the core region 401a are obtained through TEM analysis. Then, electrical tests are performed on the polysilicon layer 300a to determine its crystal contrast based on the test results. However, slicing causes irreversible destructive damage to the polysilicon layer 300a in the core region 401a, leading to damage to the semiconductor device. Furthermore, the feedback cycle of electrical tests is long, and the detection cost is high.

[0081] Based on this, embodiments of this application provide a semiconductor device. See also... Figure 2 This is a schematic diagram of the structure of a semiconductor device before crystallization, provided in an embodiment of the present invention. See also... Figure 3 This is a schematic diagram of the structure of a semiconductor device after crystallization, provided in an embodiment of the present invention. The semiconductor device includes, but is not limited to, a memory.

[0082] like Figure 2 and Figure 3 As shown, the semiconductor device provided in this embodiment of the invention includes a core region A and a non-core region B. The non-core region B includes a step region B1 and a non-functional region B2, and the step region B1 is located between the core region A and the non-functional region B2.

[0083] Before semiconductor devices are crystallized, such as Figure 2 As shown, the amorphous layer 1 can be located in the core region A, the step region B1, and the non-functional region B2. The amorphous layer 1 has an initial detection part 11 in the non-core region B. The thickness of the initial detection part 11 can be the same as the thickness of the amorphous layer 1 in the core region A, so as to ensure that the initial detection part 11 and the amorphous layer 1 in the core region A have the same degree of crystallization after being irradiated by the same laser.

[0084] It should be noted that since the amorphous layer 1 of the core region A is electrically connected to the storage channel structure in the semiconductor device after crystallization, whether the amorphous layer 1 of the core region A is completely crystallized will affect the performance of the semiconductor device. Other regions (such as the step region B1 and the regions in the non-functional region B2 other than the initial detection part) may have an amorphous layer or may not have an amorphous layer, or the thickness of the amorphous layer in other regions may be less than the thickness of the amorphous layer in the core region A, and the impact on the performance of the semiconductor device is smaller. Therefore, in this embodiment, only the degree of crystallization of the amorphous layer 1 of the core region A can be detected.

[0085] The semiconductor device may further include a substrate 2 and a stacked structure 3. The stacked structure 3 is located in the core region A, the step region B1, and the non-functional region B2. The substrate 2 is located on one side of the stacked structure 3 and covers the stacked structure 3 in the non-core region B, but the substrate 2 does not cover the stacked structure 3 in the core region A. An amorphous layer 1 is located on the side of the substrate 2 away from the stacked structure 3 and covers the stacked structure 3 in the core region A. The initial detection part 11 in the amorphous layer 1 penetrates through the substrate 2. During fabrication, a via can be formed first in the non-core region A of the substrate 2, and then the amorphous layer 1 can be formed on the side of the substrate 2 away from the stacked structure 3, so that the amorphous layer 1 covers the stacked structure of the substrate 2 and the core region A and fills the via. The amorphous layer 1 corresponding to the via (i.e., the amorphous layer 1 filling the via and the amorphous layer 1 above the via) constitutes the initial detection part 11. The upper surface of the initial detection section 11 (i.e., the surface of the initial detection section 11 facing away from the substrate 2) is flush with the upper surface of the amorphous layer 1 of the core region A (i.e., the surface of the amorphous layer 1 facing away from the substrate 2) to ensure that the thickness of the initial detection section 11 is consistent with the thickness of the amorphous layer 1 of the core region A. The amorphous layer 1 can be an amorphous silicon layer.

[0086] A laser with a preset standard energy is used to irradiate the amorphous layer 1, instantly heating it above its melting temperature. Upon cooling, the amorphous layer 1 transforms into a crystalline layer. The grain size of the crystalline layer increases with increasing laser energy. When the laser energy is below a certain threshold, the crystallization of the amorphous layer 1 is insufficient, and the resistivity or electron mobility of the crystalline layer does not meet the process requirements, affecting the performance and reliability of the semiconductor device. Therefore, detecting the degree of crystallinity of the crystalline layer and the stability of the laser energy are crucial for the yield of semiconductor devices.

[0087] like Figure 3As shown, after the semiconductor device crystallizes, the amorphous layer 1 in the semiconductor device crystallizes into a crystalline layer 1', and the initial detection unit 11 crystallizes into a detection unit 11'. The crystalline layer 1' is located in the core region A, the step region B1, and the non-functional region B2. The detection unit 11' is located in the non-core region B of the crystalline layer 1'. The thickness of the detection unit 11' can be the same as the thickness of the crystalline layer 1' in the core region A, so as to ensure that the degree of crystallization of the detection unit 11' is consistent with the degree of crystallization of the crystalline layer 1' in the core region A. Thus, the degree of crystallization of the crystalline layer 1' in the core region A can be detected by detecting the degree of crystallization of the detection unit 11'. Because the bottom structure of the crystal layer 1' in the core region A (including, for example, the memory channel structure) is relatively complex, the accuracy of directly detecting the crystallinity of the crystal layer 1' in the core region A is low due to the influence of the bottom structure. Therefore, the detection unit 11' is located in the non-core region B of the crystal layer 1', for example, in the non-functional region B2 of the crystal layer 1'. The bottom structure of the detection unit 11' is simpler, which can improve the detection accuracy of the crystallinity of the detection unit 11', thereby improving the detection accuracy of the crystallinity of the crystal layer 1' in the core region A. In addition, the detection unit 11' can detect the crystallinity of the crystal layer 1' in the core region A without damaging the semiconductor device.

[0088] When the semiconductor device also includes a substrate 2 and a stacked structure 3, such as Figure 3 As shown, the crystalline layer 1' is located on the side of the substrate 2 away from the stacked structure 3 and covers the stacked structure 3 of the core region A. The detection part 11' in the crystalline layer 1' penetrates the substrate 2 along the first direction Z. The upper surface of the detection part 11' (i.e., the surface of the detection part 11' away from the substrate 2) is flush with the upper surface of the crystalline layer 1' in the core region A (i.e., the surface of the crystalline layer 1' away from the substrate 2) to ensure that the thickness of the detection part 11' is consistent with the thickness of the crystalline layer 1' in the core region A, thereby ensuring that the degree of crystallinity of the detection part 11' is consistent with the degree of crystallinity of the crystalline layer 1' in the core region A. When the amorphous layer 1 is an amorphous silicon layer, the crystalline layer 1' is a polycrystalline silicon layer. The crystalline layer 1' can serve as a common source layer.

[0089] Specifically, such as Figure 3As shown, the substrate 2 includes a sacrificial layer 21 and a barrier layer 22. The barrier layer 22 is located in the non-core region B and is situated on one side of the stacked structure 3. The sacrificial layer 21 is located in the non-core region B and is situated on the side of the barrier layer 22 facing away from the stacked structure 3. A crystalline layer 1' is situated on the side of the sacrificial layer 21 facing away from the stacked structure 3 and covers the stacked structure 3 in the core region A. The detection unit 11' can penetrate the sacrificial layer 21 and the barrier layer 22 along the first direction Z, such that the thickness of the detection unit 11' is consistent with the thickness of the crystalline layer 1' in the core region A. The sacrificial layer 21 can be a semiconductor layer such as polysilicon. The barrier layer 22 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0090] The stacked structure 3 may include a stack layer 31 and a stop layer 32. The stop layer 32 is located in the core region A and the non-core region B, and is located on the side of the barrier layer 22 away from the sacrificial layer 21. The crystal layer 1' is located on the side of the sacrificial layer 21 away from the barrier layer 22, and covers the stop layer 32 in the core region A. It should be noted that the detection part 11' extends from the upper surface of the crystal layer 1' (i.e., the surface of the detection part 11' away from the substrate 2) to the stop layer 32, and the lower surface of the detection part 11' (i.e., the surface of the detection part 11' near the substrate 2) contacts the stop layer 32, which avoids uneven thickness due to process variations. The stop layer 32 may be a semiconductor layer such as polysilicon.

[0091] Stack layer 31 is located in the core region A and the step region B1, and stack layer 31 is located on the side of stop layer 32 opposite to crystal layer 1'. Stack layer 31 may include multiple alternately stacked gate layers 34 and interlayer insulating layers 33. The number of stacked gate layers 34 and interlayer insulating layers 33 is not limited, for example, 48 layers, 64 layers, 128 layers, etc. Gate layers 34 include, but are not limited to, tungsten, cobalt, copper, aluminum, doped silicon or doped silicide, and interlayer insulating layers 33 include, but are not limited to, any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.

[0092] The stacked layer 31 has a stepped structure formed in the step region B1. The stepped structure includes multiple steps, and each step can correspond to a gate layer 34. The stacked structure 3 may also include a dielectric layer 35, which covers the stepped structure of the step region B1 and is also formed in the non-functional region B2. The surface of the dielectric layer 35 facing away from the stop layer 32 is flush with the surface of the stacked layer 31 facing away from the stop layer 32, and the surface of the dielectric layer 35 near the stop layer 32 is flush with the surface of the stacked layer 31 near the stop layer 32. The dielectric layer 35 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0093] The semiconductor device may further include a memory channel structure 4, which is located in the core region A and extends along a first direction Z through the stack layer 31 and the stop layer 32 into the crystal layer 1'. Specifically, the memory channel structure 4 includes an isolation layer 41, a channel layer 42, and a memory dielectric layer 43. The isolation layer 41 extends through the stack layer 31 and the stop layer 32 into the crystal layer 1'. The channel layer 42 is disposed around the isolation layer 41 and extends through the stack layer 31 and the stop layer 32 into the crystal layer 1'. The memory dielectric layer 43 is disposed around the periphery of the channel layer 42 and extends through the stack layer 31 and the stop layer 32. The memory dielectric layer 43 does not extend into the crystal layer 1', allowing the channel layer 42 to contact the crystal layer 1', thus achieving an electrical connection between the channel layer 42 and the crystal layer 1'. Specifically, the storage medium layer 43 may include a tunnel layer (not shown) disposed around the periphery of the channel layer 42, a charge storage layer (not shown) disposed around the periphery of the tunnel layer, and a charge blocking layer (not shown) disposed around the periphery of the charge storage layer. The isolation layer 41 may be an oxide such as silicon oxide, the channel layer 42 may be polycrystalline silicon, the tunnel layer may be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride, the charge storage layer may be an insulating layer including quantum dots or nanocrystals or compounds containing nitrogen and silicon, and the charge blocking layer may be an oxide such as silicon oxide.

[0094] The semiconductor device may further include a virtual channel structure 5 located in the step region B1, and extending along the first direction Z through the stack layer 31, the stop layer 32, and the barrier layer 22 into the sacrificial layer 21. For example, the virtual channel structure 5 may include an isolation layer, a channel layer disposed around the isolation layer, and a storage medium layer disposed around the channel layer, wherein the isolation layer, the channel layer, and the storage medium layer in the virtual channel structure 5 all extend through the stack layer 31, the stop layer 32, and the barrier layer 22 into the sacrificial layer 21.

[0095] The semiconductor device may further include a gate gap structure 6, which extends along a first direction Z through the stacked layer 31, the stop layer 32, and the barrier layer 22 and into the sacrificial layer 21. The gate gap structure 6 also extends along a second direction X through the stacked layer 31, the stop layer 32, the barrier layer 22, and the sacrificial layer 21. The gate gap structure 6 may be an insulating layer, including but not limited to any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The gate gap structure 6 may also include a semiconductor layer 61 and a barrier layer 62, where the semiconductor layer 61 extends through the stacked layer 31, the stop layer 32, and the barrier layer 22 and into the sacrificial layer 21, and the barrier layer 62 is disposed around the semiconductor layer 61. The semiconductor layer 61 may be a semiconductor material such as polysilicon, and the barrier layer 62 includes but is not limited to any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0096] The semiconductor device may further include multiple word line contacts 7, which are located in the step region B1 and penetrate the dielectric layer 35 on the step structure of the stack layer 31 to correspond one-to-one with multiple gate layers 34 in the step structure. The word line contacts 7 include, but are not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide.

[0097] The semiconductor device may further include a metal interconnect layer 8, which is located in the core region A and the non-core region B, and is situated on the side of the stacked structure 3 facing away from the crystal layer 1'. The metal interconnect layer 8 has multiple first bonding interfaces 80, which penetrate the metal interconnect layer 8 and are connected one-to-one with word line contacts 7, channel layers 42 in the memory channel structure 4, and channel layers in the virtual channel structure 5. The first bonding interfaces 80 include, but are not limited to, tungsten, cobalt, copper, and aluminum.

[0098] The semiconductor device may further include a peripheral device structure 9, which includes a second bonding interface 90 corresponding to the first bonding interface 80, and the second bonding interface 90 is connected to the corresponding first bonding interface 80. The second bonding interface 90 includes, but is not limited to, tungsten, cobalt, copper, and aluminum. The peripheral device structure 9 also includes peripheral devices (not shown in the figure) connected to the second bonding interface 90, so that the word line contact 7 and the channel layer 42 in the memory channel structure 4 can be electrically connected to the peripheral devices in the peripheral device structure 9 through the first bonding interface 80 and the second bonding interface 90. The peripheral devices may be CMOS (Complementary Metal-Oxide-Semiconductor), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FPGA (Field-Programmable Gate Array), CPU (Central Processing Unit), etc. The semiconductor device may be a memory.

[0099] Accordingly, this invention provides a method for detecting a semiconductor device, wherein the semiconductor device is the same as the one described in the above embodiments, and will not be described in detail here.

[0100] See Figure 4 This is a schematic flowchart of the semiconductor device detection method provided in the embodiments of the present invention.

[0101] like Figure 4 As shown, the semiconductor device detection method provided in this embodiment of the invention includes steps 101 to 103, as detailed below:

[0102] Step 101: Detect the optical parameters of the detection unit.

[0103] In this embodiment of the invention, after the amorphous layer 1 is irradiated with a laser, the amorphous layer 1 crystallizes into a crystalline layer 1', and the initial detection part 11 in the amorphous layer 1 crystallizes into a detection part 11'. Since the thickness of the amorphous layer 1 in the core region A can be the same as the thickness of the initial detection part 11, after crystallization, the degree of crystallization of the crystalline layer 1' in the core region A is consistent with the degree of crystallization of the detection part 11'. The amorphous layer 1 can be an amorphous silicon layer, and the crystalline layer 1' can be a polycrystalline silicon layer.

[0104] In this embodiment, an amorphous layer 1 is irradiated with a laser of a preset standard energy to crystallize it into a crystalline layer 1'. The standard energy refers to the laser energy that precisely achieves the desired degree of crystallization in the crystalline layer 1', such as the energy required to completely crystallize the amorphous layer 1 into the crystalline layer 1'. This standard energy can be obtained through pre-testing and set in the laser stage, eliminating the need for repeated setting during subsequent testing. However, in practical applications, laser energy is unstable. Even if the laser energy is set to the standard energy in the laser stage, the actual irradiated laser energy may be less than or greater than the standard energy, resulting in the amorphous layer 1 not completely crystallizing into the crystalline layer 1' after laser irradiation. Therefore, in this embodiment, after the amorphous layer 1 crystallizes into the crystalline layer 1', the degree of crystallization of the crystalline layer 1' needs to be tested.

[0105] Since the optical parameters of crystalline layers 1' with different degrees of crystallinity are different, the degree of crystallinity of the detection unit 11' can be detected by detecting the optical parameters of the detection unit 11', thereby enabling the detection of the degree of crystallinity of the crystalline layer 1' in the core region A. The optical parameters may include at least one of refractive index n and extinction coefficient k. In this embodiment, the detection of the crystalline layer 1' in the core region A is achieved by detecting the detection unit 11', without the need to slice the crystalline layer 1' in the core region A, thus avoiding damage to the semiconductor device.

[0106] Specifically, the optical parameters of the detection unit 11' are detected using a preset detection wavelength. The preset detection wavelength can be the wavelength of ultraviolet light or infrared light, and is not specifically limited here. Since different detection wavelengths detect different optical parameters, this embodiment uses a fixed detection wavelength to detect the detection unit 11' to avoid differences in optical parameters caused by different detection wavelengths.

[0107] The optical parameters of the detection unit 11' can reflect the optical parameters of the crystal layer 1' in the core region A. Because the bottom structure of the crystal layer 1' in the core region A (e.g., the storage channel structure 4) is relatively complex, directly detecting the optical parameters of the crystal layer 1' in the core region A may result in a significant discrepancy between the detected optical parameters and the actual optical parameters of the crystal layer 1'. However, by placing the detection unit 11' in the non-core region B (especially the non-functional region B2) of the crystal layer 1', the bottom structure of the detection unit 11' is simpler. By detecting the optical parameters of the detection unit 11', the detected optical parameters are closer to the actual optical parameters of the crystal layer 1' in the core region A, thereby improving the accuracy of subsequent detection of the crystallinity of the crystal layer 1' in the core region A.

[0108] Step 102: Compare the optical parameters of the detection unit with the preset standard optical parameters.

[0109] In this embodiment of the invention, the standard optical parameters refer to the optical parameters of the crystalline layer 1' when the amorphous layer 1 crystallizes into a crystalline layer 1' that meets the preset crystallization requirements, such as the optical parameters of the crystalline layer 1' when the amorphous layer 1 crystallizes completely into a crystalline layer 1'. The standard optical parameters can be obtained through prior testing. In this embodiment, the standard optical parameters are set based on the pre-tested standard optical parameters so that during step 102, a direct comparison can be made using the set standard optical parameters, eliminating the need for further testing to obtain the standard optical parameters.

[0110] When obtaining standard optical parameters through preliminary testing, multiple amorphous test layers are provided, with the thickness of each layer being the same as that of the detection unit 11'. Multiple lasers of different energies are sequentially positioned in the laser stage, each energy corresponding to one of the amorphous test layers. Different energies are used to irradiate the corresponding amorphous layers, causing each layer to crystallize into a crystalline test layer, although the degree of crystallization varies among the different crystalline test layers. Then, the optical parameters of each crystalline test layer are sequentially detected using a preset detection wavelength, the same wavelength used by the detection unit 11'. Because the degree of crystallization varies among the different crystalline test layers, their optical parameters differ.

[0111] like Figure 5 As shown, different laser energies irradiate the amorphous test layer, resulting in different optical parameters (including refractive index n and extinction coefficient k) for the crystalline test layer. Furthermore, higher laser energy corresponds to lower optical parameters. Therefore, a one-to-one correspondence between multiple energies and multiple optical parameters can be established and stored in a database. Since there is a certain error in the detection of optical parameters, a one-to-one correspondence between multiple energies and multiple optical parameter ranges can also be established and stored in a database, with no overlap among the multiple optical parameter ranges.

[0112] Then, the degree of crystallization of multiple crystallization test layers was detected.

[0113] Specifically, each crystallized test layer is subjected to electrical tests to detect its electrical properties (including resistance value, etc.). Since different crystallization levels vary among the test layers, their electrical properties differ. Pre-set electrical properties refer to the standard electrical properties of a crystallized test layer when the non-crystalline test layer has completely crystallized into a crystalline test layer. If the electrical properties of a certain crystallized test layer are the same as these standard electrical properties, then this crystallized test layer is designated as the target crystallized test layer. The optical parameters of the target crystallized test layer are then designated as standard optical parameters for comparison with the optical parameters of the detection unit 11' during actual testing. Furthermore, the energy of the laser corresponding to the target crystallized test layer is designated as a standard energy so that the non-crystalline layer is irradiated with this standard energy laser during actual production.

[0114] It should be noted that in this embodiment, only electrical testing is required on the crystalline test layer to determine the standard optical parameters. After determining the standard optical parameters, no further electrical testing is needed. That is, in actual production, after the amorphous layer 1 is crystallized into crystalline layer 1', there is no need to perform electrical testing on crystalline layer 1'; only the corresponding optical parameters need to be tested. Compared to electrical testing, the detection cycle for optical parameters is shorter and the detection cost is lower.

[0115] Step 103: Detect the degree of crystallization of the crystallized layer in the core area based on the comparison results.

[0116] In this embodiment of the invention, since the degree of crystallization of the detection unit 11' is the same as the degree of crystallization of the crystal layer 1' of the core region A, the optical parameters of the detection unit 11' can reflect the optical parameters of the crystal layer 1' of the core region A. The comparison result between the optical parameters of the detection unit 11' and the standard optical parameters can reflect the comparison result between the optical parameters of the crystal layer 1' of the core region A and the standard optical parameters. Therefore, based on the comparison result between the optical parameters of the detection unit 11' and the standard optical parameters, the degree of crystallization of the crystal layer 1' of the core region A can be detected.

[0117] Specifically, step 103, which involves detecting the degree of crystallization of the crystalline layer in the core region based on the comparison results, includes:

[0118] If the comparison result shows that the optical parameters of the detection unit are greater than the standard optical parameters, then it is determined that the degree of crystallization of the crystal layer in the core region does not meet the preset crystallization requirements;

[0119] If the comparison result shows that the optical parameters of the detection unit are less than or equal to the standard optical parameters, then it is determined that the crystallization degree of the crystallization layer in the core region meets the preset crystallization requirements.

[0120] Because laser energy is unstable, the laser stage is set to irradiate the amorphous layer with a standard energy laser. However, the actual energy of the laser irradiating the amorphous layer may not be the standard energy. If the actual laser energy is greater than or equal to the standard energy, the amorphous layer will completely crystallize into a crystalline layer. If the actual laser energy is less than the standard energy, the amorphous layer will not completely crystallize into a crystalline layer. Since the laser energy corresponds to the optical parameters of the crystalline layer, the optical parameters of the detection unit 11' are compared with the standard optical parameters to determine the actual laser energy based on the comparison results, thereby determining the degree of crystallization of the crystalline layer 1' in the core region A.

[0121] As the laser energy increases, the optical parameters of the crystallized layer decrease. Therefore, if the optical parameters of the detection unit 11' are greater than the standard optical parameters, it indicates that the optical parameters of the crystallized layer 1' in the core region A are greater than the standard optical parameters, and the actual laser energy is less than the standard energy. In this case, it is determined that the crystallization degree of the crystallized layer 1' in the core region A does not meet the preset crystallization requirements, for example, the crystallized layer 1' in the core region A is not fully crystallized. If the optical parameters of the detection unit 11' are less than or equal to the standard optical parameters, it indicates that the optical parameters of the crystallized layer 1' in the core region A are less than or equal to the standard optical parameters, and the actual laser energy is greater than or equal to the standard energy. In this case, it is determined that the crystallization degree of the crystallized layer 1' in the core region A meets the preset crystallization requirements, for example, the crystallized layer 1' in the core region A is fully crystallized.

[0122] In this embodiment, after determining the standard optical parameters, only the optical parameters of the detection unit 11' need to be detected to detect the degree of crystallization of the crystal layer 1' in the core region A. There is no need to perform electrical tests, which improves detection efficiency and reduces detection costs.

[0123] Furthermore, in this embodiment, when detecting the degree of crystallinity of the crystallization layer 1' in the core region A, the stability of the laser energy can also be detected. Further, the method also includes:

[0124] The energy of the laser is tested to determine whether it is stable based on the comparison results.

[0125] Specifically, the step of detecting whether the energy of the laser is stable based on the comparison result includes:

[0126] If the comparison result shows that the optical parameters of the detection unit are consistent with the standard optical parameters, then the energy of the laser is determined to be stable.

[0127] If the comparison result shows that the optical parameters of the detection unit are inconsistent with the standard optical parameters, then the energy of the laser is determined to be unstable.

[0128] Since the laser stage irradiates the amorphous layer 1 with a standard energy laser, if the laser energy is stable, the crystallization degree of the crystalline layer 1' meets the preset crystallization requirements. For example, the amorphous layer 1 may completely crystallize into the crystalline layer 1', at which point the optical parameters of the crystalline layer 1' should be the standard optical parameters. Therefore, the optical parameters of the detection unit 11' are compared with the standard optical parameters to determine whether the laser energy is stable. When the comparison result shows that the optical parameters of the detection unit 11' are consistent with the standard optical parameters, it indicates that the optical parameters of the crystalline layer 1' in the core region A are consistent with the standard optical parameters, thus determining that the laser energy is the standard energy and the laser energy is stable. When the comparison result shows that the optical parameters of the detection unit 11' are inconsistent with the standard optical parameters, it indicates that the optical parameters of the crystalline layer 1' in the core region A are inconsistent with the standard optical parameters, thus determining that the laser energy is not the standard energy and the laser energy is unstable. After determining that the laser energy is unstable, the actual laser energy can be determined based on the correspondence between the laser energy and the optical parameters. If the actual energy of the laser is greater than the standard energy, no action needs to be taken on the laser stage; if the actual energy of the laser is less than the standard energy, the laser stage needs to be inspected and maintained.

[0129] Furthermore, this embodiment can also detect the ion doping concentration of the amorphous layer 1 by detecting optical parameters. For example... Figure 6 As shown, the optical parameters (including refractive index n and extinction coefficient k) of amorphous layers with different doping concentrations are different, and the higher the doping concentration of the amorphous layer, the higher the corresponding optical parameters. Therefore, a one-to-one correspondence between multiple doping concentrations and multiple optical parameters can be established and stored in a database.

[0130] After ion doping of the amorphous layer 1 in the core region A and the initial detection unit 11, the doping concentration of the amorphous layer 1 in the core region A is the same as that of the initial detection unit 11. The optical parameters of the initial detection unit 11 are detected by a preset detection wavelength to obtain the optical parameters of the amorphous layer 1 in the core region A. Then, by using the correspondence between doping concentration and optical parameters in the database, the doping concentration of the amorphous layer 1 in the core region A is determined, thereby detecting whether the doping concentration of the amorphous layer 1 in the core region A is the required doping concentration.

[0131] As can be seen from the above, the semiconductor device detection method provided in the embodiments of the present invention provides a detection unit in the non-functional area of ​​the crystal layer to detect the optical parameters of the detection unit, and compares the optical parameters of the detection unit with preset standard optical parameters to detect the degree of crystallization of the crystal layer in the core area based on the comparison results. This method does not require damage to the crystal layer in the core area, thereby ensuring that the semiconductor device is not damaged. Furthermore, it eliminates the need for electrical testing of the crystal layer, thereby improving detection efficiency and reducing detection costs.

[0132] Accordingly, embodiments of the present invention also provide a semiconductor device detection apparatus capable of implementing the above-described semiconductor device detection method.

[0133] See Figure 7 This is a schematic diagram of a semiconductor device detection device provided in an embodiment of the present invention. The semiconductor device referred to here is the same as the one described in the above embodiments, and will not be further described in detail here.

[0134] like Figure 7 As shown, the device includes:

[0135] Optical detection module 71 is used to detect the optical parameters of the detection unit;

[0136] The comparison module 72 is used to compare the optical parameters of the detection unit with preset standard optical parameters;

[0137] Crystallization degree detection module 73 is used to detect the crystallization degree of the crystallization layer in the core area based on the comparison results.

[0138] Furthermore, the device also includes:

[0139] The setting module is used to set the standard optical parameters; the standard optical parameters are the optical parameters of the target crystal test layer that meets the preset electrical properties among multiple crystal test layers, which are formed by irradiating each other with lasers of multiple energies in a one-to-one correspondence. Further, the crystallinity detection module is specifically used for:

[0140] If the comparison result shows that the optical parameters of the detection unit are greater than the standard optical parameters, then it is determined that the degree of crystallization of the crystal layer in the core region does not meet the preset crystallization requirements;

[0141] If the comparison result shows that the optical parameters of the detection unit are less than or equal to the standard optical parameters, then it is determined that the crystallization degree of the crystallization layer in the core region meets the preset crystallization requirements.

[0142] Furthermore, the crystalline layer is formed by laser irradiation with a preset standard energy;

[0143] The device further includes:

[0144] The stability detection module is used to detect whether the energy of the laser is stable based on the comparison results.

[0145] Furthermore, the stability detection module is specifically used for:

[0146] If the comparison result shows that the optical parameters of the detection unit are consistent with the standard optical parameters, then the energy of the laser is determined to be stable.

[0147] If the comparison result shows that the optical parameters of the detection unit are inconsistent with the standard optical parameters, then the energy of the laser is determined to be unstable.

[0148] Furthermore, the optical parameters include at least one of refractive index and extinction coefficient.

[0149] The semiconductor device detection apparatus provided in this embodiment of the invention has a detection unit set in the non-core area of ​​the crystal layer to detect the optical parameters of the detection unit and compare the optical parameters of the detection unit with preset standard optical parameters to detect the crystallization degree of the crystal layer in the core area based on the comparison result. This does not require damage to the crystal layer in the core area, thereby ensuring that the semiconductor device is not damaged. Moreover, it eliminates the need to perform electrical testing on the crystal layer, thereby improving detection efficiency and reducing detection costs.

[0150] Accordingly, embodiments of the present invention provide a method for manufacturing a semiconductor device, wherein the semiconductor device includes a core region A and a non-core region B, the non-core region B includes a step region B1 and a non-functional region B2, and the step region B1 is located between the core region A and the non-functional region B2.

[0151] like Figure 8 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes step 201, which is as follows:

[0152] Step 201: Form a crystalline layer, such that the non-core area of ​​the crystalline layer has a detection section, the thickness of which is the same as the thickness of the crystalline layer in the core area.

[0153] Specifically, the formation of the crystalline layer in step 201, which gives the non-core region of the crystalline layer a detection section, includes:

[0154] Provides a substrate located in a non-core area and a stacked structure located on one side of the substrate;

[0155] Through holes are formed in the substrate;

[0156] An amorphous layer is formed on the side of the substrate opposite to the stacked structure, such that the amorphous layer covers the stacked structure of the substrate and the core region and fills the through-hole;

[0157] The amorphous layer is converted into a crystalline layer, and the crystalline layer corresponding to the through hole constitutes the detection unit.

[0158] It should be noted that the non-core area A may also include a dicing channel, and the detection unit may be located on the dicing channel. After the semiconductor device is inspected, the semiconductor device can be diced to remove the dicing channel and the detection unit on the dicing channel, meaning that the final semiconductor device does not have a detection unit.

[0159] Accordingly, this invention provides a semiconductor device formed using the semiconductor device fabrication method described in the above embodiments, which will not be elaborated further here.

[0160] See Figure 9 This is a schematic diagram of the storage system provided in an embodiment of the present invention.

[0161] like Figure 9 As shown in the figure, this embodiment of the invention also provides a storage system, which includes a semiconductor device 300 and a controller 400. The semiconductor device 300 and the controller 400 are electrically connected, and the controller 400 is used to control the semiconductor device 300 to store data. The semiconductor device 300 is the semiconductor device in the above embodiment, and will not be described in detail here. The controller 400 can be a controller well known to those skilled in the art, and will not be described in detail here.

[0162] The storage system can be applied to terminal products such as computers, televisions, set-top boxes, and vehicles.

[0163] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for detecting a semiconductor device, characterized in that, The semiconductor device includes a core region and a non-core region. Before the semiconductor device is crystallized, an initial detection part in the non-core region and the amorphous layer in the core region are irradiated with the same laser to form a crystallized layer. The non-core region of the crystallized layer has a detection part, and the detection part and the crystallized layer of the core region have the same thickness. The method includes: Detect the optical parameters of the detection unit; The optical parameters of the detection unit are compared with preset standard optical parameters; The degree of crystallization of the crystallized layer in the core area was detected based on the comparison results.

2. The method for detecting semiconductor devices according to claim 1, characterized in that, The semiconductor device further includes a stacked structure and a substrate; The substrate is located on one side of the stacked structure and covers the stacked structure of the non-core area. The crystalline layer is located on the side of the substrate opposite to the stacked structure and covers the stacked structure of the substrate and the core area. The detection unit penetrates the substrate.

3. The method for detecting semiconductor devices according to claim 1, characterized in that, The method further includes: The standard optical parameters are set; the standard optical parameters are the optical parameters of the target crystal test layer that meets the preset electrical performance among multiple crystal test layers, and the multiple crystal test layers are formed by irradiating each other with lasers of multiple energies in a one-to-one correspondence.

4. The method for detecting semiconductor devices according to claim 1, characterized in that, The step of detecting the degree of crystallization of the crystallized layer in the core region based on the comparison results includes: If the comparison result shows that the optical parameters of the detection unit are greater than the standard optical parameters, then it is determined that the degree of crystallization of the crystal layer in the core region does not meet the preset crystallization requirements; If the comparison result shows that the optical parameters of the detection unit are less than or equal to the standard optical parameters, then it is determined that the crystallization degree of the crystallization layer in the core region meets the preset crystallization requirements.

5. The method for detecting semiconductor devices according to claim 1, characterized in that, The crystalline layer is formed by laser irradiation with a preset standard energy. The method further includes: The energy of the laser is tested to determine whether it is stable based on the comparison results.

6. The method for detecting semiconductor devices according to claim 5, characterized in that, The step of detecting whether the energy of the laser is stable based on the comparison result includes: If the comparison result shows that the optical parameters of the detection unit are consistent with the standard optical parameters, then the energy of the laser is determined to be stable. If the comparison result shows that the optical parameters of the detection unit are inconsistent with the standard optical parameters, then the energy of the laser is determined to be unstable.

7. The method for detecting semiconductor devices according to claim 1, characterized in that, The non-core area includes a non-functional area, and the detection unit is located in the non-functional area.

8. The method for detecting semiconductor devices according to claim 1, characterized in that, The optical parameters include at least one of refractive index and extinction coefficient.

9. The method for detecting semiconductor devices according to claim 1, characterized in that, The crystalline layer is a polycrystalline silicon layer.

10. The method for detecting a semiconductor device according to claim 1, characterized in that, The semiconductor device is a memory.

11. A semiconductor device, characterized in that, Including core and non-core areas; The semiconductor device includes: A crystalline layer is formed by irradiating an initial detection section in a non-core area and an amorphous layer in a core area with the same laser. The non-core area of ​​the crystalline layer has a detection section with the same thickness as the crystalline layer in the core area. The detection section is used to detect and acquire optical parameters. The optical parameters of the detection section are compared with preset standard optical parameters, and the degree of crystallization of the crystalline layer in the core area is detected based on the comparison results.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: Stacked structure; A substrate, located on one side of the stacked structure and covering the non-core area of ​​the stacked structure; The crystalline layer is located on the side of the substrate opposite to the stacked structure and covers the stacked structure of the substrate and the core area, and the detection unit penetrates the substrate.

13. The semiconductor device according to claim 11, characterized in that, The crystalline layer is a polycrystalline silicon layer.

14. The semiconductor device according to claim 11, characterized in that, The non-core area includes a stepped area and a non-functional area located in the stepped area away from the core area, and the detection unit is located in the non-functional area.

15. The semiconductor device according to claim 11, characterized in that, The semiconductor device is a memory.

16. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes a core region and a non-core region; The method includes: A crystalline layer is formed by irradiating the initial detection section in the non-core area and the amorphous layer in the core area with the same laser. The non-core area of ​​the crystalline layer has a detection section with the same thickness as the crystalline layer in the core area. The detection section is used to detect and acquire optical parameters. The optical parameters of the detection section are compared with preset standard optical parameters. The degree of crystallization of the crystalline layer in the core area is detected based on the comparison results.

17. The method for fabricating a semiconductor device according to claim 16, characterized in that, The step of forming a crystalline layer, such that the non-core region of the crystalline layer has a detection section, includes: Provides a substrate located in a non-core area and a stacked structure located on one side of the substrate; Through holes are formed in the substrate; An amorphous layer is formed on the side of the substrate opposite to the stacked structure, such that the amorphous layer covers the stacked structure of the substrate and the core region and fills the through-hole; The amorphous layer is converted into a crystalline layer, and the crystalline layer corresponding to the through hole constitutes the detection unit.

18. The method for fabricating a semiconductor device according to claim 16, characterized in that, The non-core area includes a cutting channel, and the detection unit is located on the cutting channel; The method further includes: Remove the cutting path and the detection section.

19. A semiconductor device, characterized in that, It is formed using the method for fabricating a semiconductor device as described in any one of claims 16 to 18.

20. A storage system, characterized in that, It includes the semiconductor device as described in any one of claims 11 to 15 or claim 19, and a controller connected to said semiconductor device.

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