A microminiaturization process for wafer sidewall openings

Abstract

The application provides a micro-shrinking process for wafer sidewall opening and relates to the technical field of wafer processing. The micro-shrinking process for wafer sidewall opening comprises the following steps: S1, on a wafer with a back surface provided with silicon oxide, ion implantation is first performed, then a chemical vapor deposition method is adopted to form a silicon nitride deposition layer, and then etching is performed on the wafer, so that the silicon nitride deposition layer forms a silicon nitride sidewall on both sides of the silicon oxide. The micro-shrinking process for wafer sidewall opening provided by the application can form a silicon oxynitride sidewall in the inside of the silicon nitride sidewall by filling a silicon oxynitride layer in the contact hole and then etching, can micro-shrink the contact hole opening originally in the inside of the silicon nitride sidewall, can make the contact hole opening micro-shrink in the inside of the silicon oxynitride sidewall, can make the contact hole opening formed above the wafer smaller, can obtain a smaller contact hole without a high-precision contact hole etching device, and can effectively improve the process precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wafer processing, in particular to a micro-shrinking process for wafer sidewall opening. BACKGROUND

[0002] The wafer refers to a silicon wafer used for manufacturing silicon semiconductor circuits, the raw material of which is silicon, high-purity polycrystalline silicon is dissolved and then doped into a silicon crystal seed, and then slowly pulled out to form a cylindrical single crystal silicon, the silicon crystal rod is ground, polished and sliced to form a silicon wafer, that is, a wafer.

[0003] In the process of wafer processing, a contact hole is formed on the wafer by etching to facilitate the deposition of metal on the wafer.

[0004] In the prior art, due to the difficulty in breaking through the high-precision etching equipment technology, only low-precision etching equipment can be selected for wafer etching, and in order to avoid over-etching or etching deviation when using low-precision wafer etching equipment for etching, a silicon nitride sidewall can be made above the wafer to protect the etching of the contact hole, but the contact hole etched by the silicon nitride sidewall protection has the same size as the silicon nitride sidewall, which is not convenient for using low-precision etching equipment to process a contact hole with higher precision. SUMMARY

[0005] To solve the problems mentioned in the background art, the purpose of the present application is to provide a micro-shrinking process for wafer sidewall opening to solve the problem that the contact hole etched by the silicon nitride sidewall protection is not convenient for using low-precision etching equipment to process a contact hole with higher precision.

[0006] The purpose of the present application can be achieved by the following technical solutions:

[0007] A micro-shrinking process for wafer sidewall opening, comprising the following steps:

[0008] S1, on a wafer with silicon oxide on the back, first ion implantation is performed, then a layer of silicon nitride deposition layer is formed by chemical vapor deposition method, and then the wafer is etched to form silicon nitride sidewalls on both sides of the silicon oxide, and finally the wafer is etched again to form a groove on the wafer;

[0009] S2, the wafer obtained in step S1 is oxidized-etched-oxidized again to form a gate oxide layer on the inner wall of the groove, then polycrystalline silicon is deposited on the back of the wafer, then the polycrystalline silicon is etched to remove the polycrystalline silicon outside the groove, and finally a layer of silicon oxynitride is deposited on the back of the wafer by chemical vapor deposition method;

[0010] S3, depositing a silicon oxide layer on the silicon oxynitride of the back surface of the wafer obtained in step S2 by chemical deposition, and then planarizing the surface of the silicon oxide layer by CMP process;

[0011] S4, etching the upper part of the silicon oxide layer of the wafer obtained in step S3, and then etching the silicon oxynitride and the silicon oxide under the silicon oxide layer in sequence to form a contact hole on the back surface of the wafer;

[0012] S5, etching the part of the surface of the wafer obtained in step S4 under the contact hole, and then implanting ions into the part of the surface of the wafer under the contact hole by ion implantation;

[0013] S6, depositing a silicon oxynitride layer on the upper part of the silicon oxide layer of the back surface of the wafer obtained in step S5 by chemical vapor deposition, and then etching the silicon oxynitride layer to etch the silicon oxynitride outside the contact hole and part of the silicon oxynitride layer inside the contact hole to form a silicon oxynitride sidewall inside the contact hole, and finally filling the contact hole with metal.

[0014] Preferably, in step S2, the back surface of the wafer is oxidized as a whole in the first oxidation, and the inner wall of the trench is oxidized alone to form a dense gate oxide layer in the second oxidation.

[0015] Preferably, in step S2, the polycrystalline silicon outside the trench is removed by etching, and the top of the polycrystalline silicon is planarized by CMP process before etching.

[0016] Preferably, in step S2, the polycrystalline silicon deposited on the back surface of the wafer is impurity-containing polycrystalline silicon to form a transistor inside the trench.

[0017] Preferably, in step S3, the etching position on the upper part of the silicon oxide layer of the wafer is located inside the silicon nitride sidewall to form a protection for the etching position by the silicon nitride sidewall, and the etching method is dry etching.

[0018] Preferably, in step S6, the implanted ions form an electrode with the ions implanted in step S1 on the wafer, and the contact surface of the filled metal and the electrode is located inside the silicon oxynitride sidewall.

[0019] The beneficial effects of the present application are as follows:

[0020] By filling the contact hole with a silicon oxynitride layer and then etching, a layer of silicon oxynitride sidewall can be formed inside the silicon nitride sidewall, the contact hole opening originally inside the silicon nitride sidewall is miniaturized, the contact hole opening is miniaturized inside the silicon oxynitride sidewall, the contact hole opening formed above the wafer is smaller, a smaller contact hole can be obtained without high-precision contact hole etching equipment, the process precision is effectively improved, it is more convenient to form a smaller contact hole above the wafer, and the protection ability of the inner part of the contact hole is further improved by the silicon oxynitride sidewall and the silicon nitride sidewall outside the contact. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings;

[0022] Figure 1 is a flowchart of step S1 of the present application;

[0023] Figure 2 is a flowchart of step S2 of the present application;

[0024] Figure 3 is a flowchart of step S3 of the present application;

[0025] Figure 4 is a flowchart of step S4 of the present application;

[0026] Figure 5 is a flowchart of step S5 of the present application;

[0027] Figure 6 is a flowchart of step S6 of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0029] A micro-miniaturization process for wafer sidewall opening, comprising the following steps:

[0030] S1, on the wafer with silicon oxide on the back, first ion implantation, then a layer of silicon nitride deposition by chemical vapor deposition method, and then etching the wafer, so that the silicon nitride deposition layer on both sides of the silicon oxide form silicon nitride sidewall, and finally etching the wafer on the top, so that the wafer on the top of the trench;

[0031] S2, the wafer obtained in step S1 is oxidized-etched-oxidized again, to form a gate oxide layer in the inner wall of the trench, then depositing polysilicon on the back of the wafer, then etching the polysilicon, etching the polysilicon outside the trench, and finally depositing a layer of silicon oxynitride on the back of the wafer by chemical vapor deposition method;

[0032] S3, on the back of the wafer obtained in step S2, a layer of silicon oxide is deposited on the silicon oxynitride by chemical deposition method, and then the surface of the silicon oxide layer is planarized by CMP process;

[0033] S4, on the wafer obtained in step S3, etching the top of the silicon oxide layer, and then etching the silicon oxynitride and silicon oxide below the silicon oxide layer in turn, to form a contact hole on the back of the wafer;

[0034] S5, on the wafer obtained in step S4, etching the position of the wafer surface below the contact hole, and then ion implantation on the position of the wafer surface below the contact hole by ion implantation method;

[0035] S6, on the wafer obtained in step S5, a layer of silicon oxynitride is deposited on the top of the silicon oxide layer on the back of the wafer by chemical vapor deposition method, and then etching the silicon oxynitride layer, etching the silicon oxynitride outside the contact hole and part of the silicon oxynitride layer inside the contact hole, to form a silicon oxynitride sidewall inside the contact hole, and finally filling the contact hole with metal.

[0036] In step S2, when the wafer is oxidized for the first time, the back of the wafer is oxidized as a whole, and when the wafer is oxidized for the second time, only the inner wall of the trench is oxidized to form a dense gate oxide layer.

[0037] In step S2, when the polysilicon outside the trench is removed by etching, first, the top of the polysilicon is planarized by CMP process, and then etching is performed.

[0038] In step S2, the polysilicon deposited on the back of the wafer is impurity-containing polysilicon, to form a transistor inside the trench.

[0039] In step S3, the position of etching the top of the silicon oxide on the wafer is inside the silicon nitride sidewall, to realize the protection of the etching position by the silicon nitride sidewall, and the etching method adopts dry etching.

[0040] In the step S6, the implanted ions form electrodes on the wafer with the ions implanted in the step S1, and the contact surface of the filled metal and the electrodes is located inside the silicon nitride oxide sidewall.

[0041] The working principle of the micro process for wafer sidewall opening provided by the application is as follows:

[0042] As Figure 1 , by etching the silicon oxide deposition layer, the silicon nitride sidewall is formed, and when the trench is opened, the trench opening is located between the two silicon nitride sidewalls, which protects the trench opening from being etched too large when the trench is etched;

[0043] As Figure 4 , when the contact hole is etched above the wafer, the silicon nitride sidewall can limit the size of the contact hole to prevent the contact hole from being too large, and also prevent the metal from contacting the polysilicon and conducting when the metal is filled in the contact hole.

[0044] As Figure 6 , by filling the silicon nitride oxide layer in the contact hole and etching, the silicon nitride oxide layer can form a silicon nitride oxide sidewall inside the contact hole, so that the metal is filled inside the silicon nitride oxide sidewall when the metal is filled.

[0045] Compared with the related art, the micro process for wafer sidewall opening provided by the application has the following beneficial effects:

[0046] By filling the silicon nitride oxide layer in the contact hole and etching, a layer of silicon nitride oxide sidewall is formed inside the silicon nitride sidewall, which shrinks the contact hole opening originally inside the silicon nitride sidewall, so that the contact hole opening is shrunk inside the silicon nitride oxide sidewall, and the contact hole opening formed above the wafer is smaller, without the need for high-precision contact hole etching equipment to obtain smaller contact holes, effectively improving the process precision, making it more convenient to form smaller contact holes above the wafer, and further improving the protection ability of the contact hole inside part through the silicon nitride oxide sidewall outside the contact and the silicon nitride sidewall.

[0047] The basic principles, main features and advantages of the application are shown and described above. Those skilled in the art should understand that the application is not limited by the above examples, and the above examples and descriptions in the specification are only to illustrate the principles of the application. Without departing from the spirit and scope of the application, various changes and improvements can be made to the application, and these changes and improvements all fall within the scope of the claimed application.

Claims

1. A miniaturization process for wafer sidewall openings, characterized in that, Includes the following steps: S1. On the wafer with silicon oxide on the back side, ion implantation is first performed, and then a silicon nitride deposition layer is formed by chemical vapor deposition. Then the wafer is etched so that the silicon nitride deposition layer forms silicon nitride sidewalls on both sides of the silicon oxide. Finally, the top of the wafer is etched again to form a trench on the top of the wafer. S2. The wafer obtained in step S1 is oxidized-etched-oxidized again to form a gate silicon oxide layer on the inner wall of the trench. Then, polysilicon is deposited on the back side of the wafer. The polysilicon is then etched to remove the polysilicon located outside the trench. Finally, a layer of silicon oxynitride is deposited on the back side of the wafer using chemical vapor deposition. S3. A silicon oxide layer is deposited on the back side of the wafer obtained in step S2 by chemical deposition, and then the surface of the silicon oxide layer is planarized by CMP process. S4. For the wafer obtained in step S3, etch the area above the silicon oxide layer, and then etch away the silicon oxynitride and silicon oxide below the silicon oxide layer in sequence to form contact holes on the back side of the wafer. S5. For the wafer obtained in step S4, etch the position on the wafer surface below the contact hole, and then use the ion implantation method to implant ions on the position on the wafer surface below the contact hole. S6. For the wafer obtained in step S5, a silicon oxynitride layer is deposited on the back side of the wafer using chemical vapor deposition on top of the silicon oxide layer. Then, the silicon oxynitride layer is etched to etch the silicon oxynitride outside the contact hole and part of the silicon oxynitride layer inside the contact hole, forming a silicon oxynitride sidewall inside the contact hole. Finally, metal is filled into the contact hole. In step S2, when the wafer is oxidized for the first time, the back side of the wafer is oxidized as a whole, and when the wafer is oxidized for the second time, the inner wall of the trench is oxidized separately to form a dense gate silicon oxide layer. In step S2, when removing the polysilicon outside the trench by etching, the top of the polysilicon is first planarized using a CMP process before etching. In step S2, the polysilicon deposited on the back side of the wafer is polysilicon containing impurities in order to form transistors inside the trench.

2. The miniaturization process for wafer sidewall openings according to claim 1, characterized in that, In step S3, the etching location above the silicon oxide on the wafer is located inside the silicon nitride sidewall, so as to protect the etching location through the silicon nitride sidewall. The etching method is dry etching.

3. The miniaturization process for wafer sidewall openings according to claim 1, characterized in that, In step S5, the implanted ions and the ions implanted in step S1 form an electrode on the wafer, and the contact surface between the filled metal and the electrode is located inside the silicon oxynitride sidewall.

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