Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate; wherein the substrate comprises a first doped region and a second doped region; a control circuit comprising a source / drain region and a gate structure; wherein the source / drain region is located in the first doped region, and the gate structure is located on the substrate; a sealing ring coupled with the second doped region, the sealing ring surrounding the control circuit; the sealing ring comprises a pad structure, the pad structure is located at one end of the sealing ring away from the substrate; wherein the pad structure is in the shape of a mouth or a back along the cross section parallel to the substrate direction; and / or the average grain diameter of the pad structure is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500nm to 600nm.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method of the semiconductor structure. BACKGROUND

[0002] In the process of manufacturing semiconductor chips, a plurality of chips are usually integrated on a wafer for simultaneous manufacturing. Then, the chips are cut from the wafer and applied to integrated circuits after packaging.

[0003] When designing the layout of devices in a semiconductor chip, a seal ring (SR) (also referred to as an isolation ring) is usually arranged around the device region of the chip. The seal ring has a certain distance from the semiconductor device to effectively separate the edge of the semiconductor device, so as to reduce mechanical damage to the device caused by the cutting process and moisture intrusion. In addition, the seal ring is usually made of conductive material to reduce damage to the internal circuit of the device caused by electrostatic charge discharge. However, the quality of the seal ring will affect the yield of the device. SUMMARY

[0004] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising:

[0005] a substrate; wherein the substrate comprises a first doped region and a second doped region;

[0006] a control circuit comprising a source / drain region and a gate structure; wherein the source / drain region is located in the first doped region, and the gate structure is located on the substrate;

[0007] a seal ring coupled with the second doped region, the seal ring surrounding the control circuit;

[0008] the seal ring comprises a pad structure located at an end of the seal ring opposite to the substrate; wherein,

[0009] the pad structure is in a mouth-shaped or a back-shaped cross section along a direction parallel to the substrate;

[0010] and / or,

[0011] an average grain diameter of a material of the pad structure is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm.

[0012] According to a second aspect of an embodiment of the present disclosure, a manufacturing method of a semiconductor structure is provided, comprising:

[0013] providing a substrate;

[0014] forming a first doped region and a second doped region in the substrate;

[0015] forming a control circuit comprising a source / drain region and a gate structure; wherein the source / drain region is located in the first doped region, and the gate structure is located on the substrate;

[0016] forming a sealing ring comprising a pad structure on the substrate; wherein the sealing ring is coupled with the second doped region, the sealing ring surrounds the control circuit, and the pad structure is located at an end of the sealing ring away from the substrate;

[0017] the pad structure is in a mouth-shaped or a U-shaped cross section along a direction parallel to the substrate; and / or an average grain diameter of a material constituting the pad structure is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm.

[0018] In the semiconductor structure provided by the embodiments of the present disclosure, the sealing ring comprises the pad structure, and the pad structure is located at an end of the sealing ring away from the substrate. The pad structure is in a mouth-shaped or a U-shaped cross section along a direction parallel to the substrate; and / or an average grain diameter of a material constituting the pad structure is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm. The pad structure provided by the embodiments of the present disclosure can be implemented in any one of the above two manners or a combination thereof.

[0019] In one aspect, in the embodiments, the pad structure is in a mouth-shaped or a U-shaped cross section along a direction parallel to the substrate, and the pad structure in the sealing ring is in a trench type, i.e., the pad structure is filled in a trench extending along a direction parallel to the substrate. In the case of the same volume of the sealing ring, the volume of the conductive material that can be deposited in the pad structure in the trench type is greater than the volume of the conductive material that can be deposited in the pad structure in a via type. Therefore, by increasing the volume of the conductive material deposited in the pad structure, the semiconductor structure provided by the embodiments can reduce the probability of a large depression of the pad structure in a cleaning process.

[0020] In another aspect, in the embodiments, an average grain diameter of a material constituting the pad structure is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm. Compared with a pad structure constituted by micrometer or even millimeter level large grains, the average grain diameter of the material constituting the pad structure is smaller. Since the material constituted by small grains has a higher material strength, the embodiments improve the strength of the pad structure, thereby reducing the probability of a large depression of the pad structure in a cleaning process and reducing the probability of defects such as a void in a bonding structure in bonding, which is conducive to improving the yield of a device. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1a A schematic view of a semiconductor structure according to an example embodiment;

[0022] Figure 1b A schematic view of a semiconductor structure according to an example embodiment; Figure 1a A schematic view of a semiconductor structure according to an example embodiment;

[0023] Figure 1c A schematic view of a sealing ring and a dummy sealing ring structure according to an example embodiment;

[0024] Figure 2a A first schematic view of a semiconductor structure according to an example embodiment;

[0025] Figure 2b A second schematic view of a semiconductor structure according to an example embodiment;

[0026] Figure 3a A top view partial schematic view of a sealing ring according to an example embodiment;

[0027] Figure 3b A top view partial schematic view of another sealing ring according to an example embodiment;

[0028] Figure 3c A top view schematic view of yet another sealing ring according to an example embodiment;

[0029] Figure 4 A schematic view of a semiconductor structure according to an example embodiment;

[0030] Figure 5 A flow chart of a method of fabricating another semiconductor structure according to an example embodiment. DETAILED DESCRIPTION

[0031] The technical solutions of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] In the embodiments of the present disclosure, the terms "first", "second", and the like are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0033] In the embodiments of the present disclosure, the term "A is in contact with B" includes the case where A is in direct contact with B, or the case where A is indirectly in contact with B with other components interposed between A and B.

[0034] In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. Also, a layer can include multiple sub-layers.

[0035] It is to be understood that the meaning of "on," "over," and "above" in the present disclosure should be interpreted in the broadest context possible, such that "on" not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes "on" something with intervening features or layers therebetween.

[0036] In a hybrid bonding process, a first wafer and a second wafer are provided, in which an interlayer dielectric layer is first formed in the first wafer and the second wafer, then a pad opening (e.g., a via) is formed in the interlayer dielectric layer, a barrier layer and a copper seed layer are formed in the pad opening, then a copper conductive layer is formed in the pad opening by an electrochemical plating (ECP) process, after the surface of the copper conductive layer is polished flat by chemical mechanical polishing (CMP), a copper pad is formed. Then the first wafer and the second wafer formed with the copper pad are cleaned, and then the copper pads of the first wafer and the second wafer can be bonded together by bonding (e.g., low-temperature thermal compression bonding) to form a bonding structure between the first wafer and the second wafer, thereby realizing the bonding of the first wafer and the second wafer.

[0037] Specifically, the first wafer can include a wafer formed with a memory array, and the second wafer can include a wafer formed with a control circuit. It is usually necessary to clean (e.g., using a plasma cleaning process) the first wafer and the second wafer before the bonding process. However, during the plasma cleaning process, the wafer surface is deprotonated in the cleaning liquid (e.g., deionized water, DIW) and becomes negatively charged, so the wafer surface after the plasma cleaning process will inevitably have a high negative charge, resulting in device property degradation and reliability failure. When the charge accumulation exceeds the breakdown voltage, discharge will cause device damage and failure.

[0038] The copper pads of the first wafer and the second wafer after cleaning are bonded together to form a bonding structure between the first wafer and the second wafer. When the surface charge accumulation of the wafer exceeds the breakdown voltage, a discharge phenomenon occurs, which causes a void problem at the pad of the filling via in the bonding structure.

[0039] It should be noted that when the pH value of the cleaning solution is greater than 2.45 and less than or equal to 10, the wafer surface is negatively charged, and the wafer surface has a negative potential. The charge density of the wafer surface decreases as the pH value decreases. When the pH value of the cleaning solution is 2.45, the wafer surface potential is zero. When the pH value of the cleaning solution is less than 2.45, the wafer surface is positively charged and has a positive potential. Therefore, during the cleaning process of the wafer, the negative charge on the wafer surface can be inhibited by increasing the acidity of the cleaning solution (i.e., reducing the pH value of the cleaning solution).

[0040] For example, in order to reduce the high negative charge on the wafer surface, a cleaning solution with added carbon dioxide (CO2) can be introduced into the plasma cleaning process, so that the pH value of the cleaning solution is reduced. In this way, at least part of the negative charge on the wafer surface can be neutralized, the high negative charge on the wafer surface can be reduced, and the device failure caused by the accumulation of negative charge on the wafer surface can be effectively reduced.

[0041] However, although the cleaning solution with added carbon dioxide (CO2) introduced into the plasma cleaning process can reduce the high negative charge on the wafer surface, the cleaning solution with added carbon dioxide (CO2) is acidic. When the pad surface of the wafer with the control circuit exposed is cleaned with the acidic cleaning solution, a large depression will be formed on the pad surface, which may cause a large void in the connection after the wafer is bonded.

[0042] The reasons for the large depression on the pad surface of the wafer with the control circuit exposed are analyzed as follows:

[0043] Figure 1a A semiconductor structure according to an exemplary embodiment is shown in a schematic view. Referring to Figure 1a The semiconductor structure includes a substrate, a P-type doped well in the substrate, a seal ring coupled to the P-type doped well, Figure 1a a seal ring via is marked in the dashed circle, the seal ring via is filled with a conductive material to form a pad, and the pad is located at an end of the seal ring opposite to the substrate. The semiconductor structure further includes a plurality of metal layers, Figure 1a five layers are shown in the figure, which are respectively marked as a first metal layer to a fifth metal layer, and the number of metal layers can be set according to the number of metal layers required by the chip to be protected. The semiconductor structure further includes a plurality of vias and contact plugs, Figure 1aIn the semiconductor structure, the contact plug is coupled with the P-type doped well, the first metal layer is coupled with the contact plug, each metal layer between the first metal layer and the fifth metal layer is coupled through the via, and the fifth metal layer is coupled with the pad.

[0044] From Figure 1a It can be seen that all the metal layers are connected together, and the P-type doped well is connected with the metal layers through the contact plug, so that all the layers (i.e. the P-type doped well, the metal layers and the pad) maintain the same electric potential.

[0045] Further tracking the process of the plasma cleaning process with the addition of carbon dioxide (CO2), the disclosure finds that the reason for the large concave of the pad in the sealing ring via is that, on the one hand, the sealing ring is coupled with the P-type doped well in the lower substrate, and a sealing ring via coupled with the sealing ring is formed at the end of the sealing ring away from the substrate, and in the process of forming the pad in the sealing ring via, due to the strong attraction of the holes in the P-type doped well to the electrons, the pad in the sealing ring via loses electrons and is oxidized to ions in the planarization or cleaning process, etc., which further causes the conductive material to leave the surface of the pad, resulting in a large butterfly-shaped concave defect on the surface of the pad in the sealing ring via, and the range of the large butterfly-shaped concave can refer to Figure 1b (e.g. 90 angstroms).

[0046] On the other hand, there is a dummy sealing ring (Dummy SR) with the same structure as the sealing ring near the sealing ring, as shown in Figure 1c , the dummy sealing ring Dummy SR is connected with the first region of the lower substrate, and the sealing ring SR is connected with the second region of the lower substrate, wherein the first region can include an undoped region or a low-doped region, and the first region can also include an oxide film region on the substrate, and the second region can include a region with P-type doping. The dummy sealing ring via (Dummy Via) is connected with the first region of the lower substrate through the multi-layer metal layers (such as Figure 1c the first metal layer to the fifth metal layer in the semiconductor structure) and the contact plug, and the sealing ring via is coupled with the P-type doped well in the lower substrate through the multi-layer metal layers (such as Figure 1c the first metal layer to the fifth metal layer in the semiconductor structure) and the contact plug. Due to the high concentration of boron ions in the P-type doped well, the surface of the pad in the sealing ring via has a lower electric potential than the surface of the pad in the dummy sealing ring via. Therefore, in the plasma cleaning process with the addition of carbon dioxide (CO2), the surface of the pad in the sealing ring via is prone to copper ion loss and forms a large butterfly-shaped concave, and the range of the large butterfly-shaped concave can refer to Figure 1b (e.g. 90 angstroms), which will cause a large void at the connection after wafer bonding.

[0047] Therefore, the embodiments of the disclosure provide another semiconductor structure.

[0048] Figure 2a Fig. 1 shows a first schematic view of a semiconductor structure according to an exemplary embodiment. Referring to Fig. 1, a semiconductor structure 100 includes: Figure 2a and Figure 3b , Figure 3c Fig. 1 shows a first schematic view of a semiconductor structure according to an exemplary embodiment. Referring to Fig. 1, a semiconductor structure 100 includes:

[0049] a substrate 110; wherein the substrate 110 includes a first doped region and a second doped region 120;

[0050] a control circuit 210 including source / drain regions and gate structures; wherein the source / drain regions are located in the first doped region, and the gate structures are located on the substrate 110;

[0051] a sealing ring 130 coupled with the second doped region 120, the sealing ring 130 surrounding the control circuit 210;

[0052] the sealing ring 130 includes a pad structure 131a located at an end of the sealing ring 130 opposite to the substrate 110; wherein,

[0053] the pad structure 131a has a cross-section in a direction parallel to the substrate 110 in a shape of a mouth or a back.

[0054] In this embodiment, the material of the substrate 110 includes, but is not limited to, monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials such as gallium arsenide and other group III-V compounds. According to the actual needs of the device, a suitable semiconductor material can be selected as the substrate 110, which is not limited herein. In this embodiment, the substrate 110 is taken as an example of a monocrystalline silicon substrate.

[0055] Here, the control circuit 210 includes a logic control circuit composed of a plurality of transistors. The control circuit 210 can be applied to a memory cell array to control the memory cells in the memory cell array to perform read / write or erase operations. Specifically, the control circuit 210 includes a plurality of transistors, and the transistors include source / drain regions and gate structures, wherein the source / drain regions are located in the first doped region of the substrate (not shown), and the gate structures can include a gate dielectric layer and a gate electrode, which can be stacked on the surface of the substrate (not shown).

[0056] Specifically, the control circuit 210 can be coupled to the array of memory cells through bit lines, word lines, source lines, source select lines, and drain select lines. The control circuit 210 can include any suitable analog, digital, and mixed-signal circuitry to perform logical operations of the array of memory cells by applying sense voltage signals and / or current signals to each target memory cell via the bit lines, word lines, source lines, source select lines, and drain select lines. The control circuit 210 can include various types of control circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0057] For example, the control circuit 210 can include voltage generation circuitry, a plurality of drive circuits, drive lines, and sense lines. It should be appreciated that the control circuit 210 can also include page buffers / sense amplifiers, column decoders / bit line drivers, row decoders, control logic units, registers, interfaces, and data buses, etc.

[0058] In the semiconductor structure, the sealing ring 130 surrounds the control circuit 210, and there is a certain distance between the sealing ring 130 and the control circuit 210, so as to effectively protect the control circuit 210 and reduce the cutting damage of the control circuit 210 and the moisture intrusion in the cutting process.

[0059] Specifically, referring to Figure 3c In the semiconductor structure 100, the sealing ring 130 includes a continuous wall structure surrounding the control circuit 210, and there is a certain distance between the sealing ring 130 and the control circuit 210, so that the sealing ring 130 can reduce the mechanical damage of the control circuit 210 in the cutting process and the moisture intrusion into the control circuit 210. In Figure 3c In the embodiment, two control circuits 210 are shown for illustration, and the number of control circuits 210 is not limited in the embodiments of the present disclosure, for example, three control circuits 210, four control circuits 210, or more can be included.

[0060] It should be emphasized that, in combination with Figure 3c In the embodiment, the surrounding of the sealing ring 130 to the control circuit 210 refers to the surrounding of the side surface of the control circuit 210, and does not involve the covering of the top surface of the control circuit 210, and the sealing ring 130 can not be in direct contact with the control circuit 210.

[0061] Compared with a small number of carriers and low conductivity in a non-doped substrate (intrinsic semiconductor), the number of free electrons or holes in the substrate 110 is increased by providing the second doped region 120 in the substrate 110. Therefore, the conductivity of the part of the substrate 110 where the second doped region 120 is provided is greatly enhanced, and the conductivity of the part of the substrate 110 where the second doped region 120 is provided can be enhanced with the increase of the doping concentration in the second doped region 120. Here, the X-axis direction and the Y-axis direction shown in the drawings of the present disclosure are parallel to the direction of the substrate plane. The Z-axis direction is perpendicular to the direction of the substrate plane.

[0062] In general, with reference to Figure 3a , the pad structure is circular in cross-section parallel to the direction of the substrate, that is, the pad structure in the sealing ring is of the via type.

[0063] In this embodiment, the pad structure 131a is changed from a circular cross-section parallel to the direction of the substrate 110 to a mouth-shaped or back-shaped cross-section. With reference to Figure 3b , Figure 3b is a schematic diagram of the part of the pad structure 131a with a back-shaped cross-section parallel to the direction of the substrate 110. The pad structure in the sealing ring 130 is of the trench type, that is, the pad structure is filled in the trench which extends in the X-axis direction parallel to the direction of the substrate 110. It can be understood that in other embodiments, the pad structure can also be filled in a trench which extends in the Y-axis direction parallel to the direction of the substrate 110 (not shown). In the case of the same volume of the sealing ring 130, the volume of the conductive material that can be deposited in the pad structure 131a of the trench type is greater than the volume of the conductive material that can be deposited in the pad structure 131a of the via type. Therefore, the semiconductor structure proposed in this embodiment significantly increases the volume of the conductive material deposited in the pad structure 131a in the sealing ring 130, and can reduce the probability of a large depression of the pad structure 131a in the cleaning process.

[0064] In some embodiments, with reference to Figure 2b and Figure 3a , Figure 3c , a semiconductor structure 100 is also provided, comprising:

[0065] a substrate 110; wherein the substrate comprises a first doped region and a second doped region 120;

[0066] a control circuit 210 comprising a source / drain region and a gate structure; wherein the source / drain region is located in the first doped region, and the gate structure is located on the substrate 110;

[0067] a sealing ring 130, the sealing ring 130 is coupled with the second doped region 120, and the sealing ring 130 surrounds the control circuit 210;

[0068] The sealing ring 130 comprises a pad structure 131b located at an end of the sealing ring 130 away from the substrate 110, wherein

[0069] The average grain diameter of the pad structure 131b is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm.

[0070] In the embodiments of the present disclosure, referring to Figure 3a The pad structure can be circular in a cross section parallel to the substrate 110, and the pad structure in the sealing ring 130 is a via type, that is, the pad structure is filled in the via, and the average grain diameter of the material of the pad structure 131b is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm. Therefore, the grain diameter in the pad structure 131b is smaller than that of the pad structure composed of micrometer or even millimeter level large grains. Since the material composed of small grains has high material strength, the strength of the pad structure 131b is improved, thereby reducing the probability of large butterfly-shaped recesses in the pad structure 131b in the cleaning process and reducing the probability of defects such as voids in the bonding structure.

[0071] In some embodiments, the pad structure is preferably in a cross section parallel to the substrate 110, and the pad structure is in a cross section parallel to the substrate 110. The pad structure is in a cross section parallel to the substrate 110. The average grain diameter of the material of the pad structure is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm. According to the above analysis, the volume of the pad structure deposited with conductive material is increased, and the grain diameter in the pad structure is smaller, and the material has high strength, so that the probability of large butterfly-shaped recesses in the pad structure in the cleaning process can be significantly reduced, thereby reducing the probability of defects such as voids in the bonding structure.

[0072] Through the above improvement of the pad structure, the pad structure has the characteristics of high-strength material and / or large volume of deposited conductive material, which can reduce the probability of large recesses on the surface of the pad structure in subsequent cleaning processes. Therefore, the sealing ring 130 comprising the pad structure can maintain an intact structure and a good sealed environment, so that the sealing ring 130 can play a better protection role on the surrounding control circuit 210.

[0073] It can be understood that, according to the above analysis, the improved pad structure has smaller recesses in the subsequent plasma cleaning process with carbon dioxide, and the recess range can refer to Figure 4(For example, 5 to 50 angstroms). Generally, the thickness of the pad structure includes, but is not limited to, 30 nm to 500 nm, and the improved pad structure has a recess range of 5 to 50 angstroms. Compared with the pre-improved recess range of 90 angstroms, the improved pad structure has a significantly reduced proportion of the recess range in the overall thickness of the pad structure, and thus the improved pad structure has a reduced probability of defects such as cavities in the bonding structure formed by bonding, thereby improving the yield of the device.

[0074] In some embodiments, the pad structure is a single-grain layer or a multi-layer composite structure; wherein the multi-layer composite structure includes at least a multi-layer structure composed of a first grain layer and a second grain layer, the first grain layer is located at one end of the sealing ring 130 away from the substrate 110, and the second grain layer is located at one end of the sealing ring 130 close to the substrate 110, and the average grain diameter of the first grain layer is smaller than the average grain diameter of the second grain layer.

[0075] For example, the pad structure can be a single-grain layer composed of small grains, and the average grain diameter of the small grains is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm. The average grain diameter of the single-grain layer can be 10 nm to 500 nm, and the grain diameter in the pad structure is small. Since the material composed of small grains has high material strength, the overall strength of the single-grain layer composed of small grains is high, thereby reducing the probability of large recesses in the pad structure during the cleaning process.

[0076] For example, the pad structure can be a multi-layer composite structure, and the multi-layer composite structure can include a multi-layer structure composed of a first grain layer and a second grain layer, the first grain layer needs to satisfy that the average grain diameter is less than or equal to a preset diameter threshold, and the average grain diameter of the second grain layer can not be limited.

[0077] In other embodiments, the multi-layer composite structure can further include at least three grain layers stacked, the top grain layer of the sealing ring 130 away from the substrate 110 is referred to as the first grain layer, and the remaining grain layers other than the first grain layer are referred to as the remaining grain layers. The average grain diameter of the remaining grain layers can not be limited.

[0078] At this time, the first grain layer at the top of the pad structure is small, and since the material composed of small grains has high material strength, the first grain layer has high material strength, thereby reducing the probability of large recesses on the surface of the pad structure during the cleaning process.

[0079] Here, the pad structure of the present embodiment is preferably a single-layer grain layer. When facing the same conditions of adding carbon dioxide (CO2) in the plasma cleaning process, the manufacturing process of the multi-layer composite structure is more complex, the process is more difficult, and the cost is higher than that of the single-layer grain layer. Therefore, the pad structure is preferably a single-layer grain layer with a simple manufacturing process.

[0080] In other embodiments, the average grain diameter of the remaining grain layer of the multi-layer composite structure can be greater than the average grain diameter of the first grain layer. Since the average grain diameter of the remaining grain layer of the multi-layer composite structure is greater than the average grain diameter of the first grain layer, the strength of the remaining grain layer is lower than that of the first grain layer, and the overall strength of the pad structure of the multi-layer composite structure is lower than that of the single-layer grain layer. Therefore, compared with the multi-layer composite structure, the overall strength of the single-layer grain layer is higher, thereby reducing the probability of large depressions on the surface of the pad structure during the cleaning process. Therefore, the pad structure is preferably a single-layer grain layer.

[0081] In some embodiments, the composition material of the pad structure includes copper.

[0082] The composition material of the pad structure can include metal materials such as copper, tungsten, or aluminum, or alloy materials.

[0083] Here, the present embodiment is described with copper as the composition material of the pad structure. As the feature size of the devices in the integrated circuit chip continues to decrease, the current density in the metal continues to increase, and the required response time continues to decrease, tungsten or aluminum cannot meet the requirements. Compared with other metals such as tungsten or aluminum, the resistivity of copper is lower, which can reduce the resistance-capacitance (RC) delay of the pad structure, improve electromigration, and improve the performance of the device.

[0084] In some embodiments, the doping type of the first doped region includes P-type doping and N-type doping, and the doping type of the second doped region 120 includes P-type doping.

[0085] Here, the doping type of the first doped region can include P-type doping and N-type doping, which is used to form the source / drain region of the control circuit 210.

[0086] The second doped region 120 includes a P-type doped well or an N-type doped well. In the present embodiment, the second doped region 120 is described with a P-type doped well as an example. Here, the P-type doped well can be formed by P-type doping of the single crystal silicon substrate with a P-type substance such as boron or a boron complex (e.g., BF2).

[0087] According to some embodiments, a P-type doped well is formed in the substrate 110, which, in addition to providing support for the semiconductor structure, also serves as a grounded device, providing a zero potential for the semiconductor device on the substrate 110. By P-doping the substrate 110, the hole carrier concentration in the substrate 110 can be increased, improving the conductivity of the substrate 110.

[0088] In other embodiments, in the P-type doped well, the hole concentration is much greater than the free electron concentration, the holes are the majority carriers, and the free electrons are the minority carriers, and the P-type doped well mainly conducts electricity by holes. The P-type doped well can be subsequently connected to the ground terminal, so that the sealing ring 130 coupled to the P-type doped well can absorb the holes in the P-type doped well, thereby reducing the cross-over noise of the substrate 110.

[0089] In this embodiment, to solve the problem of surface depression of the sealing ring caused by the coupling of the sealing ring and the P-type doped well in the substrate, the improved pad structure is in the shape of a mouth or a back in the cross section parallel to the substrate 110; and / or, the average grain diameter of the material of the improved pad structure is less than or equal to a preset diameter threshold, which is 500 nm to 600 nm. For reference Figure 2a and Figure 2b The above similar analysis of the improved pad structure shows that even if the holes in the P-type second doped region 120 have a strong attraction to the electrons, the probability of defects such as large butterfly-shaped depressions on the surface of the pad structure will be reduced.

[0090] In some embodiments, the semiconductor structure further comprises:

[0091] The memory device is bonded to the control circuit 210.

[0092] Here, the memory device can include an array of memory cells, which can be an array of NAND memory cells provided in the form of an array of NAND memory strings extending in a vertical substrate plane direction on the substrate. Each NAND memory string includes a plurality of memory cells coupled in series and vertically stacked, each memory cell capable of holding a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the memory cell region. Each memory cell can be a floating gate type memory cell including a floating gate transistor, or can be a charge trapping type memory cell including a charge trapping transistor.

[0093] Specifically, a first wafer and a second wafer are provided, the first wafer can include a wafer formed with a memory device, and the second wafer can include a wafer formed with a control circuit. In the first wafer and the second wafer, an interlayer dielectric layer is first formed, then a pad opening (for example, a trench or a via hole) is formed in the interlayer dielectric layer, a barrier layer and a copper seed layer are formed in the pad opening, then a copper conductive layer is formed in the pad opening by an electrochemical plating process, after the surface of the copper conductive layer attached outside the pad opening is polished flat by chemical mechanical polishing, a pad structure is formed. Then the first wafer and the second wafer formed with the pad structure are cleaned, and then the pad structure of the first wafer and the pad structure of the second wafer can be bonded by bonding to form a bonding structure between the first wafer and the second wafer, so as to realize the bonding of the first wafer and the second wafer.

[0094] In this way, after the first wafer and the second wafer are bonded, the memory device can be controlled by the control circuit, so as to realize the storage function while reducing the chip area.

[0095] Here, the pad structure of the first wafer and the pad structure of the second wafer satisfy that the cross section of the pad structure along the direction parallel to the substrate is a mouth-shaped or a back-shaped; and / or, the average grain diameter of the pad structure composition material is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500nm to 600nm. The specific way of realizing the bonding of the first wafer and the second wafer includes but is not limited to wafer level Cu-Cu bonding.

[0096] In the embodiment, according to the above analysis that the pad structure in the semiconductor structure has the characteristics of large deposited conductive material volume and / or high-strength material, the probability of large dishing on the surface of the pad structure in the subsequent cleaning process is reduced. Therefore, when the memory device and the control circuit are bonded, since the pad structure reduces the probability of large dishing, the probability of defects such as voids in the bonding structure is reduced, thereby improving the reliability of the bonding interface, improving the chip performance, and ensuring the yield of the formed memory.

[0097] In some embodiments, the sealing ring 130 further includes:

[0098] An interconnection structure is located above the second doped region 120 and below the pad structure 131a / 131b in a direction perpendicular to the substrate 110, and the interconnection structure is coupled to the second doped region 120 and the pad structure 131a / 131b.

[0099] Exemplarily, the sealing ring 130 includes the interconnection structure and the pad structure 131a / 131b, the interconnection structure can include a plurality of metal layers, for example Figure 1aThe 5 metal layers shown in FIG. 1 are respectively denoted as a first metal layer to a fifth metal layer. The interconnection structure can further include a plurality of vias and contact plugs, for example Figure 1a The contact plug shown in FIG. 1 is coupled with the P-type doped well, the first metal layer is coupled with the contact plug, each metal layer between the first metal layer to the fifth metal layer is coupled through a via, and the fifth metal layer is coupled with the pad.

[0100] Here, Figure 1a For example, the number of metal layers and the number of vias and contact plugs in the interconnection structure can be set according to actual needs.

[0101] In this embodiment, a sealing ring surrounding the control circuit is designed, and the sealing ring includes the interconnection structure and the pad structure, which can reduce mechanical damage and moisture intrusion of the control circuit caused by the cutting process, shield external electromagnetic interference, and reduce damage to the device caused by electrostatic discharge.

[0102] In some embodiments, the semiconductor structure further includes: a virtual sealing ring; and wherein

[0103] The virtual sealing ring is coupled with the substrate 110, and the virtual sealing ring surrounds the sealing ring 130.

[0104] For example, in the semiconductor structure, the virtual sealing ring includes a continuous wall structure surrounding the sealing ring 130, and the virtual sealing ring has a certain distance from the sealing ring 130, both the virtual sealing ring and the sealing ring 130 can reduce mechanical damage and moisture intrusion of the control circuit 210 caused by the cutting process.

[0105] It should be emphasized that the surrounding of the virtual sealing ring to the sealing ring 130 in this embodiment refers to the surrounding of the side surface of the sealing ring 130, and does not involve covering the top surface of the sealing ring 130. The virtual sealing ring can not be in direct contact with the sealing ring 130.

[0106] In this embodiment, a virtual sealing ring surrounding the sealing ring is designed, and the sealing ring and the virtual sealing ring provide multiple protective walls in combination to provide more stringent protection for the control circuit, which can further reduce mechanical damage and moisture intrusion of the control circuit caused by the cutting process, shield external electromagnetic interference, and reduce damage to the device caused by electrostatic discharge. In addition, compared with the isolated sealing ring, the combination of the sealing ring and the virtual sealing ring can provide better support for the control circuit during the subsequent chemical mechanical polishing process of the control circuit.

[0107] Figure 5 A flowchart of another method for manufacturing a semiconductor structure according to an example is shown in FIG. 2. Referring to FIG. 2, Figure 5 The manufacturing method includes:

[0108] S10: providing a substrate;

[0109] S20: forming a first doped region and a second doped region in the substrate;

[0110] S30: forming a control circuit comprising a source / drain region and a gate structure, wherein the source / drain region is located in the first doped region, and the gate structure is located on the substrate;

[0111] S40: forming a sealing ring comprising a pad structure on the substrate, wherein the sealing ring is coupled with the second doped region, the sealing ring surrounds the control circuit, and the pad structure is located at an end of the sealing ring away from the substrate;

[0112] The pad structure is in a mouth-shaped or a back-shaped cross section along a direction parallel to the substrate; and / or, an average grain diameter of a material constituting the pad structure is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm.

[0113] Exemplarily, providing the substrate can comprise providing a wafer on which a metal-oxide-semiconductor (MOS) or other control circuit is formed. Providing the substrate can also comprise providing a wafer on which a memory device is formed.

[0114] Compared with a substrate without doping (intrinsic semiconductor) in which the number of carriers is small and the conductivity is low, the number of free electrons or holes in the substrate is increased by forming the second doped region in the substrate, so that the conductivity of the substrate is greatly enhanced, and the conductivity of the substrate can be enhanced with the increase of the doping concentration in the second doped region. The way of forming the second doped region in the substrate includes but is not limited to diffusion and ion implantation.

[0115] Exemplarily, the second doped region is a P-type doped well. The process of forming the P-type doped well can include: performing photolithography on the substrate to form an implantation window, and implanting P-type ions into the substrate through the implantation window to form the P-type doped well. The P-type ions include but are not limited to one or more of boron ions, gallium ions or indium ions.

[0116] Here, the process of forming the control circuit can include forming a plurality of transistors and a logic control circuit composed of the transistors. The control circuit can include an analog circuit, a digital circuit, a high-voltage device or other semiconductor devices. The way of forming the control circuit includes but is not limited to CMOS fabrication process. Specifically, the control circuit comprising the source / drain region and the gate structure is formed, wherein the source / drain region is located in the first doped region of the substrate (not shown), and the gate structure can include a gate dielectric layer and a gate electrode, which can be stacked on the surface of the substrate (not shown).

[0117] The control circuit can include various types of control circuits formed using metal-oxide-semiconductor (MOS) technology. For example, the control circuit can include a voltage generation circuit, a plurality of drive circuits, a drive line, and a sensing line. It should be understood that the control circuit can also include a page buffer / sense amplifier, a column decoder / bit line driver, a row decoder, a control logic unit, a register, an interface, a data bus, and the like.

[0118] In the semiconductor structure, a sealing ring is formed around the control circuit, and there is a certain distance between the sealing ring and the control circuit to effectively protect the control circuit, reduce the cutting damage of the control circuit in the cutting process, and reduce the invasion of moisture.

[0119] The present disclosure finds that one of the reasons for the large concave of the pad in the sealing ring via is that the sealing ring is coupled with the P-type doped well in the substrate, a sealing ring via coupled with the sealing ring is formed at one end of the sealing ring away from the substrate, and in the process of forming the pad in the sealing ring via, the holes in the P-type doped well have a strong attraction to the electrons, which causes the pad in the sealing ring via to lose electrons and be oxidized to ions in the planarization or cleaning process, and further causes the conductive material to leave the surface of the pad, resulting in a large butterfly-shaped concave defect on the surface of the pad in the sealing ring via.

[0120] Therefore, in view of the problem of the concave of the pad in the sealing ring via caused by the coupling of the sealing ring with the P-type doped well in the substrate, the cross section of the pad structure along the direction parallel to the substrate is improved to be a mouth-shaped or a back-shaped; and / or the average grain diameter of the material constituting the pad structure is less than or equal to a preset diameter threshold, which is 500-600 nm. The improved pad structure has the characteristics of high-strength material and / or large volume of deposited conductive material, so that even if the holes in the P-type doped well have a strong attraction to the electrons, the surface of the pad structure will not have a large butterfly-shaped concave defect.

[0121] Here, the material constituting the pad structure can include copper, tungsten, or aluminum, etc. The present embodiment is described with the material constituting the pad structure being copper.

[0122] The specific analysis of the improved pad structure having the characteristics of large volume of deposited conductive material and / or high-strength material is as follows:

[0123] Specifically, forming the sealing ring including the pad structure on the substrate can include: forming the pad structure with the material being copper through an electrochemical plating (ECP) process. Generally, the electrochemical copper plating process can first deposit an insulating layer with a certain thickness, then perform corresponding photolithography and etching processes to form a complete via, then use physical vapor deposition to perform sputtering of a diffusion barrier layer and a copper seed layer, then electroplate copper, and finally perform annealing and chemical mechanical polishing to planarize and clean the copper plating layer.

[0124] The electrochemical copper plating process is followed by an annealing process (ECP Anneal) of the copper electroplating layer. It is noted that during the annealing process, the annealing process will cause the grain boundaries of the copper electroplating layer to start unstable migration, leading to grain growth, i.e. the grains in the copper electroplating layer will slowly grow, swallow each other, and undergo secondary recrystallization, eventually growing into larger grains, causing changes in material properties (e.g. reduced strength and material softening).

[0125] In this embodiment, after the pad structure composed of copper is formed by the electrochemical plating process, the annealing process of the copper electroplating layer is cancelled, reducing the probability of further grain growth, thereby reducing or eliminating larger grains in the copper electroplating layer, so that the grain diameter in the copper electroplating layer is smaller. Since the material composed of small grains has higher material strength and toughness, this embodiment improves the strength of the copper electroplating layer, thereby reducing the probability of large butterfly-shaped depressions in the copper electroplating layer during the cleaning process, reducing the probability of defects such as voids in the bonding structure, further improving the reliability of the bonding interface, improving the performance of the chip, and ensuring the yield of the formed memory. Moreover, in this embodiment, the annealing process of the copper electroplating layer is cancelled, reducing the complexity of the process and increasing the feasibility of the operation.

[0126] Specifically, forming a seal ring including a pad structure on a substrate can include: forming a dielectric layer on the substrate, and forming a trench on the dielectric layer; and filling the trench with copper to form the pad structure, wherein the pad structure is in a mouth-shaped or a back-shaped cross section along a direction parallel to the substrate.

[0127] Generally, the pad structure is circular in cross section along a direction parallel to the substrate, i.e. the pad structure in the seal ring is in a via type. In this embodiment, the cross section of the pad structure along the direction parallel to the substrate is changed from circular to mouth-shaped or back-shaped, i.e. the pad structure in the seal ring is in a trench type, i.e. the pad structure is filled in a trench extending along the direction parallel to the substrate to the X-axis direction (see Figure 3b ). It can be understood that in other embodiments, the pad structure can also be filled in a trench extending along the direction parallel to the substrate 110 to the Y-axis direction (not shown). In the case of the same volume of the seal ring, the volume of the conductive material that can be deposited in the pad structure of the trench type is greater than the volume of the conductive material that can be deposited in the pad structure of the via type. Therefore, the semiconductor structure formed by the manufacturing method proposed in this embodiment significantly increases the volume of the conductive material deposited in the pad structure in the seal ring, which can reduce the probability of large depressions in the pad structure during the cleaning process.

[0128] Specifically, forming the sealing ring including the pad structure on the substrate can include: forming the pad structure with a composition material of copper by adjusting a current and an additive of an electrochemical plating (ECP) process, wherein an average grain diameter of the pad structure composition material is less than or equal to a preset diameter threshold value, and the preset diameter threshold value is 500 nm to 600 nm. Therefore, the grain diameter in the pad structure is small.

[0129] The average grain diameter of the copper electroplating layer formed is adjusted by adjusting the current and the additive of the electrochemical plating process, so that the average grain diameter of the copper electroplating layer formed is less than or equal to a preset diameter threshold value, and the preset diameter threshold value is 500 nm to 600 nm. For example, the electroplating current range of the electrochemical plating (ECP) process is set to 1 ampere to 5 ampere, or the concentration range of the additive (such as the inhibitor and the accelerator) in the electrochemical plating process is set, so that the electroplating current meets 1 ampere to 5 ampere under the additive concentration range. Here, the concentration of the inhibitor additive includes but is not limited to about 30 ppm to about 300 ppm, and the concentration of the accelerator additive includes but is not limited to about 5 ppm to about 40 ppm, ppm is parts per million, which is equivalent to mg / L.

[0130] Since the material with small grains has high material strength, the embodiment improves the strength of the pad structure, thereby reducing the probability of large butterfly-shaped recesses in the pad structure during the cleaning process, and thereby reducing the probability of defects such as voids in the bonding structure.

[0131] The embodiment preferably forms a pad structure of a trench type, and cancels the annealing process after forming the copper electroplating layer by performing the electrochemical plating process, so that the pad structure in the formed semiconductor structure is in a mouth-shaped or back-shaped cross section parallel to the substrate direction, and the average grain diameter of the pad structure composition material is less than or equal to a preset diameter threshold value, and the preset diameter threshold value is 500 nm to 600 nm. According to the above analysis, the grain diameter in the pad structure is small in the preferred mode, has high material strength, and the volume of the pad structure deposited with conductive material is increased, so that the probability of large butterfly-shaped recesses in the pad structure during the cleaning process is reduced, and the probability of defects such as voids in the bonding structure is reduced.

[0132] In some embodiments, the sealing ring includes an interconnection structure and a pad structure; forming the sealing ring including the pad structure on the substrate includes:

[0133] forming the interconnection structure on the substrate; wherein the interconnection structure is coupled with the second doped region;

[0134] forming a dielectric layer covering the interconnection structure, and forming a trench on the dielectric layer;

[0135] The trench is filled with a conductive material to form a pad structure, wherein the pad structure has a cross-section in parallel to the substrate direction in a shape of a mouth or a back.

[0136] Here, an interconnect layer covering the substrate is formed, including but not limited to forming an interconnect structure in the interconnect layer by a wet etching method, wherein the interconnect structure is coupled with the second doped region. The etching process can also be divided into multiple steps in this process.

[0137] A dielectric layer covering the interconnect structure is formed, including but not limited to a silicide layer, such as silicon oxide. The silicon oxide can be formed by reacting Tetraethylorthosilicate (TEOS) with ozone (O3) by a chemical vapor deposition method.

[0138] Exemplarily, the dielectric layer can be reacted with a liquid etchant or a gas etchant by a wet etching method, and the product is discharged to form a trench in the dielectric layer. For example, when the dielectric layer is a silicon oxide layer, the silicon oxide layer can be etched by a hydrofluoric acid (HF) solution to form the trench, wherein the trench has a cross-section in parallel to the substrate direction in a shape of a mouth or a back.

[0139] The trench is filled with a conductive material, wherein the conductive material can include a metal material or an alloy material, such as copper, tungsten or aluminum. Here, the conductive material of the pad structure in the embodiment is copper.

[0140] Specifically, the method of filling the trench with the conductive material includes but is not limited to a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD) or an atomic layer deposition method (ALD).

[0141] In the embodiment, the pad structure formed by the above manufacturing method has a cross-section in parallel to the substrate direction in a shape of a mouth or a back. Generally, the pad structure has a cross-section in parallel to the substrate direction in a shape of a circle, i.e. the pad structure in the sealing ring is in a via type. In the embodiment, the cross-section of the pad structure in parallel to the substrate direction is changed from a circle to a shape of a mouth or a back, i.e. the pad structure in the sealing ring is in a trench type, i.e. the pad structure is filled in a trench extending in the X-axis direction in parallel to the substrate direction. It can be understood that in other embodiments, the pad structure can also be filled in a trench extending in the Y-axis direction in parallel to the substrate 110 (not shown). In the case of the same sealing ring volume, the volume of the conductive material that can be deposited in the pad structure in the trench type is greater than the volume of the conductive material that can be deposited in the pad structure in the via type. Therefore, the semiconductor structure formed by the manufacturing method proposed in the embodiment significantly increases the volume of the conductive material deposited in the pad structure in the sealing ring, and reduces the probability of a large depression of the pad structure in the cleaning process.

[0142] In some embodiments, the sealing ring includes an interconnection structure and a pad structure; forming the sealing ring including the pad structure on the substrate, including:

[0143] forming the interconnection structure on the substrate; wherein the interconnection structure is coupled with the second doped region;

[0144] forming a dielectric layer covering the interconnection structure;

[0145] forming an opening through the dielectric layer; wherein the opening exposes the interconnection structure;

[0146] forming the pad structure filling the opening by physical vapor deposition.

[0147] Here, the opening can be a via or a trench, and the present embodiment is described with the opening as a via. The forming method of the interconnection structure and the dielectric layer can refer to the above related analysis.

[0148] For example, a plurality of openings are formed in the dielectric layer by etching, and the etching method includes but is not limited to dry etching.

[0149] The trench is filled with a conductive material, which can include a metal material such as copper, tungsten, or aluminum, or an alloy material. Here, the present embodiment is described with the conductive material of the pad structure as copper.

[0150] A barrier layer is sputtered on the bottom and sidewall of the opening by physical vapor deposition (PVD), such as a laminated barrier layer composed of tantalum nitride (TaN) and tantalum (Ta). On the surface of the barrier layer, a copper seed layer with a small thickness can be formed by physical vapor deposition, and then based on the copper seed layer, a copper electroplating layer is formed by an electrochemical plating process to fill the opening.

[0151] Specifically, the average grain diameter of the copper electroplating layer formed is adjusted by adjusting the current and additives of the electrochemical plating process, so that the average grain diameter of the copper electroplating layer formed is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500nm to 600nm. For example, the electroplating current of the electrochemical plating process can be set to 1 ampere to 5 ampere, or the concentration range of the additives (such as inhibitors and accelerators) in the electrochemical plating process is adjusted, so that the electroplating current meets 1 ampere to 5 ampere under the additive concentration range.

[0152] In the embodiment, the grain diameter in the pad structure obtained by the physical vapor deposition (PVD) is small, that is, the average grain diameter of the material forming the pad structure is less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm. Since the material with small grains has high material strength, the embodiment improves the strength of the copper electroplated layer, thereby reducing the probability of large butterfly-shaped recesses in the copper electroplated layer during cleaning, reducing the probability of defects such as cavities in the bonding structure, further improving the reliability of the bonding interface, improving the performance of the chip, and ensuring the yield of the formed memory. Moreover, the annealing process of the copper electroplated layer is cancelled in the embodiment, which reduces the complexity of the process and increases the feasibility of the operation.

[0153] In some embodiments, the sealing ring includes an interconnection structure and a pad structure; the sealing ring including the pad structure is formed on the substrate, including:

[0154] The interconnection structure is formed on the substrate; wherein the interconnection structure is coupled with the second doped region;

[0155] A dielectric layer covering the interconnection structure is formed;

[0156] An opening penetrating the dielectric layer is formed; wherein the opening exposes the interconnection structure;

[0157] A seed layer covering the sidewall and the bottom of the opening is formed;

[0158] An electrochemical plating process is performed to form an electroplated layer on the seed layer to fill the opening, forming the pad structure.

[0159] Here, the opening can be a via or a trench, and the embodiment is described with the opening as a via. The formation of the interconnection structure, the dielectric layer, and the opening can refer to the related analysis described above.

[0160] In the traditional electrochemical plating process, annealing treatment (ECP Anneal) is performed on the copper electroplated layer. During the annealing treatment, the annealing treatment causes the grain boundaries of the copper electroplated layer to start unstable migration, resulting in grain growth, that is, the grains in the copper electroplated layer slowly grow, merge with each other, and undergo secondary recrystallization, eventually growing into larger grains, causing changes in material properties (such as reduced strength and softened material).

[0161] Here, the annealing treatment of the copper electroplated layer is cancelled after the electrochemical plating process is performed to form the copper electroplated layer, reducing the probability of further grain growth. The average grain diameter of the material forming the pad structure is less than the preset diameter threshold, and the preset diameter threshold can be 500 nm to 600 nm. For example, the average grain diameter of the material forming the pad structure can be 10 nm to 500 nm.

[0162] In the embodiment, after the electrochemical plating process is performed to form the copper plating layer, annealing treatment is not performed on the copper plating layer, so that the large grains in the copper plating layer are reduced or eliminated, and the grain diameter in the copper plating layer is small. Since the material composed of small grains has high material strength and toughness, the embodiment improves the strength of the copper plating layer, thereby reducing the probability of large butterfly-shaped recesses in the copper plating layer in the cleaning process, reducing the probability of defects such as cavities in the bonding structure, further improving the reliability of the bonding interface, improving the performance of the chip, and ensuring the yield of the formed memory. Moreover, in the embodiment, annealing treatment is not performed on the copper plating layer, which reduces the complexity of the process and increases the feasibility of the operation.

[0163] In some embodiments, performing the electrochemical plating process includes:

[0164] Monitoring the plating current in the electrochemical plating process to obtain a monitoring result;

[0165] When the monitoring result indicates that the plating current does not meet the preset condition, adjusting the plating current or adjusting the components of the plating solution in the electrochemical plating process to make the plating current meet the preset condition.

[0166] Illustratively, performing the electrochemical plating process includes: transferring the semiconductor substrate after forming the seed layer covering the sidewalls and the bottom of the opening into a plating device, the plating device having a plating solution and a power supply positive and negative electrode, and the semiconductor substrate is fixed to the negative electrode. In addition to inorganic components in the form of copper salt, the plating solution contains organic additives such as various organic additives such as leveler, accelerator and suppressor to achieve the desired deposition performance.

[0167] Here, the concentration of the suppressor additive includes but is not limited to about 30 ppm to about 300 ppm, and the concentration of the accelerator additive includes but is not limited to about 5 ppm to about 40 ppm, ppm is parts per million, which is equivalent to mg / L.

[0168] The semiconductor substrate is immersed in a plating solution containing copper ions. The semiconductor substrate can be plated in the plating device at a plating current of 1 ampere to 5 amperes, and the copper ions are reduced on the surface of the seed layer to form an electrodeposited copper plating layer. The electrochemical plating process will continue until the opening is filled with copper. Then the copper plating layer formed in the opening is subjected to chemical mechanical polishing to form a pad structure.

[0169] It is appreciated that the organic additives react with the anode during the electrochemical plating process. The reaction decomposes the organic additives, which makes the organic additives in the plating solution at least partially ineffective. Thus, due to the consumption of the organic additives in the electrochemical plating process, the concentration of the organic additives in the plating solution is gradually reduced. Therefore, generally the concentration of the organic additives in the plating solution is gradually reduced over time, and the plating current flowing between the anode and the semiconductor substrate is gradually reduced over time.

[0170] In the embodiment, the plating current in the electrochemical plating process is monitored during the electrochemical plating process to obtain a monitoring result. When the monitoring result indicates that the plating current does not satisfy a preset condition, for example, the monitoring result indicates that the current plating current is less than 1 ampere to 5 amperes, the plating current is increased by the electrochemical plating device, or the concentration of the organic additives (e.g., inhibitors and accelerators) in the electrochemical plating process is increased to increase the plating current flowing between the anode and the semiconductor substrate, so that the plating current satisfies the range of 1 ampere to 5 amperes.

[0171] In the embodiment, the plating current in the electrochemical plating process is monitored during the electrochemical plating process to obtain a monitoring result. When the monitoring result indicates that the plating current does not satisfy a preset condition, for example, the monitoring result indicates that the current plating current is less than 1 ampere to 5 amperes, the plating current is increased by the electrochemical plating device, or the concentration of the organic additives (e.g., inhibitors and accelerators) in the electrochemical plating process is increased to increase the plating current flowing between the anode and the semiconductor substrate, so that the plating current satisfies the range of 1 ampere to 5 amperes.

[0172] In some embodiments, forming a first doped region and a second doped region in a substrate includes:

[0173] forming a recess in the substrate;

[0174] filling the recess with a semiconductor material;

[0175] performing P-type doping and N-type doping on the semiconductor material in the recess to form the first doped region;

[0176] performing P-type doping on the semiconductor material in the recess to form the second doped region.

[0177] For example, the recess is formed by etching in the substrate, and the etching includes but is not limited to dry etching.

[0178] Exemplary semiconductor materials include, but are not limited to, elemental semiconductor materials (e.g., silicon, germanium), Group III-V compound semiconductor materials, Group II- VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

[0179] Here, the semiconductor material in the recess is N-type doped with an N-type dopant, and the semiconductor material in the recess is P-type doped with a P-type dopant to form a first doped region for forming source / drain regions of the control circuit. Specifically, the N-type dopant can include phosphorus.

[0180] Here, the semiconductor material in the recess is P-type doped with a P-type dopant, such as boron or a boron complex (e.g., BF2), to form a P-type second doped region. Exemplary doping methods include, but are not limited to, diffusion and ion implantation.

[0181] In this embodiment, the P-type second doped region is formed in the substrate, which provides support for the semiconductor structure and also serves as a device for grounding, providing a zero potential for the semiconductor device on the substrate. By P-type doping the substrate, the hole carrier concentration in the substrate can be increased, improving the conductivity of the substrate.

[0182] In other embodiments, in the P-type second doped region, the hole concentration is much greater than the free electron concentration, the holes are the majority carriers, and the free electrons are the minority carriers, and the P-type second doped region mainly conducts electricity by holes. The P-type second doped region can be subsequently connected to a ground terminal, so that the seal ring coupled to the P-type second doped region can absorb the holes in the P-type second doped region, thereby reducing the substrate's cross-talk noise.

[0183] In some embodiments, the fabrication method further includes:

[0184] forming a memory device;

[0185] bonding the memory device to the control circuit.

[0186] Here, the memory device can include a memory cell array, and the memory cell array can be formed by: forming an insulating stack structure on a front surface of another substrate, the insulating stack structure including a plurality of layers of sacrificial layers stacked and insulating layers separating the plurality of layers of sacrificial layers from each other; forming a plurality of channel pillars extending through the insulating stack structure; forming a gate line gap extending from a surface of the insulating stack structure to a vicinity of a source contact surface in the substrate; replacing the plurality of layers of sacrificial layers with a plurality of gate conductors via the gate line gap to form a gate stack structure; and filling the gate line gap with an insulating material; wherein the plurality of channel pillars and the plurality of layers of gate conductors form memory transistors and select transistors.

[0187] In some embodiments, the manner of bonding the memory device and the control circuit includes, but is not limited to, wafer-level copper-copper bonding, which is a key technology in the preparation process of three-dimensional memory, can form an electrical connection between different wafers by bonding the copper films on the bonding surfaces of different wafers, and realize the bonding of different wafers.

[0188] Specifically, a first wafer and a second wafer are provided, the first wafer can include a wafer formed with a memory device, and the second wafer can include a wafer formed with a control circuit. In the first wafer and the second wafer, an interlayer dielectric layer is first formed, then a pad opening (for example, a trench or a via hole) is formed in the interlayer dielectric layer, a barrier layer and a copper seed layer are formed in the pad opening, then a copper conductive layer is formed in the pad opening by an electrochemical plating process, and after the surface of the copper conductive layer attached outside the pad opening is polished flat by chemical mechanical polishing, a pad structure is formed. Then the first wafer and the second wafer formed with the pad structure are cleaned, and then the pad structure of the first wafer and the pad structure of the second wafer can be bonded by bonding to form a bonding structure between the first wafer and the second wafer, realizing the bonding of the first wafer and the second wafer.

[0189] In this way, after the first wafer and the second wafer are bonded, the memory device can be controlled by the control circuit, realizing the storage function while reducing the chip area. Here, wafer-level copper-copper bonding can be performed on the pad structure on the control circuit and the pad structure of the memory device to form a bonding structure between the memory device and the control circuit. Since the pad structure formed by the above-mentioned manufacturing method has the characteristics of high-strength material and / or large volume of deposited conductive material, the probability of large butterfly-shaped recesses on the surface of the pad structure during subsequent cleaning process is reduced. Therefore, when bonding the memory device and the control circuit, the probability of defects such as voids in the bonding structure is reduced, thereby improving the reliability of the bonding interface, improving the performance of the chip, and ensuring the yield of the formed memory.

[0190] It should be noted that the order of forming the control circuit and forming the memory device in the present embodiment is not limited, and the two steps can be performed simultaneously.

[0191] The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

[0192] The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0193] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; wherein the substrate comprises a first doped region and a second doped region; a control circuit comprising a source / drain region and a gate structure; wherein the source / drain region is located in the first doped region, and the gate structure is located on the substrate; a sealing ring coupled with the second doped region, the sealing ring surrounding the control circuit; the sealing ring comprises a pad structure located at an end of the sealing ring opposite to the substrate; wherein the pad structure is composed of a material with an average grain diameter less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm.

2. The semiconductor structure of claim 1, wherein, The pad structure is in a cross-sectional shape of a mouth or a back along a direction parallel to the substrate.

3. The semiconductor structure of claim 1, wherein: the pad structure is a single-layer grain layer or a multi-layer composite structure; wherein the multi-layer composite structure comprises at least a multi-layer structure composed of a first grain layer and a second grain layer, the first grain layer is located at an end of the sealing ring opposite to the substrate, the second grain layer is located at an end of the sealing ring close to the substrate, and the average grain diameter of the first grain layer is smaller than that of the second grain layer.

4. The semiconductor structure of claim 1, wherein, The pad structure is composed of: copper.

5. The semiconductor structure of claim 1, wherein, The doping type of the first doped region comprises P-type doping and N-type doping, and the doping type of the second doped region comprises P-type doping.

6. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a memory device bonded with the control circuit.

7. The semiconductor structure of claim 1, wherein, The sealing ring further comprises: an interconnection structure located between the second doped region and the pad structure in a direction perpendicular to the substrate, the interconnection structure coupling the second doped region and the pad structure.

8. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a virtual sealing ring; wherein: the virtual sealing ring is coupled with the substrate, and the virtual sealing ring surrounds the sealing ring.

9. A method of fabricating a semiconductor structure, the method comprising: The method comprises: providing a substrate; forming a first doped region and a second doped region in the substrate; forming a control circuit comprising a source / drain region and a gate structure; wherein the source / drain region is located in the first doped region, and the gate structure is located on the substrate; forming a sealing ring comprising a pad structure on the substrate; wherein the sealing ring is coupled with the second doped region, the sealing ring surrounds the control circuit, and the pad structure is located at an end of the sealing ring opposite to the substrate; the pad structure is composed of a material with an average grain diameter less than or equal to a preset diameter threshold, and the preset diameter threshold is 500 nm to 600 nm.

10. The method of manufacturing according to claim 9, wherein, The sealing ring comprises an interconnection structure and a pad structure; the forming of the sealing ring comprising a pad structure on the substrate comprises: forming an interconnection structure on the substrate; wherein the interconnection structure is coupled with the second doped region; forming a dielectric layer covering the interconnection structure, and forming a trench on the dielectric layer; filling the trench with a conductive material to form the pad structure, wherein the pad structure is in a cross-sectional shape of a mouth or a back along a direction parallel to the substrate.

11. The method of manufacturing according to claim 9, wherein, The sealing ring comprises an interconnection structure and a pad structure; the forming of the sealing ring comprising the pad structure on the substrate comprises: forming an interconnection structure on the substrate; wherein the interconnection structure is coupled with the second doped region; forming a dielectric layer covering the interconnection structure; forming an opening penetrating through the dielectric layer; wherein the opening exposes the interconnection structure; forming the pad structure filling the opening by physical vapor deposition.

12. The method of manufacturing of claim 9, wherein, The sealing ring comprises an interconnection structure and a pad structure; the forming of the sealing ring comprising the pad structure on the substrate comprises: forming an interconnection structure on the substrate; wherein the interconnection structure is coupled with the second doped region; forming a dielectric layer covering the interconnection structure; forming an opening penetrating through the dielectric layer; wherein the opening exposes the interconnection structure; forming a seed layer covering the sidewall and bottom of the opening; performing an electrochemical plating process to form an electroplated layer on the seed layer to fill the opening, thereby forming the pad structure.

13. The method of manufacturing according to claim 12, wherein, The performing of the electrochemical plating process comprises: monitoring the plating current in the electrochemical plating process to obtain a monitoring result; when the monitoring result indicates that the plating current does not satisfy a preset condition, adjusting the plating current or adjusting the composition of the electroplating solution in the electrochemical plating process so that the plating current satisfies the preset condition.

14. The method of manufacturing of claim 9, wherein, The forming of the first doped region and the second doped region in the substrate comprises: forming a recess in the substrate; filling the recess with a semiconductor material; performing P-type doping and N-type doping on the semiconductor material in the recess to form the first doped region; performing P-type doping on the semiconductor material in the recess to form the second doped region.

15. The method of manufacturing of claim 9, wherein, The method further comprises: forming a memory device; bonding the memory device with the control circuit.

Images