Array substrate, display panel, display device and method for preparing array substrate

Abstract

The present application discloses an array substrate, a display panel, a display device and a method for preparing an array substrate. An embodiment of the present application provides an array substrate, the array substrate includes an electrostatic release component, a first lead and a second lead. The electrostatic release component includes a plurality of electrostatic release blocks arranged at intervals, and a plurality of electrostatic release blocks are provided to realize electrostatic protection of the array substrate. The first lead connects the electrostatic release block with the second lead, so that the electrostatic release block is connected to the second lead through the first lead. The impedance of the second lead is less than the impedance of the first lead, increasing the resistance of the overall circuit. The first lead with a larger impedance is used to connect the electrostatic release block and the second lead to reduce the current in the circuit and avoid the display panel turning green due to excessive current.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate, a display panel, a display device and a method for preparing the array substrate. Background Art

[0002] With the rapid development of display technology, in order to meet people's high requirements for the display function of display panels, the quality of display panels is getting higher and higher.

[0003] To ensure the quality of the display panel, a series of reliability tests are carried out on the display panel in the process, including the dependence test of the display panel. For example, in the 8585 test, the display panel works continuously for 240 hours at 85 degrees Celsius and 85% relative humidity. Currently, after the 8585 test, the overloaded screen of the display panel will turn green. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display panel, a display device and a method for manufacturing the array substrate, aiming to solve the problem that the display panel turns green due to excessive current.

[0005] The first aspect of the present application provides an array substrate, characterized in that it includes: an electrostatic release component, including a plurality of electrostatic release blocks arranged at intervals; a first lead, one end of the first lead segment is connected to at least one electrostatic release block; a second lead is connected to an end of the first lead away from the electrostatic release block, and the impedance of the second lead is less than the impedance of the first lead.

[0006] An embodiment of a second aspect of the present application provides a display panel, which includes an array substrate according to any of the above embodiments.

[0007] An embodiment of a third aspect of the present application provides a method for preparing an array substrate, comprising:

[0008] preparing an electrostatic release assembly, the electrostatic release assembly comprising a plurality of electrostatic release blocks arranged at intervals;

[0009] A conductor material layer is prepared and patterned to obtain a first lead, wherein one end of the first lead segment is connected to at least one electrostatic release block;

[0010] A metal material layer is prepared on one side of the conductor material layer and patterned to obtain a second lead, which is connected to an end of the first lead away from the electrostatic release block, and has an impedance smaller than that of the first lead.

[0011] According to the array substrate of the embodiment of the present application, the array substrate includes an electrostatic release component, a first lead and a second lead. The electrostatic release component includes a plurality of electrostatic release blocks arranged at intervals, and a plurality of electrostatic release blocks are provided to realize electrostatic protection of the array substrate. The first lead connects the electrostatic release block with the second lead, so that the electrostatic release block is connected to the second lead through the first lead. The impedance of the first lead is greater than the impedance of the second lead, thereby increasing the resistance of the overall circuit. The first lead with a larger impedance is used to connect the electrostatic release block and the second lead to reduce the current in the circuit and avoid the display panel turning green due to excessive current. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0013] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the first aspect of the present application;

[0014] Figure 2 yes Figure 1 Schematic diagram of the local enlarged structure at the middle Q;

[0015] Figure 3 is a schematic diagram of a partially enlarged structure at Q in another embodiment;

[0016] Figure 4 is a schematic diagram of a partially enlarged structure at Q in another embodiment;

[0017] Figure 5 is a schematic diagram of a partially enlarged structure at Q in yet another embodiment;

[0018] Figure 6 is a schematic diagram of a partially enlarged structure at Q in yet another embodiment;

[0019] Figure 7 yes Figure 1 Partial cross-sectional view at Q in the middle;

[0020] Figure 8 It is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the fourth aspect of the present application.

[0021] Description of reference numerals:

[0022] 10. display panel; 11. array substrate;

[0023] 100, electrostatic release component; 102, first electrostatic release block; 101, second electrostatic release block;

[0024] 110, first lead; 120, second lead; 121, first segment; 122, second segment; 130, third lead; 140, fourth lead;

[0025] 200, connection point; 210, straight line

[0026] 300, gate metal layer; 400, source and drain metal layer;

[0027] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0028] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0030] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0031] For electronic devices such as mobile phones and tablet computers, it is necessary to perform a dependency test on the display panel 10 before the product leaves the factory. In some related technologies, the display panel 10 is subjected to an 8585 test. The so-called 8585 test is that the screen works continuously for 240 hours at 85 degrees Celsius and 85% relative humidity. After the display panel 10 is subjected to the 8585 test, the display panel 10 will turn green under heavy load.

[0032] To solve the above problems, an embodiment of the present application provides an array substrate 11, a display panel 10, a display device and a method for preparing the array substrate 11. The following will describe various embodiments of the array substrate 11, the display panel 10, the display device and the method for preparing the array substrate 11 in conjunction with the accompanying drawings.

[0033] Please also read Figure 1 and Figure 2 , Figure 1 is a structural schematic diagram of a display panel 10 provided in an embodiment of the first aspect of the present application; Figure 2 yes Figure 1 Schematic diagram of the local enlarged structure at the middle Q.

[0034] In some optional embodiments, the display panel 10 has a display area and a non-display area, and the present application is described with respect to the Q area in the non-display area. In some embodiments, the Q area is a special-shaped area or a C-angle area in the non-display area.

[0035] The array substrate 11 provided by the embodiment of the first aspect of the present application includes an electrostatic discharge component 100, a first lead 110 and a second lead 120. The electrostatic discharge component 100 includes a plurality of electrostatic discharge blocks arranged at intervals. One end of the first lead 110 is connected to at least one electrostatic discharge block, and the second lead 120 is connected to an end of the first lead 110 away from the electrostatic discharge block. The impedance of the second lead 120 is less than the impedance of the first lead 110.

[0036] According to the array substrate 11 of the embodiment of the present application, the array substrate 11 includes an electrostatic discharge component 100, a first lead 110 and a second lead 120. The electrostatic discharge component 100 includes a plurality of electrostatic discharge blocks arranged at intervals, and a plurality of electrostatic discharge blocks are arranged to realize electrostatic protection of the array substrate 11. The first lead 110 connects the electrostatic discharge block with the second lead 120, so that the electrostatic discharge block is connected with the second lead 120 through the first lead 110. The impedance of the first lead 110 is greater than the impedance of the second lead 120, which increases the resistance of the overall circuit. The first lead 110 with a larger impedance is used to connect the electrostatic discharge block and the second lead 120 to reduce the current in the circuit and avoid the display panel 10 turning green due to excessive current.

[0037] See also Figure 3 , Figure 3It is a schematic diagram of the local enlarged structure at Q in another embodiment.

[0038] In some optional embodiments, the array substrate 11 also includes a third lead 130 and a fourth lead 140, and the multiple electrostatic release blocks include a first electrostatic release block 102 and a second electrostatic release block 101, the first electrostatic release block 102 is connected to the second lead 120 through the first lead 110, and the second lead 120 and the third lead 130 are connected by vias; the second electrostatic release block 101 is connected to the fourth lead 140, and the fourth lead 140 and the third lead 130 are arranged in different layers.

[0039] In these optional embodiments, the third lead 130 is connected to the second lead 120 via a hole, and the second lead 120 conducts the first lead 110 and the third lead 130, so that the current flows from the second lead 120 to the third lead 130. The first lead 110 connects the first electrostatic release block 102 and the second lead 120. Since the impedance of the first lead 110 is greater than that of the second lead 120, the current flowing through the first lead 110 will be reduced, so that the current in the entire circuit is reduced, and the display panel 10 is prevented from turning green due to excessive current. The second electrostatic release block 101 is connected to the fourth lead 140, and the second electrostatic release block 101 is turned on to realize its electrostatic protection function. The fourth lead 140 and the third lead 130 are arranged in different layers. The fourth lead 140 and the third lead 130 are located in different layers, and the wiring space of both is large, which is conducive to the convenience of wiring the fourth lead 140.

[0040] In some optional embodiments, the second lead 120 and the fourth lead 140 are provided in the same layer and made of the same material.

[0041] In these optional embodiments, the second lead 120 and the fourth lead 140 are arranged in the same layer, and the second lead 120 and the fourth lead 140 can be prepared at the same time to simplify the preparation process. The second lead 120 and the fourth lead 140 are made of the same material and can be prepared together with the same material to further simplify the preparation process.

[0042] Please continue reading Figure 3 In some optional embodiments, the third lead 130 is located on one side of the electrostatic release component 100 in the first direction X, and the first electrostatic release block 102 is located on one side of the second electrostatic release block 101 facing the third lead 130.

[0043] In these optional embodiments, the third lead 130 is located on one side of the electrostatic release block in the first direction X. Since the electrostatic release blocks are arranged at intervals in the second direction Y, there is a large space on one side of the electrostatic release block in the first direction X, which is convenient for wiring the third lead 130. The first electrostatic release block 102 is located on the side of the second electrostatic release block 101 facing the third lead 130, so that the first electrostatic release block 102102 is directly connected to the first lead 110, reducing the distance between the first electrostatic release block 102102 and the first lead 110, which not only reduces the complexity of the design and reduces the design cost, but also ensures that the first lead 110 has a large resistance to reduce the current in the circuit and avoid the display panel 10 turning green due to excessive current.

[0044] In some optional embodiments, multiple first electrostatic release blocks 102 are distributed at intervals along the second direction Y, multiple second electrostatic release blocks 101 are distributed at intervals along the second direction Y, and the multiple first electrostatic release blocks 102 are located on one side of the multiple second electrostatic release blocks 101 in the first direction X toward the third lead 130.

[0045] In these optional embodiments, the plurality of first electrostatic release blocks 102 and the plurality of second electrostatic release blocks 101 are spaced apart along the second direction Y, so that both have a large space on one side of the first direction X, which is convenient for wiring the first lead 110 and the second lead 120. The plurality of first electrostatic release blocks 102 are located on the side of the plurality of second electrostatic release blocks 101 facing the third lead 130, so that the first electrostatic release blocks 102 are directly connected to the first lead 110, reducing the distance between the first electrostatic release blocks 102 and the first lead 110, which not only reduces the complexity of the design, facilitates the wiring of the first lead 110, reduces the design cost, but also ensures that the first lead 110 has a large resistance to reduce the current in the circuit and avoid the display panel 10 turning green due to excessive current.

[0046] See also Figure 4 , Figure 4 It is a schematic diagram of the local enlarged structure at Q in another embodiment.

[0047] In some optional embodiments, the second lead 120 includes a first segment 121 and a second segment 122, the first segment 121 is located on one side of the first electrostatic release block 102 in the second direction Y, the second segment 122 is connected to the first lead 110 and extends away from the first electrostatic release block 102 in the first direction X, and the second segment 122 extends obliquely toward the electrostatic release block in the second direction Y, the first lead 110 is connected to one side of the first electrostatic release block 102 in the first direction X, and the first lead 110 is connected between the second segment 122 and the first electrostatic release block 102.

[0048] In these optional embodiments, the first segment 121 is located on one side of the first electrostatic release block 102 in the second direction Y, making full use of the space between two adjacent first electrostatic release blocks 102 to improve space utilization. The second segment 122 is connected to the first lead 110 and extends away from the first electrostatic release block 102 in the first direction X. The second lead 120 and the first lead 110 are connected in the second segment 122. When the second segment 122 is extended obliquely toward the electrostatic release block in the second direction Y, the first lead 110 is connected between the second segment 122 and the first electrostatic release block 102, so that the distance between the second segment 122 and the first electrostatic release block 102 is reduced. The second segment 122 and the first electrostatic release block 102 are connected by using a shorter first lead 110, which not only reduces the complexity of the design and reduces the design cost, but also ensures that the first lead 110 has a larger resistance to reduce the current in the circuit and avoid the display panel 10 turning green due to excessive current. The first lead 110 is connected to one side of the first electrostatic release block 102 in the first direction X. Since the electrostatic release blocks are arranged at intervals in the second direction Y, there is a large space on one side of the electrostatic release block in the first direction X, which is convenient for wiring the first lead 110 .

[0049] In some optional embodiments, the angles between each second segment 122 and the second direction Y are equal.

[0050] In these optional embodiments, the second segments 122 have the same direction, which reduces the complexity of the design and facilitates unified wiring.

[0051] In some optional embodiments, the first lead 110 extends along the first direction X, and the first lead 110 extends along the first direction X as a straight line 210, which not only reduces the complexity of the design, facilitates the wiring of the first lead 110, and reduces the design cost, but also ensures that the first lead 110 has a larger resistance to reduce the current in the line and avoid the display panel 10 turning green due to excessive current.

[0052] See also Figure 5 and Figure 6 , Figure 5 is a schematic diagram of a partially enlarged structure at Q in yet another embodiment; Figure 6 It is a schematic diagram of the local enlarged structure at Q in yet another embodiment.

[0053] In some optional embodiments, the first lead 110 is in an X-shape or the first lead 110 extends along a bending path in a serpentine shape.

[0054] In these optional embodiments, the length of the first lead 110 is increased as much as possible within the limited space between the first electrostatic release block 102 and the second segment 122, ensuring that the first lead 110 has a larger resistance to reduce the current in the circuit and avoid the display panel 10 turning green due to excessive current.

[0055] Please continue reading Figure 6 In some optional embodiments, the connection points 200 of the first leads 110 and the second leads 120 corresponding to the plurality of first electrostatic release blocks 102 are located on a straight line 210 extending in the second direction Y. The straight line 210 is a reference line, and the straight line 210 does not constitute a limitation on the structure of the array substrate of the present application.

[0056] In these optional embodiments, the connection point 200 between the first electrostatic release block 102 and the first lead 110 is on the same straight line 210 in the second direction Y, and the structural design of the connection is the same, which reduces the complexity of the design, facilitates the wiring of the first lead 110, and reduces the design cost.

[0057] Optionally, the distances between adjacent connection points 200 are equal. The distances between the connection points 200 are equal and the distribution is regular, which reduces the complexity of the design, facilitates the wiring of the first lead 110, and reduces the design cost.

[0058] Optionally, the first leads 110 have the same shape. The first leads 110 have the same shape, which facilitates unified design and wiring, reduces design complexity, facilitates wiring of the first leads 110, and reduces design costs.

[0059] Optionally, the total length of each first lead 110 is the same. On the one hand, the same length of each first lead 110 facilitates unified design and wiring, reduces the complexity of design, facilitates the wiring of the first lead 110, and reduces the design cost. On the other hand, the same resistance of each first lead 110 makes the current in each section the same, ensuring the uniformity of the line.

[0060] Optionally, the first lead 110 and the second lead 120 are stacked on each other. The first lead 110 and the second lead 120 are located in different layers to avoid crowded wiring of the two and reduce the complexity of the design.

[0061] Optionally, the shapes of the first leads 110 are different. If the wiring space allows, the first leads 110 are designed according to the size of the wiring space to fully utilize the wiring space and improve space utilization.

[0062] See also Figure 7 , Figure 7 yes Figure 1 Partial cross-sectional view at Q in the middle.

[0063] In some optional embodiments, the array substrate 11 also includes a gate metal layer 300 and a source-drain metal layer 400, and the third lead 130 is located in the gate metal layer 300; the source-drain metal layer 400 is stacked with the gate metal layer 300 and insulated from each other, and the second lead 120 and the fourth lead 140 are located in the source-drain metal layer 400.

[0064] In these optional embodiments, the second lead 120 and the fourth lead 140 are arranged in the same layer, and the second lead 120 and the fourth lead 140 can be prepared at the same time, simplifying the preparation process. The third lead 130 and the second lead 120 are arranged in different layers to avoid crowded wiring and reduce the complexity of the design.

[0065] Optionally, the source-drain metal layer 400 is directly laid on the conductor layer where the first lead 110 is located, so that the second lead 120 located in the source-drain metal layer 400 is directly connected to the first lead 110, avoiding resistance fluctuations caused by vias between the first lead 110 and the second lead 120, thereby ensuring the stability of the overall impedance of the line.

[0066] Optionally, the thickness of the source-drain metal layer 400 where the second lead 120 is located is greater than the conductor layer where the first lead 110 is located, thereby reducing the possibility of disconnection between the first lead 110 and the second lead 120 and ensuring the stability of the circuit.

[0067] The embodiment of the second aspect of the present invention further provides a display panel 10, comprising an array substrate 11 of any of the above-mentioned first aspect embodiments. The display panel 10 may be an organic light emitting diode (OLED) display panel 10. Since the display panel 10 provided by the embodiment of the second aspect of the present invention comprises the array substrate 11 of any of the above-mentioned first aspect embodiments, the display panel 10 provided by the embodiment of the second aspect of the present invention has the beneficial effects of the array substrate 11 of any of the above-mentioned first aspect embodiments, which will not be described in detail herein.

[0068] The embodiment of the third aspect of the present invention further provides a display device, comprising the display panel 10 of the embodiment of the second aspect. Since the display device provided by the embodiment of the third aspect of the present invention comprises the display panel 10 of the embodiment of the second aspect, the display device provided by the embodiment of the third aspect of the present invention has the beneficial effects of the display panel 10 of the embodiment of the second aspect, which will not be described in detail here.

[0069] The display device in the embodiment of the present invention includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart fixed-line phones, consoles and other devices with display functions.

[0070] See also Figure 8 , Figure 8 1 is a schematic flow chart of a method for preparing an array substrate 11 provided in an embodiment of the fourth aspect of the present application. The array substrate 11 may be the array substrate 11 provided in any of the embodiments of the first aspect above.

[0071] like Figure 8 Please also refer to Figures 1 to 7 The array substrate 11 shown, the method for preparing the array substrate 11 includes:

[0072] Step S01: preparing an electrostatic discharge assembly 100, wherein the electrostatic discharge assembly 100 includes a plurality of electrostatic discharge blocks arranged at intervals.

[0073] Step S02: preparing a conductor material layer, and performing patterning to obtain a first lead 110 , wherein one end of the first lead 110 is connected to at least one electrostatic release block.

[0074] Step S03: Prepare a metal material layer on one side of the conductor material layer and perform patterning to obtain a second lead 120 . The second lead 120 is connected to one end of the first lead 110 away from the electrostatic release block. The impedance of the second lead 120 is smaller than the impedance of the first lead 110 .

[0075] In the method for preparing the array substrate 11 provided in the embodiment of the present application, firstly, the electrostatic release component 100 is prepared by step S01, and the electrostatic release component 100 includes a plurality of electrostatic release blocks arranged at intervals, and a plurality of electrostatic release blocks are arranged to realize electrostatic protection of the array substrate 11. Then, the first lead 110 is prepared by step S02, and one end of the first lead 110 segment is connected to at least one electrostatic release block. Finally, the second lead 120 is prepared by step S03, and one end of the first lead 110 segment is connected to at least one electrostatic release block. The first lead 110 connects the electrostatic release block with the second lead 120, so that the electrostatic release block is connected with the second lead 120 through the first lead 110. The impedance of the second lead 120 is less than the impedance of the first lead 110, which increases the resistance of the overall circuit. The first lead 110 with a larger impedance is used to connect the electrostatic release block and the second lead 120 to reduce the current in the circuit and avoid the display panel 10 turning green due to excessive current.

[0076] According to the embodiments described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that: include: An electrostatic discharge assembly, comprising a plurality of electrostatic discharge blocks arranged at intervals; A first lead, wherein one end of the first lead segment is connected to at least one of the electrostatic release blocks; The second lead is connected to an end of the first lead away from the electrostatic release block, and the impedance of the second lead is smaller than the impedance of the first lead.

2. The array substrate according to claim 1, characterized in that: It also includes a third lead and a fourth lead, the plurality of electrostatic release blocks include a first electrostatic release block and a second electrostatic release block, the first electrostatic release block is connected to the second lead through the first lead, and the second lead and the third lead are connected via a via hole; The second electrostatic release block is connected to the fourth lead, and the fourth lead and the third lead are arranged in different layers.

3. The array substrate according to claim 2, characterized in that: The second lead and the fourth lead are arranged in the same layer and made of the same material.

4. The array substrate according to claim 2, characterized in that: The third lead is located at one side of the electrostatic release block in the first direction, and the first electrostatic release block is located at a side of the second electrostatic release block facing the third lead.

5. The array substrate according to claim 4, characterized in that: The first electrostatic release blocks are spaced apart along the second direction, the second electrostatic release blocks are spaced apart along the second direction, and the first electrostatic release blocks are located on one side of the second electrostatic release blocks facing the third lead in the first direction.

6. The array substrate according to claim 3, characterized in that: The second lead includes a first segment and a second segment, the first segment is located on one side of the first electrostatic release block in the second direction, the second segment is connected to the first lead and extends away from the first electrostatic release block in the first direction, and the second segment extends obliquely toward the electrostatic release block in the second direction, the first lead is connected to one side of the first electrostatic release block in the first direction, and the first lead is connected between the second segment and the first electrostatic release block.

7. The array substrate according to claim 6, characterized in that: The included angles between each of the second segments and the second direction are all equal.

8. The array substrate according to claim 2, characterized in that: The first lead extends along a first direction.

9. The array substrate according to claim 2, characterized in that: The first lead is in a "X" shape or extends along a bending path in a serpentine shape.

10. The array substrate according to claim 2, characterized in that: The connection points between the first lead lines and the second lead lines corresponding to the first electrostatic release blocks are located on a straight line extending in the second direction.

11. The array substrate according to claim 10, characterized in that: The distances between adjacent connection points are all equal.

12. The array substrate according to claim 10, characterized in that: The first leads have the same shape.

13. The array substrate according to claim 10, characterized in that: The total lengths of the first leads are the same.

14. The array substrate according to claim 1, characterized in that: The first lead and the second lead are stacked on each other.

15. The array substrate according to claim 2, characterized in that: Also includes: A gate metal layer, wherein the third lead is located on the gate metal layer; The source-drain metal layer is stacked with the gate metal layer and insulated from each other, and the second lead and the fourth lead are located in the source-drain metal layer.

16. A display panel, characterized in that: Comprising the array substrate as described in any one of claims 1-15.

17. A display device, characterized in that: Comprising the display panel as claimed in claim 16.

18. A method for preparing an array substrate, characterized in that: include: preparing an electrostatic release assembly, the electrostatic release assembly comprising a plurality of electrostatic release blocks arranged at intervals; Prepare a conductor material layer, and perform patterning to obtain a first lead, wherein one end of the first lead segment is connected to at least one of the electrostatic release blocks; A metal material layer is prepared on one side of the conductor material layer and patterned to obtain a second lead, the second lead is connected to an end of the first lead away from the electrostatic release block, and the impedance of the second lead is smaller than the impedance of the first lead.

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