Shielded gate power transistor and method for manufacturing the same

Abstract

The embodiments of this specification provide a shielded gate power transistor and a method for preparing the same. The shielded gate power transistor includes: a first conductive type substrate, a first conductive type epitaxial layer stacked on the first conductive type substrate, a cell region and a terminal region provided in the first conductive type epitaxial layer; a first trench surrounding the cell region is provided in the terminal region, a first gate structure is provided in the first trench, the first gate structure starting end of the first gate structure is close to the cell region, the first gate structure end is away from the cell region, and the potential connected to the starting end of the first gate structure is lower than the potential connected to the end of the first gate structure. The first trench in the terminal region and the first gate structure extend together around and surround the cell region. The potential connected to the end of the first gate structure is higher than the potential connected to the starting end of the first gate structure, which can make the electric field in the terminal region more uniform and improve the voltage resistance reliability of the shielded gate power transistor. At the same time, the first gate structure can be used as a high-voltage resistor to simplify the peripheral drive circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a shielded gate power transistor and a method for manufacturing the same. Background Art

[0002] A shielded-gate trench MOSFET (SGT-MOSFET) is a power device. As a trench transistor structure, it utilizes a shielded gate electrode to reduce the gate-drain overlap area of ​​the transistor device, thereby reducing gate-drain capacitance. As a result, SGT-MOSFETs offer fast switching speeds and low device losses, making them suitable for use as power devices.

[0003] When used as a power device, shielded-gate power transistors need to withstand a certain voltage. Therefore, voltage resistance reliability becomes a major factor limiting the application of shielded-gate power transistors. Summary of the Invention

[0004] In view of this, multiple embodiments of this specification are dedicated to providing a shielded gate power transistor and a method for manufacturing the same, which are beneficial to improving the voltage resistance reliability of the shielded gate power transistor.

[0005] An embodiment of the present specification provides a shielded gate power transistor, comprising: a first conductive type substrate; a first conductive type epitaxial layer stacked on one side of the first conductive type substrate, a cell region and a terminal region surrounding the cell region being provided in the first conductive type epitaxial layer, a first trench being provided in the terminal region, the first trench surrounding the cell region; a first gate structure being provided in the first trench, the first gate structure surrounding the cell region, the first gate structure comprising a first gate structure starting end close to the cell region and a first gate structure ending away from the cell region, the potential for connection at the first gate structure starting end being lower than the potential for connection at the first gate structure ending end.

[0006] An embodiment of the present specification provides a method for preparing a shielded gate power transistor, including: providing a first conductive type epitaxial layer, the first conductive type epitaxial layer being stacked on one side of the first conductive type substrate, a cell region and a terminal region surrounding the cell region being provided in the first conductive type epitaxial layer; a first trench surrounding the cell region being provided in the terminal region; a first gate structure being provided in the first trench, the first gate structure surrounding the cell region, the first gate structure including a first gate structure starting end close to the cell region and a first gate structure ending away from the cell region, the potential for connection at the first gate structure starting end being lower than the potential for connection at the first gate structure ending end.

[0007] In the shielded-gate power transistor provided in the embodiments of this specification, a first trench in the terminal region is arranged to extend around and surround the cell region, and a first gate structure is disposed in the first trench. The on-state potential of the first gate structure at the end is higher than that at the beginning, making the electric field in the terminal region more uniform and improving the withstand voltage reliability of the shielded-gate power transistor. Furthermore, the first gate structure can function as a high-voltage resistor, simplifying the peripheral drive circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG2 is a schematic top view of a shielded gate power transistor according to an embodiment of the present invention.

[0009] Figure 2 FIG2 is a schematic cross-sectional view of a shielded gate power transistor according to an embodiment of the present invention.

[0010] Figure 3 FIG2 is a schematic cross-sectional view of a shielded gate power transistor according to an embodiment of the present invention.

[0011] Figure 4 FIG2 is a schematic cross-sectional view of a shielded gate power transistor according to an embodiment of the present invention.

[0012] Figure 5 FIG2 is a schematic top view of a shielded gate power transistor according to an embodiment of the present invention.

[0013] Figure 6 FIG2 is a schematic cross-sectional view of a shielded gate power transistor according to an embodiment of the present invention.

[0014] Figure 7 FIG2 is a schematic cross-sectional view of a shielded gate power transistor according to an embodiment of the present invention.

[0015] Figures 8-17 FIG2 is a structural diagram of a shielded gate power transistor manufacturing process provided by one embodiment. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in some embodiments of the specification to clearly and completely describe the technical solutions in some embodiments of the specification. Obviously, the embodiments described are only some embodiments of the specification, not all embodiments. Based on the embodiments of the specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of this specification.

[0017] The present disclosure provides a shielded gate power transistor. The shielded gate power transistor may include: a first conductive type substrate 110; a first conductive type epitaxial layer 130 stacked on one side of the first conductive type substrate 110, wherein the first conductive type epitaxial layer 130 includes a cell region I and a terminal region II surrounding the cell region I, wherein the terminal region II includes a first trench 400, and the first trench 400 surrounds the cell region I; and a first gate structure 410 disposed within the first trench 400, the first gate structure 410 surrounding the cell region I, and including a first gate structure start end 411 proximate to the cell region I and a first gate structure end 412 distal to the cell region I, wherein the potential for connection at the first gate structure start end 411 is lower than the potential for connection at the first gate structure end 412.

[0018] See also Figure 2 . Figure 2 To correspond Figure 1 Schematic diagram of a cross-sectional structure along line A-A1 in FIG. In some embodiments, a first conductivity type auxiliary layer 120 may be disposed between the first conductivity type substrate 110 and the first conductivity type epitaxial layer 130. The material of the first conductivity type substrate 110 may include a semiconductor material. The material of the first conductivity type substrate 110 may include at least one of silicon, silicon germanium, and silicon carbide. The material of the first conductivity type epitaxial layer 130 may include silicon. For example, the first conductivity type epitaxial layer 130 is a single crystal silicon epitaxial layer.

[0019] In some embodiments, the first conductive type substrate 110 contains first conductive type ions. The first conductive type epitaxial layer 130 contains first conductive type ions. The concentration of the first conductive type ions in the first conductive type substrate 110 can be greater than the concentration of the first conductive type ions in the first conductive type epitaxial layer 130. The concentration of the first conductive type ions in the first conductive type substrate 110 is greater than the concentration of the first conductive type ions in the first conductive type epitaxial layer 130. This is beneficial for improving device stability.

[0020] In some embodiments, the first conductive type auxiliary layer 120 may contain first conductive type ions, and the first conductive type epitaxial layer 130 may contain first conductive type ions. The resistivity of the first conductive type auxiliary layer 120 may be less than the resistivity of the first conductive type epitaxial layer 130. This is beneficial to reducing the on-resistance of the shielded gate power transistor. The resistivity of the first conductive type auxiliary layer 120 and the resistivity of the first conductive type epitaxial layer 130 can be adjusted by controlling the concentration of the first conductive type ions. The concentration of the first conductive type ions in the first conductive type auxiliary layer 120 may be greater than the concentration of the first conductive type ions in the first conductive type epitaxial layer 130, so that the resistivity of the first conductive type auxiliary layer 120 is less than the resistivity of the first conductive type epitaxial layer 130. In other embodiments, the concentration of the first conductive type ions in the first conductive type auxiliary layer 120 may be less than the concentration of the first conductive type ions in the first conductive type epitaxial layer 130.

[0021] See also Figure 1 and Figure 2 In some embodiments, the first conductive type epitaxial layer 130 is provided with a cell region I and a terminal region II surrounding the cell region I. The cell region I is located in the terminal region II.

[0022] See also Figure 8 and Figure 9 In some embodiments, the first conductivity type epitaxial layer 130 is provided with a cell region I, a transition region III, and a terminal region II, with the transition region III being located between the cell region I and the terminal region II. It is understood that the transition region III surrounds the cell region I, and the terminal region II surrounds the transition region III. The range of the transition region III can be designed according to actual needs.

[0023] In some embodiments, a first trench 400 is provided in the terminal region II, and the first trench 400 surrounds the cellular region I. The first trench 400 may extend continuously and surround the cellular region I. The first conductivity type epitaxial layer 130 may have opposing first and second surfaces, and the opening of the first trench 400 may be coplanar with the first surface. The first trench 400 surrounds the cellular region I and may be within the first surface, with the cellular region I located within the area enclosed and defined by the opening of the first trench 400.

[0024] In some embodiments, the first trench 400 surrounds cell region I and can extend continuously along the perimeter of cell region I, forming a multi-level structure along the direction from cell region I to terminal region II. The first trench 400 can extend continuously, and the notch of the continuously extended first trench 400 can have a spiral morphology, which facilitates the formation of a multi-level structure surrounding cell region I. This allows the first gate structure 410 disposed within the first trench 400 to surround cell region I. This facilitates improving the uniformity of voltage drop reduction in all directions and locations, and can ensure a more uniform electric field in the terminal region during withstand voltage.

[0025] In some embodiments, there may be multiple first trenches 400. A single first trench 400 may surround at least a portion of the cell region I, and multiple first trenches 400 may collectively form a structure surrounding the cell region I. The multiple first trenches 400 may not be connected to each other.

[0026] See also Figure 1 and Figure 2 In some embodiments, the first gate structure 410 disposed within the first trench 400 includes a first gate structure start end 411 proximate to cell region I and a first gate structure end 412 distal to cell region I. The potential for switching on the first gate structure start end 411 is lower than the potential for switching on the first gate structure end 412. It is understood that the first gate structure start end 411 and the first gate structure end 412 are separated from each other.

[0027] In some embodiments, the first gate structure 410 surrounds the cell region I. The first gate structure 410 may extend continuously within the first trench, completely filling the first trench 400 along the extension direction of the first trench. The number of times the first gate structure 410 surrounds the cell region I may be greater than one. The first gate structure 410 may extend continuously within the first trench 400, and the upper surface of the continuously extended first gate structure 410 may have a spiral morphology, facilitating the formation of a multi-level structure surrounding the cell region I. The upper surface of the first gate structure 410 may refer to the surface of the first gate structure 410 near the notch of the first trench 400.

[0028] In some embodiments, the first gate structure 410 includes a first gate 402 and a first dielectric layer 401 located between the first gate 402 and the first conductivity type epitaxial layer 130. The first dielectric layer 401 is used to electrically isolate the first gate 402 from the first conductivity type epitaxial layer 130. It will be understood that the first dielectric layer 401 is located on the sidewalls of the first trench 400 and at the bottom of the first trench 400. The material of the first dielectric layer 401 can be an insulating material. For example, it can be silicon oxide. The first gate structure 410 can include a single layer or multiple layers of the first dielectric layer 401. The materials of the multiple layers of the first dielectric layer 401 can be the same. Each layer can be prepared separately. Figure 2 Schematically, two first dielectric layers 401 are shown. The material of the first gate 402 may include polysilicon.

[0029] In some embodiments, the potential used to connect the first gate structure start 411 is lower than the potential used to connect the first gate structure end 412. The potential used to connect the first gate structure start 411 and / or the first gate structure end 412 can be a necessary potential in an existing shielded gate power transistor device. For example, the shielded gate power transistor includes a potential for a control gate, etc. This is conducive to simplifying the design of the shielded gate power transistor structure. The potential used to connect the first gate structure start 411 and / or the second gate structure end 412 can be a potential that is not present in a shielded gate power transistor device that does not have a second gate structure. An additional potential can be added, as long as the potential used to connect the first gate structure start 411 is lower than the potential used to connect the first gate structure end 412.

[0030] The shielded-gate power transistor provided in the embodiments of this specification features a first gate structure 410 surrounding cell region I in terminal region II. The potential at the start 411 of the first gate structure, used for connection, is lower than the potential at the end 412 of the first gate structure, thereby decreasing the potential of terminal region II from the outside to the inside. This makes the electric field in terminal region II more uniform during withstand voltage, reduces the peak electric field in terminal region II, and improves the withstand voltage reliability of the shielded-gate power transistor. Furthermore, the first gate structure 410 in this structure can function as a high-voltage resistor, simplifying and facilitating peripheral drive circuitry.

[0031] In some embodiments, cell region I is provided with a plurality of third trenches 200. The third trenches 200 may extend along a first direction, with the plurality of third trenches 200 arranged along a second direction different from the first direction. The first and second directions may both be parallel to the plane where the openings of the third trenches 200 are located. It will be understood that the third trenches 200 are embedded within the first conductivity type epitaxial layer 130 along the thickness direction of the first conductivity type epitaxial layer 130. The plurality of third trenches 200 may be spatially separated from each other, forming a structure spaced apart from each other. The plurality of third trenches 200 may have the same depth. The plurality of third trenches 200 may be fabricated in the same process. The first and second directions may be different and intersect. In some embodiments, the first and second directions may be perpendicular to each other. In other embodiments, the plurality of third trenches 200 may be arranged in other manners.

[0032] In some embodiments, since the first gate structure 410 surrounds the cell region I, the distance between different positions of the first gate structure 410 and the cell region I can be determined along the first direction or along a direction perpendicular to the first direction according to the specific position.

[0033] In some embodiments, the depth of the third trench 200 may be the same as the depth of the first trench 400. The first trench 400 and the third trench 200 may be formed in one process. Alternatively, the third trench 200 and the first trench 400 may be formed separately in different processes.

[0034] See also Figure 2 In some embodiments, a shielded gate power transistor may include a control gate structure 310 and a shield gate structure 210 disposed within a third trench 200. The control gate structure 310 and the shield gate structure 210 are stacked within the third trench 200, with the shield gate structure 210 being close to the bottom of the third trench 200. The control gate structure 310 may be disposed within a portion of the depth of the third trench 200, and the shield gate structure 210 may be disposed within a portion of the depth of the third trench 200. Along the depth direction of the third trench 200, the control gate structure 310 and the shield gate structure 210 may have no overlapping region; alternatively, along the depth direction of the third trench 200, the control gate structure 310 and the shield gate structure 210 may have a partial overlap. Along the depth direction of the third trench 200, the control gate structure 310 and the shield gate structure 210 do not overlap in at least a portion of the region. The shield gate structure 210 is close to the bottom of the third trench 200, and accordingly, the control gate structure 310 is close to the notch of the third trench 200.

[0035] In some embodiments, the control gate structure 310 and the shield gate structure 210 are electrically isolated from each other, and the electrical isolation may be achieved by insulating materials.

[0036] In some embodiments, the shield gate structure 210 includes a shield gate 202 and a second dielectric layer 201 located between the shield gate 202 and the first conductive type epitaxial layer 130. The second dielectric layer 201 is used to electrically isolate the shield gate 202 from the first conductive type epitaxial layer 130. It will be understood that the second dielectric layer 201 is located on the sidewalls of the third trench 200 and the bottom of the third trench 200. The material of the second dielectric layer 201 can be an insulating material. For example, the material of the second dielectric layer 201 can be silicon oxide. The shield gate structure 210 can include one or more layers of the second dielectric layer 201. The materials of the multiple layers of the second dielectric layer 201 can be the same. Each layer of the second dielectric layer 201 can be prepared separately, which is beneficial for improving the anti-breakdown capability of the shield gate power transistor. The material of the shield gate 202 can include polysilicon.

[0037] See also Figure 2 and Figure 3 . Figure 3 To correspond Figure 1 Schematic diagram of a cross-sectional structure along line B-B1 in FIG. In some embodiments, the control gate structure 310 includes a control gate 302 and a second dielectric layer 301 located between the control gate 302 and the first conductive type epitaxial layer 130. The second dielectric layer 301 is also located between the shield gate structure 210 and the control gate 302. The second dielectric layer 301 is used to electrically isolate the control gate 302 from the first conductive type epitaxial layer 130, and to electrically isolate the control gate 302 from the shield gate 202. It will be understood that the second dielectric layer 301 is located on the sidewalls of the third trench 200 and between the control gate 302 and the shield gate 202. The material of the second dielectric layer 301 can be an insulating material, for example, silicon oxide. The control gate structure 310 can include a single layer or multiple layers of the second dielectric layer 301. In the multiple layers of the second dielectric layer 301, each layer can be made of the same material and can be prepared separately. The material of the control gate 302 can include polycrystalline silicon.

[0038] In some embodiments, the control gate 302 covers the shield gate 202, and along the width direction of the third trench 200, the width of the control gate 302 can be greater than the width of the shield gate 202. The width direction of the third trench 200 can be a direction perpendicular to the first direction within the plane where the notch of the third trench 200 is located.

[0039] In some embodiments, the depth of the third trench 200 is less than or equal to the depth of the first trench 400. The depth of the first trench 400 is greater than the depth of the third trench 200, which is beneficial to improving the voltage resistance of the termination region II.

[0040] See also Figure 2 、 Figure 3 and Figure 4 . Figure 4 To correspond Figure 1Schematic diagram of a cross-sectional structure along line C-C1 in FIG. In some embodiments, the first conductive type substrate 110 has first conductive type ions, and along a direction close to the first conductive type substrate 110, a portion of the thickness of the first conductive type epitaxial layer 130 is a body region 1221, wherein the body region 1221 has second conductive type ions, and the second conductive type ions have an electrical property opposite to that of the first conductive type ions; the first conductive type epitaxial layer 130 includes a first source doping region 1222 located within the cell region I, wherein the first source doping region 1222 has first conductive type ions and is superimposed on a surface of the body region 1221 facing away from the first conductive type substrate 110; the shielded gate power transistor further includes: a source metal layer 320 disposed on a side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110, wherein the source metal layer 320 is electrically connected to the first source doping region 1222.

[0041] In some embodiments, a portion of the thickness of the first conductive type epitaxial layer 130 along a direction close to the first conductive type substrate 110 is a body region 1221. The body region 1221 may be a portion of the first conductive type epitaxial layer 130, extending from the first surface of the first conductive type epitaxial layer 130 along the thickness direction of the first conductive type epitaxial layer 130. The thickness direction of the first conductive type epitaxial layer 130 may be parallel to the depth direction of the first trench 400. The first conductive type epitaxial layer 130 includes a cell region I and a terminal region II surrounding the cell region I. The body region 1221 may be located in the cell region I and the terminal region II. The body region 1221 contains second conductive type ions, which have an electrical property opposite to that of the first conductive type ions.

[0042] In some embodiments, the first conductivity type epitaxial layer 130 includes a first source doping region 1222 located within the cell region I. The first source doping region 1222 contains first conductivity type ions and is superposed on a surface of the body region 1221 facing away from the first conductivity type substrate 110. Along the arrangement of the plurality of third trenches 200, first source doping regions 1222 may be provided on both sides of the third trenches 200 within the cell region I.

[0043] In some embodiments, the first conductive type ions may have an N-type charge, and the second conductive type ions may have a P-type charge. The first conductive type ions may be at least one of phosphorus ions, arsenic ions, and antimony ions. The second conductive type ions may be at least one of boron ions, boron fluoride ions, and indium ions.

[0044] See also Figure 2In some embodiments, the shielded gate power transistor further includes: a source metal layer 320 disposed on a side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110, the source metal layer 320 being electrically connected to the first source doped region 1222. The source metal layer 320 may be made of a metal or a metal nitride. The metal may be at least one of copper, aluminum, tungsten, cobalt, nickel, and tantalum. The metal nitride may be at least one of tantalum nitride and titanium nitride.

[0045] See also Figure 2 . In some embodiments, a fourth dielectric layer 710 may be provided between the first conductive type epitaxial layer 130 and the source metal layer 320. The fourth dielectric layer 710 may be provided with a first opening, the first opening exposing a portion of the surface of the first source doping region 1222 on the side facing away from the first conductive type substrate 110. The source metal layer 320 and the first source doping region 1222 may be electrically connected through a first connection layer 330 located in the first opening. Furthermore, the source metal layer 320 is electrically connected to the first source doping region 1222. The material of the first connection layer 330 may be a metal or a metal nitride. The metal may be at least one of copper, aluminum, tungsten, cobalt, nickel and tantalum. The metal nitride may be at least one of tantalum nitride and titanium nitride.

[0046] See also Figure 3 In some embodiments, the shield gate structure 210 may be electrically connected to the source metal layer 320 . Specifically, the shield gate structure 210 may be electrically connected to the source metal layer 320 through the shield gate 202 .

[0047] See also Figure 2 . In some embodiments, the first opening may penetrate the fourth dielectric layer 710, the first source doping region 1222 and a partial thickness of the body region 1221. This is beneficial to improving the stability of the electrical connection. A first contact region 340 may be provided around the body region 1221 of the first opening, and the concentration of the second conductive type ions in the first contact region 340 is greater than the concentration of the second conductive type ions in the body region 1221, thereby forming an ohmic contact. This is beneficial to reducing the contact resistance. The first contact region 340 may be connected to the first source doping region 1222, or may be located only in the body region 1221. The first contact region 340 contacts the bottom surface and part of the side surface of the first connection layer 330 near the bottom of the first opening.

[0048] In some embodiments, the source metal layer 320 is also electrically connected to the body region 1221 of a portion of transition region III. A via can be provided between the fourth dielectric layer 710 and the body region 1221 in transition region III. The electrical connection between the body region 1221 and the source metal layer 320 in transition region III is achieved through the transition region connection layer 360 located within the via. A third contact region 370 can be provided at the bottom of the via. The concentration of the second conductive type ions in the third contact region 370 is greater than that in the body region 1221, thereby forming an ohmic contact. This helps reduce contact resistance. The third contact region 370 contacts the bottom surface and a portion of the side surface of the transition region connection layer 360.

[0049] See also Figure 5 、 Figure 6 and Figure 7 . Figure 6 correspond Figure 5 Schematic diagram of the cross-sectional structure along line D-D1. Figure 7 correspond Figure 5 Schematic diagram of a cross-sectional structure taken along line E-E1. In some embodiments, the first conductive type epitaxial layer 130 is provided with a second trench 800 located in the terminal region II, and the second trench 800 is located between the cell region I and the first trench 400. The shielded gate power transistor also includes: a second gate structure 810 disposed in the second trench 800, the second gate structure 810 surrounding the cell region I and connected end to end, and the source metal layer 320 is electrically connected to the second gate structure 810.

[0050] In some embodiments, the depth of the second trench 800 can be the same as the depth of the first trench 400. They can be fabricated using the same process. The second trench 800 can be connected end to end and surround the cell region I. The depth of the second trench 800 can be different from the depth of the first trench 400.

[0051] In some embodiments, the second gate structure 810 is located within the second trench 800. The second gate structure 810 surrounds the cell region I and is connected end to end. The second gate structure 810 forms a closed, surrounding structure. The second gate structure 810 may include a second gate 802 and a fifth dielectric layer 801. The fifth dielectric layer 801 is located between the second gate 802 and the first conductivity type epitaxial layer 130. The fifth dielectric layer 801 serves to electrically isolate the second gate 802 from the first conductivity type epitaxial layer 130. It is understood that the fifth dielectric layer 801 is located on the sidewalls and bottom of the second trench 800. The material of the fifth dielectric layer 801 can be an insulating material. For example, it can be silicon oxide. The second gate structure 810 may include one or more fifth dielectric layers 801. Each layer of the multiple fifth dielectric layers 801 can be made of the same material. Each layer of the fifth dielectric layer 801 can be prepared separately. The material of the second gate 802 may include polysilicon.

[0052] See also Figure 6 and Figure 7 In some embodiments, the source metal layer 320 is electrically connected to the second gate structure 810. Specifically, the source metal layer 320 can be electrically connected to the second gate 802. The potential used to turn on the second gate 802 can be the same as the potential used to turn on the first source doped region 1222. The source metal layer 320 and the second gate structure 810 can be electrically connected via a second connection layer 350 located in the second opening of the fourth dielectric layer 710. For details, please refer to the first opening and the first connection layer 330, and will not be repeated here.

[0053] By setting a second gate structure 810, the second gate structure 810 is electrically connected to the source metal layer 320, which can further improve the voltage resistance of the terminal area II and protect the cell area I. At the same time, the second gate structure 810 is electrically connected to the source metal layer 320, which can simplify the electrical connection method and reduce the complexity of the shielded gate power transistor structure.

[0054] In some embodiments, the potential at which the second gate structure 810 is turned on is the same as the potential at which the first source doped region 1222 is turned on. A second opening can be provided in the fourth dielectric layer 710, and a second connection layer 350 can be provided within the second opening. The second connection layer 350 can be electrically connected to the source metal layer 320, so that the potential at which the second gate structure 810 is turned on is the same as the potential at which the first source doped region 1222 is turned on.

[0055] In some embodiments, a second gate connection layer may be provided on the side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110. The second gate connection layer may be prepared in a single process with the source metal layer 320. The second gate connection layer may be spaced apart from the source metal. This is beneficial for improving the applicability of the device. The source metal layer 320 is electrically connected to the first source doping region 1222, and the first source doping region 1222 is connected to the potential for connection through the source metal layer 320. The second gate structure 810 is connected to the potential for connection through the second gate connection layer, and the potential is the same as the potential for connection of the first source doping region 1222. The second gate structure 810 and the second gate connection layer may be electrically connected by providing an opening at least in the fourth dielectric layer 710 and providing an electrical connection layer in the opening. For details, please refer to the first opening and the first connection layer 330, which will not be described in detail here.

[0056] See also Figure 2 or Figure 6 . In some embodiments, the potential at which the first gate structure start 411 is turned on is the same as the potential at which the first source doping region 1222 is turned on. A first gate start electrode 420 can be provided on the side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110. The first gate start electrode 420 is electrically connected to the first gate structure start 411. Specifically, the first gate start electrode 420 is electrically connected to the first gate 402. The first gate start electrode 420 can be prepared in one process with the source metal layer 320. The first gate start electrode 420 can be spaced apart from the source metal layer 320. The source metal layer 320 is electrically connected to the first source doping region 1222, and the first source doping region 1222 is connected to the potential for turning on through the source metal layer 320. The first gate structure start 411 is connected to the potential for turning on through the first gate start electrode 420, and the potential is the same as the potential at which the first source doping region 1222 is turned on. The first gate structure start 411 and the first gate start electrode 420 can be electrically connected by providing an opening at least in the fourth dielectric layer 710 and providing an electrical connection layer in the opening. For details, please refer to the first opening and the first connection layer 330, which will not be described in detail here. It can be understood that the first gate structure 410 is connected to the potential through the first gate 402. By making the potential used for connection at the first gate structure start 411 the same as the potential used for connection at the first source doping region 1222, the circuit design of the shielded gate power transistor can be simplified, and the requirement that the potential used for connection at the first gate structure start 411 is lower than the potential used for connection at the first gate structure end 412 can be met.

[0057] In some embodiments, the potential at the first gate structure start end 411 for switching on is lower than the potential at the first gate structure end 412 for switching on. The potential at the first gate structure start end 411 for switching on may be zero potential.

[0058] In some embodiments, the potential used to connect the first gate structure start 411 is the same as the potential used to connect the control gate structure 310. The first gate structure 410 is connected to a potential through the first gate 402, and the control gate structure 310 is connected to a potential through the control gate 302. By making the potential used to connect the first gate structure start 411 the same as the potential used to connect the control gate structure 310, the circuit design of the shielded gate power transistor can be simplified, and the requirement that the potential used to connect the first gate structure start 411 is lower than the potential used to connect the first gate structure end 412 can be met.

[0059] See also Figure 2 or Figure 6 In some embodiments, the shielded gate power transistor further includes: a drain metal layer 610 located on the side of the first conductive type substrate 110 facing away from the first conductive type epitaxial layer 130, and the potential at which the first gate structure end 412 is turned on is the same as the potential at which the drain metal layer 610 is turned on. The material of the drain metal layer 610 can be a metal or a metal nitride. The metal can be at least one of copper, aluminum, tungsten, cobalt, nickel, and tantalum. The metal nitride can be at least one of tantalum nitride and titanium nitride.

[0060] See also Figure 2 or Figure 6 In some embodiments, the first conductive type epitaxial layer 130 is provided with a fourth trench 500 located in the terminal region II, and the fourth trench 500 surrounds the first trench 400; the shielded gate power transistor further includes: a third gate structure 510 provided in the fourth trench 500, the third gate structure 510 surrounds the first trench 400 and is connected end to end, and the potential for connecting to the third gate structure 510 is the same as the potential for connecting to the drain metal layer 610.

[0061] In some embodiments, the fourth trench 500 can have the same depth as the first trench 400. They can be fabricated using the same process. The fourth trench 500 can be connected end to end and surround the first trench 400. It is understood that the fourth trench 500 surrounds cell region I. The fourth trench 500 can completely surround cell region I. The depth of the fourth trench 500 can be different from the depth of the first trench 400.

[0062] In some embodiments, the third gate structure 510 is located within the fourth trench 500. The third gate structure 510 surrounds the cell region I and is connected end to end. The third gate structure 510 forms a closed, surrounding structure. The third gate structure 510 may include a third gate 502 and a sixth dielectric layer 501. The sixth dielectric layer 501 is located between the third gate 502 and the first conductivity type epitaxial layer 130. The sixth dielectric layer 501 serves to electrically isolate the third gate 502 from the first conductivity type epitaxial layer 130. It is understood that the sixth dielectric layer 501 is located on the sidewalls and bottom of the fourth trench 500. The material of the sixth dielectric layer 501 can be an insulating material, for example, silicon oxide. The third gate structure 510 may include one or more sixth dielectric layers 501. Each layer of the multiple sixth dielectric layers 501 may be made of the same material. Each sixth dielectric layer 501 may be fabricated separately. The material of the third gate 502 may include polysilicon.

[0063] By providing a third gate structure 510 that surrounds the first trench 400 and is connected end to end, the potential used to connect the third gate structure 510 is the same as the potential used to connect the drain metal layer 610, thereby blocking peripheral ions and protecting the shielded gate power transistor. The same potential used to connect the third gate structure 510 and the drain metal layer 610 can simplify circuit design.

[0064] See also Figure 2 or Figure 7 In some embodiments, the first conductive type epitaxial layer 130 includes a second source doping region 1223 located on a side of the fourth trench 500 away from the cell region I, the second source doping region 1223 having first conductive type ions, and the second source doping region 1223 is superimposed on a surface of the body region 1221 of the terminal region II facing away from the first conductive type substrate 110; the shielded gate power transistor further includes a drain metal layer 620 disposed on a side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110, the drain metal layer 620 being electrically connected to the second source doping region 1223, the third gate structure 510, and the first gate structure end 412.

[0065] In some embodiments, the second source doping region 1223 can be formed using the same process as the first source doping region 1222. The drain metal layer 620 can be located on the surface of the fourth dielectric layer 710 facing away from the first conductive type substrate 110. Openings can be formed in at least four dielectric layers to expose the second source doping region 1223, the third gate structure 510, and the first gate structure end 412. An electrical connection layer can be formed in the opening to electrically connect the drain metal layer 620 to the second source doping region 1223, the third gate structure 510, and the first gate structure end 412. For details, please refer to the first opening and the first connection layer 330, and will not be repeated here. The potential used to connect the third gate structure 510 is the same as the potential used to connect the drain metal layer 610, which can be achieved by electrically connecting the drain metal layer 620 to the third gate structure 510; the potential used to connect the first gate structure end 412 is the same as the potential used to connect the drain metal layer 610, which can be achieved by electrically connecting the drain metal layer 620 to the first gate structure end 412.

[0066] In some embodiments, the drain metal layer 620 is electrically connected to the second source doping region 1223 via the second contact region 520. The second contact region 520 can be formed in the same process as the first contact region 340 to achieve ohmic contact between the drain metal layer 620 and the second source doping region 1223.

[0067] The embodiments of this specification provide a method for manufacturing a shielded gate power transistor. The method for manufacturing a shielded gate power transistor may include the following steps.

[0068] Step S110 : providing a first conductive type epitaxial layer 130 , wherein the first conductive type epitaxial layer 130 is stacked on one side of the first conductive type substrate 110 , and the first conductive type epitaxial layer 130 is provided with a cell region I and a terminal region II surrounding the cell region I.

[0069] See also Figure 8 and Figure 9 . Figure 9 To correspond Figure 8 Schematic diagram of a cross-sectional structure along line F-F1 in FIG. In some embodiments, a first conductivity type auxiliary layer 120 may be disposed between the first conductivity type epitaxial layer 130 and the first conductivity type substrate 110. The first conductivity type epitaxial layer 130 may include a cell region I, a transition region III, and a terminal region II, with the transition region III surrounding the cell region I and the terminal region II surrounding the transition region III.

[0070] Step S120: providing a first trench 400 surrounding the cell region I in the terminal region II.

[0071] See also Figure 10In some embodiments, providing the first trench 400 surrounding the cell region I in the terminal region II may include: forming a first mask layer on the surface of the first conductive type epitaxial layer 130, the first mask layer exposing a portion of the surface of the first conductive type epitaxial layer 130 in the terminal region II, and etching the first conductive type epitaxial layer 130 using the first mask layer as a mask to form the first trench 400 located in the terminal region II.

[0072] In some embodiments, a plurality of third trenches 200 are provided in the cell region I. The third trenches 200 can be formed in the same process as the first trenches 400. A first mask layer is used to expose a portion of the surface of the first conductive type epitaxial layer 130 in the cell region I. The first conductive type epitaxial layer 130 is etched using the first mask layer as a mask to form a plurality of third trenches 200 in the cell region I. The plurality of third trenches 200 can be arranged along a second direction different from the first direction, with both the first and second directions being parallel to the plane where the openings of the third trenches 200 are located. The third trenches 200 can be located in the first conductive type epitaxial layer 130.

[0073] In some embodiments, the third trench 200 can be formed in a single process with the first trench 400. In this case, the first mask layer can expose a portion of the surface of the first conductivity type epitaxial layer 130 in the cell region I and a portion of the surface of the first conductivity type epitaxial layer 130 in the terminal region II. The depth of the third trench 200 can be the same as the depth of the first trench 400. If the depth of the first trench 400 is greater than that of the third trench 200, a first trench structure with the same depth as the third trench 200 can be formed in a single process, and then the first trench structure can be further etched to form the final first trench 400.

[0074] Step S130: A first gate structure 410 is set in the first trench 400, wherein the first gate structure 410 includes a first gate structure starting end 411 close to the cell region I and a first gate structure end 412 away from the cell region I, and the potential used for connection at the first gate structure starting end 411 is lower than the potential used for connection at the first gate structure end 412.

[0075] See also Figure 11 In some embodiments, disposing the first gate structure 410 in the first trench 400 includes disposing a first dielectric material layer 201a on the sidewalls and bottom of the first trench 400. The first dielectric material layer 201a can be made of an insulating material. For example, the first dielectric material layer 201a can be made of silicon oxide. The first dielectric material layer 201a can be formed using a thermal oxidation process or a deposition process.

[0076] In some embodiments, providing the first gate structure 410 in the first trench 400 may include: forming a first dielectric material within the first trench 400 and on the surface of the first conductive type epitaxial layer 130, and planarizing the first dielectric material until the first surface of the first conductive type epitaxial layer 130 is exposed, thereby forming a first dielectric material layer 201a in the first trench 400. In some embodiments, multiple layers of the first dielectric material layer 201a may be provided. The multiple layers of the first dielectric material layer 201a may be prepared separately, and each layer may be made of the same material. The multiple layers may be prepared using different processes. For example, the multiple layers of the first dielectric material layer 201a may be formed using one or more of a thermal oxidation process and a deposition process.

[0077] See also Figure 12 In some embodiments, disposing the first gate structure 410 in the first trench 400 may include forming a gate material layer 202a within a region defined by the first dielectric material layer 201a. The gate material layer 202a may include polysilicon. The gate material layer 202a may be formed using a physical vapor deposition process or a chemical vapor deposition process. The first dielectric material layer 201 within the first trench 400 forms a first dielectric layer 801, and the gate material layer 202a within the first trench 400 forms a first gate 802.

[0078] In some embodiments, a gate material is formed in the region defined by the first dielectric material layer 201a and planarized until the first surface of the first conductive type epitaxial layer 130 is exposed, forming a gate material layer 202a. The gate material layer 202a may include polysilicon.

[0079] In some embodiments, the potential used to connect the first gate structure start 411 is lower than the potential used to connect the first gate structure end 412. The potential used to connect the first gate structure start 411 and / or the second gate structure end 412 can be a potential required in existing shielded gate power transistor devices. For example, the control gate included in the shielded gate power transistor is used to connect the potential. The potential used to connect the first gate structure start 411 and / or the second gate structure end 412 can be a potential not found in existing shielded gate power transistor devices, as long as the potential used to connect the first gate structure start 411 is lower than the potential used to connect the first gate structure end 412.

[0080] The shielded-gate power transistor fabrication method provided in the embodiments of this specification forms a first trench 400 surrounding cell region I and a first gate structure 410 located within the first trench 400. The first gate structure 410 surrounds cell region I. Furthermore, when the potential at the first gate structure's start 411, used for switching on, is lower than the potential at the first gate structure's end 412, the potential at the terminal region II decreases from the outside inward, making the electric field at the terminal region II more uniform and improving the withstand voltage reliability of the shielded-gate power transistor. Furthermore, the first gate structure 410 in this structure can function as a high-voltage resistor, simplifying and facilitating peripheral drive circuitry.

[0081] In some embodiments, the shielded gate power transistor manufacturing method may further include: providing a control gate structure 310 and a shielding gate structure 210 electrically isolated from each other in the third trench 200 , wherein the shielding gate structure 210 is close to the bottom of the third trench 400 .

[0082] See also Figure 11 and Figure 12 In some embodiments, the first dielectric material layer 201a and the gate material layer 202a can be formed in the first trench in a single process with the first gate structure 410. The first gate structure 410 can be formed without etching back the first dielectric material layer 201a and the gate material layer 202a. The first dielectric material layer 201a and the gate material layer 202a located in the first trench 400 form the first dielectric layer 401 and the first gate 402, respectively. The first gate structure 410 includes the first dielectric layer 401 and the first gate 402.

[0083] See also Figure 13 In some embodiments, providing a control gate structure 310 and a shield gate structure 210 electrically isolated from each other in the third trench 200 further includes: etching back the shield gate material layer 202a and the first dielectric material layer 201a in the third trench 200, and the shield gate material layer 202a and the first dielectric material layer 201a that are not removed in the third trench 200 form a shield gate 202 and a second dielectric layer 201, respectively. The shield gate structure 210 includes a shield gate 202 and a second dielectric layer 201. Different processes can be used to etch back the initial shield gate material layer 202a and the first dielectric material layer 201a, respectively. The method of etching back can refer to the existing process and will not be repeated here.

[0084] See also Figure 14In some embodiments, providing a mutually electrically isolated control gate structure 310 and shield gate structure 210 in the third trench 200 may further include: forming a third dielectric layer 301 on the control gate structure 310 and on the sidewalls of the third trench 200; and forming a control gate 302 within the region defined by the third dielectric layer 301. The material of the second dielectric layer 301 includes silicon oxide. The material of the control gate 302 includes polysilicon. The control gate 302 and the first conductivity type epitaxial layer 130 are electrically isolated by the second dielectric layer 301.

[0085] In some embodiments, the method for preparing a shielded gate power transistor may further include: setting a second trench 800 in the first conductive type epitaxial layer 130; wherein the second trench 800 is located in the terminal region II, and the second trench 800 is located between the third trench 200 and the cell region I; setting a second gate structure 810 in the second trench 800; wherein the second gate structure 810 surrounds the cell region I and is connected end to end.

[0086] See also Figure 10 In some embodiments, the second trench 800 can be formed in the same process as the first trench 400 . The depth of the second trench 800 can be the same as the depth of the first trench 400 . The second trench 800 can be located in the first conductivity type epitaxial layer 130 .

[0087] See also Figure 11 and Figure 12 In some embodiments, the second gate structure 810 can be formed in the same process as the first dielectric material layer 201a and the shielding gate material layer 202a. Alternatively, the second gate structure 810 can be formed in the same process as the first gate structure 810. The first dielectric material layer 201a and the shielding gate material layer 202a located in the second trench 800 form a fifth dielectric layer 801 and a second gate 802, respectively. The second gate structure 810 includes the fifth dielectric layer 801 and the second gate 802.

[0088] In some embodiments, the method for preparing a shielded gate power transistor may further include: setting a fourth trench 500 in the first conductive type epitaxial layer 130; wherein the fourth trench 500 is located in the terminal region II, and the fourth trench 500 surrounds the first trench 400; and setting a third gate structure 510 in the fourth trench 500; wherein the third gate structure 510 surrounds the first trench 400 and is connected end to end.

[0089] See also Figure 10In some embodiments, the fourth trench 500 can be formed in the same process as the first trench 400 . The depth of the fourth trench 500 can be the same as the depth of the first trench 400 . The fourth trench 500 can be located in the first conductivity type epitaxial layer 130 .

[0090] In some embodiments, the first trench 400 , the third trench 200 , the second trench 800 , and the fourth trench 500 may have the same depth, may be located in the first conductivity type epitaxial layer 130 , and may be formed using the same process.

[0091] See also Figure 11 and Figure 12 In some embodiments, the third gate structure 510 can be formed in the same process as the first dielectric material layer 201a and the shield gate material layer 202a. The first dielectric material layer 201a and the shield gate material layer 202a located in the fourth trench 500 form the sixth dielectric layer 501 and the third gate 502, respectively. The third gate structure 510 includes the sixth dielectric layer 501 and the third gate 502.

[0092] In some embodiments, the first conductive type substrate 110 has first conductive type ions, and the shielded gate power transistor preparation method may further include: doping second conductive type ions in a partial thickness of the first conductive type epitaxial layer 130 in a direction close to the first conductive type substrate 110 to form a body region 1221, wherein the second conductive type ions have opposite electrical properties to the first conductive type ions; doping the first conductive type ions in the first conductive type epitaxial layer 130 on the side of the body region 1221 facing away from the first conductive type substrate 110 to form a first source doping region 1222; wherein the first source doping region 1222 is located in the cell region I.

[0093] See also Figure 15 In some embodiments, a portion of the thickness of the first conductive type epitaxial layer 130 in the cell region I and a portion of the thickness of the first conductive type epitaxial layer 130 in the terminal region II form the body region 1221. An ion implantation process may be used to dope the first conductive type epitaxial layer 130 with second conductive type ions.

[0094] In some embodiments, an ion implantation process can be used to dope first conductivity type ions into the first conductivity type epitaxial layer 130 on the side of the body region 1221 facing away from the first conductivity type substrate 110 to form a first source doping region 1222. The concentration of the first conductivity type ions in the first source doping region 1222 is greater than the concentration of the second conductivity type ions in the body region 1221. The first source doping region 1222 is located in cell region I. Along the arrangement direction of the third trench 200, the first source doping region 1222 can be located on both sides of the third trench 200.

[0095] In some embodiments, the method for preparing a shielded gate power transistor may further include: setting a source metal layer 320 on the side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110; wherein the second gate structure 810 is set in the third trench 800, and the source metal layer 320 is electrically connected to the first source doping region 1222 and the second gate structure 810.

[0096] In some embodiments, the shielded gate power transistor preparation method may further include: disposing a source metal layer 320 on the side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110 ; wherein the source metal layer 320 is electrically connected to the first source doping region 1222 .

[0097] See also Figure 16 In some embodiments, before forming the source metal layer 320, the process may further include disposing a fourth dielectric layer 710 on the side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110, and forming a plurality of first openings in the fourth dielectric layer 710, wherein the first openings expose a portion of the first source doping region 1222. The first openings may penetrate the fourth dielectric layer 710, the first source doping region 1222, and a portion of the thickness of the body region 1221. A first contact region 340 may be formed in the body region 1221 at the bottom of the first opening; after forming the first contact region 340, a first connection layer 330 may be formed in the first opening. The first contact region 340 may be formed by implanting second conductive type ions using an ion implantation process, wherein the concentration of the second conductive type ions in the first contact region 340 is greater than the concentration of the second ions in the body region 1221.

[0098] In some embodiments, multiple second openings may be formed in the fourth dielectric layer 710, where the second openings expose a portion of the second gate 802. The first openings may penetrate the fourth dielectric layer 710. A second connection layer 350 may be formed in the second openings. The second connection layer 350 electrically connects the second gate structure 810 to the source metal layer 320.

[0099] In some embodiments, a via can be formed in transition region III, extending through at least the fourth dielectric layer 710. The via can be partially located in the body region 1221. A transition region connection layer 360 is disposed within the via to electrically connect the body region 1221 of transition region III to the source metal layer 320. A third contact region 370 can be disposed at the bottom of the via. The concentration of the second conductive type ions in the third contact region 370 is greater than that in the body region 1221, thereby forming an ohmic contact. This helps reduce contact resistance. The third contact region 370 contacts the bottom surface and a portion of the side surface of the transition region connection layer 360.

[0100] In some embodiments, a connection material layer can be formed on the fourth dielectric layer 710 and in the first opening, and the connection material layer can be planarized until the surface of the fourth dielectric layer 710 facing away from the first conductive type substrate 110 is exposed, thereby forming the first connection layer 330 in the first opening. The second connection layer 350 and the transition region connection layer 360 can be formed using the same process, which will not be further described here.

[0101] In some embodiments, disposing the source metal layer 320 on the side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110 may include: forming a metal material layer on the first connection layer 330 and the fourth dielectric layer 710; planarizing the metal material layer, and forming the source metal layer 320 on the first connection layer 330 and the fourth dielectric layer 710. The source metal layer 320 is electrically connected to the first source doped region 1222 and the second gate structure 810 via the first connection layer 330 and the second connection layer 350, respectively. The metal material layer can be formed using a physical vapor deposition process or an electroplating process. The metal material layer can be planarized using a chemical mechanical polishing process.

[0102] In some embodiments, the first conductive type substrate 110 has first conductive type ions, and the shielded gate power transistor preparation method may further include: doping second conductive type ions in a partial thickness of the first conductive type epitaxial layer 130 in a direction close to the first conductive type substrate 110 to form a body region 1221, wherein the second conductive type ions have opposite electrical properties to the first conductive type ions; and doping the first conductive type ions on a side of the third gate structure 510 away from the cell region I to form a second source doping region 1223; wherein the second source doping region 1223 is located on the side of the body region 1221 facing away from the first conductive type substrate 110.

[0103] See also Figure 16 In some embodiments, the second source doping region 1223 can be fabricated using the same process as the first source doping region 1222, with the difference being that they are located in the terminal region II and the cell region I, respectively. The body region 1221 of the first conductive type epitaxial layer 130 in each region can be fabricated using a single process.

[0104] In some embodiments, the method for preparing a shielded gate power transistor may further include: a drain metal layer 620 on the side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110; wherein the drain metal layer 620 is electrically connected to the second source doping region 1223, the third gate structure 510 and the first gate structure end 412.

[0105] See also Figure 16In some embodiments, the fourth dielectric layer 710 covers the first conductive type epitaxial layer 130. Vias penetrating the fourth dielectric layer 710 can be formed in regions corresponding to the third gate structure 510 and the first gate structure end 412, respectively. A connection layer can be further formed in the vias to electrically connect the drain metal layer 620 to the third gate structure 510 and the drain metal layer 620 to the first gate structure end 412. The electrical connection between the drain metal layer 620 and the second source doped region 1223 can be formed by referring to the electrical connection between the source metal layer 320 and the first source doped region 1222, and will not be repeated here.

[0106] In some embodiments, the method for manufacturing a shielded gate power transistor may further include: disposing a drain metal layer 610 on a surface of the first conductive type substrate 110 facing away from the first conductive type epitaxial layer 130 .

[0107] See also Figure 17 In some embodiments, a method for forming the drain metal layer 610 may include: forming a metal material layer on the second surface of the substrate; and planarizing the metal material layer to form the drain metal layer 610. The metal material layer may be formed using a physical vapor deposition process or an electroplating process. The metal material layer may be planarized using a chemical mechanical polishing process. The material of the drain metal layer 610 may include a metal or a metal nitride.

[0108] See also Figure 12 and Figure 16In some embodiments, the method for preparing a shielded gate power transistor may further include: providing a first gate start electrode 420 electrically connected to the first gate structure start 411 on the side of the first conductive type epitaxial layer 130 facing away from the first conductive type substrate 110; wherein the potential used to connect the first gate start electrode 420 is the same as the potential used to connect the first source doping region 1221; or, the potential used to connect the first gate start electrode 420 is the same as the potential used to connect the control gate structure 310. It can be understood that the first gate structure start 411 is electrically connected to the first gate start electrode 420, and specifically, the first gate 402 at the first gate structure start 411 is connected to the first gate start electrode 420. The first gate start electrode 420 can be located on the surface of the fourth dielectric layer 710 on the side facing away from the first conductive type substrate 110, and an opening can be provided in the fourth dielectric layer 710 to achieve the electrical connection between the first gate structure start 411 and the first gate start electrode 420. The potential used to connect the first gate starting electrode 420 is the same as the potential used to connect the first source doping region 1221; or, the potential used to connect the first gate starting electrode 420 is the same as the potential used to connect the control gate structure 310, which is conducive to design simplification and can meet the requirement that the potential used to connect the first gate structure starting end is lower than the potential used to connect the first gate structure end.

[0109] In some embodiments, the potential of the first gate start electrode 420 for turning on can be other additional designed potentials, as long as it is lower than the potential of the first gate structure start end 412 for turning on.

[0110] The various embodiments in this specification emphasize the differences between the various embodiments, and the various embodiments can be interpreted in comparison with each other. Any combination of the various embodiments in this specification based on general technical knowledge by those skilled in the art is within the scope of this specification.

[0111] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above descriptions are only some of the implementation methods in this specification and are not intended to limit this specification. Any modifications, equivalent replacements, etc. made within the spirit and principles of this specification should be included in the scope of disclosure of this specification.

Claims

1. A shielded gate power transistor, characterized in that: include: a first conductive type substrate; a first conductive type epitaxial layer stacked on one side of the first conductive type substrate, wherein the first conductive type epitaxial layer is provided with a cell region and a terminal region surrounding the cell region, and a first trench is provided in the first conductive type epitaxial layer in the terminal region, wherein the first trench spirally surrounds the cell region; a first gate structure disposed in the first trench, the first gate structure surrounding the cell region, the first gate structure including a first gate structure start end proximate to the cell region and a first gate structure end distal to the cell region, wherein a potential for switching on at the first gate structure start end is lower than a potential for switching on at the first gate structure end end; The first gate structure includes a first gate and a first dielectric layer located between the first gate and the first conductive type epitaxial layer, wherein the first dielectric layer is used to electrically isolate the first gate and the first conductive type epitaxial layer, wherein the first dielectric layer is located on the sidewalls of the first trench and the bottom of the first trench.

2. The shielded gate power transistor according to claim 1, wherein: The first conductive type substrate has first conductive type ions, and along a direction close to the first conductive type substrate, a portion of the thickness of the first conductive type epitaxial layer is a body region, and the body region has second conductive type ions, and the electrical properties of the second conductive type ions are opposite to those of the first conductive type ions; The first conductive type epitaxial layer includes a first source doping region located in the cell region, the first source doping region has first conductive type ions, and the first source doping region is superimposed on a surface of the body region facing away from the first conductive type substrate; The shielded gate power transistor further includes a source metal layer disposed on a side of the first conductive type epitaxial layer facing away from the first conductive type substrate, and the source metal layer is electrically connected to the first source doped region.

3. The shielded gate power transistor according to claim 2, wherein: A second trench located in the terminal region is provided in the first conductive type epitaxial layer, and the second trench is located between the first trench and the cell region; The shielded gate power transistor further includes: a second gate structure disposed in the second trench, the second gate structure surrounds the cell region and is connected end to end, and the source metal layer is electrically connected to the second gate structure.

4. The shielded gate power transistor according to claim 2, wherein: The potential at the start end of the first gate structure for being turned on is the same as the potential at the first source doping region for being turned on; or, a plurality of third trenches are provided in the cell region, and a control gate structure and a shield gate structure electrically isolated from each other are provided in the third trenches, and the shield gate structure is close to the bottom of the third trenches; The potential at the start end of the first gate structure for turning on is the same as the potential at the control gate structure for turning on.

5. The shielded gate power transistor according to claim 1, wherein: Also includes: The drain metal layer is located on the side of the first conductive type substrate facing away from the first conductive type epitaxial layer, and the potential of the first gate structure end for connection is the same as the potential of the drain metal layer for connection.

6. The shielded gate power transistor according to claim 5, wherein: The first conductive type epitaxial layer is provided with a fourth trench located in the terminal region, and the fourth trench surrounds the first trench; The shielded gate power transistor further includes: a third gate structure disposed in the fourth trench, the third gate structure surrounding the first trench and connected end to end, the potential for the third gate structure to be connected being the same as the potential for the drain metal layer to be connected.

7. The shielded gate power transistor according to claim 6, wherein: The first conductive type substrate has first conductive type ions, and along a direction close to the first conductive type substrate, a portion of the thickness of the first conductive type epitaxial layer is a body region, and the body region has second conductive type ions, and the electrical properties of the second conductive type ions are opposite to those of the first conductive type ions; The first conductive type epitaxial layer includes a second source doping region located on a side of the fourth trench away from the cell region, the second source doping region has first conductive type ions, and the second source doping region is superimposed on a surface of the body region of the terminal region facing away from the first conductive type substrate; The shielded gate power transistor further includes a drain metal layer disposed on the side of the first conductive type epitaxial layer facing away from the first conductive type substrate, and the drain metal layer is electrically connected to the second source doping region, the third gate structure, and an end of the first gate structure.

8. The shielded gate power transistor according to claim 1, wherein: A plurality of third trenches are provided in the cell region, wherein a control gate structure and a shielding gate structure electrically isolated from each other are provided in the third trenches, and the shielding gate structure is close to the bottom of the third trench; the depth of the third trench is less than or equal to the depth of the first trench.

9. A method for preparing a shielded gate power transistor, characterized in that: include: Providing a first conductive type epitaxial layer, wherein the first conductive type epitaxial layer is stacked on one side of a first conductive type substrate, and the first conductive type epitaxial layer is provided with a cell region and a terminal region surrounding the cell region; A first groove is provided in the terminal region that spirally surrounds the cell region; A first gate structure is provided in the first trench, the first gate structure surrounding the cell region, the first gate structure including a first gate structure start end close to the cell region and a first gate structure end away from the cell region, and a potential for connection at the first gate structure start end is lower than a potential for connection at the first gate structure end end; The first gate structure includes a first gate and a first dielectric layer located between the first gate and the first conductive type epitaxial layer, wherein the first dielectric layer is used to electrically isolate the first gate and the first conductive type epitaxial layer, wherein the first dielectric layer is located on the sidewalls of the first trench and the bottom of the first trench.

10. The method for preparing a shielded gate power transistor according to claim 9, wherein: Also includes: A second trench is provided in the first conductive type epitaxial layer; wherein the second trench is located in the terminal region, and the second trench is located between the first trench and the cell region; A second gate structure is disposed in the second trench; wherein the second gate structure surrounds the cell region and is connected end to end.

11. The method for preparing a shielded gate power transistor according to claim 9 or 10, wherein: The first conductive type substrate has first conductive type ions, and the method further includes: doping a portion of the thickness of the first conductive type epitaxial layer with second conductive type ions in a direction close to the first conductive type substrate to form a body region, wherein the second conductive type ions have opposite electrical properties to the first conductive type ions; The first conductive type ions are doped into the first conductive type epitaxial layer on the side of the body region facing away from the first conductive type substrate to form a first source doping region; wherein the first source doping region is located in the cell region.

12. The method for preparing a shielded gate power transistor according to claim 11, wherein: Also includes: A first gate start electrode electrically connected to the start end of the first gate structure is provided on the side of the first conductive type epitaxial layer facing away from the first conductive type substrate; wherein the potential for connecting the first gate start electrode is the same as the potential for connecting the first source doping region; Alternatively, a plurality of third grooves are provided in the cell region; A control gate structure and a shield gate structure electrically isolated from each other are provided in the third trench, and the shield gate structure is close to the bottom of the third trench; the potential used for connecting the first gate starting electrode is the same as the potential used for connecting the control gate structure.

13. The method for preparing a shielded gate power transistor according to claim 11, wherein: Also includes A source metal layer is arranged on the side of the first conductive type epitaxial layer facing away from the first conductive type substrate; wherein the source metal layer is electrically connected to the first source doping region; or, the second gate structure is arranged in the second trench, and a source metal layer is arranged on the side of the first conductive type epitaxial layer facing away from the first conductive type substrate, and the source metal layer is electrically connected to the first source doping region and the second gate structure.

14. The method for preparing a shielded gate power transistor according to claim 9, wherein: Also includes: A fourth trench is provided in the first conductive type epitaxial layer; wherein the fourth trench is located in the terminal region and surrounds the first trench; A third gate structure is disposed in the fourth trench; wherein the third gate structure surrounds the first trench and is connected end to end.

15. The method for preparing a shielded gate power transistor according to claim 14, wherein: The first conductive type substrate has first conductive type ions, and the method further includes: doping a portion of the thickness of the first conductive type epitaxial layer with second conductive type ions in a direction close to the first conductive type substrate to form a body region, wherein the second conductive type ions have opposite electrical properties to the first conductive type ions; The first conductive type ions are doped on a side of the third gate structure away from the cell region to form a second source doping region; wherein the second source doping region is located on a side of the body region facing away from the first conductive type substrate.

16. The method for preparing a shielded gate power transistor according to claim 15, wherein: Also includes: A drain metal layer is provided on the side of the first conductive type epitaxial layer facing away from the first conductive type substrate; wherein the drain metal layer is electrically connected to the second source doping region, the third gate structure and an end of the first gate structure.

17. The method for preparing a shielded gate power transistor according to claim 16, wherein: Also includes: A drain metal layer is provided on a surface of the first conductive type substrate facing away from the first conductive type epitaxial layer.

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