Micro-LED device based on photoelectric isolation and preparation method thereof

Abstract

The present invention discloses a Micro-LED device based on photoelectric isolation and a method for preparing the same. The Micro-LED device comprises, arranged in order from bottom to top, a substrate, an N-type semiconductor layer, a multi-quantum well layer, a P-type semiconductor layer, and electrodes. The multi-quantum well layer comprises several separately arranged multi-quantum well structures, the P-type semiconductor layer comprises several P-type semiconductor structures located on the multi-quantum well structures, the multi-quantum well structures are further provided with an isolation layer formed on the sidewalls of the P-type semiconductor structures, the isolation layer and the sidewalls of the multi-quantum well structures are provided with a reflective layer, and the electrodes comprise an N-electrode electrically connected to the N-type semiconductor layer and a P-electrode electrically connected to the P-type semiconductor structure. By introducing the isolation layer and the reflective layer, the Micro-LED device of the present invention can achieve electrical and optical isolation of the device, thereby improving the device's luminous efficiency and display contrast and reducing optical crosstalk.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor display technology, and specifically relates to a Micro-LED device based on photoelectric isolation and a preparation method thereof. Background Art

[0002] Existing methods for fabricating Micro-LED devices utilize a micro-etching process based on conventional LEDs to produce micron-sized LED micro-light-emitting devices. However, during the fabrication of these Micro-LED devices, the etching process creates numerous sidewall damage and dangling bonds. These damages result in a high density of defect levels at the edge of the Micro-LED device, while dangling bonds act as leakage paths for charge carriers, significantly limiting the device's ability to achieve optimal optoelectronic properties. Furthermore, conventionally fabricated Micro-LED devices experience significant optical crosstalk between adjacent Micro-LED devices, severely impacting the device's micro-display performance. For example, the emission of a single Micro-LED pixel can cause reflections from the sidewalls of adjacent Micro-LED pixels. When micro-displays require a black surround around the illuminated pixel to enhance contrast, this optical crosstalk significantly reduces the display quality. Furthermore, optical crosstalk can cause light transmission dispersion, significantly reducing the brightness of the Micro-LED device. If used in traffic light signals, strong sunlight can severely affect the device, potentially leading to driver errors and compromising safety.

[0003] To improve the brightness and contrast of Micro-LED devices, it is necessary to continuously enhance their luminous efficiency and reduce optical crosstalk between adjacent Micro-LED devices. Traditional etching methods are particularly damaging to Micro-LED devices. As the size of Micro-LED devices decreases, sidewall damage will significantly reduce the electro-optical conversion efficiency of the entire light-emitting array, and will also place higher demands on device yield and process reliability.

[0004] Therefore, in response to the above technical problems, it is necessary to provide a Micro-LED device based on photoelectric isolation and a preparation method thereof. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a Micro-LED device based on photoelectric isolation and a preparation method thereof.

[0006] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:

[0007] A Micro-LED device based on photoelectric isolation includes a substrate, an N-type semiconductor layer, a multi-quantum well layer, a P-type semiconductor layer, and electrodes arranged in sequence from bottom to top. The multi-quantum well layer includes several separately arranged multi-quantum well structures. The P-type semiconductor layer includes several P-type semiconductor structures located on the multi-quantum well structure. The multi-quantum well structure is also provided with an isolation layer formed on the sidewall of the P-type semiconductor structure. A reflective layer is provided on the isolation layer and the sidewall of the multi-quantum well structure. The electrodes include an N-electrode electrically connected to the N-type semiconductor layer and a P-electrode electrically connected to the P-type semiconductor structure.

[0008] In one embodiment, the height of the isolation layer is equal to the height of the P-type semiconductor structure; and / or the sidewall of the isolation layer is flush with the sidewall of the P-type semiconductor structure.

[0009] In one embodiment, the reflective layer at least covers the isolation layer and the sidewalls of the multi-quantum well structure, and the height of the reflective layer is greater than or equal to the sum of the height of the isolation layer and the height of the multi-quantum well structure.

[0010] In one embodiment, N steps are formed on the N-type semiconductor layer, and the N electrode is located on the N step; the reflective layer is also formed on the surface and sidewall of the N step, and the height of the reflective layer is equal to the sum of the height of the isolation layer, the height of the multi-quantum well structure and the depth of the N step.

[0011] In one embodiment, a current diffusion layer is formed on the top surface of the P-type semiconductor structure, a P-electrode is formed on the current diffusion layer, and the P-electrode is electrically connected to the P-type semiconductor structure through the current diffusion layer.

[0012] In one embodiment, the current spreading layer is further formed on the top surfaces of the isolation layer and the reflective layer and on all or part of the sidewalls of the reflective layer.

[0013] In one embodiment, the substrate is a sapphire substrate; and / or,

[0014] The N-type semiconductor layer is an N-type GaN layer; and / or,

[0015] The P-type semiconductor layer is a P-type GaN layer, and the P-type semiconductor structure is a P-type GaN structure; and / or,

[0016] The multi-quantum well layer is an InGaN / GaN multi-quantum well layer; and / or,

[0017] The isolation layer is H + an ion barrier; and / or,

[0018] A buffer layer is formed between the substrate and the N-type semiconductor layer.

[0019] Another embodiment of the present invention provides a technical solution as follows:

[0020] A method for preparing a Micro-LED device based on photoelectric isolation, the method comprising:

[0021] providing a substrate;

[0022] epitaxially growing an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer on the substrate in sequence;

[0023] Ion implantation is performed on the non-luminescent region of the P-type semiconductor layer to form a plurality of ion implantation regions;

[0024] Etching a portion of the ion implantation region and the multi-quantum well layer thereunder to form a plurality of separately arranged multi-quantum well structures, and a P-type semiconductor structure and an isolation layer thereon;

[0025] forming a reflective layer on the sidewalls of the isolation layer and the multi-quantum well structure;

[0026] A P-electrode is formed on the P-type semiconductor structure, and an N-electrode is formed on the N-type semiconductor layer.

[0027] In one embodiment, the ions implanted in the ion implantation step are H + ion.

[0028] In one embodiment, the preparation method further comprises:

[0029] forming a current diffusion layer on the top surfaces of the P-type semiconductor structure, the isolation layer, and the reflective layer, and forming a P electrode on the current diffusion layer; and / or,

[0030] A portion of the N-type semiconductor layer is etched to form an N-step, and an N-electrode is formed on the N-step.

[0031] The present invention has the following beneficial effects:

[0032] The Micro-LED device in the present invention can achieve electrical isolation and optical isolation of the device by introducing an isolation layer and a reflective layer, thereby improving the luminous efficiency and display contrast of the device and reducing the optical crosstalk effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1A schematic structural diagram of a Micro-LED device in a specific embodiment of the present invention;

[0035] Figure 2 Schematic diagram of a process for preparing a Micro-LED device according to a specific embodiment of the present invention;

[0036] Figures 3a to 3f FIG. 4 is a process flow chart of a Micro-LED device in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0038] The present invention discloses a Micro-LED device based on photoelectric isolation. The Micro-LED device includes a substrate, an N-type semiconductor layer, a multi-quantum well layer, a P-type semiconductor layer and electrodes arranged in sequence from bottom to top. The multi-quantum well layer includes several separately arranged multi-quantum well structures. The P-type semiconductor layer includes several P-type semiconductor structures located on the multi-quantum well structure. The multi-quantum well structure is also provided with an isolation layer formed on the sidewall of the P-type semiconductor structure. A reflective layer is provided on the isolation layer and the sidewall of the multi-quantum well structure. The electrodes include an N-electrode electrically connected to the N-type semiconductor layer and a P-electrode electrically connected to the P-type semiconductor structure.

[0039] The present invention also discloses a method for preparing a Micro-LED device based on photoelectric isolation, comprising:

[0040] providing a substrate;

[0041] epitaxially growing an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer on the substrate in sequence;

[0042] Ion implantation is performed on the non-luminescent region of the P-type semiconductor layer to form a plurality of ion implantation regions;

[0043] Etching a portion of the ion implantation region and the multi-quantum well layer thereunder to form a plurality of separately arranged multi-quantum well structures, and a P-type semiconductor structure and an isolation layer thereon;

[0044] forming a reflective layer on the sidewalls of the isolation layer and the multi-quantum well structure;

[0045] A P-electrode is formed on the P-type semiconductor structure, and an N-electrode is formed on the N-type semiconductor layer.

[0046] The Micro-LED device and the preparation method thereof of the present invention are further described below with reference to specific embodiments.

[0047] Ginseng Figure 1 As shown, a Micro-LED device in a specific embodiment of the present invention includes a substrate 10, an N-type semiconductor layer 20, a multi-quantum well layer 30, a P-type semiconductor layer 40 and electrodes arranged in sequence from bottom to top.

[0048] Specifically, the multi-quantum well layer 30 includes a plurality of separately arranged multi-quantum well structures 31, the P-type semiconductor layer 40 includes a plurality of P-type semiconductor structures 41 located on the multi-quantum well structures, and the multi-quantum well structures 31 are further provided with an isolation layer 60 formed on the sidewalls of the P-type semiconductor structures. A reflective layer 70 is provided on the isolation layer 60 and the sidewalls of the multi-quantum well structures 31. The electrodes include an N-electrode 51 electrically connected to the N-type semiconductor layer 20 and a P-electrode 52 electrically connected to the P-type semiconductor structures 31.

[0049] Preferably, in this embodiment, the height of the isolation layer 60 is equal to the height of the P-type semiconductor structure 41 , and the sidewall of the isolation layer 60 is flush with the sidewall of the P-type semiconductor structure 41 .

[0050] Furthermore, in this embodiment, an N-step is etched on the N-type semiconductor layer 20, and the N-electrode 51 is located on the N-step. The reflective layer 70 covers the isolation layer 60 and the sidewalls of the multi-quantum well structure 31, and is also formed on the surface and sidewalls of the N-step. In the area outside the N-step, the height of the reflective layer is equal to the sum of the height of the isolation layer and the height of the multi-quantum well structure. In the N-step area, the height of the reflective layer is equal to the sum of the height of the isolation layer, the height of the multi-quantum well structure, and the depth of the N-step.

[0051] In addition, a current diffusion layer 80 is formed on the top surface of the P-type semiconductor structure 41. A P-electrode 52 is formed on the current diffusion layer. The P-electrode 52 is electrically connected to the P-type semiconductor structure 41 through the current diffusion layer 80. Preferably, in this embodiment, the current diffusion layer 80 is formed not only on the top surface of the P-type semiconductor structure 41, but also on the top surfaces of the isolation layer and the reflective layer, and on the sidewalls of the reflective layer.

[0052] Preferably, the substrate in this embodiment is a sapphire substrate, the N-type semiconductor layer is an N-type GaN layer, the P-type semiconductor layer is a P-type GaN layer, the P-type semiconductor structure is a P-type GaN structure, the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, and the isolation layer is H + The ion isolation layer and the current diffusion layer are ITO current diffusion layers, and the electrodes are Cr / Al / Ti / Au metal electrodes.

[0053] Preferably, a buffer layer 90 is formed between the substrate and the N-type semiconductor layer in this embodiment. The buffer layer 90 may be a non-doped GaN buffer layer or the like.

[0054] Of course, in other embodiments, the materials for the substrate, N-type semiconductor layer, P-type semiconductor layer, multi-quantum well layer, current diffusion layer, electrode, and buffer layer may also be other materials known in the art. For example, the substrate may be a silicon substrate or a silicon carbide substrate, the P-type semiconductor layer / N-type semiconductor layer may be P-type / N-type doped GaAs, InP, or InGaAsP, and the current diffusion layer may be an IZO current diffusion layer, etc., and these will not be described in detail here.

[0055] Ginseng Figure 2 and combined Figure 3a to Figure 3f As shown, the method for preparing the Micro-LED device in this embodiment includes the following steps:

[0056] Ginseng Figure 3a As shown, a substrate 10 is provided, and a buffer layer 90, an N-type semiconductor layer 20, a multi-quantum well layer 30 and a P-type semiconductor layer 40 are epitaxially grown in sequence on the substrate, wherein the substrate is a sapphire substrate, the buffer layer is an undoped GaN buffer layer, the N-type semiconductor layer is an N-type GaN layer, the P-type semiconductor layer is a P-type GaN layer, and the multi-quantum well layer is an InGaN / GaN multi-quantum well layer.

[0057] Ginseng Figure 3b As shown, the non-light emitting area of ​​the P-type semiconductor layer 40 is subjected to H + Ion implantation is performed to form a plurality of ion implantation regions 401 .

[0058] Ions are implanted into the P-type semiconductor layer 40 through an implantation mask to form a high-resistance P-type isolation region. The P-type semiconductor layer 40 is isolated by the ion implantation region to form a plurality of P-type semiconductor structures 41 .

[0059] Ginseng Figure 3c As shown, a dry etching process is used to etch part of the ion implantation region and the multi-quantum well layer thereunder, thereby forming a plurality of separately arranged multi-quantum well structures 31 and a P-type semiconductor structure 41 and an isolation layer 60 thereon.

[0060] In addition, a portion of the N-type semiconductor layer 20 is etched to form an N-step 201 .

[0061] Ginseng Figure 3d As shown, a reflective layer 70 is formed on the sidewalls of the isolation layer 60 and the multi-quantum well structure 31 , and on a portion of the surface and sidewalls of the N-step 201 .

[0062] The reflective layer can be prepared by a sputtering process, an evaporation process, an electroplating process or the like.

[0063] Ginseng Figure 3e As shown, a current diffusion layer 80 is deposited on the top surfaces of the P-type semiconductor structure 41 , the isolation layer 60 , and the reflective layer 70 , and on the sidewalls of the reflective layer 60 . The current diffusion layer is an ITO current diffusion layer.

[0064] Ginseng Figure 3f As shown, a P electrode is formed on the current diffusion layer 80 , and an N electrode is formed on the N step 201 .

[0065] Preferably, in this embodiment, annealing is also performed on the ITO / P-GaN contact and the P / N electrodes.

[0066] The above process can produce a Micro-LED device with high energy efficiency and low optical crosstalk, which can be used in various terminal display fields such as mobile phones, computers and wearable devices.

[0067] In this embodiment, an ion implantation method is used to inject ions into the non-luminous area to make it present a high resistance state, thereby achieving electrical isolation of the Micro-LED device; a sidewall structure is introduced into the ion implantation area using a dry etching process, and a reflective layer is coated on the sidewall to reduce the optical crosstalk effect of adjacent light-emitting units and improve the display contrast of the device.

[0068] Ion implantation can be an effective method to achieve high-light-efficiency Micro-LED devices. By injecting high-energy ions into non-luminous areas, the lattice of the semiconductor material can be destroyed, significantly reducing the electrical properties of the material. When its conductivity is reduced to a certain range, the material in the implanted area is close to being electrically insulating, and can thus serve as an electrical isolation area between adjacent light-emitting units. The preparation of Micro-LED devices through ion implantation isolation also has the important feature of being compatible with mainstream silicon processes, which has significant advantages in improving the yield and reducing the cost of Micro-LED devices. As a preparation method with high repeatability, planarization, and large-scale batch production, ion implantation is conducive to simplifying the preparation process of Micro-LED devices. It is worth mentioning that ion implantation greatly reduces the probability of non-radiative recombination of carriers. On this basis, by further adjusting the light reflective structure of the device sidewalls, the impact of optical crosstalk on the display effect can be effectively reduced.

[0069] It can be seen from the above technical solutions that the present invention has the following advantages:

[0070] The Micro-LED device in the present invention can achieve electrical isolation and optical isolation of the device by introducing an isolation layer and a reflective layer, thereby improving the luminous efficiency and display contrast of the device and reducing the optical crosstalk effect.

[0071] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0072] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A method for preparing a Micro-LED device based on photoelectric isolation, characterized in that: The preparation method comprises: providing a substrate; epitaxially growing an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer on the substrate in sequence; Ion implantation is performed on the non-luminescent region of the P-type semiconductor layer to form a plurality of ion implantation regions; Etching a portion of the ion implantation region and the multi-quantum well layer thereunder to form a plurality of separately arranged multi-quantum well structures, and a P-type semiconductor structure and an isolation layer thereon; forming a reflective layer on the sidewalls of the isolation layer and the multi-quantum well structure; A P-electrode is formed on the P-type semiconductor structure, and an N-electrode is formed on the N-type semiconductor layer.

2. The preparation method according to claim 1, characterized in that The ions implanted in the ion implantation step are H + ion.

3. The preparation method according to claim 1, characterized in that The preparation method further comprises: forming a current diffusion layer on the top surface of the P-type semiconductor structure, and forming a P electrode on the current diffusion layer; and / or, A portion of the N-type semiconductor layer is etched to form an N-step, and an N-electrode is formed on the N-step.

4. A Micro-LED device based on photoelectric isolation prepared by the preparation method of claim 1, characterized in that: The Micro-LED device includes a substrate, an N-type semiconductor layer, a multi-quantum well layer, a P-type semiconductor layer and an electrode arranged in sequence from bottom to top. The multi-quantum well layer includes several separately arranged multi-quantum well structures. The P-type semiconductor layer includes several P-type semiconductor structures located on the multi-quantum well structure. The multi-quantum well structure is also provided with an isolation layer formed on the sidewall of the P-type semiconductor structure. A reflective layer is provided on the isolation layer and the sidewall of the multi-quantum well structure. The electrode includes an N-electrode electrically connected to the N-type semiconductor layer and a P-electrode electrically connected to the P-type semiconductor structure.

5. The Micro-LED device based on photoelectric isolation according to claim 4, characterized in that: The height of the isolation layer is equal to the height of the P-type semiconductor structure; and / or the sidewall of the isolation layer is flush with the sidewall of the P-type semiconductor structure.

6. The Micro-LED device based on photoelectric isolation according to claim 4, characterized in that: The reflective layer at least covers the isolation layer and the sidewalls of the multi-quantum well structure. The height of the reflective layer is greater than or equal to the sum of the height of the isolation layer and the height of the multi-quantum well structure.

7. The Micro-LED device based on photoelectric isolation according to claim 6, characterized in that: N steps are formed on the N-type semiconductor layer, and the N electrode is located on the N steps; the reflective layer is also formed on the surface and sidewalls of the N steps, and the height of the reflective layer is equal to the sum of the height of the isolation layer, the height of the multi-quantum well structure and the depth of the N steps.

8. The Micro-LED device based on photoelectric isolation according to claim 4, characterized in that: A current diffusion layer is formed on the top surface of the P-type semiconductor structure, a P-electrode is formed on the current diffusion layer, and the P-electrode is electrically connected to the P-type semiconductor structure through the current diffusion layer.

9. The Micro-LED device based on photoelectric isolation according to claim 4, characterized in that: The substrate is a sapphire substrate; and / or, The N-type semiconductor layer is an N-type GaN layer; and / or, The P-type semiconductor layer is a P-type GaN layer, and the P-type semiconductor structure is a P-type GaN structure; and / or, The multi-quantum well layer is an InGaN / GaN multi-quantum well layer; and / or, The isolation layer is H + an ion barrier; and / or, A buffer layer is formed between the substrate and the N-type semiconductor layer.

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