element substrate

Abstract

This disclosure relates to a component substrate. A switch is configured to switch the connection between a second terminal of an input data signal and a memory control signal of a memory element based on a switching signal included in a data signal. During writing to the memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for writing to the memory element is input via the second terminal.

Description

Technical Field

[0001] This invention relates to component substrates. Background Technology

[0002] Polysilicon fuse memory is known as an OTP (One-Time Programmable) ROM configured to record specific information such as product ID and setting parameters in a head mounted on a printed element substrate on a conventional liquid discharge head. Polysilicon fuse memory uses polysilicon to form transistor gate wiring, resistive elements, etc., and is advantageous because the memory can be formed on the printed element substrate without adding new steps to existing semiconductor manufacturing processes. As a conventional technique using a write circuit to write to the polysilicon fuse memory, for example, there is Japanese Patent Publication No. 2006-15736.

[0003] In recent years, antifuse memory, as described in Japanese Patent Publication No. 2006-15736, has emerged as a memory that can make memory modules smaller than polysilicon fuse memory and can be produced using conventional semiconductor manufacturing processes without adding new steps. The gate oxide film of a MOS transistor is formed into a memory, an overvoltage is applied to the gate oxide film to cause a short circuit, and the change in characteristics is used as the memory.

[0004] In Japanese Patent Publication No. 2006-15736, during the write operation of a polysilicon fuse memory, a serial data signal is synchronously input to a shift register along with a clock signal, and then the serial data signal is held in a latch circuit according to a latch signal. This latch signal serves as a control signal for the write operation. Initially, the latch signal was used to keep the data in the shift register in the latch circuit. Therefore, the latch signal is usually not input at a high frequency. Summary of the Invention

[0005] The present invention provides a technique that can prevent circuit operation errors and reliably write data to memory elements in a short time without adding terminals configured to input signals dedicated to writing to memory elements.

[0006] The present invention provides, in a first aspect, a component substrate comprising: a plurality of printed elements; a plurality of memory elements; a first terminal for receiving a clock signal; a second terminal for receiving a data signal; a control data supply unit configured to receive the data signal input from the second terminal synchronously with the clock signal input from the first terminal, and to output selection signals for selecting groups and blocks of memory elements and printed elements; and a switch configured to switch the connection between the second terminal and memory control signals of the memory elements according to a switching signal included in the data signal, wherein, during writing to the memory elements, the switching signal switches such that the switch connects the second terminal and the memory control signals of the memory elements, and a pulse signal for writing to the memory elements is input via the second terminal.

[0007] In a second aspect, the present invention provides a component substrate comprising: a plurality of sets of printed elements; a plurality of sets of memory elements; a first terminal for receiving a clock signal; a second terminal for receiving a data signal; a third terminal for receiving a drive signal for driving the printed elements; a control data supply unit configured to receive the data signal input from the second terminal synchronously with the clock signal input from the first terminal, and to output selection signals for selecting groups and blocks of memory elements and printed elements; and a selection unit configured to select based on a switching signal included in the data signal, to connect one of the clock signal input from the first terminal and the drive signal input from the third terminal to a printed element control signal for controlling the driving of the printed elements and a memory control signal for controlling the memory elements, wherein when driving the printed elements, the switching signal switches to cause the selection unit to select the drive signal input from the third terminal, and when driving the memory elements, the switching signal switches to cause the selection unit to select the clock signal input from the first terminal, and a pulse signal for writing to the memory elements is input via the first terminal.

[0008] In a third aspect, the present invention provides a component substrate comprising: a plurality of printed elements; a plurality of memory elements; a first terminal for receiving a clock signal; a second terminal for receiving a data signal; a control data supply unit configured to receive the data signal input from the second terminal synchronously with the clock signal input from the first terminal, and to output selection signals for selecting groups and blocks of memory elements and printed elements; and a switch configured to switch the connection between the first terminal and memory control signals of memory elements according to a switching signal included in the data signal, wherein, during writing to memory elements, the switching signal switches such that the switch connects the first terminal and the memory control signals of memory elements, and a pulse signal for writing to memory elements is input via the first terminal.

[0009] According to the present invention, circuit operation errors can be prevented and data can be reliably written to memory elements in a short time without adding terminals configured to input signals dedicated to writing to memory elements.

[0010] Other features of the invention will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a view showing a portion of the configuration of the discharge module, memory module, and drive circuit mounted on the component substrate 11 according to the first embodiment;

[0012] Figures 2A to 2D It is a view used to explain the circuit configuration of a printing device, a printhead unit, a printhead, and a memory module that can include a printhead unit according to an embodiment;

[0013] Figure 3A This is a timing diagram used to explain the operation of signals input from the printing device to the head substrate and the driving of the emission module according to the first embodiment;

[0014] Figure 3B This is a timing diagram used to explain the signals input from the printing device to the head substrate and the operations when writing to the memory module according to the first embodiment;

[0015] Figure 3C This is a timing diagram used to explain the signals input from the printing device to the head substrate and the operations when writing to the memory module according to the second embodiment;

[0016] Figure 3D This is a timing diagram used to explain the signals input from the printing device to the head substrate and the operations when writing to the memory module according to the third embodiment;

[0017] Figure 4 This is a flowchart explaining the process when the printing device according to the first embodiment drives the emission module;

[0018] Figure 5 This is a flowchart for explaining the write process of the memory module by the printing device according to the first embodiment;

[0019] Figure 6 This is a view showing a portion of the configuration of the discharge module, memory module, and drive circuit mounted on the component substrate 11a according to the second embodiment;

[0020] Figure 7 This is a flowchart used to explain the process when the printing device according to the second embodiment drives the emission module;

[0021] Figure 8This is a flowchart for explaining the write process of the memory module by the printing device according to the second embodiment;

[0022] Figure 9 This is a block diagram used to explain an overview of the control configuration for controlling a printing device according to an embodiment;

[0023] Figure 10 This is a view showing a portion of the configuration of the discharge module, memory module, and drive circuit mounted on the component substrate 11b according to the third embodiment;

[0024] Figure 11 This is a flowchart explaining the process when the printing device according to the third embodiment drives the emission module; and

[0025] Figure 12 This is a flowchart for explaining the write process of the memory module by the printing device according to the third embodiment. Detailed Implementation

[0026] In the following, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but the invention is not limited to requiring all such features, and multiple such features can be appropriately combined. Furthermore, in the drawings, the same reference numerals are given the same or similar configuration, and redundant descriptions are omitted.

[0027] Because polysilicon fuse memory uses the principle of writing by disconnecting the resistor body, it can be written by applying a DC voltage only once within a predetermined time. Therefore, even if a latch signal is used as the control signal for the write operation, no problem is raised.

[0028] On the other hand, antifuse memories use the principle of writing by breaking the gate oxide film. Therefore, writing is not done using DC voltage, and multiple pulse waveforms are applied to intermittently apply the voltage. Therefore, to write within a short time, a high-frequency pulse waveform is required. Therefore, if a latch signal is used as the control signal for writing to the antifuse memory, the latch circuit is activated at a high frequency. This may lead to operational errors in the latch circuit and potentially retain incorrect data. To prevent this, a dedicated control signal for writing to the antifuse memory can be provided. However, the addition of terminals for this signal increases the number of terminals, resulting in an increase in the size of the printed element substrate.

[0029] According to the following embodiments, circuit operation errors can be prevented and data can be reliably written to memory elements in a short time without adding terminals configured to input signals dedicated to writing to memory elements.

[0030] Note that in the following description of the embodiments, "printing" includes not only the formation of important information such as characters or graphic patterns, but also the formation of images, designs, or patterns on the printing medium and the processing of the printing medium in a broader sense, regardless of whether the information is important or not, and regardless of whether the information has become explicit enough to allow human visual perception. Furthermore, in this embodiment, it is assumed that the "printing medium" is a sheet of paper, but it could be fabric, plastic film, etc.

[0031] Figure 2A This is a schematic perspective view illustrating a printing apparatus 1000 capable of including a printhead unit 20 according to an embodiment of the present invention.

[0032] like Figure 2A As shown, the lead screw 5004 is interlocked with the forward and reverse rotation of the drive motor 5013, and rotates via drive force transmission gears 5008 and 5009. The printhead unit 20 can be placed on the carriage HC. The carriage HC includes a pin (not shown) configured to engage with the helical groove 5005 of the lead screw 5004, and reciprocates in the directions of arrows a and b as the lead screw 5004 rotates.

[0033] Figure 2B This is a perspective view showing an example of a printhead unit 20 including a printhead 10 according to an embodiment.

[0034] The printhead unit 20 includes a printhead 10 and a storage unit 24 for storing printing material (ink) to be supplied to the printhead 10, and these are integrated to form a cartridge. The printhead 10 is positioned... Figure 2A The surface facing the printing medium P is shown. Note that these do not always need to be integrated and may also be in a form that allows the storage unit 24 to be detached. Additionally, the printhead unit 20 includes a belt member 22. The belt member 22 includes terminals configured to supply power to the printhead 10 and to send / receive power and various signals to / from the printing device body via contacts 23.

[0035] Figure 2C This is a schematic perspective view of the printhead 10 according to an embodiment.

[0036] The printhead 10, which acts as a discharge head, includes a print element substrate 11 and a channel forming member 120. The print element substrate 11 is provided with an array of multiple thermal actuation units 117 configured to apply heat generated by an electrothermal transducer to the printing material. The channel forming member 120 also acts as an orifice member, wherein an array of multiple orifices 121 configured to discharge printing material is provided corresponding to the thermal actuation units 117. Power and signals are transmitted from the printing device body to the print element substrate 11 via a belt member 22, causing heat generated by driving the electrothermal transducer to be applied to the printing material (liquid; ink) via the thermal actuation units 117, and the printing material is discharged from the orifices 121.

[0037] [First Embodiment]

[0038] Next, we will refer to Figure 1 Figures 3 to 3 illustrate the circuit configuration of the emission module 204 and the memory module 206 mounted on a printed element substrate (hereinafter also simply referred to as "substrate") that serves as a semiconductor substrate, according to a first embodiment of the present invention.

[0039] Figure 1 This is a view showing a portion of the circuit configuration of a printed element substrate 11 according to a first embodiment of the present invention. Note that the printed element substrate 11 is used as... Figure 2C The printed element substrate 11 shown above.

[0040] The substrate 11 includes multiple sets of discharge modules 204 and multiple sets of memory modules 206. Discharge modules 204 include a printing element Rh (e.g., an electrothermal transducer), a driving element (transistor) MD1 configured to drive the printing element Rh, and an AND circuit AND1 for selecting the printing element. When the printing element Rh is driven, printing material, such as ink, is discharged from the aperture 121, thereby performing printing.

[0041] Furthermore, memory module 206 includes an antifuse element AF that acts as a memory element, a driving element (transistor) MD2 configured to write information to the antifuse element AF, and an AND circuit AND2 for selecting the memory element. When an overvoltage is supplied, the antifuse element AF statically retains the information. That is, the antifuse element AF functions as a memory that can only be programmed once.

[0042] The driving of the printing element Rh or the antifuse element AF is controlled based on the logic data signal output from the control data supply circuit 201, which serves as a signal supply circuit. The control data supply circuit 201 includes a shift register (S / R) 239, a latch (LT) circuit 238, a decoder 237, etc. Logic data signals such as clock signal CLK, data signal DATA, and latch signal LT are input to the control data supply circuit 201 via the main body or host PC (not shown) of the printing device 1000. In addition, a first power supply voltage VDD (e.g., 3 to 5V) is supplied as a logic power supply voltage to AND circuits AND1, AND circuits AND2, and the control data supply circuit 201. Here, when selecting the printing element and the memory element, the data signal includes serial data for selecting the discharge module 204 or the memory module 206, which will be described later, and specific bits of the data (e.g., the first bit of the serial data) act as a switching signal 205, which will be described later.

[0043] Here, the control data supply circuit 201 can be time-division driven to control the operation of each emission module 204 and drive, for example, the printing element Rh in each of m groups comprising n emission modules 204. The control data supply circuit 201 outputs an m-bit group selection signal 202 and an n-bit block selection signal 203. Furthermore, the control data supply circuit 201 outputs at least one bit of a switching signal 205 for switching between the printing element and the memory element. Each emission module 204 receives at least one bit of the group selection signal 202, at least one bit of the block selection signal 203, at least one bit of the switching signal 205, and the printing element control signal HE (hot-on) 220, thereby driving the printing element Rh in a time-division manner.

[0044] Additionally, the control data supply circuit 201 can be time-division driven to control the operation of each memory module 206 and drive the antifuse element AF in each of, for example, groups y comprising x memory modules 206. Each memory module 206 receives at least one bit of each of the group selection signal 202, block selection signal 203, and switching signal 205 output from the control data supply circuit 201, as well as a memory control (ME) signal, thereby driving the antifuse element AF in a time-division manner. Here, the connection of the memory control signal 221 is controlled by the switch SW3 controlled by the switching signal 205.

[0045] In other words, when writing to memory module 206, switch SW3 is turned on, and the signal generated by memory write pulse generation unit 226 and input to data terminal 231 is input as memory control signal 221. On the other hand, when driving discharge module 204, switch SW3 is turned off by switching signal 205, and memory control signal 221 is not input to memory module 206. This operation will be described in detail later. In addition, the group selection signal 202, block selection signal 203, and switching signal 205 determine the memory module 206 including the antifuse element AF that should be written to based on signals CLK, DATA, LT, and HE.

[0046] Note that the emission module 204 and the memory module 206 are exclusively driven by the switching signal 205 and are configured such that all print elements Rh and all antifuse elements AF are not driven simultaneously. That is, the switching signal 205 is a signal used to switch the drive to drive one of the print elements Rh and the antifuse elements AF.

[0047] The corresponding group selection signal 202, block selection signal 203, switching signal 205, and print element control signal 220 are input to the AND circuit AND1 for print element selection. The drive element MD1 is set to the on state in response to the input signal, and the print element Rh, which is connected in series with the drive element MD1 for print element selection, is driven.

[0048] Here, as the driving element MD1 for the printed element, a DMOS transistor (double-diffused MOSFET) as a high breakdown voltage transistor is used, for example. If the antifuse element AF is used as a memory element, the drive current of the memory element is typically less than the drive current of the printed element, and the current drive capability of the DMOS transistor can also be very small. Therefore, the area of ​​the driving element MD2 for the memory element can be smaller than the area of ​​the driving element MD1 for the printed element. Additionally, as the AND circuit AND1 for selecting the printed element, a MOS transistor is used, for example. Here, the power supply voltage (VH, e.g., 24V) for driving the emission module is supplied from the VH terminal to the emission module 204, and the ground potential is defined as GNDH.

[0049] The corresponding group selection signal 202, block selection signal 203, switching signal 205, and memory control signal 221 are input to the AND circuit AND2 for memory element selection. The signal based on the input signal is output to the driving element MD2 for the memory element, and the on / off state of the driving element MD2 is switched. As the driving element MD2, for example, a DMOS transistor is used, similar to the driving element MD1 used for the printing element. Furthermore, as the AND circuit AND2 for memory element selection, a MOS transistor is used. Here, a memory write power supply voltage (e.g., 24V) for writing information to the antifuse element AF is supplied to the memory module 206 from the VID terminal, and the ground potential is defined as GNDH. Figure 1 As shown, the driving element MD1 for the printing element and the driving element MD2 for the memory element can be configured to be connected to the common GNDH terminal via a common ground wiring.

[0050] Note that an example is shown in which the memory write power supply circuit 228 and the emission module drive power supply circuit 229 are separate power lines. However, if the minimum voltage required to write to the antifuse element AF is equal to or less than the emission module drive voltage, the emission module drive power supply can be used in addition to, for example, a buck circuit.

[0051] Figure 2D This is a view showing an example of the circuit configuration of the memory module 206 used in the substrate 11.

[0052] Here, the AND circuit AND2 for selecting memory elements is represented by a NAND circuit and an inverter INV. The inverter INV is formed by a PMOS transistor MP1 and an NMOS transistor MN1, with MOSFETs used as transistors MP1 and MN1. The input signal Sig is input to the inverter INV, and the output signal Vg is output to the gate of the driving element MD2 for the memory element. Note that... Figure 2D The arrangement in relation to Figure 1 The driving element MD2 and the AND circuit AND2 are on opposite sides.

[0053] Before information is written, the antifuse element AF is used as, for example, the capacitor element Ca. Figure 2D The diagram shows the state before information is written to the antifuse element AF, which is represented as capacitor Ca. One terminal of capacitor Ca, which acts as antifuse element AF, is connected in series with the drive element MD2. Additionally, when writing / reading information, the memory write voltage VID is supplied to the other terminal of capacitor Ca.

[0054] The memory module 206 also includes a resistor element (having a resistance value Rp, and also simply referred to as "resistor element Rp") connected in parallel with the antifuse element AF. This prevents an overvoltage from being applied to the antifuse element AF and information from being incorrectly written to the antifuse element AF even though the drive element MD2 is in a non-conducting state.

[0055] The operation of the memory module 206 when information is written to the antifuse element AF will be described next. When information is written to the antifuse element AF, a low-level signal is input as a control signal Sig, thereby setting the drive element MD2 to the on state. Therefore, a memory write voltage VID is applied to the gate oxide film forming the antifuse element AF, and the gate oxide film is damaged, thereby writing information to the antifuse element AF. That is, before writing information, the antifuse element AF is a capacitive element Ca, and after writing, it changes to a resistive element.

[0056] The operation of memory module 206 when reading information from antifuse element AF will be described next.

[0057] When information is read from the antifuse element AF, a low-level signal is input as the control signal Sig, thereby setting the drive element MD2 to the on state. The resistance between VID and GNDH at this time is measured to distinguish whether information has been written to the antifuse element AF.

[0058] When reading Figure 1 When the antifuse element AF in the substrate shown is being read, after driving the selected memory module, as in the writing process, the memory read current generation unit 227 side is selected by switch SW1. Then, the voltage Vout supplying the constant current is measured, and the resistance between VID and GNDH is measured, thereby distinguishing whether information has been written to memory module 206.

[0059] The information to be written to the antifuse element AF is product-specific, such as chip ID or setting parameters. This is written using inspection equipment at the factory when the product is shipped. Alternatively, if the memory is installed in the product body and the user writes information after starting to use the product, a voltage corresponding to the high voltage VID is supplied from the product body.

[0060] Before describing the first embodiment, reference will be made below. Figure 9 The configuration of the control circuit of the printing device 1000 according to the first embodiment is described.

[0061] Figure 9 This is a block diagram that provides an overview of the control configuration for controlling a printing device 1000 according to an embodiment of the present invention.

[0062] The controller 900 controls the operation of the printing device 1000. The controller 900 includes a CPU 901, RAM 902, ROM 903, and an input / output interface (I / OI / F) 904. The CPU 901 reads the program stored in the ROM 903 and executes the program, thereby performing the processing shown in the flowchart described later. Furthermore, the CPU 901 controls various operations of the printing device 1000, such as printing processing. The input / output interface (I / OI / F) 904 is connected to a motor driver 905, which rotatably drives the aforementioned transport motor 5013. Note that the printing device 1000 according to the embodiment also includes an operation panel, various sensors, a paper feeding unit, etc., which will be omitted here. Figure 1 The functions of the unit of the printing device 1000 shown are implemented by the CPU 901 executing the program stored in the ROM 903.

[0063] The following will refer to Figure 1 , Figure 3A and Figure 4 Describe the operation when driving emission module 204.

[0064] Figure 3A This is a timing diagram used to explain the operation of signals input from the printing device 1000 to the head substrate 11 and the driving of the emission module 204 according to the first embodiment.

[0065] Figure 3A The CLK, DATA, LT, and HE values ​​shown are the input values ​​from the printing device 1000 to... Figure 1 The signals at the CLK terminal 230, data terminal 231, LT terminal 232, and HE terminal 233 of the printed element substrate 11. Ihe represents the current flowing to the discharge module 204, and Iaf represents the current flowing to the memory module 206. Figure 3A In this circuit, serial data (DATA) for selecting the print element is input synchronously to the shift register (S / R) 239 along with the CLK signal, and latched by the multi-stage latch (LT) circuit 238 according to the latch (LT) signal. When a drive signal is input from the HE terminal, current Ihe flows to the selected print element Rh.

[0066] Figure 4 This is a flowchart explaining the process when the printing device 1000 drives the emission module 204 according to the first embodiment. Note that the process shown in the flowchart is implemented by the CPU 901 executing a program stored in the ROM 903.

[0067] exist Figure 4In step S401, the printing device 1000 begins the drive operation of the emission module 204. At this time, in step S402, the emission module drive power supply circuit 229 is turned on before the signal is generated. Therefore, the emission module drive power supply voltage VH (e.g., 24V) is applied to the emission module 204 via the VH terminal 235. At this time, the GNDH terminal 236 is set to 0V. Note that step S402 can be performed simultaneously with the power-on of the printing device 1000, independent of the control of the CPU 901.

[0068] In the first embodiment, switch SW2 is switched to selectively connect the outputs of data generation unit 223 and memory write pulse generation unit 226 to data terminal 231. Therefore, in step S403, CPU 901 switches switch SW2 to the data generation unit 223 side. Thus, the data signal generated by data generation unit 223 is input to data terminal 231.

[0069] Next, the process proceeds to step S404, and CPU 901 causes CLK generation unit 222 to generate a CLK signal, and data generation unit 223 synchronously outputs a data signal for selectively driving emission module 204 in sync with the CLK signal. Here, the data signal is formed by 20 bits, including 15 groups of bits, 4 groups of selection signal bits, and 1 bit of switching signal 205, as shown below. Figure 3A As shown in the diagram, the group bit and block select bit are signals in which the bit corresponding to the emission module 204 to be driven is "1". When the emission module 204 is selected and driven, the switching signal 205 changes to a low level.

[0070] When the emission module 204 is driven, the switching signal 205 is supplied at a low level. The emission module 204 and the memory module 206 are driven exclusively by the switching signal 205, and all printing elements Rh and all antifuse elements AF are not driven simultaneously.

[0071] In step S405, CPU 901 outputs a data signal synchronized with the CLK signal input from CLK terminal 230 and serially inputs it to shift register (S / R) 239. When 20 bits of data are input to shift register 239 in this manner, the process proceeds to step S406. In step S406, CPU 901 supplies a latch (LT) signal generated by LT generation unit 224 from LT terminal 232. Therefore, the 20-bit data signal is held by latch circuit 238. Thus, the input serial signal is converted into a parallel signal. At this time, some data signal bits of the 20-bit data are output via decoder 237 as block select signal 203.

[0072] In the first embodiment, the 4-bit data used to select the block of the emission module 204 is decoded by the decoder 237 into a 16-bit block selection signal 203 and output. Additionally, the control data supply circuit 201 outputs a switching signal 205 based on the value of a switching bit included in the 20-bit data signal.

[0073] At this time, the switch SW3, which controls the connection between the memory control signal 221 and the data terminal 231, is turned off by the low-level switching signal 205 supplied from the control data supply circuit 201. Therefore, the memory control signal 221, which is to be input to the memory module 206, is set to the on state, and the memory control signal ME 221 is not input to the memory module 206.

[0074] The process proceeds to step S407, and CPU 901 inputs the HE (hot-on) signal generated by HE generation unit 225 from HE terminal 233. This HE signal is a print element control signal. Therefore, the corresponding group selection signal 202, block selection signal 203, switching signal 205, and print element control signal HE 220 are input to the AND circuit AND1 for the selected print element. Consequently, the drive element MD1 of the selected discharge module 204 is set to the ON state in response to the control signal HE 220, and the print element Rh connected in series with the drive element MD1 is energized and driven, with current Ihe flowing to the discharge module. The process proceeds to step S408, and CPU 901 determines, for example, whether printing one line has ended. If printing has not ended, the process returns to step S405 to perform the above-described process. If printing one line has ended, the process ends.

[0075] Note that in Figure 3A In parallel with the driving of the emission module 204, a CLK signal and a data signal are supplied for the next printing process. Thus, a signal for selecting the emission module 204 to be driven in the next column is input to the shift register 239. When the print element control signal HE 220 is input in this manner to end the driving of the emission module 204 and then the LT signal is input, the signal for selecting the emission module 204 to be driven in the next column is latched by the latch circuit 238. When the HE signal supplied from the control data supply circuit 201 is input again, the operation of driving the selected print element Rh and causing current Ihe to flow to the selected emission module 204 is repeated.

[0076] Next, we will refer to Figure 1 , Figure 3B and Figure 5 Describes the operation when driving memory module 206.

[0077] Figure 3BThis is a timing diagram used to explain the operation of signals input from the printing device 1000 to the head substrate 11 and the writing to the memory module 206 according to the first embodiment.

[0078] Figure 5 This is a flowchart explaining the write process of the printing device 1000 to the memory module 206 according to the first embodiment. Note that the process shown in the flowchart is implemented by the CPU 901 executing a program stored in the ROM 903.

[0079] First, in step S501, the printing device 1000 begins the write operation to the memory module 206. Next, the process proceeds to step S502, where the CPU 901 turns on the memory write power circuit 228 before signal generation and applies the memory write power supply voltage VID (e.g., 24V) to the memory module 206 via the VID terminal 234. Here, the GNDH terminal 236 is set to 0V. Note that step S502 can be performed simultaneously with the power-on of the printing device 1000, independent of the control of the CPU 901.

[0080] Next, the process proceeds to step S503, and CPU 901 connects switch SW2 to the data generation unit 223 to input the generated data signal to data terminal 231. Next, the process proceeds to step S504, and CPU 901 causes CLK generation unit 222 to generate a CLK signal, causes data generation unit 223 to generate a data signal, and sets switching signal 205 to a high level. In step S505, CPU 901 outputs a data signal generated by data generation unit 223 to drive memory module 206, which is synchronized with the CLK signal. Here, the data signal is formed by 20 bits, including 15 block select bits, 4 block select bits, and a 1-bit switching signal 205, as shown below. Figure 3B As shown in the diagram. The configuration of the transmission bits is the same as in the drive of the discharge module 204. In the group select bit and block select bit, the bit corresponding to the memory module 206 to be written to changes to a high level. At this time, due to the writing to the memory module 206, the switching signal 205 is at a high level.

[0081] Here, although the switching signal 205 is supplied at a high level when writing to the memory module 206, all printing elements Rh and all antifuse elements AF are not driven simultaneously because the emission module 204 and the memory module 206 are driven exclusively by the switching signal 205.

[0082] The process proceeds to step S506, and the CPU 901 outputs the LT signal generated by the LT generation unit 224 via the LT terminal 232. Therefore, the 20-bit data signal is latched by the latch circuit 238, and the input serial signal is converted into a parallel signal. At this time, some data signal bits pass through the decoder 237, and the group selection signal 202 and block selection signal 203 are supplied from the control data supply circuit 201.

[0083] Here, the four block select bits of memory module 206 are converted into 16-bit block select signals 203 by decoder 237 and supplied. Additionally, since switching signal 205 is high, switch SW3, which controls the connection between the memory control signal and data terminal 231, is activated. In this way, the memory control signal ME and data terminal 231 are connected.

[0084] Next, in step S507, CPU 901 switches switch SW2 to the memory write pulse generation unit 226 side. Therefore, the memory write pulse generation unit 226 is connected to the data terminal 231. When the output of the memory write pulse generation unit 226 is connected to the memory control signal ME in this way to be input to the memory module 206, the process proceeds to step S508. In step S508, CPU 901 causes the memory write pulse generation unit 226 to generate a memory write pulse signal, and inputs the pulse signal as the memory control signal ME to the memory module 206 via the data terminal 231.

[0085] Therefore, the corresponding group selection signal 202, block selection signal 203, switching signal 205, and memory element control signal ME are input to the AND circuit AND2 for memory element selection. In response to the input memory element control signal ME, the drive element MD2 for the selected memory element is set to a pulse drive state. Therefore, current Iaf flows to the antifuse element AF, which is connected in series with the drive element MD2 for the memory element.

[0086] In step S509, it is determined whether the writing process has ended. If the writing process has not ended, that is, if a write operation is to be performed on another memory module 206, the process returns to step S503 to repeat the above series of operations. The above-described drive operation of the discharge module 204 can also be performed.

[0087] Here, as described above, the writing principle of an antifuse memory involves applying a voltage to the gate oxide film forming the antifuse element AF, which disrupts the gate oxide film, thereby writing information into the antifuse element AF. On the other hand, in a device like a polysilicon fuse memory where writing is performed by disconnecting a resistive element, writing is performed by applying a DC voltage for a predetermined time. However, in the antifuse element AF, DC voltage cannot be used for writing.

[0088] In the antifuse memory, intermittent application of a signal with characteristics like... Figure 3B The voltage burst drive is the same as the DATA (memory element control signal ME) pulse waveform shown. This damages the gate oxide film of the antifuse element AF and writes information to the memory module 206. As the memory element control signal ME, a pulse waveform with arbitrary frequency and number of pulses is generated by the memory write pulse generation unit 226 of the printing device 1000 and used.

[0089] In the first embodiment, the memory write pulse generation unit 226 generates a rectangular wave with a frequency of 5 MHz and 100,000 pulses, and outputs the rectangular wave as a memory element control signal ME to the memory module 206 for writing.

[0090] Note that in the first embodiment, as Figure 3B As shown, when writing to memory module 206, no CLK signal is output, which is consistent with... Figure 3A The drive of the emission module 204 shown is different. This results in a circuit configuration (not shown) that prevents writing to the memory module 206 even when the CLK signal is output. This is because when driving the emission module 204, the group select signal 202 and the block select signal 203 are used, as when writing to the memory module 206. Even if the switching signal 205 is reversed by noise or other factors and an operational error occurs, erroneous writing to the memory module 206 is prevented.

[0091] As described above, according to the first embodiment, when data is written to the antifuse memory element, a memory write pulse is given via switch SW3 as a memory control signal, thereby writing data to the memory element without increasing the number of terminals on the element substrate.

[0092] [Second Embodiment]

[0093] Figure 6 This is a view showing a portion of the configuration of the discharge module 204, memory module 206, and drive circuitry mounted on a component substrate 11a (hereinafter also simply referred to as the "substrate") according to a second embodiment. Note that, with Figure 1 The same reference numerals in the above-described component substrate 11 indicate Figure 6 The same parts in the text will be omitted and their descriptions will be omitted.

[0094] Component substrate 11a and Figure 1 The printed element substrate 11 according to the first embodiment shown differs in two aspects. First, the CLK generation unit 222 and the memory write pulse generation unit 226 can be selectively connected to the CLK terminal 230 via a switching switch SW2. Second, the memory control signal ME 221 and the printed element control signal HE 220 are selectively supplied to the memory module 206 and the emission module 204 via a common wiring by a multiplexer 240. Here, if the switching signal 205 is low, the multiplexer 240 selects the HE (hot-enabled) signal input from the HE terminal 233 and outputs it as the HE signal 220. On the other hand, if the switching signal 205 is high, the multiplexer 240 selects the CLK signal input from the CLK terminal 230 and outputs it as the memory control signal ME 221. Figure 6 In the circuit shown, the switching signal 205 is input to the AND circuit AND1 of the emission module 204 and the AND circuit AND2 of the memory module 206. If the switching signal 205 is low, the AND circuit AND1 can output a high-level signal. If the switching signal 205 is high, the AND circuit AND2 can output a high-level signal. Therefore, the emission module 204 and the memory module 206 are not simultaneously driven by the printing element control signal HE 220.

[0095] The following will refer to Figure 6 , Figure 3A and Figure 7 The operation of the emission module 204 when it is driven is described. Note that the timing diagram of the emission module 204 driven according to the second embodiment is different from that of the first embodiment described above. Figure 3A The same, and its description will be omitted.

[0096] Figure 7 This is a flowchart explaining the process when the printing device 1000 drives the emission module 204 according to the second embodiment. Note that the process shown in the flowchart is implemented by the CPU 901 executing a program stored in the ROM 903. Note the connection to the above. Figure 4 The same step numbers in Figure 7 indicate the same process. However, even if the processing is the same, Figure 6 The operation of the circuit shown also differs from that of the first embodiment described above, and the differences will be described in detail.

[0097] As described above, in the printed element substrate 11a according to the second embodiment, the CLK generation unit 222 and the memory write pulse generation unit 226 can be selectively connected to the CLK terminal 230 via the switching switch SW2.

[0098] Therefore, in step S701, CPU 901 switches switch SW2 to the CLK generation unit 222 side. This obtains a state where the CLK signal generated by CLK generation unit 222 is input to CLK terminal 230. The process proceeds to step S404, and CPU 901 causes CLK generation unit 222 to generate a CLK signal, and causes data generation unit 223 to output a data signal synchronously with the CLK signal for selectively driving emission module 204. Here, the data signal is formed by 20 bits, including 15 group bits, 4 group selection signal bits, and 1 bit switching signal 205, such as... Figure 3A As shown in the diagram, the group and block select bits are signals in which the bit corresponding to the emission module 204 to be driven is "1". When emission module 204 is selected and driven, switching signal 205 changes to a low level. Therefore, multiplexer 240 selects the HE (hot-enabled) signal input from HE terminal 233.

[0099] In step S405, CPU 901 outputs a data signal synchronously with the CLK signal input from CLK terminal 230 and serially outputs it to shift register (S / R) 239. When 20 bits of data are input to shift register 239 in this manner, the process proceeds to step S406. In step S406, CPU 901 supplies the LT signal generated by LT generation unit 224 from LT terminal 232. Therefore, the 20-bit data signal is held by LT circuit 238. Thus, the input serial signal is converted into a parallel signal. At this time, some data signal bits of the 20-bit data are output via decoder 237 as block select signal 203.

[0100] In step S407, a HE (hot-on) signal, generated by the HE generation unit 225, serving as a print element control signal, is supplied from the HE terminal 233. At this time, as described above, the multiplexer 240 selects the input to the HE terminal 233 according to the switching signal 205 and outputs it to the common wiring for the memory control signal ME 221 and the print element control signal HE 220. Therefore, the corresponding group selection signal 202, block selection signal 203, switching signal 205, and print element control signal HE 220 are input to the AND circuit AND1 for the selected print element. Consequently, the drive element MD1 of the selected emission module is set to the ON state in response to the control signal HE 220, the print element Rh connected in series with the drive element MD1 is energized and driven, and current Ihe flows to the emission module.

[0101] The emission module 204 can be driven in the manner described above for printing.

[0102] Next, we will refer to Figure 6 , Figure 3C and Figure 8 The operation of the driving memory module 206 according to the second embodiment is described.

[0103] Figure 3C This is a timing diagram used to explain the operation of signals input from the printing device 1000 to the head substrate 11a and the writing to the memory module 206 according to the second embodiment.

[0104] Figure 8 This is a flowchart explaining the write process of the printing device 1000 to the memory module 206 according to the second embodiment. Note that the process shown in the flowchart is implemented by the CPU 901 executing a program stored in the ROM 903. Note that, as described in the first embodiment above... Figure 5 The same step number in the text indicates Figure 8 The same process as in [the previous sentence]. However, even though the processing is the same, Figure 6 The operation of the circuit shown also differs from that of the first embodiment described above, and the differences will be described in detail.

[0105] In step S801, CPU 901 switches switch SW2 to the CLK generation unit 222 side. Therefore, the CLK signal is input to CLK terminal 230. The process proceeds to step S504, and CPU 901 causes CLK generation unit 222 to generate the CLK signal. In step S505, CPU 901 outputs a data signal generated by data generation unit 223 to drive memory module 206, which is synchronized with the CLK signal. At this time, switching signal 205 changes to a high level because writing to memory module 206 is selected. Here, although switching signal 205 is supplied at a high level when writing to memory module 206, because emission module 204 and memory module 206 are exclusively driven by switching signal 205, all printing elements Rh and all antifuse elements AF are not driven simultaneously.

[0106] The process proceeds to step S506, and the CPU 901 outputs the LT signal generated by the LT generation unit 224 via the LT terminal 232. At this time, some data signal bits are supplied by the decoder 237, as well as the group selection signal 202 and the block selection signal 203 from the control data supply circuit 201.

[0107] The process proceeds to step S802, and CPU 901 switches switch SW2 to the memory write pulse generation unit 226 side. This obtains a state where the pulse signal generated by the memory write pulse generation unit 226 is input to the CLK terminal 230. Here, since the switching signal 205 is high when writing to the memory module 206, the multiplexer 240 selects the input from the CLK terminal 230. Therefore, the pulse signal generated by the memory write pulse generation unit 226 is supplied as the memory control signal ME 221. In this way, in step S508, in response to the input memory element control signal ME 221, the drive element MD1 for the selected memory element is set to the on state, and current Iaf flows to the antifuse element AF connected in series with the drive element MD2 for the memory element, thereby writing to the memory element.

[0108] Therefore, as Figure 3C As shown, during writing to a memory element, the pulse signal generated by the memory write pulse generation unit 226 is supplied as the memory control signal ME 221. Therefore, the memory element can be written to by repeatedly applying pulse waveforms that intermittently apply voltage to the antifuse element AF.

[0109] Note that, as Figure 3C As shown, when writing to memory module 206 is in progress, there is no input data signal, unlike when the discharge module 204 is driven. This results in a circuit configuration (not shown) that prevents writing to memory module 206 even when an input data signal is present. This is because when driving discharge module 204, group select signal 202, block select signal 203, and print element control signal HE 220 are typically used, and even if switching signal 205 causes data inversion and operational errors due to noise, erroneous writing to memory module 206 is prevented.

[0110] As described above, according to the second embodiment, when data is written to the antifuse element AF, writing is performed by supplying a pulse signal generated by the memory write pulse generation unit 226, thereby realizing data writing to the memory element. Furthermore, since the pulse signal uses the common terminal of the CLK signal, the increase in the number of terminals on the substrate can be suppressed.

[0111] [Third Embodiment]

[0112] Figure 10 This is a view showing a portion of the configuration of the discharge module 204, memory module 206, and drive circuitry mounted on a component substrate 11b (hereinafter also simply referred to as the "substrate") according to a third embodiment. Note that, with Figure 1The same reference numerals in the above-described component substrate 11 indicate Figure 10 The same part in.

[0113] The third embodiment differs from the first embodiment in two aspects. First, it does not provide a memory write pulse generation unit 226 capable of generating pulse waveforms with arbitrary frequency and number of pulses, nor does it include a switch SW2. Second, the CLK signal supplied to the CLK terminal 230 is used as a memory control signal ME 221. Furthermore, during writing to the memory module 206, a signal with the CLK frequency and multiple pulses is repeatedly transmitted during the writing process to the memory module 206, thereby writing to the memory module 206.

[0114] Figure 3D This is a timing diagram used to explain the operation of signals input from the printing device 1000 to the head substrate and the writing to the memory module 206 according to the third embodiment.

[0115] Figure 11 This is a flowchart explaining the process when the printing device 1000 drives the emission module 204 according to the third embodiment. Note that the process shown in the flowchart is implemented by the CPU 901 executing a program stored in the ROM 903. Note that, as described above... Figure 4 The same step number in the middle represents Figure 11 The same process as in the first embodiment. Figure 4 The only difference in the flowchart shown is the removal of Figure 4 S402 in the example. The remaining operations are the same as in the first embodiment. Moreover, the operation when driving the emission module according to the third embodiment is as follows: Figure 3A As shown in the first embodiment.

[0116] In the third embodiment, since the memory write pulse generation unit 226 and switch SW2 are not provided as described above, it is not necessary to perform... Figure 4 The operation of control switch SW2 is performed in step S402.

[0117] Next, we will refer to Figure 10 , Figure 3D and Figure 12 The operation of the driving memory module 206 according to the third embodiment is described.

[0118] Figure 12 This is a flowchart explaining the write process of the printing device 1000 to the memory module 206 according to the third embodiment. Note that, compared with the above-described first embodiment... Figure 5 The same step number in the flowchart indicates Figure 12 The same process as in the flowchart will be used, and its description will be omitted.

[0119] In the third embodiment, since the memory write pulse generation unit 226 and switch SW2 are not provided as described above, it is not necessary to perform... Figure 5 The operation of control switch SW2 is performed in steps S503 and S507.

[0120] refer to Figure 12 In step S504, the switching signal 205 changes to a high level, thereby turning on switch SW3. Therefore, in step S508, the CLK signal generated by the CLK generation unit 222 is input to the memory module 206 as the memory control signal ME 221 via the CLK terminal 230. Therefore, the corresponding group selection signal 202, block selection signal 203, switching signal 205, and memory element control signal ME 221 are input to the AND circuit AND2 for memory element selection. In response to the input memory element control signal ME, the drive element MD1 for the selected memory element is set to the on state, and the current Iaf flows to the antifuse element AF connected in series with the drive element MD2 for the memory element.

[0121] Here, as described above, in the antifuse memory, burst drives with voltages having pulse waveforms are applied intermittently to break the gate oxide film of the antifuse element and write information to the memory module 206.

[0122] In the third embodiment, as Figure 3D As shown, since the CLK signal has 10 pulses (frequency 8MHz) in a single column of data transmission, the data transmission is repeated 10,000 times, thereby applying 100,000 rectangular wave pulses, as in the first embodiment described above. Note that since the pulse conditions to be applied vary depending on conditions such as the applied voltage and the structure of the memory element AF, it is preferable to set the optimal pulse conditions according to the printing device 1000 or the printing element.

[0123] Furthermore, in the third embodiment, the CLK terminal 230 and the data terminal 231 are used only for the CLK signal and the data signal, such as... Figure 10 As shown on the substrate, the data signal for writing to the next column can be transmitted in parallel with the writing to the memory module 206, as in the driving of the emission module 204 (unlike the first and second embodiments described above). Therefore, when the element substrate 11b receives the next LT signal, the memory module 206 to be written to in the next column is selected. Each time the LT signal is output, the writing to the memory element and the transmission of selected data can be performed in parallel. Therefore, if data is repeatedly transmitted, the writing to the memory module 206 can be performed in a shorter time.

[0124] In the third embodiment, since the memory write pulse generation unit 226 and switch SW2 are not provided, the circuit configuration and operation of the printing device 1000 can be simplified compared to the first and second embodiments.

[0125] In the first to third embodiments, examples of partially changing the configuration of the printed element substrate have been described. The changed portions can be combined to form various configurations in each embodiment. For example, the first and third embodiments can employ the configuration according to the second embodiment, wherein the memory control signal ME 221 and the printed element control signal HE 220 are selectively supplied to the memory module 206 and the emission module 204 via a common wiring by a multiplexer 240.

[0126] Alternatively, in the second embodiment, the data generation unit 223 and the memory write pulse generation unit 226 can be selectively connected to the CLK terminal 230 via a switching switch SW2. Furthermore, in the third embodiment, the data signal supplied to the data terminal 231 can be used as the memory control signal ME 221.

[0127] Note that when driving the emission module 204 and writing to the memory module 206, it is preferable that the memory control signal ME 221 is not used as the printing element control signal HE 220, so that even if the switching signal 205 is switched by noise or other factors, no operational errors or incorrect writing will occur.

[0128] As described above, according to the third embodiment, the control signal for writing to the antifuse memory also functions as a data signal and a clock signal. Therefore, the clock signal and the data signal transmitted synchronously with the clock signal can typically be transmitted at high frequencies. Thus, even when transmitting high-frequency signals, reliable data writing can be performed in a short time without any problems.

[0129] Furthermore, since no independent control signal is provided for writing to the antifuse memory element, the number of terminals can be reduced, thus achieving the effect of suppressing the increase in the size of the element substrate.

[0130] As described above, according to the embodiment, there is no problem even when high-frequency signal transmission is used as a clock signal and a data signal transmitted synchronously with the clock signal. Therefore, when the data signal or clock signal is used as a control signal for writing to the antifuse memory, reliable data writing can be performed in a shorter time.

[0131] Furthermore, since no independent control signal is provided for writing to the antifuse memory, the increase in the number of terminals can be prevented, thus achieving the effect of suppressing the increase in the size of the printed element substrate.

[0132] Other embodiments

[0133] One or more embodiments of the present invention can also be implemented by a computer of a system or device and by a method performed by the computer of the system or device, the computer reading and executing computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more comprehensively referred to as a "non-transitory computer-readable storage medium") to perform one or more of the functions of the above embodiments and / or including one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing one or more of the functions of the above embodiments, the methods performed by the computer of the system or device, for example, reading and executing computer-executable instructions from the storage medium to perform one or more of the functions of the above embodiments and / or controlling one or more circuits to perform one or more of the functions of the above embodiments. The computer may include one or more processors (e.g., a central processing unit (CPU), a microprocessor unit (MPU)) and may include separate computers or a network of separate processors to read and execute the computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or a storage medium. Storage media may include, for example, hard disks, random access memory (RAM), read-only memory (ROM), the storage unit of a distributed computing system, and optical discs (such as optical discs (CD), digital versatile discs (DVD), or Blu-ray discs (BD)). TM One or more of the following: flash memory devices, memory cards, etc.

[0134] Other embodiments

[0135] The embodiments of the present invention can also be implemented by providing software (programs) that perform the functions of the above embodiments to a system or device via a network or various storage media, and the computer or central processing unit (CPU) or microprocessor unit (MPU) of the system or device reads and executes the program.

[0136] While the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to include all such modifications and equivalent structures and functions.

Claims

1. A component substrate, characterized in that, include: Multiple sets of printed components; Multiple sets of memory elements; The first terminal receives the clock signal. The second terminal receives the input data signal; The control data supply unit is configured to receive a data signal input from the second terminal in synchronization with a clock signal input from the first terminal, and to output selection signals for selecting groups and blocks of memory elements and printing elements; and The switch is configured to switch the connection between the second terminal and the memory control signal of the memory element based on a switching signal included in the data signal. Specifically, when writing to the memory element, a switching signal is switched such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for writing to the memory element is input via the second terminal.

2. A component substrate, characterized in that, include: Multiple sets of printed components; Multiple sets of memory elements; The first terminal receives the clock signal. The second terminal receives the input data signal; The third terminal is used to input drive signals to drive the printing elements; The control data supply unit is configured to receive a data signal input from the second terminal in synchronization with a clock signal input from the first terminal, and to output selection signals for selecting groups and blocks of memory elements and printing elements; and The selection unit is configured to select based on a switching signal included in the data signal, to connect one of a clock signal input from the first terminal and a drive signal input from the third terminal to a printing element control signal for controlling the drive of the printing element and a memory control signal for controlling the memory element. Specifically, when driving the printing element, the switching signal switches so that the selection unit selects the driving signal input from the third terminal, and when driving the memory element, the switching signal switches so that the selection unit selects the clock signal input from the first terminal, and inputs a pulse signal for writing to the memory element via the first terminal.

3. A component substrate, characterized in that, include: Multiple sets of printed components; Multiple sets of memory elements; The first terminal receives the clock signal. The second terminal receives the input data signal; The control data supply unit is configured to receive a data signal input from the second terminal in synchronization with a clock signal input from the first terminal, and to output selection signals for selecting groups and blocks of memory elements and printing elements; and A switch is configured to switch the connection between the first terminal and the memory control signal of the memory element based on a switching signal included in the data signal. Specifically, when writing to the memory element, the switching signal switches such that the switch connects the first terminal and the memory control signal of the memory element, and a pulse signal for writing to the memory element is input via the first terminal.

4. The substrate according to claim 1, wherein The control data supply unit includes: The shift register is configured to receive and hold the data signal input from the second terminal in synchronization with the clock signal input from the first terminal; A multi-stage latch circuit is configured to latch serial data held in the shift register based on a latch signal; and The decoder is configured to decode the output of the multi-stage latch circuit and output selection signals for selecting groups and blocks of memory elements and print elements.

5. The substrate according to claim 4, wherein, The switching signal is the output of a specific latch circuit in the multi-level latch circuit.

6. The substrate according to claim 1, wherein, The switching signal is a signal that exclusively selects the printing element and the memory element.

7. The substrate according to claim 1, wherein, The block of the printed element or the memory element includes a plurality of printed elements or memory elements, wherein a printed element or memory element is selected in each of a plurality of groups.

8. The substrate according to claim 1, wherein, The memory element includes an antifuse memory element.

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