Jumping data clearing method and data storage system

Abstract

A jump data clearing method and a data storage system. The method comprises: receiving a data clearing instruction from a host system, wherein the data clearing instruction is used to clear data belonging to a target logical range; and executing a jump data clearing operation in response to the data clearing instruction. The jump data clearing operation comprises writing preset data to a plurality of discontinuous logical block addresses within the target logical range.

Description

Technical Field

[0001] The present invention relates to a data clearing technology, and more particularly to a jump data clearing method and a data storage system. Background Art

[0002] Generally speaking, data stored in a memory device can be cleared in a variety of ways. For example, the most common and fastest way to clear data is to modify or clear the mapping relationship between a specific logical block address and a physical block address. However, this data clearing method does not actually clear the data, and there are security risks in practice. Alternatively, a full disk clearing instruction or a clearing instruction for a specified logical range can be issued to the memory device, so that the memory device overwrites the random data on the entire disk or within the specified logical range to achieve the actual effect of clearing the data.

[0003] However, whether it is a full disk clear or a data clear within a specified logical range, the memory device is preset to perform sequential write. In practice, this large-scale sequential write easily causes the cache area that is preset to be used first within the memory device to be quickly exhausted, resulting in a significant drop in the data clearing speed of the memory device in the middle and late stages. Summary of the invention

[0004] The invention provides a jump data clearing method and a data storage system, which can improve the data clearing efficiency of a memory device.

[0005] An embodiment of the present invention provides a skip data clearing method for a memory device. The skip data clearing method comprises: receiving a data clearing instruction from a host system, wherein the data clearing instruction is used to clear data within a target logical range; and executing a skip data clearing operation in response to the data clearing instruction. The skip data clearing operation comprises writing preset data to a plurality of discontinuous logical block addresses within the target logical range.

[0006] The embodiment of the present invention further provides a data storage system, which includes a host system and a memory device. The memory device is coupled to the host system. The host system is used to send a data clearing instruction to the memory device. The data clearing instruction is used to clear data belonging to a target logical range. In response to the data clearing instruction, the memory device is used to perform a jump data clearing operation. The jump data clearing operation includes writing preset data to a plurality of discontinuous logical block addresses within the target logical range.

[0007] Based on the above, after receiving a data clearing instruction corresponding to a target logical range from a host system, the memory device can automatically perform a skip data clearing operation. In particular, the skip data clearing operation includes writing preset data to a plurality of discontinuous logical block addresses within the target logical range. In this way, the data clearing efficiency of the memory device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention.

[0009] Figure 2 is a schematic diagram of a memory management module according to an embodiment of the present invention.

[0010] Figure 3 FIG. 4 is a schematic diagram of a logical block address to be cleared by a data clearing instruction according to an embodiment of the present invention.

[0011] Figure 4 FIG. 4 is a schematic diagram of a jump data clearing operation according to an embodiment of the present invention.

[0012] Figure 5 FIG. 4 is a flow chart of a jump data clearing method according to an embodiment of the present invention.

[0013] in:

[0014] 10: Data storage system;

[0015] 11: Host system;

[0016] 12: memory device;

[0017] 121: connection interface;

[0018] 122: memory module;

[0019] 123: memory controller;

[0020] 210: storage area;

[0021] 220: idle area;

[0022] 201(1)~201(B): solid element;

[0023] 202(1)~202(C):Logical unit;

[0024] S501, S502: steps. DETAILED DESCRIPTION

[0025] Figure 1is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a memory device 12. The host system 11 may be any type of computer system. For example, the host system 11 may be a notebook computer, a desktop computer, a smart phone, a tablet computer, or an industrial computer. The memory device 12 is coupled to the host system 11 and is used to store data from the host system 11. For example, the memory device 12 may include a solid state drive, a portable USB flash drive, or other types of non-volatile memory storage devices.

[0026] The host system 11 can be electrically connected to the memory device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express), a Universal Serial Bus (USB), or other types of connection interfaces. Therefore, the host system 11 can store data in the memory device 12 and / or read data from the memory device 12.

[0027] The memory device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory device 12 to the host system 11. For example, the connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. The memory device 12 may communicate with the host system 11 via the connection interface 121. In one embodiment, the connection interface 121 also supports the NVM Express (NVMe) standard.

[0028] The memory module 122 is used to store data. The memory module 122 may include a rewritable non-volatile memory module. The memory module 122 includes a memory cell array. For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which one memory cell can store 1 bit), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which one memory cell can store 2 bits), a triple level cell (TLC) NAND flash memory module (i.e., a flash memory module in which one memory cell can store 3 bits), a quad level cell (QLC) NAND flash memory module (i.e., a flash memory module in which one memory cell can store 4 bits), or other memory modules with similar characteristics. In addition, the memory cells in the memory module 122 store data by changing the threshold voltage.

[0029] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be used to control the memory device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 to perform data access and data management. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (Digital Signal Processor, DSP), programmable controllers, application specific integrated circuits (Application Specific Integrated Circuits, ASIC), programmable logic devices (Programmable Logic Device, PLD) or other similar devices or combinations of these devices.

[0030] In one embodiment, the memory controller 123 is also called a flash memory controller. In one embodiment, the memory module 122 is also called a flash memory module. The memory module 122 can receive a command sequence from the memory controller 123 and access data stored in the memory cell according to the command sequence.

[0031] Figure 2 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figure 1 and Figure 2, the memory module 122 includes a plurality of physical units 201(1)-201(B). Each of the physical units 201(1)-201(B) includes a plurality of memory cells and is used to store data in a non-volatile manner. For example, a physical unit may include one or more physical pages, one or more physical blocks, or other physical management units. Multiple memory cells in a physical page may be programmed to store data at the same time. Multiple memory cells in a physical block may be erased at the same time.

[0032] In one embodiment, the memory controller 123 may allocate the physical units 201(1)-201(A) to the storage area 210 and allocate the physical units 201(A+1)-201(B) to the idle area 220. When new data from the host system 11 needs to be stored, one or more physical units in the idle area 220 may be selected to store the data and allocated to the storage area 210.

[0033] In one embodiment, the memory controller 123 may configure a plurality of logical units 202 ( 1 ) to 202 (C) to map physical units in the storage area 210. A logical unit may include one or more logical block addresses (LBAs).

[0034] In one embodiment, the memory controller 123 may record the mapping relationship between the logical unit and the physical unit in a mapping table (also referred to as a logical to physical mapping table). For example, the mapping table may include a mapping table of a flash translation layer (FTL) or a similar mapping table. The memory controller 123 may access the memory module 122 according to the mapping information in the mapping table.

[0035] In one embodiment, the physical units 201(1)-201(A) in the storage area 210 can store valid data and invalid data. Valid data is the latest data belonging to a certain logical unit. Invalid data is not the latest data belonging to any logical unit. For example, if the host system 11 writes new data to a certain logical unit and overwrites the old data originally stored in this logical unit (i.e., updates the data belonging to this logical unit), then the new data stored in the storage area 210 is the latest data belonging to this logical unit and will be marked as valid, while the overwritten old data may still be stored in the storage area 210 but marked as invalid.

[0036] In one embodiment, if the data belonging to a certain logical unit is updated, the memory controller 123 may remove the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit from the mapping table. At the same time, the memory controller 123 may establish a new mapping relationship between the logical unit and the physical unit storing the latest data belonging to the logical unit and store the new mapping relationship in the mapping table.

[0037] In one embodiment, the memory controller 123 may associate one or more physical units that do not store valid data with the idle area 220 and may erase these physical units. The data stored in the erased physical units will be cleared.

[0038] In one embodiment, the memory controller 123 may receive a write instruction from the host system 11. The write instruction may indicate that data from the host system 11 is stored in one or more logical block addresses. The memory controller 123 may write the data carried by the write instruction to the logical block address specified by the write instruction according to the write instruction. It should be noted that in the process of writing the data carried by the write instruction to the logical block address specified by the write instruction, the memory controller 123 may instruct the memory module 122 to store the data carried by the write instruction to one or more physical units. Then, the memory controller 123 may map the logical block address specified by the write instruction to the physical unit for storing the data carried by the write instruction. At the same time, the memory controller 123 may store the mapping relationship between the logical block address specified by the write instruction and the physical unit for storing the data in the mapping table. Thereby, the memory controller 123 can complete the data write operation corresponding to the write instruction.

[0039] In one embodiment, the host system 11 may send a data clearing instruction to the memory device 12. The memory controller 123 may receive the data clearing instruction from the host system 11. The data clearing instruction is used to clear the data belonging to a certain logical range (also referred to as a target logical range). In response to the data clearing instruction, the memory controller 123 may perform a skip data clearing operation. It should be noted that the skip data clearing operation includes writing the preset data to a plurality of non-contiguous logical block addresses within the target logical range. For example, the preset data may include random data or meaningless data that is not user data.

[0040] In one embodiment, the data clear instruction may include at least one write instruction. The at least one write instruction may instruct to write the preset data to all logical block addresses within the target logical range. It should be noted that although the data clear instruction (or write instruction) instructs to write the preset data to all logical block addresses within the target logical range, the memory controller 123 will not completely follow the instruction of the host system 11 to write the preset data to all logical block addresses within the target logical range.

[0041] In one embodiment, in the skip data clear operation, the memory controller 123 may write the preset data to a certain logical block address (also referred to as the first logical block address) and another logical block address (also referred to as the second logical block address) within the target logical range. There are P logical block addresses between the first logical block address and the second logical block address. The P logical block addresses are not written with the preset data, and P is a positive integer.

[0042] In other words, in the skip data clearing operation, the memory controller 123 can skip some logical block addresses within the target logical range by skipping writing, and only skip data writing to some discontinuous logical block addresses within the target logical range, thereby speeding up the overwriting speed of old data within the target logical range.

[0043] Figure 3 FIG. 1 is a schematic diagram of a logical block address to be cleared by a data clearing instruction according to an embodiment of the present invention. Figure 3 , in one embodiment, from Figure 1 The data clearing instruction of the host system 11 instructs to write the preset data to the consecutive 9 logical block addresses N to N+8. That is to say, for the host system 11, the host system 11 wants to instruct the memory device 12 to sequentially write the preset data to the logical block addresses N to N+8 through the data clearing instruction, so as to clear the old data in the logical range covering the logical block addresses N to N+8. In response to the data clearing instruction, the memory controller 123 can perform a jump data clearing operation on the logical block addresses N to N+8 in this logical range.

[0044] Figure 4 is a schematic diagram of a jump data clearing operation according to an embodiment of the present invention. Figure 4 , continued by Figure 3In an embodiment of the present invention, in a skipping data clearing operation, the memory controller 123 may skip the logical block addresses N+1 to N+3 and N+5 to N+7 within the logical range, and only perform skipping data writing on the logical block addresses N, N+4 and N+8 within the logical range to write the preset data to the logical block addresses N, N+4 and N+8.

[0045] It should be noted that in Figure 4 In the embodiment, it is assumed that P is 3 (ie, there are 3 skipped logical block addresses between two consecutively written logical block addresses). However, in another embodiment, P may also be other positive integers (eg, 1 or 4, etc.).

[0046] In one embodiment, the same or similar Figure 4 The jump-type data clearing operation can jump over some old data in the target logic range to destroy the old data in the target logic range. In addition, compared with completely overwriting all data or all logical block addresses in the target logic range, the jump-type data clearing operation can effectively reduce the amount of data required to be written.

[0047] In one embodiment, in a jump data clearing operation, before writing data to a certain logical block address within the target logical range (i.e., overwriting data), the memory controller 123 may also determine whether the logical block address stores valid data. If the logical block address stores valid data, the memory controller 123 may write the preset data to the logical block address to overwrite the valid data. However, if the logical block address does not store valid data, the memory controller 123 may skip the logical block address and not write the preset data to the logical block address. In this way, meaningless data overwriting behavior can be reduced.

[0048] In one embodiment, in a jump data clearing operation, before writing data to a certain logical block address within the target logical range (i.e., overwriting data), the memory controller 123 may also determine whether the mapping information of this logical block address exists in the mapping table. If the mapping information of this logical block address exists in the mapping table (i.e., the mapping information related to this logical block address is recorded in the mapping table), it means that this logical block address currently stores valid data. Therefore, the memory controller 123 may write the preset data to this logical block address to overwrite the valid data. However, if the mapping information of this logical block address does not exist in the mapping table (i.e., the mapping information related to this logical block address is not recorded in the mapping table), it means that this logical block address currently does not store valid data. Therefore, the memory controller 123 may skip this logical block address and not write the preset data to this logical block address.

[0049] In one embodiment, before receiving the data clear instruction from the host system 11, the host system 11 may first transmit an enable instruction to the memory device 12. The memory controller 123 may receive the enable instruction from the host system 11. In response to the enable instruction, the memory controller 123 may enable the skip data clear operation. For example, the memory controller 123 may set a control parameter corresponding to the skip data clear operation to an enable state according to the enable instruction. When the control parameter is in the enable state, when the data clear instruction (or write instruction) is received from the host system 11, the memory controller 123 may perform the skip data clear operation according to the data clear instruction (or write instruction).

[0050] In one embodiment, after the memory device 12 completes the jump data clear operation, the host system 11 may transmit a disable command to the memory device 12. In response to the disable command, the memory controller 123 may disable the jump data clear operation. For example, the memory controller 123 may set a control parameter corresponding to the jump data clear operation to a disable state according to the disable command. When the control parameter is in a disabled state, when a write command is received from the host system 11, the memory controller 123 may perform a normal data write operation according to the write command. In a normal data write operation, the memory controller 123 may write data to all logical block addresses indicated by the write command according to the instructions of the write command. Figure 3 For example, when receiving a write instruction indicating that data is to be written to logical block addresses N to N+8, in a normal data write operation, the memory controller 123 may perform a complete sequential write to the logical block addresses N to N+8, rather than Figure 4The data is written in a jumpy manner as shown.

[0051] Figure 5 is a flow chart of a jump data clearing method according to an embodiment of the present invention. Figure 5 In step S501, a data clearing instruction is received from a host system, wherein the data clearing instruction is used to clear data within a target logical range. In step S502, in response to the data clearing instruction, a skipping data clearing operation is performed. The skipping data clearing operation includes writing preset data to a plurality of discontinuous logical block addresses within the target logical range.

[0052] However, Figure 5 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 5 Each step in the above-mentioned embodiment can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 5 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0053] In summary, after receiving a data clearing instruction from a host system to clear data within a target logical range, the memory device can automatically perform a skip data clearing operation. In particular, the skip data clearing operation includes writing preset data to a plurality of discontinuous logical block addresses within the target logical range. In this way, the data clearing efficiency of the memory device can be effectively improved.

[0054] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A skip data clearing method for a memory device, and the skip data clearing method comprises: Receiving a data clearing command from a host system, wherein the data clearing command is used to clear data belonging to a target logic range; as well as In response to the data clearing instruction, a jump data clearing operation is performed; wherein, in response to the data clearing instruction, a jump data clearing operation is performed, including: Determine whether a specific logic block address within the target logic range stores valid data; If the specific logical block address stores the valid data, writing a preset data into a plurality of discontinuous logical block addresses within the target logical range; If the specific logical block address does not store the valid data, the preset data is not written to the specific logical block address.

2. The jump data clearing method as claimed in claim 1, characterized in that: The data clearing instruction includes at least one write instruction, and the at least one write instruction instructs to write the preset data into all logical block addresses within the target logical range.

3. The jump data clearing method as claimed in claim 1, characterized in that: The preset data includes random number data or meaningless data.

4. The jump data clearing method as claimed in claim 1, characterized in that: The step of writing the preset data into the plurality of discontinuous logical block addresses within the target logical range comprises: The preset data is written into a first logic block address and a second logic block address within the target logic range, There are P logical block addresses between the first logical block address and the second logical block address, the P logical block addresses are not written into the preset data, and P is a positive integer.

5. The jump data clearing method as claimed in claim 1, characterized in that: The step of determining whether the specific logical block address within the target logical range has stored the valid data comprises: It is determined whether mapping information of the specific logical block address exists in a mapping table.

6. The jump data clearing method as claimed in claim 1, characterized in that: Also includes: Before receiving the data clearing command from the host system, receiving an enable command from the host system; as well as In response to the enable instruction, the skip data clear operation is enabled.

7. A data storage system comprising: A host system; as well as a memory device coupled to the host system, The host system is used to send a data clearing instruction to the memory device, wherein the data clearing instruction is used to clear data belonging to a target logic range, and In response to the data clearing instruction, the memory device is used to perform a jump data clearing operation; wherein, in response to the data clearing instruction, the memory device is used to perform a jump data clearing operation, including: Determine whether a specific logic block address within the target logic range stores valid data; If the specific logical block address stores the valid data, writing a preset data into a plurality of discontinuous logical block addresses within the target logical range; If the specific logical block address does not store the valid data, the preset data is not written to the specific logical block address.

8. The data storage system as claimed in claim 7, wherein: The operation of writing the preset data to the plurality of discontinuous logical block addresses within the target logical range includes: The preset data is written into a first logic block address and a second logic block address within the target logic range, There are P logical block addresses between the first logical block address and the second logical block address, the P logical block addresses are not written into the preset data, and P is a positive integer.

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