Ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic

Abstract

This invention discloses an ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic, comprising the following steps: S1, buffering the input one-dimensional signed number sequence x(n) into five points and outputting the data in two's complement form in parallel according to a specific timing sequence; S2, preprocessing the parallel data output in S1; S3, performing parallel pairwise comparisons on the preprocessed data in S2 to obtain the size relationship between the data, and storing the comparison results in the corresponding size relationship registers; S4, calculating the redundancy output median index number based on the preprocessed parallel data in S2 and the value of the size relationship register in S3; S5, using the median index number calculated in S4, selecting the index value of the corresponding index number in the original parallel data for output using a MUX. This method outputs the median filtering result with fewer comparisons, less clock delay, less hardware logic resources, and lower computational latency.

Description

Technical Field

[0001] This invention relates to the field of ultra-high-speed real-time signal processing technology, specifically to an ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic. Background Technology

[0002] Median filtering is a nonlinear signal processing technique based on order statistics theory. Its basic principle is to replace the value of a point in a digital image or digital sequence with the median value of all points in a neighborhood of that point, thereby eliminating isolated noise points and achieving the filtering purpose.

[0003] In the implementation of median filtering algorithms using hardware logic, calculating the median of each window is the core step. This median calculation consumes most of the logic operation time; therefore, the efficiency of median calculation largely determines the operating speed of the entire filtering circuit. Currently, median filtering schemes implemented using FPGAs or ASICs generally employ three or more stages of pipelines to compare data within a window in blocks when calculating the median. This approach consumes significant hardware logic resources and requires a considerable number of clock cycles. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes an ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic, which can output median filtering results with fewer comparisons and less clock delay.

[0005] The technical solution of this invention is as follows:

[0006] A high-speed pipelined five-point median filtering method based on fully parallel hardware logic includes the following steps:

[0007] S1. The input one-dimensional signed number sequence x(n) is buffered at five points through the data buffer and shaping module, and the data in two's complement form is transmitted to the first-level pipeline module in parallel according to a specific time sequence.

[0008] S2. The parallel data output in S1 is preprocessed by the preprocessing logic of the first-level pipeline module. The preprocessing includes data format conversion and low-order data padding.

[0009] S3. The comparison unit of the first-level pipeline module performs parallel pairwise comparisons on the preprocessed data in S2 to obtain the size relationship between each data and other data, and stores the comparison results in the corresponding size relationship register.

[0010] The median index determination logic of the S4 secondary pipeline module calculates redundancy based on the preprocessed parallel data in S2 and the values ​​of the ten size relationship registers in S3. This determines the location of the median and outputs the median index.

[0011] S5, the median selection unit of the secondary pipeline module selects the index value of the corresponding index number in the original parallel data and outputs it based on the median index number calculated in S4 using MUX.

[0012] Preferably, in step S1, a five-point data buffer for the input one-dimensional signed number sequence x(n) is implemented through a register array with a width of N bits and a length of 5, and a counter defined inside the data buffer and shaping module. The two's complement form of the data is output in parallel with a specific timing sequence. Specifically, the input one-dimensional N-bit signed number sequence is converted from sign-magnitude to two's complement using combinational logic. At the rising edge of the current clock, the converted two's complement is input to the register array for shift storage, while the counter increments by one. The above process is repeated until the counter count is 4. In the next clock cycle, the counter is cleared and the valid output signal out_vld is pulled high, maintaining this for one clock cycle to complete one data transmission.

[0013] Preferably, the specific method of step S2 is as follows:

[0014] S21. When out_vld of the data cache and shaping module is high, determine whether there are negative numbers in the five parallel data. If there are, perform data format conversion and proceed to step S22. If there are no negative numbers, skip the data format conversion and proceed directly to step S22.

[0015] S22. Perform low-bit supplementation on the data obtained in step S21, that is, according to the data index number index, add 3 bits of redundant bits index+1'b1 to the low bits of each data channel, and the preprocessing logic outputs five parallel data channels with a width of N+3+1 bits.

[0016] Preferably, in step S21, the data format conversion method is as follows: perform a logical OR operation on the sign bits of the five parallel data streams; determine the result of the logical OR operation; if it is "1", then invert the sign bit of each data stream and fill the highest bit with 1 bit of data "0" as the sign bit; if it is "0", then skip step S21.

[0017] Preferably, in step S22, the method for supplementing the low-order data is as follows: 3 redundant bits 001 are spliced ​​into the low-order data with index number 0; 3 redundant bits 010 are spliced ​​into the low-order data with index number 1, and so on, until five parallel data channels are finally obtained; the obtained five parallel data channels are used as the output signal of the preprocessing logic and input to the comparison unit of the first-level pipeline module.

[0018] Preferably, in step S3, the preprocessed data from S2 is compared in parallel pairwise. The specific comparison method is as follows:

[0019] Based on the carry-lookahead calculation formula:

[0020] G n =A n .B n

[0021] P n =A n +B n

[0022] C n+1 =G n +P n ·C n

[0023] Among them, A n and B n Let P be the nth bit logic value of addends A and B. n and G n C is an intermediate variable. n This is the carry-over value from the lower digit to the current digit.

[0024] Assuming five parallel data streams are A, B, C, D, and E, with corresponding index numbers 0, 1, 2, 3, and 4, they are parallelized pairwise comparisons. Specifically, Cn is calculated in parallel for ten sets of data: A with -B, A with -C, B with -C, and so on. The calculated Cn for each set of data is then stored in the corresponding size relation register, BT01, BT02, BT12, etc.

[0025] Preferably, step S4 includes the following sub-steps:

[0026] S41. Based on whether the index value corresponding to the index number participates in this comparison, the ten size relationship registers are classified into class1 to class5.

[0027] S42. After processing the register values ​​in each class accordingly, sum them up to obtain the accumulated value S. n ;

[0028] S43, Accumulate the value S n The redundancy is calculated by subtracting from a predetermined threshold T. calculate;

[0029] S44. Output the index number with redundancy of 0, which is the index number of the median;

[0030] Preferably, the method for processing the register value in each class in step S42 is as follows: if x1 in the BT[x1][x2] register of classn is not n, then the register value is inverted; if it is n, then no operation is performed.

[0031] Preferably, the predetermined threshold T in step S43 is the median value of the index number, which changes according to the change of the filter length, and is a constant of 2 here.

[0032] This invention has the following characteristics and beneficial effects:

[0033] By adopting the above technical solution, the sorting strategy is optimized and the pipeline stage is compressed, so that the median filtering result can be output with fewer comparisons and less clock delay. Compared with the traditional median filtering implementation method, it consumes less hardware logic resources, has lower computational latency, and the theoretical maximum clock frequency can reach more than 450MHz. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart illustrating the steps of an ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic in this embodiment.

[0036] Figure 2 This is an FPGA hardware logic architecture diagram of the ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic in this embodiment.

[0037] Figure 3 This is the register classification table for class1 to class5 in the ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic in this embodiment. Detailed Implementation

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0039] The technical solution of the present invention will be further described in detail below through specific embodiments and in conjunction with the accompanying drawings.

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0041] Conversely, this invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the invention as defined in the claims. Furthermore, to provide a better understanding of the invention, certain specific details are described in detail below. However, those skilled in the art will fully understand the invention even without these detailed descriptions.

[0042] This embodiment provides an ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic, such as... Figure 1 As shown, and in combination Figure 2 FPGA hardware logic architecture diagram and Figure 3 The register classification table is explained, including the following steps:

[0043] S1. The input one-dimensional signed number sequence x(n) is buffered at five points through the data buffering and shaping module, and the data in two's complement form is transmitted to the first-level pipeline module in parallel according to a specific time sequence.

[0044] Specifically, in step S1, a register array with a width of N bits and a length of 5, and a counter are defined within the data buffer and shaping module to achieve five-point data buffering of the input one-dimensional signed number sequence x(n). The two's complement form of the data is output in parallel with a specific timing sequence. The specific method is as follows: the input one-dimensional N-bit signed number sequence is converted from sign-magnitude to two's complement using combinational logic. At the rising edge of the current clock, the converted two's complement is input into the register array for shift storage, while the counter increments by one. The above process is repeated until the counter count is 4. In the next clock cycle, the counter is cleared to zero, and the valid output signal out_vld is pulled high. This is maintained for one clock cycle to complete one data transmission.

[0045] It should be noted that the data transmitted in parallel to the first-level pipeline module after the data complementation is completed is called parallel data.

[0046] S2. The parallel data output from S1 is preprocessed by the preprocessing logic of the first-level pipeline module. The preprocessing includes data format conversion and low-order data padding.

[0047] S21. When out_vld of the data cache and shaping module is high, determine whether there are negative numbers in the five parallel data. If there are, perform data format conversion and proceed to step S22. If there are no negative numbers, skip the data format conversion and proceed directly to step S22.

[0048] Specifically, the data format conversion method is as follows: perform a logical OR operation on the sign bits of the five parallel data streams; determine the result of the logical OR operation. If it is "1", then invert the sign bit of each data stream and fill the highest bit with 1 bit of data "0" as the sign bit; if it is "0", then skip step S21.

[0049] S22. Perform low-bit supplementation on the data obtained in step S21, that is, according to the data index number index, add 3 bits of redundant bits index+1'b1 to the low bits of each data channel, and the preprocessing logic outputs five parallel data channels with a width of N+3+1 bits.

[0050] Specifically, the method for supplementing low-order data is as follows: 3 redundant bits 001 are appended to the low-order data at index 0; 3 redundant bits 010 are appended to the low-order data at index 1, and so on, until five parallel data streams are obtained; the obtained five parallel data streams are used as the output signal of the preprocessing logic and input to the comparison unit of the first-level pipeline module.

[0051] S3. The comparison unit of the first-level pipeline module performs parallel pairwise comparisons on the preprocessed data in S2 to obtain the size relationship between each data and other data, and stores the comparison results in the corresponding size relationship register.

[0052] Specifically, based on the carry-lookahead calculation formula:

[0053] G n =A n .B n

[0054] P n =A n +B n

[0055] C n+1 =G n +P n ·C n

[0056] Among them, A n and B n Let P be the nth bit logic value of addends A and B. n and G n C is an intermediate variable. n This is the carry-over value from the lower digit to the current digit.

[0057] Assuming five parallel data streams are A, B, C, D, and E, with corresponding index numbers 0, 1, 2, 3, and 4, they are parallelized pairwise comparisons. Specifically, Cn is calculated in parallel for ten sets of data: A with -B, A with -C, B with -C, and so on. The calculated Cn for each set of data is then stored in the corresponding size relation register, BT01, BT02, BT12, etc.

[0058] It should be noted that carry-ahead solves the addition of two numbers, so it should be seen as A + (-B), that is, a pairwise comparison of A and -B.

[0059] The median index determination logic of the S4 secondary pipeline module calculates redundancy based on the preprocessed parallel data in S2 and the values ​​of the ten size relationship registers in S3. This determines the location of the median and outputs the median index.

[0060] Specifically, step S4 includes the following sub-steps:

[0061] S41. Based on whether the index value corresponding to the index number participates in this comparison, the ten size relationship registers are classified into class1 to class5.

[0062] Furthermore, classification methods such as Figure 3 As shown, the classification principle is: whether the index value corresponding to a certain index number participates in the current comparison. For example, for data with index 0, it participates in the comparison process with data with indices 1, 2, 3, and 4 respectively. Therefore, the five registers BT01, BT02, BT03, and BT04 are classified as class1, and so on, class2 to 5 are classified.

[0063] S42. After processing the register values ​​in each class accordingly, sum them up to obtain the accumulated value S. n ;

[0064] Furthermore, the processing method for the register value in each class is as follows: if x1 in the BT[x1][x2] register in classn is not n, then the register value is inverted; if it is n, then no operation is performed.

[0065] S43, Accumulate the value S n The redundancy is calculated by subtracting from a predetermined threshold T. The calculation is expressed as follows:

[0066]

[0067] Sn corresponds to the sum of the values ​​of each register in classn, and the predetermined threshold T is the median of the index number, which changes according to the filter length.

[0068] As is understandable, this embodiment uses five-point median filtering, so the predetermined threshold T is a constant of 2.

[0069] S44. Output the index number with redundancy of 0, which is the index number of the median.

[0070] S5, the median selection unit of the secondary pipeline module selects the index value of the corresponding index number in the original parallel data and outputs it based on the median index number calculated in S4 using MUX.

[0071] Specifically, the index number calculated in S44 is used as the gating signal, and the five N-bit raw data in the pipeline register is used as the data signal for median selection and output.

[0072] The above technical solution primarily addresses the problem of high latency and large logic resource consumption in existing median filtering algorithms based on traditional sorting strategies when calculating the median value in each window. By optimizing the sorting strategy and compressing the pipeline stages, the above solution outputs the median filtering result with fewer comparisons and less clock latency. Experimental verification using FPGA hardware logic deployment of this method demonstrates that, compared to traditional median filtering implementations, the method described in this invention consumes fewer hardware logic resources, has lower computational latency, and theoretically can achieve a maximum clock frequency of over 450MHz.

[0073] It should be noted that the FPGA hardware logic architecture implementation method in this embodiment is existing technology. Therefore, the data buffer and shaping module, the first-level pipeline module and the second-level pipeline module will not be specifically described in this embodiment.

[0074] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments, including components, without departing from the principles and spirit of the present invention, and these variations still fall within the protection scope of the present invention.

Claims

1. A high-speed pipelined five-point median filtering method based on fully parallel hardware logic, characterized in that: Includes the following steps: S1. Process the input one-dimensional signed number sequence through the data caching and shaping module. Five-point data buffering is performed, and the data in two's complement form is transmitted to the first-level pipeline module in parallel according to a specific timing sequence; S2. The parallel data output from S1 is preprocessed by the preprocessing logic of the first-level pipeline module. The preprocessing includes data format conversion and low-bit data padding. The low-bit data padding method is as follows: 3 bits of redundant 001 are added to the low-bit data with index number 0; 3 bits of redundant 010 are added to the low-bit data with index number 1, and so on, to finally obtain five parallel data streams. S3. The comparison unit of the first-level pipeline module performs parallel pairwise comparisons on the preprocessed data in S2 to obtain the size relationship between each data and other data, and stores the comparison results in the corresponding size relationship register. The median index determination logic of the S4 secondary pipeline module calculates redundancy based on the preprocessed parallel data in S2 and the values ​​of the ten size relationship registers in S3. This determines the median position and outputs the median index. Step S4 includes the following sub-steps: S41. Based on whether the index value corresponding to the index number participates in this comparison, the ten size relationship registers are classified into class1 to class5. S42. After processing the register values ​​in each class accordingly, sum them up to obtain the accumulated value. The processing method for register values ​​in each class is as follows: if x1 in the BT[x1][x2] register of classn is not n, then the register value is inverted; if it is n, then no operation is performed. S43, Accumulated value With a predetermined threshold Difference and redundancy calculation Calculate; the predetermined threshold T is the median of the index number, set as a constant of 2; S44. Output the index number with redundancy of 0, which is the index number of the median; S5, the median selection unit of the secondary pipeline module selects the index value of the corresponding index number in the original parallel data and outputs it based on the median index number calculated in S4 using MUX.

2. The ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic according to claim 1, characterized in that, In step S1, a register array with a width of N bits and a length of 5, and a counter are defined within the data buffer and shaping module to process the input one-dimensional signed number sequence. The five-point data buffer; the two's complement form of the data is output in parallel with a specific timing sequence. The specific method is as follows: the input one-dimensional N-bit signed number sequence is converted from sign-magnitude to two's complement using combinational logic. At the rising edge of the current clock, the converted two's complement is input to the register array for shift storage. At the same time, the counter increments by one. The above process is repeated until the counter count is 4. In the next clock cycle, the counter is cleared and the valid output signal out_vld is pulled high. This is maintained for one clock cycle to complete one data transmission.

3. The ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic according to claim 1, characterized in that, The specific method for step S2 is as follows: S21. When out_vld of the data cache and shaping module is high, determine whether there are negative numbers in the five parallel data. If there are, perform data format conversion and proceed to step S22. If there are no negative numbers, skip the data format conversion and proceed directly to step S22. S22. Perform low-bit supplementation on the data obtained in step S21, that is, according to the data index number index, add 3 bits of redundant bits index+1'b1 to the low bits of each data channel, and the preprocessing logic outputs five parallel data channels with a width of N+3+1 bits.

4. The ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic according to claim 3, characterized in that, In step S21, the data format conversion method is as follows: perform a logical OR operation on the sign bits of the five parallel data; determine the result of the logical OR operation. If it is "1", then invert the sign bit of each data and fill the highest bit with 1 bit of data "0" as the sign bit; if it is "0", then skip step S21.

5. The ultra-high-speed pipelined five-point median filtering method based on fully parallel hardware logic according to claim 1, characterized in that, In step S3, the preprocessed data from S2 is compared pairwise in parallel. The specific comparison method is as follows: Based on the carry-lookahead calculation formula: in, and Let A and B be the nth bit logic values. and As an intermediate variable, This is the carry-over value from the lower digit to the current digit; Assuming five parallel data streams are A, B, C, D, and E, with corresponding index numbers 0, 1, 2, 3, and 4, they are compared in parallel pairwise. That is, Cn is calculated in parallel for ten sets of data, including A and -B, A and -C, B and -C, etc. The calculated Cn for each set of data is stored in the corresponding size relation register, which is BT01, BT02, BT12, etc.

Images