Access systems, memory systems, and access methods for 3D data access

Abstract

This invention relates to the field of integrated circuit design technology, and particularly to an access system, memory system, and access method for three-dimensional data access. The access system includes: a configuration register unit, an address generation unit, a data assembly and splitting unit, and a dual-pipeline controller. The address generation unit, connected to the configuration register unit and the dual-pipeline controller, calculates a one-dimensional physical address based on a target index value input by the user and sends it to the dual-pipeline controller. The dual-pipeline controller, connected to the memory interface, independently manages read and write flows based on user read / write requests, enabling read and write operations in the memory based on the one-dimensional physical address. The data assembly and splitting unit, connected to the dual-pipeline controller, assembles and splits data during the read / write flow before sending it to the dual-pipeline controller. This solution uses hardware to implement three-dimensional data indexing, which can improve data processing efficiency and system flexibility.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an access system, memory system and access method for three-dimensional data access. Background Technology

[0002] In modern signal and data processing applications, the use of three-dimensional data is becoming increasingly widespread. Traditionally, access to three-dimensional data blocks is usually achieved through software calculations, mapping three-dimensional indices to one-dimensional physical addresses in memory. This software implementation has several drawbacks: First, the address calculation process is complex, adding additional computational latency and limiting data access throughput, becoming a bottleneck for system performance improvement; second, the index value width and data width are often fixed, making it impossible to flexibly adjust according to actual needs during data processing, easily leading to a waste of storage resources and bandwidth, and making it difficult to meet the requirements of large-scale indexing or high-precision data; furthermore, because read and write operations are scheduled sequentially by software, resource contention exists, resulting in low access efficiency.

[0003] Therefore, existing software-based solutions for 3D data indexing suffer from low efficiency, poor flexibility, and an inability to achieve parallel read and write operations. Summary of the Invention

[0004] To address the problems of low efficiency, poor flexibility, and inability to achieve parallel read and write operations in existing software-based 3D data indexing solutions, this invention provides a memory access system, memory, and access method for 3D data storage.

[0005] In a first aspect, embodiments of the present invention provide an access system for three-dimensional data access, comprising: a configuration register unit, an address generation unit, a data assembly and splitting unit, and a dual pipeline controller; The address generation unit, connected to the configuration register unit and the dual pipeline controller, is used to calculate a one-dimensional physical address based on the target index value input by the user and the configuration parameters from the configuration register unit. The dual pipeline controller is connected to the memory interface and is used to independently manage the read and write processes based on user read and write requests, so as to control memory access based on the one-dimensional physical address. The data assembly and splitting unit is connected to the dual pipeline controller and is used to perform data assembly or splitting operations during the read and write process.

[0006] Secondly, embodiments of the present invention also provide a memory system based on an access system described in any embodiment of the specification, comprising: a main control unit, an access system as described in any embodiment of the specification, and a memory; The main control unit is connected to the access system and is used to configure the configuration register unit in the access system and to send read / write requests to the access system. The access system is connected to the memory via a memory interface, the memory being used to store three-dimensional data blocks.

[0007] Thirdly, embodiments of the present invention also provide an access method for a memory system based on any embodiment of this specification, comprising: In response to a user's read / write request, the address generation unit calculates a one-dimensional physical address based on the target index value input by the user and the parameters in the configuration register unit; The dual pipeline controller independently controls the read or write process based on the one-dimensional physical address. During the read process, the data assembly and splitting unit splits the target data from the data block read from the memory and returns it; During the write process, the data assembly and splitting unit assembles the data to be written into a data block read from the memory and writes it back to the memory.

[0008] This invention provides an access system, memory system, and access method for three-dimensional data storage. The access system comprises a configuration register unit, an address generation unit, a data assembly and splitting unit, and a dual pipeline controller. It uses hardware to implement the three-dimensional data index, rather than a software algorithm. Therefore, the bit width of the index values ​​in the three dimensions is independently configurable, and the data bit width is also configurable, allowing for flexible adjustment during data processing. Automatic hardware mapping from three-dimensional to one-dimensional addresses reduces computational latency and improves processing efficiency. Due to the hardware approach, independent read and write pipeline controllers can be used to achieve parallel read and write processing. Therefore, this solution solves the problems of low efficiency, poor flexibility, and resource waste inherent in traditional memory access methods when processing three-dimensional data. It is suitable for high-performance signal processing scenarios such as radar CFAR detection, and can significantly improve data processing throughput and system flexibility. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the composition of a memory system provided in an embodiment of the present invention; Figure 2This is a flowchart of an access method for three-dimensional data storage provided in an embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0012] Please refer to Figure 1 This invention provides an access system for three-dimensional data access, including: a configuration register unit, an address generation unit, a data assembly and splitting unit, and a dual pipeline controller; The address generation unit, connected to the configuration register unit and the dual pipeline controller, is used to calculate a one-dimensional physical address based on the target index value input by the user and the configuration parameters from the configuration register unit. A dual-pipeline controller, connected to the memory interface, is used to independently manage the read and write processes based on user read and write requests, and to control memory access based on a one-dimensional physical address. The data assembly and splitting unit is connected to the dual pipeline controller and is used to assemble or split data during the read and write process.

[0013] In this embodiment of the invention, the access system comprises a configuration register unit, an address generation unit, a data assembly and splitting unit, and a dual pipeline controller. It uses hardware to implement the three-dimensional data index, rather than a software algorithm. Therefore, the bit width of the index values ​​in the three dimensions is independently configurable, and the data bit width is also configurable, allowing for flexible adjustment during data processing. By automatically mapping the three-dimensional data to one-dimensional addresses through hardware, computational latency can be reduced, and processing efficiency improved. Due to the hardware approach, independent read and write pipeline controllers can be used to achieve parallel read and write processing. Therefore, this solution solves the problems of low efficiency, poor flexibility, and resource waste inherent in traditional memory access methods when processing three-dimensional data. It is suitable for high-performance signal processing scenarios such as radar CFAR detection, and can significantly improve data processing throughput and system flexibility.

[0014] The following is based on Figure 1 The diagram shown is used for illustration.

[0015] In some implementations, the configuration register unit includes: an index bit-width register, a data bit-width register, a base address register, and a step size register; The index bit width register is used to store the bit width of each dimension of the target index value. The data bit width register is used to store the bit width for reading and writing data; The base address register is used to store the starting address of the three-dimensional data block in memory; The step size register is used to store the step size for each dimension separately.

[0016] In this embodiment, the index bit-width register is used to store the bit width of the three dimensions (X, Y, Z) of the target index value, supporting independent and flexible configurations of 8-bit, 12-bit, or 16-bit. The data bit-width register is used to store the bit width of the data that can be read and written, supporting independent and flexible configurations of 32-bit, 64-bit, or 128-bit. For example, in radar CFAR processing, X dimension is the range dimension, Y dimension is the Doppler dimension, and Z dimension is the angle dimension. The three-dimensional bit width of the index value is configured as 12 bits, and the data bit width is configured as 32 bits, i.e., the target intensity value to be stored. The step size is used to calculate the address offset.

[0017] In some implementations, the address generation unit, when performing the calculation of a one-dimensional physical address based on a target index value input by the user, includes: Receive the target index value input by the user and obtain the bit width of each dimension of the index value stored in the index bit width register; For each dimension of the target index value, the target index value of that dimension is expanded to the bit width of the index value of that dimension stored in the index bit width register; Obtain the starting address stored in the base address register, and the step size in the three dimensions stored in the step size register; Calculate the one-dimensional physical address based on the starting address, the target index value, and the step size in three dimensions.

[0018] In this embodiment, the hardware address generation unit automatically completes the mapping from three-dimensional to one-dimensional addresses. The hardware implementation of the mapping is described below.

[0019] It's understandable that when a user sends a read request, they carry the target index value; when a user sends a write request, they carry the target index value and the data to be written. Both read and write requests require calculating a one-dimensional physical address based on the target index value. First, the unit receives the three-dimensional target index values ​​(idx_x, idx_y, idx_z) from the user. Then, according to the index width register settings, this unit extends the index value of each dimension by either a sign bit or zero to the width configured in the index width register. Finally, based on the starting address stored in the base address register, the target index value, and the step size of the three dimensions stored in the step size register, the one-dimensional physical address is calculated. Because the mapping from three-dimensional to one-dimensional addresses is automatically completed in hardware, there is no need for complex address calculations using software algorithms, freeing up the CPU / DSP and significantly reducing software overhead and access latency.

[0020] In some implementations, the address generation unit calculates a one-dimensional physical address by summing the product of the starting address and the target index values ​​of each dimension and the corresponding step size.

[0021] Specifically, the calculation method for a one-dimensional physical address is as follows: Address=Base_Address+idx_x*X_Step+idx_y*Y_Step+idx_z*Z_Step In the formula, Address is a one-dimensional physical address, Base_Address is the starting address, idx_x, idx_y and idx_z are the target index values ​​in three dimensions, and X_Step, Y_Step and Z_Step are the step sizes in three dimensions.

[0022] In this embodiment, the address generation unit obtains the starting address and the step size in three dimensions from the base address register and the step size register, and calculates the one-dimensional physical address by combining the target index value. The calculation method is simple and further improves the mapping efficiency.

[0023] In some implementations, the dual-pipeline controller includes independent read pipeline control logic and write pipeline control logic, which operate in parallel. The dual-pipeline controller also includes an arbitration unit for scheduling read and write requests according to a preset priority strategy when they arrive simultaneously, thereby avoiding access conflicts to the memory interface.

[0024] In some implementations, the read process of the dual pipeline controller includes: After receiving the one-dimensional physical address calculated by the address generation unit, a read request is sent to the memory interface to read the data block from the memory and send it to the data assembly and splitting unit. The data assembly and splitting unit, based on the data bit width stored in the data bit width register and the one-dimensional physical address, splits the target data from the read data block and returns it to the user.

[0025] For example, a 128-bit data block of surrounding cells is read from memory. The data assembly and splitting unit calculates the offset based on the low-order bits of the one-dimensional physical address, selects the required 64-bit continuous data from the 128-bit data using a multiplexer, and returns it to the user via a dual pipeline controller. The data width register stores a 64-bit data width.

[0026] In some implementations, the write process of the dual-pipeline controller includes: After receiving the one-dimensional physical address calculated by the address generation unit and the data to be written input by the user, the data block is read from the memory and sent to the data assembly and splitting unit. The data assembly and splitting unit, based on the one-dimensional physical address and the data bit width stored in the data bit width register, concatenates the data to be written to the data block to be read, forming a concatenated data block. The dual pipeline controller writes the spliced ​​data blocks to a designated location in the memory via the memory interface.

[0027] In this embodiment, traditional request processing can only process the first request before processing the next. Although read and write operations share the same memory interface, this embodiment is transparent to the internal scheduling logic. The dual-pipeline controller uses independent read and write pipelines, i.e., each unit's pipeline processing, allowing the next read request to be processed before the previous write request is completed. For example, if the previous write request is being assembled in the data assembly and splitting unit, the next request is being calculated for a one-dimensional physical address in the address generation unit. Therefore, the execution of read and write operations can be controlled in parallel without resource contention, enabling full-speed parallel execution of read and write operations, greatly improving data throughput, and is particularly suitable for streaming data processing. Essentially, it achieves the performance of simultaneous access to True Dual-Port RAM or two single-port memory blocks.

[0028] refer to Figure 1 This embodiment also provides a memory system based on any access system of the embodiments of the specification, including: a main control unit, an access system as described in any embodiment of the specification, and a memory; The main control unit is connected to the access system and is used to configure the configuration register unit in the access system and to send read and write requests to the access system. The access system connects to the memory via a memory interface, and the memory is used to store three-dimensional data blocks.

[0029] The information interaction and execution process between the modules in the above-mentioned memory system are based on the same concept as the access system embodiment of the present invention, and the specific details can be found in the description of the access system embodiment of the present invention, and will not be repeated here.

[0030] like Figure 2 As shown, this embodiment also provides an access method based on the memory system described in this specification, the method including: Step 200: In response to the user's read / write request, the address generation unit calculates a one-dimensional physical address based on the target index value input by the user and the parameters in the configuration register unit; Step 202: The dual pipeline controller independently controls the read or write process based on a one-dimensional physical address. Step 204: In the read process, the data assembly and splitting unit splits the target data from the data block read from the memory and returns it; Step 206: In the write process, the data assembly and splitting unit assembles the data to be written into a data block read from the memory and writes it back to the memory.

[0031] The information interaction and execution process of the above access method are based on the same concept as the access system embodiment of the present invention, and the specific details can be found in the description of the access system embodiment of the present invention, and will not be repeated here.

[0032] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An access system for three-dimensional data storage, characterized in that, include: Configuration register unit, address generation unit, data assembly and splitting unit, and dual pipeline controller; The configuration register unit includes: an index bit width register, a data bit width register, a base address register, and a step size register; The address generation unit, connected to the configuration register unit and the dual pipeline controller, is used to calculate a one-dimensional physical address based on the target index value input by the user and the configuration parameters from the configuration register unit. The dual pipeline controller is connected to the memory interface and is used to independently manage the read and write processes based on user read and write requests, so as to control memory access based on the one-dimensional physical address. The data assembly and splitting unit is connected to the dual pipeline controller and is used to perform data assembly and splitting operations during the read and write process. The read process of the dual pipeline controller includes: After receiving the one-dimensional physical address calculated by the address generation unit, a read request is initiated to the memory interface to read the data block from the memory and send it to the data assembly and splitting unit. The data assembly and splitting unit, based on the data bit width stored in the data bit width register and the one-dimensional physical address, splits the target data from the read data block and returns it to the user; The write process of the dual-pipeline controller includes: After receiving the one-dimensional physical address calculated by the address generation unit and the data to be written input by the user, the data block is read from the memory and sent to the data assembly and splitting unit. The data assembly and splitting unit, based on the one-dimensional physical address and the data bit width stored in the data bit width register, concatenates the data to be written to the read data block to form a concatenated data block. The dual pipeline controller writes the spliced ​​data block to a designated location in the memory via the memory interface.

2. The access system according to claim 1, characterized in that, The index bit width register is used to store the bit width of each dimension of the target index value respectively; The data bit width register is used to store the bit width of read and write data; The base address register is used to store the starting address of the three-dimensional data block in the memory; The step size register is used to store the step size for each dimension.

3. The access system according to claim 2, characterized in that, When the address generation unit performs the calculation of the one-dimensional physical address based on the target index value input by the user, it includes: Receive the target index value input by the user, and obtain the bit width of each dimension of the index value stored in the index bit width register; For each dimension of the target index value, the target index value of that dimension is expanded to the bit width of the index value of that dimension stored in the index bit width register; Obtain the starting address stored in the base address register, and the step size in the three dimensions stored in the step size register; The one-dimensional physical address is calculated based on the starting address, the target index value, and the step size of the three dimensions.

4. The access system according to claim 3, characterized in that, The address generation unit calculates the one-dimensional physical address by multiplying and summing the starting address with the target index value of each dimension and the corresponding step size.

5. The access system according to claim 1, characterized in that, The dual-pipeline controller includes independent read pipeline control logic and write pipeline control logic, which work in parallel. The dual-pipeline controller also includes an arbitration unit, which is used to schedule read and write requests according to a preset priority strategy when they arrive at the same time, so as to avoid access conflicts to the memory interface.

6. A memory system, characterized in that, include: The main control unit, the access system as described in any one of claims 1-5, and the memory; The main control unit is connected to the access system and is used to configure the configuration register unit in the access system and to send read / write requests to the access system. The access system is connected to the memory via a memory interface, the memory being used to store three-dimensional data blocks.

7. An access method based on the memory system of claim 6, characterized in that, include: In response to a user's read / write request, the address generation unit calculates a one-dimensional physical address based on the target index value input by the user and the parameters in the configuration register unit; The dual pipeline controller independently controls the read or write process based on the one-dimensional physical address. During the read process, the data assembly and splitting unit splits the target data from the data block read from the memory and returns it; During the write process, the data assembly and splitting unit assembles the data to be written into a data block read from the memory and writes it back to the memory.

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