Analog Calculation Method for Drain Current and Gate Voltage of FinFET

Abstract

In a simulation method for fitting a curve of the drain current and gate voltage of a FinFET, the method includes: determining whether the FinFET is a triple-gate FinFET with non-vertical wall fins; if so, obtaining a simulation circuit diagram of a triple-gate FinFET with vertical wall fins or a surround-gate FinFET in parallel with a plurality of double-gate FinFETs; performing simulation on the simulation circuit diagram, including: debugging the fitting parameters of the double-gate FinFET, debugging the fitting parameters of the triple-gate FinFET with vertical wall fins or the fitting parameters of the surround-gate FinFET, so that the output fitting curve is close to the curve of the actual drain current and gate voltage of the triple-gate FinFET with non-vertical wall fins. The present invention can make the fitting curve of the drain current and gate voltage closer to the curve of the actual drain current and gate voltage of the FinFET.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a method for simulating and calculating the drain current and gate voltage of a FinFET. Background Art

[0002] FinFET devices (fin field-effect transistors) and FinFET structures are non-planar devices and structures typically fabricated on a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. With the continuous development of semiconductor technology, in order to control the leakage problem of MOSFETs, the device has changed from the original planar structure to the current three-dimensional FinFET structure. Compared with planar transistors, the fin field-effect transistor (FinFET) has a three-dimensional channel structure, so it has better on-current and off-current characteristics and can also improve the short-channel effect (SCE). In some cases, it is necessary to simulate the FinFET to obtain the drain current and gate voltage of the FinFET and obtain the fitting curve of the drain current and gate voltage. When using the BSIM-CMG model to model the FinFET, the FinFET is generally divided into four categories. The first type of FinFET has no gate on the top of the fin, but both sides connected to the top have gates, that is, the first type of FinFET is a double-gate FinFET. The second type of FinFET has gates on the top of the fin and both sides connected to the top, that is, the second type of FinFET is a triple-gate FinFET, that is, a triple-gate FinFET. Among them, the triple-gate FinFET is further divided into the case where the two side walls of the longitudinal section of the fin are vertical and the case where the two side walls of the longitudinal section of the fin are non-vertical, that is, the longitudinal section of the fin is trapezoidal. When the two side walls of the longitudinal section of the fin are vertical, the FinFET is a FinFET with vertical side walls. When the two side walls of the longitudinal section of the fin are non-vertical, the FinFET is a FinFET with non-vertical side walls. The third type is a quadruple-gate FinFET, and the fourth type is a surround-gate FinFET. Specifically, in the BSIM-CMG model, geomod = 0, geomod = 1, geomod = 2, and geomod = 3 are used to represent the modeling of these three types of FinFETs, that is, (geomod = 0: double gate, geomod = 1: triple gate, geomod = 2: quadruple gate, geomod = 3: cylindrical gate)

[0003] The analog model of the double-sided gate FinFET already exists and will not be elaborated here. For the triple-gate FinFET with two vertical sidewalls in the longitudinal section of the fin, the prior art generally uses the BSIM-CMG model to simulate the FinFET. BSIM-CMG is a model based on the double-gate FinFET (Double Gate FinFET) and is established under the approximate solution of the Poisson equation. For the triple-gate FinFET, BSIM-CMG further approximates the simulation model of the triple-gate FinFET by adopting different short-channel effects and quantum effects on the basis of the simulation model of the double-sided gate FinFET, which largely avoids the solution of the complex Poisson equation and has a fast simulation speed.

[0004] However, due to the complexity of the three-dimensional structure, it is often unrealistic to fabricate a FinFET with two vertical sidewalls in the longitudinal section of the fin in terms of technology. The change in the shape or size of each FinFET will bring a significant difference in electrical properties. For example, when the fin has different widths at different heights, the fin will have different threshold voltages at different heights. If the BSIM-CMG model is used, when the device transitions from weak inversion to strong inversion (near vth), the model often has difficulty simulating the leakage current parameters and gate voltage parameters of the real FinFET. Therefore, the deviation between the simulation curves of the leakage current parameters and gate voltage parameters and the actual leakage current parameters and gate voltage parameters curves is relatively large. Specifically, the deviation between the simulation curves of the leakage current parameters and gate voltage parameters near vth and the actual leakage current parameters and gate voltage parameters curves is relatively large. If the derivative of this section of the simulation curve is calculated, the value after derivation will deviate even more from the value of the actual curve. However, this section of the simulation curve is very important in the subsequent parameter solving of circuits such as RF. Therefore, once there is a large deviation between this section of the simulation curve and the actual curve, it will seriously affect the parameters of subsequent circuits such as RF. Therefore, it is inaccurate to use the BSIM-CMG model of the prior art to describe the fitting curves of the drain current and gate voltage of the triple-gate FinFET with non-vertical sidewalls in the longitudinal section of the fin. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for simulating and calculating the drain current and gate voltage of a FinFET, which can simulate the drain current and gate voltage closer to the actual FinFET, making the fitting curves of the drain current and gate voltage closer to the curves of the actual drain current and gate voltage of the FinFET.

[0006] To achieve the above object, the present invention provides a method for simulating the fitting curve of the drain current and gate voltage of a FinFET, including:

[0007] Determine whether the FinFET to be simulated is a triple-gate FinFET with non-vertical wall fins;

[0008] If it is a triple-gate FinFET with non-vertical wall fins, obtain a simulation circuit diagram of a triple-gate FinFET with vertical wall fins or a simulation circuit diagram in which a surround-gate FinFET is connected in parallel with a number of double-gate FinFETs; and

[0009] Simulate the simulation circuit diagram, including: debugging the fitting parameters of the double-gate FinFET, and at the same time, debugging the fitting parameters of the triple-gate FinFET with vertical wall fins or the fitting parameters of the surround-gate FinFET, so that the output fitting curve is close to the curve of the actual drain current and gate voltage of the triple-gate FinFET with non-vertical wall fins.

[0010] Optionally, in the simulation method of the fitting curve of the drain current and gate voltage of the FinFET, the longitudinal cross-section of the fins of the triple-gate FinFET with non-vertical wall fins is trapezoidal.

[0011] Optionally, in the simulation method of the fitting curve of the drain current and gate voltage of the FinFET, use the BSIM-CMG model to simulate the simulation circuit diagram.

[0012] Optionally, in the simulation method of the fitting curve of the drain current and gate voltage of the FinFET, it further includes: constructing a netlist for the simulation circuit diagram.

[0013] Optionally, in the simulation method of the fitting curve of the drain current and gate voltage of the FinFET, the simulation circuit diagram includes: a double-gate FinFET and a triple-gate FinFET with vertical wall fins connected in parallel.

[0014] Optionally, in the simulation method of the fitting curve of the drain current and gate voltage of the FinFET, the simulation circuit diagram includes: two double-gate FinFETs and a triple-gate FinFET with vertical wall fins connected in parallel.

[0015] Optionally, in the simulation method of the fitting curve of the drain current and gate voltage of the FinFET, the simulation circuit diagram includes: three double-gate FinFETs and a triple-gate FinFET with vertical wall fins connected in parallel.

[0016] Optionally, in the simulation method of the fitting curve of the drain current and gate voltage of the FinFET, the simulation circuit diagram includes: a double-gate FinFET and a surround-gate FinFET connected in parallel.

[0017] Optionally, in the simulation method of the fitting curve of the FinFET drain current and gate voltage, the simulation circuit diagram includes: two double-gate FinFETs and one surround-gate FinFET in parallel.

[0018] Optionally, in the simulation method of the fitting curve of the FinFET drain current and gate voltage, the simulation circuit diagram includes: three double-gate FinFETs and one surround-gate FinFET in parallel.

[0019] In the simulation method of the fitting curve of the FinFET drain current and gate voltage provided by the present invention, it is determined whether the FinFET to be simulated is a triple-gate FinFET with non-vertical wall fins; if it is a triple-gate FinFET with non-vertical wall fins, a simulation circuit diagram of one triple-gate FinFET with vertical wall fins or one surround-gate FinFET and several double-gate FinFETs in parallel is obtained; the simulation circuit diagram is simulated, including: debugging the fitting parameters of the double-gate FinFET, and at the same time, debugging the fitting parameters of the triple-gate FinFET with vertical wall fins or the fitting parameters of the surround-gate FinFET, so that the output fitting curve is close to the curve of the actual drain current and gate voltage of the triple-gate FinFET with non-vertical wall fins. The present invention can simulate the drain current and gate voltage closer to the actual FinFET, making the fitting curve of the drain current and gate voltage closer to the curve of the actual drain current and gate voltage of the FinFET. Description of the Drawings

[0020] Figure 1 is the simulation method of the fitting curve of the FinFET drain current and gate voltage according to the embodiment of the present invention. Detailed Embodiments

[0021] The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0022] In the following text, terms such as "first" and "second" are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is understood that, where appropriate, these terms may be replaced. Similarly, if the method described herein includes a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be executed, and some of the described steps may be omitted and / or some other steps not described herein may be added to the method.

[0023] Please refer to Figure 1, the present invention provides a simulation method for the fitting curve of the drain current and gate voltage of a FinFET, including:

[0024] Step S11: Determine whether the FinFET to be simulated is a triple-gate FinFET with non-vertical wall fins;

[0025] Step S12: If it is a triple-gate FinFET with non-vertical wall fins, obtain a simulation circuit diagram of a triple-gate FinFET with vertical wall fins or a simulation circuit diagram of a surround-gate FinFET in parallel with several double-gate FinFETs; and

[0026] Step S13: Simulate the simulation circuit diagram, including: debugging the fitting parameters of the double-gate FinFET, and at the same time, debugging the fitting parameters of the triple-gate FinFET with vertical wall fins or the fitting parameters of the surround-gate FinFET, so that the output fitting curve is close to the curve of the actual drain current and gate voltage of the triple-gate FinFET with non-vertical wall fins.

[0027] In the embodiment of the present invention, the longitudinal section of the fins of the triple-gate FinFET with non-vertical wall fins is trapezoidal.

[0028] Preferably, the BSIM-CMG model is used to simulate the simulation circuit diagram. The BSIM-CMG model can simulate double-gate FinFETs, triple-gate FinFETs with vertical wall fins, and surround-gate FinFETs, but the settings are different. In the embodiment of the present invention, a parallel combination of double-gate FinFETs and triple-gate FinFETs with vertical wall fins or a parallel combination of double-gate FinFETs and surround-gate FinFETs is used for simulation to obtain the final fitting curve, which is closer to the curve of the actual drain current and gate voltage of the triple-gate FinFET with non-vertical wall fins than directly using the fitting curve of the triple-gate FinFET with vertical wall fins.

[0029] Further, the simulation method for the fitting curve of the drain current and gate voltage of a FinFET further includes: constructing a netlist for the simulation circuit diagram. For example, the netlists of Embodiment 1, Embodiment 2, and Embodiment 4. In the embodiment of the present invention, a simulation software can be used to automatically output the fitting curve.

[0030] In Embodiment 1, the simulation circuit diagram includes: a double-gate FinFET and a triple-gate FinFET with vertical wall fins in parallel. The netlist constructed for the simulation circuit diagram of Embodiment 1 is as follows:

[0031] double-gate&&triple-gate FET # a double-gate FinFET and a triple-gate FinFET with vertical wall fins

[0032] .subckt NFet d g s b # Define a sub - circuit with four ports d, g, s, and b, named NFet

[0033] m1 d g s b NFet1 l=1.4e - 10 nf=1 nfin=6 m=1 # m1 calls the mos model, d, g, s, b are the four ports of the model, l = 1.4e - 10, nf = 1, nfin = 6, and m = 1 are the device instances

[0034] .MODEL NFet1 nmos

[0035] +level=72 version=110geomod=1 # level = 72 and version = 110 are the model versions, geomod = 1 means using the TG model

[0036] +devtype=1 tfin=1.1e - 10 # The following are the model parameters

[0037] +phig=4.7

[0038] m2 d g s b NFet2 l=1.4e - 10 nf=1 nfin=6m=1

[0039] .MODEL NFet2 nmos

[0040] +level=72 version=110geomod=0 # geomod = 0 means using the DG model

[0041] +devtype=1 tfin=1.4e - 10

[0042] +phig=4.3

[0043] .ends NFet

[0044] Embodiment 2, the simulation circuit diagram includes: two double - gate FinFETs and one triple - gate FinFET with vertical - wall fins in parallel.

[0045] .subckt NFet d g s b

[0046] m1 d g s b NFet1 l=1.4e - 10 nf=1 nfin=6 m=1

[0047] .MODEL NFet1 nmos

[0048] +level=72 version=110geomod=1

[0049] +devtype = 1 tfin = 1.1e-10

[0050] +phig = 4.7

[0051] m2 d g s b NFet2 l = 1.4e-10 nf = 1 nfin = 6 m = 1

[0052] .MODEL NFet2 nmos

[0053] +level = 72 version = 110 geomod = 0

[0054] +devtype = 1 tfin = 1.4e-10

[0055] +phig = 4.3

[0056] m3 d g s b NFet3 l = 1.4e-10 nf = 1 nfin = 6 m = 1

[0057] .MODEL NFet3 nmos

[0058] +level = 72 version = 110 geomod = 0

[0059] +devtype = 1 tfin = 1.4e-10

[0060] +phig = 4.1

[0061] .ends NFet

[0062] Example 3, the simulation circuit diagram includes: three double-gate FinFETs and one triple-gate FinFET with a vertical-wall fin in parallel.

[0063] Example 4, the simulation circuit diagram includes: one double-gate FinFET and one surround-gate FinFET in parallel.

[0064] double-gate && surround-gate FET

[0065] .subckt NFet d g s b

[0066] m1 d g s b NFet1 l = 1.4e-10 nf = 1 nfin = 6 m = 1

[0067] .MODEL NFet1 nmos

[0068] +level=72 version=110 geomod=3 #geomod=3 is the SG model used

[0069] +devtype=1 tfin=1.1e - 10

[0070] +phig=4.7

[0071] m2 d g s b NFet2 l=1.4e - 10 nf=1 nfin=6 m=1

[0072] .MODEL NFet2 nmos

[0073] +level=72 version=110 geomod=0

[0074] +devtype=1 tfin=1.4e - 10

[0075] +phig=4.3

[0076] .ends NFet

[0077] Example 5, the simulation circuit diagram includes: two double - gate FinFETs and one surround - gate FinFET in parallel.

[0078] Example 6, the simulation circuit diagram includes: three double - gate FinFETs and one surround - gate FinFET in parallel. The netlists of Example 3, Example 4, and Example 6 can be designed with reference to Example 1, Example 2, and Example 5, so they will not be elaborated here.

[0079] In other embodiments of the present invention, it can also be a combination of other double - gate FinFETs and FINFETs with vertical - wall fins or surround - gate FinFETs. The embodiments of the present invention will not be elaborated here.

[0080] In summary, in the simulation method of the fitting curve of the drain current and gate voltage of the FinFET provided by the embodiment of the present invention, it is determined whether the FinFET to be simulated is a triple-gate FinFET with non-vertical wall fins; if it is a triple-gate FinFET with non-vertical wall fins, a simulation circuit diagram of a triple-gate FinFET with vertical wall fins or a surround-gate FinFET in parallel with several double-gate FinFETs is obtained; the simulation circuit diagram is simulated, including: debugging the fitting parameters of the double-gate FinFET, and at the same time, debugging the fitting parameters of the triple-gate FinFET with vertical wall fins or the fitting parameters of the surround-gate FinFET, so that the output fitting curve is close to the curve of the actual drain current and gate voltage of the triple-gate FinFET with non-vertical wall fins. The present invention can simulate the drain current and gate voltage closer to the actual FinFET, making the fitting curve of the drain current and gate voltage closer to the curve of the actual drain current and gate voltage of the FinFET.

[0081] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A simulation method for the fitting curve of the drain current and gate voltage of a FinFET, characterized in that, Comprising: Determine whether the FinFET to be simulated is a triple-gate FinFET with non-vertical wall fins; If it is a triple-gate FinFET with non-vertical wall fins, obtain a simulation circuit diagram of a triple-gate FinFET with vertical wall fins in parallel with a plurality of double-gate FinFETs or a simulation circuit diagram of a gate-all-around FinFET in parallel with a plurality of double-gate FinFETs; And Simulate the said simulation circuit diagram, including: debugging the fitting parameters of the double-gate FinFET, and at the same time, debugging the fitting parameters of the triple-gate FinFET with vertical wall fins or the fitting parameters of the gate-all-around FinFET, so that the output fitting curve is close to the curve of the actual drain current and gate voltage of the triple-gate FinFET with non-vertical wall fins.

2. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, The longitudinal section of the fins of the triple-gate FinFET with non-vertical wall fins is trapezoidal in shape.

3. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, Use the BSIM-CMG model to simulate the said simulation circuit diagram.

4. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, Also comprising: Construct a netlist for the said simulation circuit diagram.

5. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, The said simulation circuit diagram includes: a double-gate FinFET and a triple-gate FinFET with vertical wall fins in parallel.

6. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, The said simulation circuit diagram includes: two double-gate FinFETs and a triple-gate FinFET with vertical wall fins in parallel.

7. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, The said simulation circuit diagram includes: three double-gate FinFETs and a triple-gate FinFET with vertical wall fins in parallel.

8. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, The said simulation circuit diagram includes: a double-gate FinFET and a gate-all-around FinFET in parallel.

9. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, The said simulation circuit diagram includes: two double-gate FinFETs and a gate-all-around FinFET in parallel.

10. The simulation method for the fitting curve of the drain current and gate voltage of a FinFET according to claim 1, characterized in that, The said simulation circuit diagram includes: three double-gate FinFETs and a gate-all-around FinFET in parallel.

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