A GOA unit and its driving method, and GOA circuit

Abstract

A GOA unit and a driving method thereof, and a GOA circuit, relate to the field of liquid crystal display technology, and can compensate for leakage in a circuit, fully open a transistor, and reduce the time it takes for the output signal of the circuit to fall. The gate drive GOA unit includes: an input subcircuit, an output subcircuit, and a compensation subcircuit. The input subcircuit is coupled to a pull-up control node and an input signal terminal, and is configured to transmit a signal from the input signal terminal to the pull-up control node. The output subcircuit is coupled to a first clock signal terminal and a pull-up control node, and is configured to receive a first clock signal from the first clock signal terminal, and output the first clock signal under the action of the pull-up control node. The compensation subcircuit is coupled to the pull-up control node and the output subcircuit, and is configured to compensate for at least part of the output signal terminal of the pull-up control node and / or the GOA unit.

Description

Technical Field

[0001] The present application relates to the field of liquid crystal display technology, and in particular to a GOA unit and a driving method thereof, and a GOA circuit. Background Art

[0002] With the development of electronic technology, gate on array (GOA) circuits have been widely used in display devices due to their narrow borders and low costs.

[0003] However, since there are a large number of noise reduction units in the GOA circuit, these noise reduction units will leak when not working, causing the voltage of the pull-up control node in the GOA circuit to drop significantly after the second stage of pull-up, resulting in insufficient opening of the transistor connected to the output signal end. The time required for the voltage at the output signal end to drop from 90% to 10% is long, resulting in incorrect charging or insufficient charging. Summary of the invention

[0004] The embodiments of the present application provide a GOA unit and a driving method thereof, and a GOA circuit, which can compensate for leakage in the circuit, fully open the transistor for outputting signals, reduce the time it takes for the output signal of the circuit to fall, and obtain a better display effect.

[0005] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0006] On the one hand, a GOA unit is provided, comprising: an input subcircuit, an output subcircuit and a compensation subcircuit. The input subcircuit is coupled to a pull-up control node and an input signal terminal, and is configured to transmit a signal from the input signal terminal to the pull-up control node. The output subcircuit is coupled to a first clock signal terminal and a pull-up control node, and is configured to receive a first clock signal from the first clock signal terminal, and output the first clock signal under the action of the pull-up control node. The compensation subcircuit is coupled to the pull-up control node and the output subcircuit, and is configured to compensate for at least part of the output signal terminal of the pull-up control node and / or the GOA unit.

[0007] In some embodiments, the output subcircuit includes: a first transistor, a second transistor and a first capacitor. The control terminal of the first transistor is coupled to the first electrode of the first capacitor, the control terminal of the second transistor and the pull-up control node, the first electrode of the first transistor is coupled to the first clock signal terminal, the second electrode of the first transistor is coupled to the second electrode of the first capacitor, and the second electrode of the first transistor is coupled to the first output signal terminal of the GOA unit. The first electrode of the second transistor is coupled to the first clock signal terminal, and the second electrode of the second transistor is coupled to the second output signal terminal of the GOA unit.

[0008] In some embodiments, the compensation subcircuit includes: a third transistor, the first electrode of the third transistor is coupled to the second clock signal terminal, the control terminal of the third transistor is coupled to the second electrode of the second transistor, and the second electrode of the third transistor is coupled to the pull-up control node; wherein the second clock signal at the second clock signal terminal is a constant voltage signal.

[0009] In some embodiments, the compensation subcircuit also includes: a fourth transistor and a second capacitor, the first electrode of the fourth transistor is coupled to the second clock signal end, the control end of the fourth transistor is coupled to the pull-up control node and the first electrode of the second capacitor, and the second electrode of the fourth transistor is coupled to the second electrode of the second capacitor; wherein the second clock signal at the second clock signal end is an upstream signal of the first clock signal.

[0010] In some embodiments, the compensation subcircuit further includes: a third capacitor, a first electrode of the third capacitor is coupled to the first signal line or the second signal line, the first signal line is used to receive the third clock signal, the second signal line is used to receive the fourth clock signal, and the second electrode of the third capacitor is coupled to the first output signal terminal of the GOA unit. The third capacitor is configured to compensate the first output signal terminal based on the third clock signal and the first clock signal; or, to compensate the first output signal terminal based on the fourth clock signal and the first clock signal.

[0011] In some embodiments, the GOA unit further includes a first reset subcircuit and a second reset subcircuit, the first reset subcircuit is configured to reset the pull-up control node, and the second reset subcircuit is configured to reset the pull-up control node and the output signal terminal of the GOA unit.

[0012] In some embodiments, the first reset subcircuit includes a fifth transistor, a first electrode of the fifth transistor is coupled to the pull-up control node, a control terminal of the fifth transistor is coupled to the reset signal terminal, and a second electrode of the fifth transistor is coupled to the first voltage terminal. The second reset subcircuit includes a sixth transistor, a seventh transistor, and an eighth transistor, a control terminal of the sixth transistor, a control terminal of the seventh transistor, and a control terminal of the eighth transistor are all coupled to the pull-down control node; a first electrode of the sixth transistor is coupled to the pull-up control node, and a second electrode of the sixth transistor is coupled to the first voltage terminal; a first electrode of the seventh transistor is coupled to the first output signal terminal of the GOA circuit, and a second electrode of the seventh transistor is coupled to the third voltage terminal; a first electrode of the eighth transistor is coupled to the second output signal terminal of the GOA circuit, and a second electrode of the eighth transistor is coupled to the first voltage terminal.

[0013] In some embodiments, the GOA unit further includes: a first control subcircuit and a second control subcircuit. The first control subcircuit is coupled to the pull-down control node, the pull-up control node and the first voltage terminal, and is configured to control the signal of the pull-down control node to be a second level signal when the signal of the pull-up control node is a first level signal. The second control subcircuit is coupled to the second voltage terminal and the pull-down control node, and is configured to control the signal of the pull-down control node to be a first level signal when the signal of the pull-up control node is a second level signal.

[0014] In some embodiments, the first control subcircuit includes a ninth transistor and a tenth transistor, the control terminal of the ninth transistor and the control terminal of the tenth transistor are both coupled to the pull-up control node, the second electrode of the ninth transistor and the second electrode of the tenth transistor are both coupled to the first voltage terminal, and the first electrode of the tenth transistor is coupled to the pull-down control node. The second control subcircuit includes an eleventh transistor and a twelfth transistor, the first electrode of the eleventh transistor, the control terminal of the eleventh transistor, and the first electrode of the twelfth transistor are all coupled to the second voltage terminal, the second electrode of the eleventh transistor is coupled to the first electrode of the ninth transistor and the control terminal of the twelfth transistor, and the second electrode of the twelfth transistor is coupled to the pull-down control node.

[0015] In some embodiments, the input sub-circuit includes a thirteenth transistor, a first electrode of the thirteenth transistor and a control terminal of the thirteenth transistor are coupled to the input signal terminal, and a second electrode of the thirteenth transistor is coupled to the pull-up control node.

[0016] On the other hand, a GOA circuit is provided, comprising N cascaded GOA units as in any of the above embodiments. A first electrode of a third capacitor of an i-th GOA unit among the N GOA units is coupled to a first signal line, where i is an odd number greater than or equal to 1 and less than or equal to N. A first electrode of a third capacitor of a j-th GOA unit among the N GOA units is coupled to a second signal line, where j is an even number greater than 1 and less than or equal to N.

[0017] In some embodiments, the first signal line is used to receive a third clock signal, the second signal line is used to receive a fourth clock signal, the third clock signal at least partially overlaps with the effective level of the first clock signal, and the fourth clock signal at least partially overlaps with the effective level of the first clock signal.

[0018] On the other hand, a driving method for a GOA unit is provided, comprising: an input subcircuit transmits a signal from an input signal end to a pull-up control node; an output subcircuit receives a first clock signal from a first clock signal end, and outputs the first clock signal under the action of the pull-up control node; and a compensation subcircuit compensates for the pull-up control node and / or at least part of the output signal end of the GOA unit.

[0019] In some embodiments, the compensation subcircuit compensates for at least part of the output signal end of the pull-up control node and / or the GOA unit, including: after the voltage of the pull-up control node is pulled up for the second time by the output subcircuit, the compensation subcircuit charges the pull-up control node to maintain the voltage of the pull-up control node.

[0020] In some embodiments, the compensation subcircuit compensates for at least part of the output signal end of the pull-up control node and / or the GOA unit, including: the compensation subcircuit pulls up the voltage of the pull-up control node for a second time.

[0021] In some embodiments, the driving method of the GOA unit further includes: the output sub-circuit pulls up the voltage of the pull-up control node for a third time.

[0022] In some embodiments, at least part of the output signal end of the GOA unit includes a first output signal end, and the compensation subcircuit compensates for the pull-up control node and / or at least part of the output signal end of the GOA unit, including: the compensation subcircuit compensates the first output signal end based on the third clock signal and the first clock signal; or, compensates the first output signal end based on the fourth clock signal and the first clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0024] Figure 1 is a structural diagram of a GOA unit in the related art;

[0025] Figure 2 is a signal timing diagram of a GOA unit in the related art;

[0026] Figure 3 is a structural diagram of a display panel according to some embodiments;

[0027] Figure 4 is a block diagram of a GOA unit according to some embodiments;

[0028] Figure 5 is a circuit diagram of a GOA unit according to some embodiments;

[0029] Figure 6 is a signal timing diagram of a GOA unit according to some embodiments;

[0030] Figure 7 is a circuit diagram of yet another GOA unit according to some embodiments;

[0031] Figure 8 is a signal timing diagram of another GOA unit according to some embodiments;

[0032] Fig. 9 is a circuit diagram of yet another GOA unit according to some embodiments;

[0033] Fig.10 is a circuit diagram of yet another GOA unit according to some embodiments;

[0034] Fig.11 is a circuit diagram of yet another GOA unit according to some embodiments;

[0035] Fig.12 is a schematic diagram of connection between a signal line and a first output signal terminal according to some embodiments;

[0036] Fig.13 is a corresponding timing diagram of a clock signal of a signal line and a first clock signal according to some embodiments. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments applied for here are not necessarily limited to the contents of this document.

[0041] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0042] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0043] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0044] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0045] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0046] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0047] Throughout the specification, reference to "one embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment. Therefore, the phrase "in one embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0048] The first electrode of the transistor in the embodiment of the present application may be one of the source and the drain, and the second electrode of the transistor may be the other of the source and the drain. Since the source and drain of the transistor may be symmetrical in structure, there may be no difference in structure between the source and the drain, that is, there may be no difference in structure between the first electrode and the second electrode of the transistor in the embodiment of the present application. Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source. The following embodiment is exemplified by taking the transistor in the GOA unit as an N-type transistor as an example.

[0049] Figure 1 is a circuit diagram of a GOA unit, such as Figure 1As shown, the GOA unit includes multiple transistors and a capacitor C. Figure 2 , taking the GOA unit including multiple transistors of N-type as an example, the working principle of the GOA unit is introduced in four stages.

[0050] In the first stage t1, the input signal input of the input signal terminal INPUT is at a high level, the thirteenth transistor M13 is turned on, the input signal input is written to the pull-up control node PU, and the voltage of the pull-up control node PU is pulled up for the first time. At this time, the pull-up control node PU is at a high level, the first transistor M1 and the second transistor M2 are turned on, and the first clock signal clk1 is at a low level, so the first output signal g_out output by the first output signal terminal G_OUT and the second output signal out_c output by the second output signal terminal OUT_C ​​are both at a low level. The ninth transistor M9 to the twelfth transistor M12 are turned on, and since the first voltage terminal LVGL is a constant voltage low level signal, the first voltage terminal LVGL pulls the signal of the pull-down control node PD down to a low level. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0051] It should be noted that the second voltage terminal VDD1 is a constant voltage high level signal, and the eleventh transistor M11 and the twelfth transistor M12 always remain in an on state at the first level of the second voltage terminal VDD1. However, since the driving capability of the ninth transistor M9 is greater than the driving capability of the eleventh transistor M11, and the driving capability of the tenth transistor M10 is greater than the driving capability of the twelfth transistor M12, when the ninth transistor M9 to the twelfth transistor M12 are all turned on, the voltage of the second electrode of the eleventh transistor M11 is determined by the ninth transistor M9, and the voltage of the pull-down control node PD is determined by the tenth transistor M10. That is, when the tenth transistor M10 and the twelfth transistor M12 are both turned on, the first voltage terminal LVGL pulls the voltage of the pull-down control node PD down to a low level through the tenth transistor M10.

[0052] In the second stage t2, the input signal input of the input signal terminal INPUT is at a low level, and the thirteenth transistor M13 is turned off. The first transistor M1 and the second transistor M2 remain turned on, and the first clock signal clk1 is at a high level, so that the first output signal g_out and the second output signal out_c are both at a high level. Due to the bootstrap effect of the first capacitor C1, the voltage of the pull-up control node PU is pulled up for the second time. The ninth transistor M9 to the twelfth transistor M12 remain turned on, and the signal of the pull-down control node PD remains at a second level. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0053] In the third stage t3, the first transistor M1 and the second transistor M2 remain turned on. Since the first clock signal clk1 is at a low level, the first output signal g_out and the second output signal out_c are both at a low level. The voltage of the pull-up control node PU is pulled down for the first time by the first output signal g_out and the second output signal out_c. The ninth transistor M9 to the twelfth transistor M12 remain turned on, and the signal of the pull-down control node PD remains at a second level. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0054] In the fourth stage t4, the signal rst of the reset signal terminal RST is at a high level, the fifth transistor M5 is turned on, and the low level signal of the first voltage terminal LVGL pulls down the voltage of the pull-up control node PU for the second time through the fifth transistor M5, and the voltage of the pull-up control node PU is pulled down to a low level, and the first transistor M1, the second transistor M2, the ninth transistor M9 and the tenth transistor M10 are turned off. The eleventh transistor M11 and the twelfth transistor M12 remain turned on, and the high level of the second voltage terminal VDD2 makes the pull-down control node PD at a high level through the twelfth transistor M12. The high level of the pull-down control node PD turns on the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8, and performs noise reduction on the pull-up control node PU and the first output signal terminal G_OUT.

[0055] like Figure 2 As shown, due to Figure 1 There are a large number of noise reduction units (for example, the fifth transistor M5 to the twelfth transistor M12) in the GOA unit shown. These noise reduction units do not work during the voltage holding stage of the pull-up control node PU, which will cause leakage, causing the pull-up control node PU to be in the holding stage after the second stage of pulling up (such as Figure 2 The voltage drop in the t2 phase shown in the figure is large, causing the first transistor M1 to be insufficiently turned on, resulting in the first output signal g_out Tf being too large, which may cause charging errors or insufficient charging. g_out Tf, or g_out Time Fall, refers to the time it takes for the g_out voltage to drop from 90% to 10%.

[0056] To this end, some embodiments of the present application provide a display device 30, which can be any device with a display function, such as a tablet computer, a monitor, a mobile phone, a billboard, a digital photo frame or a personal digital assistant (PDA).

[0057] Exemplarily, the display device 30 may be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QLED) display device, or an active-matrix organic light emitting diode (AMOLED) display device. The embodiment of the present application does not impose any special restrictions on the specific type of the display device 30. The following embodiments are described in detail by taking an OLED display device as an example.

[0058] like Figure 3 As shown, the display device 30 includes a display area A and a peripheral area B arranged on at least one side of the display area A. The display area A is an area for displaying an image, and the display area A is configured to set a sub-pixel P. The peripheral area B is an area for not displaying an image, and the peripheral area B is configured to set a display driving circuit, for example, a GOA circuit.

[0059] The multiple sub-pixels P are arranged in multiple rows and multiple columns, each row includes multiple sub-pixels P arranged along the first direction X, and each column includes multiple sub-pixels P arranged along the second direction Y. Each row of sub-pixels P may include multiple sub-pixels P, and each column of sub-pixels P may include multiple sub-pixels P.

[0060] In some embodiments, Figure 3 As shown, the display device 30 may further include a plurality of gate lines GL and a plurality of data lines DL located in the display area A. The plurality of gate lines GL extend along a first direction X, and the plurality of data lines DL extend along a second direction Y.

[0061] For example, sub-pixels P arranged in a row along the first direction X may be referred to as sub-pixels P in the same row, and sub-pixels P arranged in a column along the second direction Y may be referred to as sub-pixels P in the same column. Sub-pixels P in the same row may be coupled to the same gate line GL, and sub-pixels P in the same column may be coupled to the same data line DL.

[0062] Each sub-pixel P may include a pixel circuit and a light-emitting element coupled to the pixel circuit. A gate line GL may be coupled to multiple pixel circuits in the same row of sub-pixels P, and a data line DL may be coupled to multiple pixel circuits in the same column of sub-pixels P.

[0063] A plurality of cascaded GOA units may be provided in the peripheral area B. For each sub-pixel P, its pixel circuit may receive a GOA driving signal from the GOA unit through the gate line GL, and receive a voltage signal at the data voltage end through the data line DL, so that the pixel circuit drives the corresponding light-emitting element to emit light according to the voltage signal at the data voltage end under the control of the GOA driving signal.

[0064] Some embodiments of the present application provide a GOA unit, such as Figure 4 As shown, the GOA unit 40 includes: an input subcircuit 41, an output subcircuit 42, a compensation subcircuit 43, a first control subcircuit 44, a second control subcircuit 45, a first reset subcircuit 46 and a second reset subcircuit 47.

[0065] The input sub-circuit 41 is coupled to the pull-up control node PU and the input signal terminal INPUT, and is configured to transmit the input signal input of the input signal terminal INPUT to the pull-up control node PU.

[0066] The output sub-circuit 42 is coupled to the first clock signal terminal CLK1 and the pull-up control node PU, and is configured to: receive the first clock signal clk1 from the first clock signal terminal CLK1, and output the first clock signal clk1 under the action of the pull-up control node PU.

[0067] The compensation sub-circuit 43 is coupled to the pull-up control node PU and the output sub-circuit, and is configured to compensate for at least part of the output signal end of the pull-up control node PU and / or the GOA unit.

[0068] Exemplarily, the compensation subcircuit 43 in the embodiment of the present application can only compensate the pull-up control node PU, or only compensate at least part of the output signal terminal (for example, the first output signal terminal G_OUT) of the GOA unit, or simultaneously compensate the pull-up control node PU and the first output signal terminal G_OUT. In the embodiment of the present application, by adding a compensation subcircuit 43 in the GOA unit, the pull-up control node PU and / or the first output signal terminal G_OUT are compensated by the compensation subcircuit 43, so that the pull-up control node PU can maintain a high voltage, fully open the first transistor M1 and the second transistor M2, reduce the time for the output signal g_out of the GOA unit to fall, and obtain a better display effect.

[0069] The first control subcircuit 44 is coupled to the pull-down control node PD, the pull-up control node PU and the first voltage terminal LVGL, and is configured to: when the signal of the pull-up control node PU is a first level signal, control the signal of the pull-down control node PD to be a second level signal. The embodiment of the present application is exemplified by taking the first level signal as a high level signal and the second level signal as a low level signal as an example.

[0070] The second control sub-circuit 45 is coupled to the second voltage terminal VDD1 and the pull-down control node PD, and is configured to control the signal of the pull-down control node PD to be a first level signal when the signal of the pull-up control node PU is a second level signal.

[0071] The first reset sub-circuit 46 is coupled to the reset signal terminal RST, the pull-up control node PU and the first voltage terminal LVGL. The first reset sub-circuit is configured to reset the pull-up control node PU.

[0072] The second reset subcircuit 47 is coupled to the pull-down control node PD, the pull-up control node PU and the first voltage terminal LVGL, and is configured to reset the pull-up control node PU and the output signal terminal of the GOA unit. The output signal terminal of the GOA unit includes a first output signal terminal G_OUT and a second output signal terminal OUT_C.

[0073] Some embodiments of the present application provide a circuit diagram of a GOA unit, such as Figure 5 shown.

[0074] The input sub-circuit 41 includes a thirteenth transistor M13. The first electrode of the thirteenth transistor M13 and the control end of the thirteenth transistor M13 are coupled to the input signal terminal INPUT, and the second electrode of the thirteenth transistor M13 is coupled to the pull-up control node PU. The input signal input of the input signal terminal INPUT can be the signal stv of the frame start discharge signal terminal STV, or the second output signal out_c output by the second output signal terminal OUT_C ​​of the previous GOA unit.

[0075] Exemplarily, the first electrode of the thirteenth transistor M13 and the control terminal of the thirteenth transistor M13 may be coupled together or not. For example, the first electrode of the thirteenth transistor M13 and the control terminal of the thirteenth transistor M13 may also be coupled to different high-level signal terminals respectively.

[0076] The output subcircuit 42 includes: a first transistor M1, a second transistor M2 and a first capacitor C1. The control end of the first transistor M1 is coupled to the first electrode of the first capacitor C1, the control end of the second transistor M2 and the pull-up control node PU, the first electrode of the first transistor M1 is coupled to the first clock signal terminal CLK1, the second electrode of the first transistor M1 is coupled to the second electrode of the first capacitor C1, and the second electrode of the first transistor M1 is coupled to the first output signal terminal G_OUT of the GOA unit. The first electrode of the second transistor M2 is coupled to the first clock signal terminal CLK1, and the second electrode of the second transistor M2 is coupled to the second output signal terminal OUT_C ​​of the GOA unit.

[0077] The first control subcircuit 44 includes a ninth transistor M9 and a tenth transistor M10. The control end of the ninth transistor M9 and the control end of the tenth transistor M10 are both coupled to the pull-up control node PU, the second electrode of the ninth transistor M9 and the second electrode of the tenth transistor M10 are both coupled to the first voltage terminal LVGL. The first electrode of the tenth transistor M10 is coupled to the pull-down control node PD.

[0078] The second control subcircuit 45 includes: an eleventh transistor M11 and a twelfth transistor M12. A first electrode of the eleventh transistor M11, a control terminal of the eleventh transistor M11, and a first electrode of the twelfth transistor M12 are all coupled to the second voltage terminal VDD1. A second electrode of the eleventh transistor M11 is coupled to a first electrode of the ninth transistor M9 and a control terminal of the twelfth transistor M12, and a second electrode of the twelfth transistor M12 is coupled to a pull-down control node PD.

[0079] Exemplarily, the first electrode of the eleventh transistor M11 and the control end of the eleventh transistor M11 may be coupled together, or may be respectively coupled to different signal ends, which is not limited in the embodiment of the present application.

[0080] The first reset sub-circuit 46 includes a fifth transistor M5 . A first electrode of the fifth transistor M5 is coupled to the pull-up control node PU, a control terminal of the fifth transistor M5 is coupled to the reset signal terminal RST, and a second electrode of the fifth transistor M5 is coupled to the first voltage terminal LVGL.

[0081] The second reset sub-circuit 47 includes: a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8. The control end of the sixth transistor M6, the control end of the seventh transistor M7 and the control end of the eighth transistor M8 are all coupled to the pull-down control node PD. The first electrode of the sixth transistor M6 is coupled to the pull-up control node PU, and the second electrode of the sixth transistor M6 is coupled to the first voltage terminal LVGL. The first electrode of the seventh transistor M7 is coupled to the first output signal terminal G_OUT, and the second electrode of the seventh transistor M7 is coupled to the third voltage terminal VGL. The first electrode of the eighth transistor M8 is coupled to the second output signal terminal OUT_C, and the second electrode of the eighth transistor M8 is coupled to the first voltage terminal LVGL.

[0082] The compensation subcircuit 43 in the embodiment of the present application can compensate the pull-up control node PU and / or the first output signal terminal G_OUT through a variety of different circuit structures. The circuit structure of the compensation subcircuit 43 and the working principle of the GOA unit are introduced in three cases below.

[0083] The first case, such as Figure 5As shown, the compensation sub-circuit 43 includes: a third transistor M3, a first electrode of the third transistor M3 is coupled to the second clock signal terminal CLK2, a control terminal of the third transistor M3 is coupled to the second electrode of the second transistor M2, and a second electrode of the third transistor M3 is coupled to the pull-up control node PU. Among them, the second clock signal clk2 of the second clock signal terminal CLK2 is a constant voltage signal clkb that is substantially equivalent to the voltage of the pull-up control node PU. For example, the second clock signal clk2 is a constant voltage signal clkb greater than 60V.

[0084] Figure 6 A signal timing diagram of a GOA unit is provided for some embodiments of the present application. Figure 6 , divided into four stages Figure 5 The working principle of the GOA unit shown is introduced.

[0085] In the first stage t1, the input signal input of the input signal terminal INPUT is the first level (high level), the thirteenth transistor M13 is turned on, the input signal input is written to the pull-up control node PU, and the voltage of the pull-up control node PU is pulled up for the first time. At this time, the pull-up control node PU is at a high level, so that the first transistor M1 and the second transistor M2 are turned on, and the first clock signal clk1 is at a second level (low level), so the first output signal terminal G_OUT and the second output signal terminal OUT_C ​​output a low level, that is, the first output signal g_out and the second output signal out_c are both low levels. The ninth transistor M9 to the twelfth transistor M12 are turned on, the first voltage terminal LVGL is a constant voltage low level signal, and the first voltage terminal LVGL pulls the signal of the pull-down control node PD down to a low level. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0086] In the second stage t2, the input signal input of the input signal terminal INPUT is at a low level, and the thirteenth transistor M13 is turned off. The first transistor M1 and the second transistor M2 remain turned on, and the first clock signal clk1 is at a high level, so that the first output signal g_out and the second output signal out_c are both at a high level. The second pole of the first capacitor C1 is also at a high level. Due to the bootstrap effect of the first capacitor C1, the signal of the pull-up control node PU is compensated, and the voltage of the pull-up control node PU is pulled up for the second time. The second output signal out_c is at a high level, so that the third transistor M3 is turned on. At this time, the second clock signal clkb charges the pull-up control node PU through the third transistor M3, and compensates the signal of the pull-up control node PU. The ninth transistor M9 to the twelfth transistor M12 remain turned on, and the signal of the pull-down control node PD remains at a low level. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0087] In the third stage t3, the first transistor and the second transistor remain in the on state due to the low level signal of the pull-up control node, and the first clock signal is input at a low level, so that the first output signal g_out and the second output signal out_c are both at a low level. The voltage of the pull-up control node is pulled down for the first time by the first output signal g_out and the second output signal out_c. Since the second output signal out_c is at a low level, the third transistor M3 is turned off, and the second clock signal clkb stops inputting. The ninth transistor M9 to the twelfth transistor M12 remain turned on, and the signal of the pull-down control node PD remains at a low level. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all turned off.

[0088] In the fourth stage t4, the signal rst of the reset signal terminal RST is at a high level, the fifth transistor M5 is turned on, and the low level of the first voltage terminal LVGL pulls down the voltage of the pull-up control node PU for the second time through the fifth transistor M5, and the voltage of the pull-up control node PU is pulled down to a low level. As a result, the first transistor M1, the second transistor M2, the ninth transistor M9, and the tenth transistor M10 are turned off. The eleventh transistor M11 and the twelfth transistor M12 remain turned on, and the high level of the second voltage terminal VDD2 makes the signal of the pull-down control node PD a high level through the twelfth transistor M12. The high level of the pull-down control node PD turns on the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8, and performs noise reduction on the pull-up control node PU and the first output signal terminal G_OUT.

[0089] In some embodiments, the leakage degree of the pull-up control node PU in the GOA units with different structures is different. Figure 1 In the scheme shown, the voltage drop value of the pull-up control node PU is relatively large. For example, the voltage drop value of the pull-up control node PU is about 7V or about 10V. In the embodiment of the present application, the compensation subcircuit 43 compensates the signal of the pull-up control node PU, so that the voltage of the pull-up control node PU can be maintained or have a small drop. For example, the compensation subcircuit 43 compensates the signal of the pull-up control node PU, so that the voltage drop value of the pull-up control node PU after the second pull-up can be ensured to be within 4V.

[0090] The second case, such as Figure 7 As shown, the compensation sub-circuit 43 also includes: a fourth transistor M4 and a second capacitor C2, the first electrode of the fourth transistor M4 is coupled to the second clock signal terminal CLK2, the control terminal of the fourth transistor M4 is coupled to the pull-up control node PU and the first electrode of the second capacitor C2, and the second electrode of the fourth transistor M4 is coupled to the second electrode of the second capacitor C2; wherein the second clock signal clk2 of the second clock signal terminal CLK2 is an upstream signal of the first clock signal clk1.

[0091] Exemplarily, the second clock signal clk2 may be a signal of the previous row of the first clock signal clk1, that is, the first clock signal clk1 is clk(n), and the second clock signal clk2 is clk(n-1). The second clock signal clk2 may also be a signal of the previous two rows of the first clock signal clk1, that is, the first clock signal clk1 is clk(n), and the second clock signal clk2 is clk(n-2). The present application does not limit the relationship between the second clock signal clk2 and the first clock signal clk1.

[0092] Figure 8 Another signal timing diagram of a GOA unit is provided for some embodiments of the present application. Figure 8 , divided into six stages Figure 7 The working principle of the GOA unit shown is introduced.

[0093] In the first stage t1, the input signal input of the input signal terminal INPUT is at a high level, the thirteenth transistor M13 is turned on, the input signal input is written to the pull-up control node PU, and the voltage of the pull-up control node PU is pulled up for the first time. At this time, the pull-up control node PU is at a high level, so that the first transistor M1, the second transistor M2 and the fourth transistor M4 are turned on, and the first clock signal clk1 and the second clock signal clk2 are input at a low level, so the first output signal terminal G_OUT and the second output signal terminal OUT_C ​​output a low level, that is, the first output signal g_out and the second output signal out_c are both low levels. At the same time, the ninth transistor M9 to the twelfth transistor M12 are turned on, the first voltage terminal LVGL is a constant voltage low level signal, and the first voltage terminal LVGL pulls the signal of the pull-down control node PD down to a low level. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0094] In the second stage t2, the thirteenth transistor M13 remains turned on at the high level of the input signal terminal INPUT, the pull-up control node PU is at a high level, and the first transistor M1, the second transistor M2 and the fourth transistor M4 remain turned on. At this time, the second clock signal clk2 (for example, clk (n-1)) is at a high level, the first clock signal clk1 is at a low level, and the second clock signal clk2 makes the second pole of the second capacitor C2 at a high level through the fourth transistor M4, and the bootstrap effect of the second capacitor C2 compensates the signal of the pull-up control node PU, and the voltage of the pull-up control node PU is pulled up for the second time. In addition, the ninth transistor M9 to the twelfth transistor M12 remain turned on, and the signal of the pull-down control node PD remains at a low level. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0095] In the third stage t3, the input signal input of the input signal terminal INPUT is at a low level, and the thirteenth transistor M13 is turned off. The first transistor M1, the second transistor M2 and the fourth transistor M4 remain turned on, and the first clock clk1 and the second clock signal clk2 are both at a high level, so that the first output signal g_out and the second output signal out_c are both at a high level. The second pole of the first capacitor C1 is coupled to the first output signal terminal G_OUT, and the second pole of the first capacitor C1 is also at a high level. The signal of the pull-up control node PU is compensated by the bootstrap effect of the first capacitor C1, and the voltage of the pull-up control node PU is pulled up for the third time. In addition, the ninth transistor M9 to the twelfth transistor M12 remain turned on, and the signal of the pull-down control node PD remains at a low level. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0096] In the fourth stage t4, the thirteenth transistor M13 remains closed. The first transistor M1, the second transistor M2 and the fourth transistor M4 remain turned on. The second clock signal clk2 is low, so that the second pole of the second capacitor C2 is low, and the bootstrap effect of the second capacitor C2 pulls down the voltage of the pull-up control node PU for the first time. Since the pull-down effect of the capacitor is less than the pull-up effect, the voltage of the pull-up control node PU after the first pull-down (i.e., the fourth stage t4) is greater than the voltage after the second pull-up (i.e., the second stage t2). In addition, the ninth transistor M9 to the twelfth transistor M12 remain turned on, and the signal of the pull-down control node PD remains low. The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off.

[0097] In the fifth stage t5, the thirteenth transistor M13 remains turned off. The first transistor M1, the second transistor M2 and the fourth transistor M4 remain turned on. The first clock clk1 and the second clock signal clk2 are both low levels, so that the first output signal g_out and the second output signal out_c are both low levels. The second electrode of the first capacitor C1 is coupled to the first output signal terminal G_OUT, and the pull-up control node PU is pulled down for the second time through the bootstrap effect of the first capacitor C1. In addition, the ninth transistor M9 to the twelfth transistor M12 remain turned on, and the signal of the pull-down control node PD remains at a low level. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all turned off.

[0098] In the sixth stage t6, the signal rst of the reset signal terminal RST is at a high level, the fifth transistor M5 is turned on, and the low level of the first voltage terminal LVGL pulls down the voltage of the pull-up control node PU for the third time through the fifth transistor M5, and the voltage of the pull-up control node PU is pulled down to a low level. As a result, the first transistor M1, the second transistor M2, the fourth transistor M4, the ninth transistor M9, and the tenth transistor M10 are turned off. The eleventh transistor M11 and the twelfth transistor M12 remain turned on, and the high level of the second voltage terminal VDD1 makes the pull-down control node PD a high level through the twelfth transistor M12. The high level of the pull-down control node PD turns on the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8, and performs noise reduction on the pull-up control node PU and the first output signal terminal G_OUT.

[0099] Combining the above content, we can see that Figure 7 The voltage of the pull-up control node PU of the GOA unit shown can be pulled up three times, so that the first transistor M1 and the second transistor M2 can be fully turned on, the time for the output signal g_out of the GOA unit to fall is reduced, and a better display effect is obtained. Fig.11 As shown, the compensation subcircuit 43 also includes: a third capacitor C3, a first electrode of the third capacitor C3 is coupled to the first signal line or the second signal line, the first signal line is used to receive the third clock signal clk3, the second signal line is used to receive the fourth clock signal clk4, and the second electrode of the third capacitor C3 is coupled to the first output signal terminal G_OUT of the GOA unit. The third capacitor C3 is configured to compensate the first output signal terminal G_OUT based on the third clock signal clk3 and the first clock signal clk1. Alternatively, the first output signal terminal G_OUT is compensated based on the fourth clock signal clk4 and the first clock signal clk1.

[0100] like Fig.11 As shown, by adding the third capacitor C3, and the third clock signal clk3 of the first signal line or the fourth clock signal clk4 of the second signal line overlaps with the first clock signal clk1, the coupling effect of the third capacitor C3 is utilized to pull the first output signal g_out in the rising stage and the falling stage of the first output signal g_out, so that both g_out Tf and g_out Tr are reduced, thereby solving the problem of wrong charging or insufficient charging caused by leakage of the noise reduction unit, and improving the display effect.

[0101] In some embodiments, the GOA unit may include two groups of first control subcircuits 44 and 44', two groups of second control subcircuits 45 and 45', and two groups of second reset subcircuits 47 and 47'. Fig. 9 and Fig.10As shown, the first control subcircuit 44' includes: a transistor M9' having the same function as the ninth transistor M9, and a transistor M10' having the same function as the tenth transistor M10. The second control subcircuit 45' includes: a transistor M11' having the same function as the eleventh transistor M11, a transistor M12' having the same function as the twelfth transistor M12, and a fourth voltage terminal VDD2 having the same function as the second voltage terminal VDD1. The second reset subcircuit 47' includes: a transistor M6' having the same function as the sixth transistor M6, a transistor M7' having the same function as the seventh transistor M7, and a transistor M8' having the same function as the eighth transistor M8.

[0102] like Fig. 9 and Fig.10 As shown, since the GOA unit includes two groups of first control subcircuits 44 and 44', two groups of second control subcircuits 45 and 45', and two groups of second reset subcircuits 47 and 47'. When the GOA unit is working, by alternately using the first control subcircuit 44, the second control subcircuit 45, and the second reset subcircuit 47, and the first control subcircuit 44', the second control subcircuit 45', and the second reset subcircuit 47', the transistors with the same function work alternately, it is possible to avoid the sixth transistor M6 to the twelfth transistor M12 being in a high voltage state all the time, reduce the probability of transistor polarization, and extend the service life of the transistor.

[0103] Combination Figure 6 ,right Fig. 9 The working process of the first control subcircuit 44', the second control subcircuit 45' and the second reset subcircuit 47' in the GOA circuit shown in FIG.

[0104] In the first phase t1, transistors M9' to M12' are turned on, the first voltage terminal LVGL is a constant voltage low level signal, and the first voltage terminal LVGL pulls down the signal of the pull-down control node PD' to a low level. Transistors M6' to M8' are all turned off.

[0105] From the second stage t2 to the third stage t3, the transistors M9' to M12' remain turned on, so that the pull-down control node PD' remains at a low level. The transistors M6' to M8' remain turned off.

[0106] In the fourth stage t4 , the transistors M9 ′ and M10 ′ are turned off, the transistors M11 ′ and M12 ′ remain turned on, and the fourth voltage terminal VDD2 makes the pull-down control node PD′ high level through the transistor M12 ′.

[0107] Combination Figure 8 ,right Fig.10The working process of the first control subcircuit 44', the second control subcircuit 45' and the second reset subcircuit 47' of the GOA circuit shown in FIG.

[0108] In the first phase t1 , the transistors M9 ′ to M12 ′ are turned on, and the first voltage terminal LVGL is a constant voltage low level signal. The first voltage terminal LVGL pulls down the signal of the pull-down control node PD′ to a low level.

[0109] During the second stage t2 to the fifth stage t5 , the transistor M9 ′ and the transistor M10 ′ remain turned on, so that the pull-down control node PD′ maintains a low level.

[0110] In the sixth phase t6 , the transistors M9 ′ and M10 ′ are turned off, the transistors M11 ′ and M12 ′ remain turned on, and the fourth voltage terminal VDD2 makes the pull-down control node PD′ high level through the transistor M12 ′.

[0111] In some embodiments, Fig. 9 and Fig.10 As shown, the GOA unit may further include: a fourteenth transistor M14, a control terminal of the fourteenth transistor M14 coupled to the frame start discharge signal terminal STV, a first electrode of the fourteenth transistor M14 coupled to the pull-up control node PU, and a second electrode of the fourteenth transistor M14 coupled to the first voltage terminal LVGL. When the fourteenth transistor M14 responds to the signal stv of the frame start discharge signal terminal STV, the pull-up control node PU can be reset when the GOA unit is initially powered on.

[0112] Some embodiments of the present application provide a GOA circuit, comprising N cascaded GOA units. Fig.12 Schematic diagram of the connection between the signal line and the first output signal terminal in some embodiments of the present application. Fig.12 As shown, the first electrode of the third capacitor C3 of the i-th GOA unit among the N GOA units is coupled to the first signal line, and i is an odd number greater than or equal to 1 and less than or equal to N. The first electrode of the third capacitor C3 of the j-th GOA unit among the N GOA units is coupled to the second signal line, and j is an even number greater than 1 and less than or equal to N.

[0113] In the rising and falling stages of the first output signal g_out, the coupling effect of the third capacitor C3 compensates the first output signal g_out, so that the first output signal g_out Tf and g_out Tr are reduced. g_out Tr, i.e., g_outTime Rise, refers to the time for the voltage of the first output signal g_out to rise from 10% to 90%. Although the first signal line and the second signal line cause the waveform of the first output signal g_out to fluctuate during the low level holding stage of the first output signal g_out, the fluctuation is small and the impact on the GOA unit can be ignored.

[0114] The present application does not limit the circuit structure of N cascaded GOA units. The first type of GOA unit including the third transistor M3 can be used, the second type of GOA unit including the fourth transistor M4 and the second capacitor C2 can be used, and the GOA unit in the related art can also be used.

[0115] In some embodiments, the first signal line is used to receive a third clock signal clk3, and the second signal line is used to receive a fourth clock signal clk4. The effective levels of the third clock signal clk3 and the first clock signal clk1 at least partially overlap, and the effective levels of the fourth clock signal clk4 and the first clock signal clk1 at least partially overlap.

[0116] Exemplarily, taking N as 6, that is, the GOA circuit includes 6 GOA units, the first output signal of the i-th GOA unit is g_out(i), the first clock signal is clk1(i), the first output signal of the j-th GOA unit is g_out(j), the first clock signal is clk1(j), and the first output signal g_out is output by the first clock signal clk1 through the first transistor M1. The rising edge and the falling edge of the clk(i) signal both correspond to part of the rising edge and part of the falling edge of the third clock signal clk3, and the rising edge and the falling edge of the clk(j) signal both correspond to part of the rising edge and part of the falling edge of the fourth clock signal clk4. Fig.13 is a timing diagram corresponding to the clock signal of the signal line and the first clock signal in some embodiments of the present application, such as Fig.13As shown, the first clock signals clk(1), clk(3) and clk(5) correspond to part of the rising edge and part of the falling edge of the third clock signal clk3, and the first clock signals clk(2), clk(4) and clk(6) correspond to part of the rising edge and part of the falling edge of the fourth clock signal clk4. Due to the delay phenomenon of the signal, it is difficult to achieve the corresponding coincidence of the rising edges or falling edges of the two signals in practice. It can also be understood that the effective levels of the third clock signal clk3 and the first clock signal clk1 at least partially overlap, and the effective levels of the fourth clock signal clk4 and the first clock signal clk1 at least partially overlap.

[0117] Some embodiments of the present application provide a driving method of a GOA unit 40, including: an input subcircuit 41 transmits an input signal input of an input signal terminal INPUT to a pull-up control node PU. An output subcircuit 42 receives a first clock signal clk1 from a first clock signal terminal CLK1, and outputs the first clock signal clk1 under the action of the pull-up control node PU. A compensation subcircuit 43 compensates the pull-up control node PU and / or at least part of the output signal terminal of the GOA unit 40.

[0118] There are multiple implementations of the compensation subcircuit 43 in the embodiment of the present application to compensate for at least part of the output signal end of the pull-up control node PU and / or the GOA unit 40. The compensation method of the compensation subcircuit 43 is introduced in three cases below. At least part of the output signal end of the GOA unit 40 includes the first output signal end G_OUT.

[0119] The first case applies to Figure 5 After the voltage of the pull-up control node PU is pulled up for the second time by the output sub-circuit 42, the compensation sub-circuit 43 charges the pull-up control node PU to maintain the voltage of the pull-up control node PU. Figure 6 shown.

[0120] The second case applies to Figure 7 The circuit of the GOA unit shown in FIG. 4 is a circuit diagram of the GOA unit. The compensation subcircuit 43 pulls up the voltage of the pull-up control node PU for the second time. In this case, the signal timing diagram of the GOA unit is as follows: Figure 8 As shown, the output sub-circuit 42 pulls up the voltage of the pull-up control node PU for the third time.

[0121] The third case is applied to Fig.11The circuit of the GOA unit shown in FIG. The compensation subcircuit 43 compensates the first output signal terminal G_OUT based on the third clock signal clk3 and the first clock signal clk1. Alternatively, the first output signal terminal G_OUT is compensated based on the fourth clock signal clk4 and the first clock signal clk1. When the method is applied to a circuit including a plurality of cascaded GOA units, the cascade relationship of the GOA units is as follows: Fig.12 The corresponding relationship between the third clock signal clk3, the fourth clock signal clk4 and the first clock signal clk1 is shown in Fig.13 shown.

[0122] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A GOA unit, characterized in that: include: an input subcircuit coupled to the pull-up control node and the input signal terminal and configured to transmit the signal of the input signal terminal to the pull-up control node; an output subcircuit, coupled to the first clock signal terminal and the pull-up control node, and configured to receive the first clock signal from the first clock signal terminal and output the first clock signal under the action of the pull-up control node; a compensation subcircuit, coupled to the pull-up control node and the output subcircuit, and configured to compensate the first output signal terminal of the GOA unit; The compensation subcircuit includes a third capacitor, a first electrode of the third capacitor is coupled to the first signal line or the second signal line, the first signal line is used to receive a third clock signal, the second signal line is used to receive a fourth clock signal, and a second electrode of the third capacitor is coupled to the first output signal terminal of the GOA unit; The effective levels of the third clock signal and the first clock signal at least partially overlap, and the effective levels of the fourth clock signal and the first clock signal at least partially overlap.

2. The GOA unit according to claim 1, characterized in that The output subcircuit includes: a first transistor, a second transistor and a first capacitor, The control terminal of the first transistor is coupled to the first electrode of the first capacitor, the control terminal of the second transistor and the pull-up control node, the first electrode of the first transistor is coupled to the first clock signal terminal, the second electrode of the first transistor is coupled to the second electrode of the first capacitor, and the second electrode of the first transistor is coupled to the first output signal terminal of the GOA unit; A first electrode of the second transistor is coupled to the first clock signal terminal, and a second electrode of the second transistor is coupled to the second output signal terminal of the GOA unit.

3. The GOA unit according to claim 2, characterized in that The third capacitor is configured to compensate the first output signal terminal based on the third clock signal and the first clock signal; or to compensate the first output signal terminal based on the fourth clock signal and the first clock signal.

4. The GOA unit according to any one of claims 1 to 3, characterized in that It also includes a first reset subcircuit and a second reset subcircuit, the first reset subcircuit is configured to reset the pull-up control node, and the second reset subcircuit is configured to reset the pull-up control node and the output signal end of the GOA unit.

5. The GOA unit according to claim 4, characterized in that The first reset subcircuit comprises a fifth transistor, a first electrode of the fifth transistor is coupled to the pull-up control node, a control terminal of the fifth transistor is coupled to the reset signal terminal, and a second electrode of the fifth transistor is coupled to the first voltage terminal; The second reset subcircuit comprises a sixth transistor, a seventh transistor and an eighth transistor, wherein the control end of the sixth transistor, the control end of the seventh transistor and the control end of the eighth transistor are all coupled to the pull-down control node; the first electrode of the sixth transistor is coupled to the pull-up control node, and the second electrode of the sixth transistor is coupled to the first voltage end; A first electrode of the seventh transistor is coupled to the first output signal terminal of the GOA unit, and a second electrode of the seventh transistor is coupled to the third voltage terminal; A first electrode of the eighth transistor is coupled to the second output signal terminal of the GOA unit, and a second electrode of the eighth transistor is coupled to the first voltage terminal.

6. The GOA unit according to any one of claims 1 to 3, characterized in that Also includes: a first control subcircuit coupled to the pull-down control node, the pull-up control node and the first voltage terminal, and configured to control the signal of the pull-down control node to be a second level signal when the signal of the pull-up control node is a first level signal; The second control subcircuit is coupled to the second voltage terminal and the pull-down control node, and is configured to control the signal of the pull-down control node to be the first level signal when the signal of the pull-up control node is the second level signal.

7. The GOA unit according to claim 6, characterized in that The first control subcircuit includes a ninth transistor and a tenth transistor, the control end of the ninth transistor and the control end of the tenth transistor are both coupled to the pull-up control node, the second electrode of the ninth transistor and the second electrode of the tenth transistor are both coupled to the first voltage terminal, and the first electrode of the tenth transistor is coupled to the pull-down control node; The second control subcircuit includes an eleventh transistor and a twelfth transistor, the first electrode of the eleventh transistor, the control end of the eleventh transistor and the first electrode of the twelfth transistor are all coupled to the second voltage end, the second electrode of the eleventh transistor is coupled to the first electrode of the ninth transistor and the control end of the twelfth transistor, and the second electrode of the twelfth transistor is coupled to the pull-down control node.

8. The GOA unit according to claim 7, characterized in that The input sub-circuit includes a thirteenth transistor, a first electrode of the thirteenth transistor and a control terminal of the thirteenth transistor are coupled to the input signal terminal, and a second electrode of the thirteenth transistor is coupled to the pull-up control node.

9. A GOA unit, characterized in that: include: an input subcircuit coupled to the pull-up control node and the input signal terminal and configured to transmit the signal of the input signal terminal to the pull-up control node; an output subcircuit, coupled to the first clock signal terminal and the pull-up control node, and configured to receive the first clock signal from the first clock signal terminal and output the first clock signal under the action of the pull-up control node; a compensation subcircuit coupled to the pull-up control node and the output subcircuit and configured to compensate the pull-up control node; The compensation subcircuit includes: a fourth transistor and a second capacitor, the first electrode of the fourth transistor is coupled to the second clock signal end, the control end of the fourth transistor is coupled to the pull-up control node and the first electrode of the second capacitor, and the second electrode of the fourth transistor is coupled to the second electrode of the second capacitor; wherein the second clock signal at the second clock signal end is an upstream signal of the first clock signal.

10. A GOA circuit, characterized in that: A device comprising N cascaded GOA units as claimed in any one of claims 1 to 8; A first electrode of the third capacitor of the i-th GOA unit among the N GOA units is coupled to the first signal line, where i is an odd number greater than or equal to 1 and less than or equal to N; A first electrode of the third capacitor of the j-th GOA unit among the N GOA units is coupled to the second signal line, where j is an even number greater than 1 and less than or equal to N.

11. A method for driving a GOA unit, characterized in that: include: The input subcircuit transmits the signal at the input signal terminal to the pull-up control node; The output subcircuit receives the first clock signal from the first clock signal terminal, and outputs the first clock signal under the action of the pull-up control node; The compensation subcircuit compensates the first output signal terminal of the GOA unit; Wherein, the compensation subcircuit includes a third capacitor, a first electrode of the third capacitor is coupled to the first signal line or the second signal line, the first signal line is used to receive a third clock signal, the second signal line is used to receive a fourth clock signal, and the second electrode of the third capacitor is coupled to the first output signal terminal of the GOA unit; The effective levels of the third clock signal and the first clock signal at least partially overlap, and the effective levels of the fourth clock signal and the first clock signal at least partially overlap.

12. The method according to claim 11, characterized in that The compensation subcircuit compensates the first output signal end of the GOA unit, including: The compensation subcircuit compensates the first output signal end based on the third clock signal and the first clock signal; or compensates the first output signal end based on the fourth clock signal and the first clock signal.

13. A method for driving a GOA unit, characterized in that: include: The input subcircuit transmits the signal at the input signal terminal to the pull-up control node; The output subcircuit receives the first clock signal from the first clock signal terminal, and outputs the first clock signal under the action of the pull-up control node; The compensation subcircuit compensates the pull-up control node; The compensation subcircuit includes: a fourth transistor and a second capacitor, a first electrode of the fourth transistor is coupled to the second clock signal terminal, a control terminal of the fourth transistor is coupled to the pull-up control node and the first electrode of the second capacitor, and a second electrode of the fourth transistor is coupled to the second electrode of the second capacitor; wherein the second clock signal at the second clock signal terminal is an uplink signal of the first clock signal; The compensation sub-circuit pulls up the voltage of the pull-up control node for a second time, and the output sub-circuit pulls up the voltage of the pull-up control node for a third time.

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