Semiconductor device and method for forming a word line structure that avoids shorting thereof

Abstract

The present disclosure relates to a semiconductor device and a method for forming a word line structure that avoids shorting thereof. The semiconductor device includes a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; a plurality of word lines extending across the memory cell region and the peripheral region; and a plurality of contacts respectively connected to edge portions of even-numbered word lines of the plurality of word lines in the peripheral region; wherein one side of each of the edge portions of the even-numbered word lines of the plurality of word lines is adjacent to a portion lacking odd-numbered word lines; and wherein the other side of each of the edge portions of the even-numbered word lines of the plurality of word lines is adjacent to a cut-away portion of another odd-numbered word line.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming a word line structure to avoid short circuits thereon. Background Technology

[0002] For example, in semiconductor devices such as Dynamic Random Access Memory (DRAM), circuit features are becoming increasingly refined to increase data storage capacity. For instance, the repeatability of wiring such as DRAM word lines is reduced, and the distance between word lines is also decreased. However, when forming contact electrodes to be connected to word lines, if the positioning is not aligned with the word lines, in some cases, the contact electrodes can short-circuit with adjacent word lines. Summary of the Invention

[0003] In one aspect, this disclosure discloses a semiconductor device comprising: a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; a plurality of word lines extending across the memory cell region and the peripheral region; and a plurality of contacts respectively connected to edge portions of even-numbered word lines among the plurality of word lines in the peripheral region; wherein one side of each of the edge portions of the even-numbered word lines among the plurality of word lines is adjacent to a portion lacking an odd-numbered word line; and wherein the other side of each of the edge portions of the even-numbered word lines among the plurality of word lines is adjacent to a cut-off portion of another odd-numbered word line.

[0004] In another aspect, this disclosure discloses a semiconductor device comprising: a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; and first, second, and third word lines extending across the memory cell region and the peripheral region; wherein the first word line is provided adjacently between the second word line and the third word line; wherein a first length of the first word line in the peripheral region is longer than a second length of the second word line in the peripheral region; and wherein the second length of the second word line in the peripheral region is longer than a third length of the third word line in the peripheral region. Attached Figure Description

[0005] Figure 1 A plan view illustrating a schematic configuration of a portion of the memory cell region of a semiconductor device according to the first and second embodiments. Figure 1A A plan view illustrating a schematic configuration of memory chips.

[0006] Figure 2 This is a plan view illustrating a schematic configuration of the memory cell region of the semiconductor device according to the first and second embodiments, and is... Figure 1A An enlarged view of the end region X of the memory chip.

[0007] Figure 3 This is a plan view layout diagram illustrating a schematic configuration of the memory cell region of the semiconductor device according to the first and second embodiments, and is... Figure 1A An enlarged view of the end region Y of the memory chip.

[0008] Figure 4 A longitudinal cross-sectional view illustrating an example of the general schematic configuration of a semiconductor device according to the first and second embodiments.

[0009] Figure 5A and 5B The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and describes an example of an exemplary configuration in an exemplary processing stage. Figure 5A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 5B To explain along Figure 5A A longitudinal section view showing the schematic configuration of lines AA, BB, and CC in the diagram.

[0010] Figure 6A and 6B The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figure 5A and 5B An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 6A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 6B To explain along Figure 6A A longitudinal section view showing the schematic configuration of lines AA, BB, and CC in the diagram.

[0011] Figure 7A and 7B The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figure 6A and 6B An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 7A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 7B To explain along Figure 7A A longitudinal section view showing the schematic configuration of lines AA, BB, and CC in the diagram.

[0012] Figure 8A and 8B The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figure 7A and 7BAn example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 8A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 8B To explain along Figure 8A A longitudinal section view showing the schematic configuration of lines AA, BB, and CC in the diagram.

[0013] Figures 9A to 9C The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figure 8A and 8B An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 9A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 9B To explain along Figure 9A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 9C To explain along Figure 9A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0014] Figures 10A to 10C The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figure 9A , 9B Examples of illustrative configurations in the exemplary processing phase following the processing phases described in 9C. Figure 10A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 10B To explain along Figure 10A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 10C To explain along Figure 10A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0015] Figures 11A to 11C The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figures 10A to 10C An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 11A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 11B To explain along Figure 11A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 11C To explain along Figure 11A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0016] Figures 12A to 12EThe diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figures 11A to 11C Examples of illustrative configurations in the subsequent demonstrative processing phase. Figure 12A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 12B To explain along Figure 12A A longitudinal section view showing the schematic configuration of section AA in the diagram. Figure 12C To explain along Figure 12A A longitudinal section view showing the schematic configuration of the section BB in the diagram. Figure 12D To explain along Figure 12A A longitudinal section view showing the schematic configuration of the CC section in the diagram. Figure 12E To explain along Figure 12A A longitudinal section view showing the schematic configuration of the line DD portion in the diagram.

[0017] Figures 13A to 13D The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figures 12A to 12E An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 13A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 13B To explain along Figure 13A A longitudinal section view showing the schematic configuration of section AA in the diagram. Figure 13C To explain along Figure 13A A longitudinal section view showing the schematic configuration of the section BB in the diagram. Figure 13D To explain along Figure 13A A longitudinal section view showing the schematic configuration of the CC section in the diagram.

[0018] Figures 14A to 14E The diagram illustrates a method for forming a semiconductor device according to the first embodiment, and explains the process of... Figures 13A to 13D An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 14A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 14B To explain along Figure 14A A longitudinal section view showing the schematic configuration of section AA in the diagram. Figure 14C To explain along Figure 14A A longitudinal section view showing the schematic configuration of the section BB in the diagram. Figure 14D To explain along Figure 14A A longitudinal section view showing the schematic configuration of the CC section in the diagram. Figure 14E To explain along Figure 14A A longitudinal section view showing the schematic configuration of the line DD portion in the diagram.

[0019] Figures 15A to 15F The figure illustrates the semiconductor device and its formation method according to the first embodiment. Figures 15A to 15F Explanation in Figures 14A to 14E An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 15A A plan view illustrating an example of a schematic configuration of a semiconductor device according to the first embodiment. Figure 15B To explain along Figure 15A A longitudinal section view showing the schematic configuration of section AA in the diagram. Figure 15C To explain along Figure 15A A longitudinal section view showing the schematic configuration of the section BB in the diagram. Figure 15D To explain along Figure 15A A longitudinal section view showing the schematic configuration of the CC section in the diagram. Figure 15E To explain along Figure 15A A longitudinal section view showing the schematic configuration of the line DD portion in the diagram. Figure 15F To explain along Figure 15A A longitudinal section view illustrating the schematic configuration of the line EE portion.

[0020] Figures 16A to 16C The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and provides an example of an illustrative configuration in an exemplary processing stage. Figure 16A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 16B To explain along Figure 16A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 16C To explain along Figure 16A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0021] Figures 17A to 17C The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 16A to 16C An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 17A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 17B To explain along Figure 17A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 17C To explain along Figure 17A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0022] Figures 18A to 18C The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 17A to 17CAn example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 18A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 18B To explain along Figure 18A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 18C To explain along Figure 18A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0023] Figures 19A to 19C The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 18A to 18C An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 19A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 19B To explain along Figure 19A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 19C To explain along Figure 19A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0024] Figures 20A to 20C The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 19A to 19C An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 20A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 20B To explain along Figure 20A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 20C To explain along Figure 20A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0025] Figures 21A to 21C The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 20A to 20C An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 21A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 21B To explain along Figure 21A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 21C To explain along Figure 21A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0026] Figures 22A to 22CThe diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 21A to 21C An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 22A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 22B To explain along Figure 22A A longitudinal section view showing the schematic configuration of the sections AA and CC in the diagram. Figure 22C To explain along Figure 22A A longitudinal section view showing the schematic configuration of the section BB in the diagram.

[0027] Figures 23A to 23D The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 22A to 22C An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 23A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 23B To explain along Figure 23A A longitudinal section view showing the schematic configuration of section AA in the diagram. Figure 23C To explain along Figure 23A A longitudinal section view showing the schematic configuration of the section BB in the diagram. Figure 23D To explain along Figure 23A A longitudinal section view showing the schematic configuration of the CC section in the diagram.

[0028] Figures 24A to 24D The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 23A to 23D An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 24A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 24B To explain along Figure 24A A longitudinal section view showing the schematic configuration of section AA in the diagram. Figure 24C To explain along Figure 24A A longitudinal section view showing the schematic configuration of the section BB in the diagram. Figure 24D To explain along Figure 24A A longitudinal section view showing the schematic configuration of the CC section in the diagram.

[0029] Figures 25A to 25E The diagram illustrates a method for forming a semiconductor device according to the second embodiment, and explains the process of... Figures 24A to 24D An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 25A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 25BTo explain along Figure 25A A longitudinal section view showing the schematic configuration of section AA in the diagram. Figure 25C To explain along Figure 25A A longitudinal section view showing the schematic configuration of the section BB in the diagram. Figure 25D To explain along Figure 25A A longitudinal section view showing the schematic configuration of the CC section in the diagram. Figure 25E To explain along Figure 25A A longitudinal section view showing the schematic configuration of the line DD portion in the diagram.

[0030] Figures 26A to 26F The figure illustrates the semiconductor device and its formation method according to the first embodiment. Figures 26A to 26F Explanation in Figures 25A to 25E An example of an illustrative configuration in the exemplary processing stage following the processing stage described herein. Figure 26A A plan view illustrating an example of a schematic configuration in the exemplary processing phase. Figure 26B To explain along Figure 26A A longitudinal section view showing the schematic configuration of section AA in the diagram. Figure 26C To explain along Figure 26A A longitudinal section view showing the schematic configuration of the section BB in the diagram. Figure 26D To explain along Figure 26A A longitudinal section view showing the schematic configuration of the CC section in the diagram. Figure 26E To explain along Figure 26A A longitudinal section view showing the schematic configuration of the line DD portion in the diagram. Figure 26F To explain along Figure 26A A longitudinal section view illustrating the schematic configuration of the line EE portion. Detailed Implementation

[0031] Various embodiments of the invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of the invention that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made, without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0032] Several embodiments will be described below with reference to the drawings. In the following description, DRAM is given as an example of semiconductor device 1 (1A, 1B). Figures 1 to 4 The configuration of the semiconductor device according to the first and second embodiments described below will be explained.

[0033] In the following description, semiconductor device 1 includes semiconductor device 1A according to a first embodiment and semiconductor device 1B according to a second embodiment. The semiconductor device will be designated 1A in the description of the first embodiment and 1B in the description of the second embodiment. In each of the embodiments described below, common elements, related elements, or substantially the same elements will be designated by the same reference numerals, and descriptions will be omitted. In the drawings mentioned below, the dimensions and aspect ratios of each unit in each drawing may not match those in the embodiments. Furthermore, the vertical direction described below refers to the vertical direction when the semiconductor substrate 10 is oriented such that it is located on the bottom.

[0034] (First Embodiment)

[0035] In the following text, reference will be made to Figures 1 to 15F The semiconductor device 1 (1A) according to the first embodiment and the method of forming the same are described.

[0036] Figures 1 to 3 This is a plan view layout diagram illustrating the semiconductor device 1 (1A) according to the first embodiment. Figure 1 As described herein, the semiconductor device 1 includes a plurality of memory chips 2 arranged in a matrix on the surface of a semiconductor substrate. For example... Figure 1A As explained, multiple word lines 4 are arranged in parallel in each of the memory blocks 2.

[0037] The direction parallel to word line 4 specifies the word line direction W. Memory block end regions X and Y are located at the ends of each memory block 2 along the word line direction W. The end of each word line 4 is connected to an unspecified row decoder. The row address selected when reading from or writing to a memory cell is input from the row decoder into the word line 4. Each of the plurality of word lines 4 is paired (e.g., coupled) to a corresponding one of the plurality of memory cells and controls access to that corresponding memory cell among the plurality of memory cells.

[0038] Figure 2 To explain Figure 1A A layout diagram of an enlarged view of the end region X of the memory chip. Figure 3 To explain Figure 1A A layout diagram showing an enlarged view of the end region Y of the memory chip. (See attached diagram.) Figure 2 As described herein, in the end region X of the memory chip, the semiconductor device 1 includes a memory cell region M and a peripheral region N. In the memory cell region M, a plurality of word lines 4 and a plurality of bit lines 5 are arranged vertically at equal intervals. An active region 10a contained within the memory cell is located at the intersection point between the word lines 4 and the bit lines 5. The word lines 4 include word lines 4e, 4f, 4g, 4h, and 4i, as described below.

[0039] The longitudinal direction of the active region 10a is tilted at a predetermined angle relative to the bit line 5. The word line 4 serves as the gate electrode of the access transistor of the memory cell in the active region 10a. The bit line 5 is connected to the center portion of the active region 10a via the bit line contact 7. In the active region 10a, a capacitor contact 6 is disposed on the side of the word line 4 opposite to the bit line contact 7. A capacitor (not shown) is connected to the capacitor contact 6.

[0040] Word lines 4 are positioned to extend straight across memory cell region M to peripheral region N. In peripheral region N, word line contacts 8 are provided that are electrically connected to word lines 4 (4e, 4h, 4i). Word line contacts 8 are connected to word lines 4 (4e, 4h, 4i) at edge portions 9 of word lines 4. Edge portions 9 correspond to overlapping portions where word lines 4 and word line contacts 8 overlap. In peripheral region N, word line contacts 8 are electrically connected to every other word line 4 (4e, 4h, 4i). Word lines 4 (4f, 4g) not connected to word line contacts 8 are positioned adjacent to word lines 4 (4e, 4h, 4i) connected to word line contacts 8. Word line 4g has a cut-off portion 4c. Word line 4g is adjacent to one side of word line 4e connected to one of the word line contacts 8. The cut-off portion 4c is positioned next to the edge portion 9 of word line 4e.

[0041] Between the cut-off portion 4c and the word line 4g, a first portion 4a is provided where the word line 4 is absent. The first portion 4a is located near the boundary between the memory cell region M and the peripheral region N. The word line 4g and the cut-off portion 4c are physically and electrically isolated by the first portion 4a. The cut-off portion 4c is not connected to either of the word lines 4 and is electrically floating. On the extension of another word line 4f that is not connected to the word line contact 8, a second portion 4b in which the word line 4 is absent is provided next to the word line contact 8.

[0042] like Figure 2 As described above, in the memory block end region X, word line 4e is sandwiched between word line 4f and word line 4g. Word line 4h, having a similar configuration to word line 4e, is positioned adjacent to word line 4g. Word line 4g is sandwiched between word line 4e and word line 4h. Word line 4i, having a similar configuration to word line 4e, is positioned adjacent to word line 4f. Word line 4f is sandwiched between word line 4e and word line 4i. Multiple word lines 4 (4e to 4i) are arranged in the order described above, and subsequently repeated in the above order. In the memory block end region Y, word lines 4e, 4h, and 4i are longer than word line 4f. Word line 4f is longer than word line 4g. Word line 4f has a second portion 4b, in which the edge portion 9 adjacent to one of the word lines 4 (4e or 4h) does not contain word line 4. Word line 4g has a cut-off portion 4c of the edge portion 9 adjacent to one of word lines 4 (4e or 4h). Word lines 4 (4e, 4h, 4i) connected to word line contacts 8 do not have a first portion 4a or a second portion 4b.

[0043] Figure 3 The plan view layout of the memory block end region Y described herein is such that word lines 4e, 4h, and 4i are interchanged with word lines 4f and 4g compared to the plan view layout of the memory block end region X. If word lines 4e, 4h, and 4i in the memory block end region X are defined as even-numbered word lines 4, then word lines 4f and 4g are odd-numbered word lines 4. In this case, word line contacts 8 are connected to the even-numbered word lines 4. The odd-numbered word lines 4 have a second portion 4b or a cutoff portion 4c. The memory block end region Y has a layout in which even-numbered word lines and odd-numbered word lines in the memory block end region X are interchanged. The word lines 4 (4e, 4h, and 4i) connected to the word line contacts 8 in the peripheral region N of the memory block end region X have a configuration similar to that of word lines 4 (4f or 4g) not connected to the word line contacts 8 in the memory block end region Y. Word lines 4f and 4g in the peripheral area N of the memory block end region X have a configuration similar to that of word lines 4 (4e, 4h, or 4i) connected to word line contacts 8 in the memory block end region Y. The remainder of the configuration of the memory block end region Y is substantially the same as that of the memory block end region X.

[0044] Figure 4 A longitudinal cross-sectional view illustrating an example of the general schematic configuration of a memory cell region in a semiconductor device 1 according to an embodiment of the present invention. Figure 4 As described, below capacitor 128, components included in the DRAM memory cell 145 are provided, such as semiconductor substrate 140, shallow trench isolation 141, access transistor 142, and capacitor contacts 143. Capacitor 128 is provided on semiconductor substrate 140, in which components such as shallow trench isolation 141, access transistor 142, and capacitor contacts 143 are formed. Semiconductor substrate 140 corresponds to semiconductor substrate 10, which will be described later.

[0045] Figure 4 The bottom electrode of capacitor 128, as described, is electrically connected via capacitor contact 143 to one side of the source-drain region of access transistor 142 formed in the active region of semiconductor substrate 140. The bottom electrode of capacitor 128 is connected to semiconductor substrate 140. The gate electrode of access transistor 142 corresponds to... Figure 2 and 3 The character line 4 in the middle. Capacitor contact 143 corresponds to Figure 2 and 3 Capacitor contact 6 in the middle.

[0046] like Figure 4As described, an upper layer portion 154 comprising multiple upper wiring layers is located above a capacitor 128, the upper wiring layers containing components such as interconnects 148, 149, 150, and 151. The upper layer portion 154 is positioned above a memory cell 145. The top electrode of the capacitor 128 is located near the upper wiring layers containing components such as interconnects 148, 149, 150, and 151. Figure 4 The reference numerals 146, 147 and 152 in the accompanying drawings indicate insulating films.

[0047] Similar to Figure 4 As described in the configuration, capacitor 128 and upper layer portion 154 are provided in Figures 15B to 15F Above the diagram described in the text, and further described later. Figures 26B to 26F Above the diagram described in the text.

[0048] Reference Figures 5A to 15F The semiconductor device 1A according to the first embodiment and the method of forming the same are described. Figures 5A to 15F To explain in sequence Figure 1A The diagram illustrates the schematic configuration of the end region X of the memory chip.

[0049] First, a method for forming the semiconductor device 1A according to the first embodiment will be described. For example... Figure 5A and 5B As described, a first insulating film 12, a second insulating film 14, a third insulating film 16, a fourth insulating film 18, a fifth insulating film 20, a sixth insulating film 22, a polycrystalline silicon film 24, a seventh insulating film 26, an eighth insulating film 28, a ninth insulating film 30, and a photoresist 32 are formed on a semiconductor substrate 10.

[0050] For the semiconductor substrate 10, a single-crystal silicon substrate may be used, for example. The first insulating film 12, the second insulating film 14, and the sixth insulating film 22 contain, for example, an insulating material, such as silicon dioxide (SiO2). The third insulating film 16 contains, for example, an insulating material, such as silicon nitride (SiN). The fourth insulating film 18 and the seventh insulating film 26 contain, for example, an insulating material, such as amorphous carbon (α-C). The first insulating film 12, the second insulating film 14, the third insulating film 16, the fourth insulating film 18, the sixth insulating film 22, and the seventh insulating film 26 are formed by, for example, chemical vapor deposition (hereinafter referred to as CVD).

[0051] The fifth insulating film 20 and the eighth insulating film 28 contain, for example, a dielectric antireflective coating (DARC), such as a silicon oxynitride film (SiON film). The fifth insulating film 20 and the eighth insulating film 28 are formed by thermal CVD processes, plasma CVD processes, etc., in which a substrate, such as a silicon wafer, is heated while a film-forming gas is supplied to the substrate. The film-forming gas, for example, contains silane gas as a source of silicon (Si) and nitrous oxide (N₂O) gas as a source of nitrogen and oxygen.

[0052] Multiple polysilicon films 24 are formed on a sixth insulating film 22 using CVD and subsequently patterned using known photolithography and anisotropic dry etching techniques. Each of the multiple polysilicon films 24 is patterned with a line and space arrangement having the same size and the same repeating pitch. Furthermore, the polysilicon films 24 can also be formed using known multiple patterning techniques, such as dual or quadruple patterning processes. If a multiple patterning technique, such as a dual or quadruple patterning process, is used, then a polysilicon film 24 with a repeating pitch of 1 / 2 or 1 / 4 of the size limit of the photolithographic exposure can be formed.

[0053] The ninth insulating film 30 contains, for example, an insulating material, such as silicon dioxide (SiO2). The ninth insulating film 30 is formed by CVD and subsequently patterned using known photolithography and anisotropic dry etching techniques. The ninth insulating film 30 is patterned with lines and spaces of the same size and repeating spacing. The polysilicon film 24 and the ninth insulating film 30 are arranged to intersect at a predetermined angle.

[0054] The resist 32 is patterned using a known photolithography technique. The resist 32 is patterned to cover the peripheral region N and open the memory cell region M.

[0055] Next, as Figure 6A and 6B As described, anisotropic dry etching is performed using resist 32 and the ninth insulating film 30 as a mask to etch the eighth insulating film 28 and the seventh insulating film 26. This etching is performed under the following conditions: the etching rate of the silicon oxynitride film contained in the eighth insulating film 28 and the amorphous carbon contained in the seventh insulating film 26 is high, while the etching rate of the silicon dioxide contained in the ninth insulating film 30 and the polycrystalline silicon contained in the polycrystalline silicon film 24 is extremely low.

[0056] Next, anisotropic dry etching is performed to sequentially etch the silicon dioxide contained in the sixth insulating film 22, the silicon oxynitride film contained in the fifth insulating film 20, the amorphous carbon contained in the fourth insulating film 18, the silicon nitride contained in the third insulating film 16, and the silicon dioxide contained in the second insulating film 14.

[0057] This etching process uses the superimposed pattern of the ninth insulating film 30 and the polysilicon film 24 as a mask to perform anisotropic dry etching on the memory cell region M. The etching transfers the superimposed pattern of the resist 32, the ninth insulating film 30, and the polysilicon film 24 onto the sixth insulating film 22, the fifth insulating film 20, the fourth insulating film 18, the third insulating film 16, and the second insulating film 14 in the memory cell region M. Subsequently, the polysilicon film 24, the sixth insulating film 22, and the fifth insulating film 20 are removed.

[0058] Next, as Figure 7A and 7B As described, anisotropic dry etching is performed using the fourth insulating film 18, the third insulating film 16, and the second insulating film 14 as masks to form trenches 34 in the semiconductor substrate 10. During etching, a portion of the fourth insulating film 18, the third insulating film 16, and the second insulating film 14 is removed, thereby leaving a portion of the first insulating film 12 and a portion of the second insulating film 14 on the semiconductor substrate 10.

[0059] Next, as Figure 8A and 8B As described, the second insulating film 14 and the first insulating film 12 are removed, and then the trench 34 is filled to form a tenth insulating film 36 to cover the top surface of the semiconductor substrate 10. The tenth insulating film 36 contains, for example, an insulating material, such as silicon dioxide (SiO2). The tenth insulating film 36 is formed, for example, using CVD.

[0060] Next, as Figure 9A , 9B As described in 9C, the 11th insulating film 38, the 12th insulating film 40, the 13th insulating film 42 and the photoresist 44 are formed on the top of the semiconductor substrate 10 on which the 10th insulating film 36 is formed.

[0061] like Figure 9A , 9B As explained in 9C, opening 44a is formed in resist 44. Furthermore, as... Figure 9A and 9C As described, a protrusion 44b is formed that protrudes from the memory cell region M toward the peripheral region N. The protrusion 44b has a protrusion length 44c extending from the edge of the memory cell region M.

[0062] Next, as Figure 10A , 10BAs described in 10C, anisotropic dry etching is performed on the 13th insulating film 42, the 12th insulating film 40, the 11th insulating film 38, the 10th insulating film 36, and the semiconductor substrate 10 using a photoresist 44 as a mask. With this arrangement, a peripheral trench 46 is formed in the semiconductor substrate 10. Subsequently, the photoresist 44, the 13th insulating film 42, the 12th insulating film 40, and the 11th insulating film 38 are removed.

[0063] The peripheral trench 46 is formed in the peripheral region N. It will be formed by... Figure 9A The pattern formed by the resist 44 of the protrusion 44b described herein is transferred to the semiconductor substrate 10, and a protrusion 10c with a protrusion length 10d is formed at a distance of 10d from the edge of the memory cell region M. In the protrusion 10c, the active region 10a extends by an amount equal to the protrusion length 10d.

[0064] Next, as Figures 11A to 11C As described, the 14th insulating film 48 is formed on the surface of the semiconductor substrate 10 and on the inner surface of the peripheral trench 46. Next, the 14th insulating film 48, the 15th insulating film 50, and the 16th insulating film 52 are formed to be thick enough to fill the peripheral trench 46, and then an anisotropic dry etching is performed to fill the peripheral trench 46 with the 14th insulating film 48, the 15th insulating film 50, and the 16th insulating film 52.

[0065] The 14th insulating film 48 and the 16th insulating film 52 contain, for example, an insulating material, such as silicon dioxide. The 15th insulating film 50 contains, for example, an insulating material, such as silicon nitride. The 14th insulating film 48, the 15th insulating film 50, and the 16th insulating film 52 are formed, for example, by CVD. The 14th insulating film 48 may also be formed by thermal oxidation of silicon contained in the semiconductor substrate 10 instead of by CVD.

[0066] Next, as Figures 12A to 12E As described, the 17th insulating film 54, the 18th insulating film 56, the 19th insulating film 58, the hard mask 59, and the resist 60 patterned by known photolithography techniques are formed on the top of the semiconductor substrate 10 on which the 14th insulating film 48, the 15th insulating film 50, and the 16th insulating film 52 are formed.

[0067] The 17th insulating film 54, the 18th insulating film 56, the 19th insulating film 58, and the hard mask 59 contain insulating materials. The 17th insulating film 54 contains, for example, amorphous carbon. The 18th insulating film 56 contains, for example, a dielectric antireflective coating (DARC), such as silicon oxynitride (SiON). The 19th insulating film 58 and the hard mask 59 contain silicon dioxide. The 17th insulating film 54, the 18th insulating film 56, the 19th insulating film 58, and the hard mask 59 are formed by CVD. The hard mask 59 is patterned with lines and spaces of the same size and the same repeating spacing.

[0068] And, as Figure 12A and 12E As explained, the hard mask 59 can also be formed using known multiple patterning techniques, such as dual patterning or quadruple patterning processes. If a multiple patterning technique, such as dual patterning or quadruple patterning, is used, then a hard mask 59 with a repeating pitch of 1 / 2 or 1 / 4 of the size limit of the photolithographic exposure can be formed.

[0069] like Figure 12A and 12D As described, the resist 60 has a protrusion 60a extending from the edge position 60c of the resist 60 toward the memory cell region M. The protrusion 60a protrudes from the edge position 60c toward the memory cell region M with a protrusion length 60b. Both the edge position 60c of the resist 60 and the protruding end 60d of the protrusion 60a are located inside the peripheral region N.

[0070] Next, as Figures 13A to 13D As explained, resist 60 and hard mask 59 are used as masks to perform anisotropic dry etching.

[0071] Due to anisotropic dry etching, portions of the 17th insulating film 54, the 18th insulating film 56, and the 19th insulating film 58 are not covered by the resist 60 with protrusions 60a, and the hard mask 59 is etched. Furthermore, straight trenches 62 are formed in areas not covered by the resist 60 and the hard mask 59. Conductive material is embedded in the trenches 62 in a later step, and the embedded conductive material serves as DRAM word lines 4 (e.g., word lines 4 are embedded in the trenches 62). Next, the resist 60 and the 17th insulating film 54, the 18th insulating film 56, the 19th insulating film 58, and the 14th insulating film 48 on the top surface of the semiconductor substrate 10 in the removed area are removed.

[0072] like Figures 13B to 13D As explained, trenches 62 with a resist 60 shape and a hard mask 59 transferred thereon are formed in the memory cell region M and the peripheral region N by dry etching. Furthermore, as... Figure 13C As explained, protrusion 10c protrudes outward by a length 10d further than edge 10b at position BB along line BB. Therefore, the length L2 of protrusion 10c is longer than... Figure 13B The length L1 of edge 10b is described in the figure.

[0073] In other words, because the protrusion 10c is relatively long, it does not recede due to the aforementioned dry etching. Therefore, the top surface of the protrusion 10c is formed at a position that is higher than the top surface of the active region 10a by a height difference T, and the protrusion 10c protrudes upward. The height difference T depends on the length L2 of the protrusion 10c. For example, the optimal value of the length L2 of the protrusion 10c sufficient to obtain the necessary height difference T can be found by using a test element group (TEG) chip to test protrusions 10c with various lengths L2.

[0074] And, as Figure 13D As explained in the text, along Figure 13A In the part of line CC, Figure 12A The protrusions 60a of the resist 60 described herein are transferred and patterned. For example... Figure 13A and 13D As described in the document, the edge position 62c of the 15th insulating film 50 is different from other parts (or in other words, along the edge position 62c). Figure 13A The edge position 62b of the line AA or BB portion protrudes further toward the memory cell area M with a protrusion length 62a. This arrangement forms a protrusion 62d. A groove 62 is not formed in the area providing the protrusion 62d. Therefore, the word line 4 is not formed in the portion providing the protrusion 62d in the subsequent step.

[0075] Next, as Figures 14A to 14E As described, the conductive portion 64 is embedded in the trench 62, and in addition, known photolithography techniques and undescribed anisotropic dry etching are performed to form a step 64a in the conductive portion 64 in the memory cell region M.

[0076] The conductive portion 64 contains, for example, a conductive material, such as titanium nitride (TiN). For example, the conductive portion 64 is formed by depositing titanium nitride by CVD and then performing an anisotropic dry etching to retain the titanium nitride inside the trench 62.

[0077] Here, as Figure 14C As explained, in the section along line BB, a protrusion 10c is formed whose top surface protrudes outward and is higher than the active region 10a. An anisotropic dry etching process is performed to form the conductive portion 64 until the polysilicon on the top surface of the protrusion 10c is removed and the top surface of the protrusion 10c is exposed. With this arrangement, the conductive portion 64 is not formed on the top of the protrusion 10c, thereby dividing the conductive portion 64. With this arrangement, the top of the protrusion 10c serves as the first portion 4a in which the conductive portion 64 is not formed.

[0078] Furthermore, in the section along CC, such as Figure 14DAs described herein, this includes a protrusion 62d in which the 16th insulating film 52 protrudes toward the memory cell region M. Since the trench 62 is not formed in this portion, the protrusion 62d serves as the second portion 4b in which the conductive portion 64 is not formed.

[0079] Next, as Figures 15A to 15F As explained, step 64a is filled with polysilicon 68, and subsequently, a 20th insulating film 70 is formed on top of the semiconductor substrate 10 to cover the 14th insulating film 48, the 16th insulating film 52, the conductive portion 64, the polysilicon 68, etc. formed on the semiconductor substrate 10.

[0080] Polycrystalline silicon 68 is formed, for example, by CVD deposition of polycrystalline silicon, followed by an anisotropic dry etching process to fill step 64a. The 20th insulating film 70 contains, for example, an insulating material, such as silicon dioxide. The 20th insulating film 70 is formed, for example, by CVD.

[0081] Subsequently, contact holes reaching each conductive portion 64 are formed by the top surface of the 20th insulating film 70, and the contact holes are filled with a conductive material to form word line contacts 8. The word line contacts 8 contain, for example, a conductive material, such as tungsten. The word line contacts 8 are formed by, for example, depositing a conductive material such as tungsten by CVD to fill the contact holes, and then performing an etch-back process by anisotropic dry etching. Through the above steps, a semiconductor device 1A according to the first embodiment can be formed.

[0082] According to the semiconductor device 1A and its formation method according to the first embodiment, the following effects are obtained. For example... Figure 15A As explained, in the peripheral area N, word line contacts 8 are connected to every other word line 4. Word line contacts 8 in the memory block end area Y are not connected to word lines 4; the word lines 4 are connected to word line contacts 8 in the memory block end area X. Word line contacts 8 in the memory block end area Y are connected to word lines 4, but the word lines 4 are not connected to word line contacts 8 in the memory block end area X.

[0083] In the memory block end region X, a first portion 4a in which word line 4 is absent is positioned closer to the memory cell region M than the location of the word line contact 8 adjacent to word line 4. Word line 4 and cut-off portion 4c are physically and electrically isolated by the first portion 4a. Cut-off portion 4c is electrically floating. In the memory block end region X, a second portion 4b in which word line 4 is absent is provided in the region adjacent to word line contact 8.

[0084] A word line 4 having a second portion 4b and two word lines 4 connected to a word line contact 8 exist between a word line 4 having a first portion 4a. A word line 4 having a first portion 4a and two word lines 4 having neither a first portion 4a nor a second portion 4b exist between a word line 4 having a second portion 4b. The word line contact 8 is connected to the two word lines 4 that have neither a first portion 4a nor a second portion 4b.

[0085] By configuring the word lines 4 in this way, even if one of the word line contacts 8 is misaligned, the word line contact 8 will not contact anything on the side of the second portion 4b, and even if the word line contact 8 contacts the cut-off portion 4c, the cut-off portion 4c will not connect to any of the word lines 4. With this arrangement, short circuits with adjacent word lines 4 can be avoided or reduced even if the word line contacts 8 are misaligned. Therefore, the manufacturing yield of the semiconductor device 1A can be improved.

[0086] Furthermore, according to the semiconductor device 1A and its formation method according to the first embodiment, the first portion 4a without word lines 4 is formed by the presence of protrusions 10c. This is achieved by using the semiconductor device 1A provided with... Figure 9A and 9C The protrusion 44b in the resist 44 described herein serves as a model for forming the protrusion 10c. In other words, the first part 4a is formed on the basis of the protrusion 44b in the resist 44.

[0087] On the other hand, the second part 4b, in which the word line 4 is not formed, is provided by using Figure 12A and 12D The protrusions 60a in the resist 60 described herein are formed as a mask to transfer the pattern onto the underlying material. In other words, the second portion 4b is formed by using the protrusions 60a of the resist 60 as a model. Therefore, even if the first portion 4a and the second portion 4b are closer to each other than the lithographic resolution limit, the patterning of the first portion 4a and the second portion 4b is still possible because the portions are formed in separate lithographic steps.

[0088] Furthermore, according to the semiconductor device 1A and its formation method according to the first embodiment, as described above, a first portion 4a in which word lines 4 are not formed is formed by using the protrusions 44b of the resist 44 as a model. Three word lines 4 are arranged, and sufficient distance is provided between two of them in the first portion 4a. Therefore, since sufficient distance is provided between the plurality of protrusions 44b that serve as a model for the patterning of the first portion 4a without exceeding the photolithographic resolution limit, it is possible to avoid phenomena such as the first portion 4a being unpatternable.

[0089] Furthermore, according to the semiconductor device 1A and its formation method according to the first embodiment, as described above, a second portion 4b in which word lines 4 are not formed is formed by using the protrusions 60a of the resist 60 as a model. Three word lines 4 are arranged, and sufficient distance is provided between two of them in the second portion 4b. Therefore, since sufficient distance is provided between the plurality of protrusions 60a that serve as a model for patterning the second portion 4b without exceeding the photolithographic resolution limit, it is possible to avoid phenomena such as the second portion 4b being unable to be patterned.

[0090] (Second Embodiment)

[0091] In the following text, reference will be made to Figures 1 to 4 and Figures 16A to 26F A semiconductor device 1B according to a second embodiment and a method for forming the same are described. In the description of the method for forming the semiconductor device according to the second embodiment, in the second embodiment... Figures 16A to 16C The execution process in the first embodiment is the same as that in the second embodiment. Figure 5A and 5B The process is the same as that executed in the middle.

[0092] exist Figures 17A to 17C The execution process in the first embodiment is the same as that in the second embodiment. Figure 6A and 6B The process executed in the middle is the same. Figures 18A to 18C The execution process in the first embodiment is the same as that in the second embodiment. Figure 7A and 7B The process is the same as that executed in the middle. Figures 19A to 19C The execution process in the first embodiment Figure 8A and 8B The process is the same as that executed in the middle.

[0093] exist Figures 20A to 20C The execution process in the first embodiment is the same as that in the second embodiment. Figures 9A to 9C The process executed in the middle is the same. Figures 21A to 21C The execution process in the first embodiment is the same as that in the second embodiment. Figures 10A to 10C The process executed in the middle is the same. Figures 22A to 22C The execution process in the first embodiment is the same as that in the second embodiment. Figures 11A to 11C The process is the same as that executed in the middle.

[0094] exist Figures 23A to 23D The execution process in the first embodiment is the same as that in the second embodiment. Figures 12A to 12E The process executed in the middle is the same. Figures 24A to 24D The execution process in the first embodiment is the same as that in the second embodiment. Figures 13A to 13D The process executed in the middle is the same. Figures 25A to 25E The execution process in the first embodiment is the same as that in the second embodiment. Figures 14A to 14E The process executed in the middle is the same. Figures 26A to 26F The execution process in the first embodiment is the same as that in the second embodiment. Figures 15A to 15FThe process is the same as that executed in the middle.

[0095] Figures 1 to 3 The plan view layout of the semiconductor device 1 (1B) according to the second embodiment is described below. Furthermore, Figure 4 The image shows a longitudinal cross-sectional view illustrating an example of the general schematic configuration of the memory cell region in the semiconductor device 1 (1B) according to the second embodiment. Figures 1 to 4 The configuration of the semiconductor device 1B according to the second embodiment described herein is similar to the configuration of the semiconductor device 1A according to the first embodiment.

[0096] Reference Figures 16A to 26F The semiconductor device 1B according to the second embodiment and the method of forming the same are described. Figures 16A to 26F To explain in sequence Figure 1A The diagram illustrates the schematic configuration of the end region X of the memory chip.

[0097] First, a method for forming the semiconductor device 1B according to the second embodiment will be described. For example... Figure 16A and 16B As described herein, the execution is the same as that in the first embodiment. Figure 5A and 5B The process described is similar to that described.

[0098] like Figure 16A and 16C As described, in the portion along line BB, the resist 32 has a protrusion 32a protruding toward the memory cell region M. The protrusion 32a has a predetermined protrusion length 32b. Otherwise, the configuration is different from that of the first embodiment. Figure 5A and 5B The configurations described in the document are largely the same.

[0099] Next, as Figures 17A to 17C As described herein, the execution is the same as that in the first embodiment. Figure 6A and 6B The process described is similar. Anisotropic dry etching is performed on the memory cell region M. This transfers the superimposed pattern of resist 32, the ninth insulating film 30, and the polysilicon film 24 onto the sixth insulating film 22, the fifth insulating film 20, the fourth insulating film 18, the third insulating film 16, and the second insulating film 14. Subsequently, the polysilicon film 24, the sixth insulating film 22, and the fifth insulating film 20 are removed.

[0100] like Figure 17A , 17B As described in 17C, this step enables the following: Figure 16AThe pattern of the resist 32, as described above, is transferred onto the fourth insulating film 18, the third insulating film 16, and the second insulating film 14. Through this arrangement, protrusions 18a with a protrusion length 18b are formed in the portion along line BB, as shown below. Figure 17A and 17C As explained in the text.

[0101] Next, as Figures 18A to 18C As described herein, the execution is the same as that in the first embodiment. Figure 7A and 7B The process described is similar. Through this step, the pattern of the protrusion 18a is transferred onto the second insulating film 14, the first insulating film 12 and the semiconductor substrate 10, and a protrusion 14a with a protrusion length 14b is formed.

[0102] Next, as Figure 19A and 19B As described herein, the execution is the same as that in the first embodiment. Figure 8A and 8B The process described is similar to that described. Figure 19A and 19B The configuration described herein is the same as that in the first embodiment. Figure 8A and 8B The configurations described in the document are largely the same.

[0103] Next, as Figures 20A to 20C As described herein, the execution is the same as that in the first embodiment. Figures 9A to 9C The described process is similar to that of a process. For example... Figure 20A and 20C As explained herein, in the method of forming the semiconductor device 1B according to the second embodiment, the resist 44 does not have Figure 9A The protrusions 44b, etc., described herein. The rest of the configuration is similar to that of the first embodiment. Figures 9A to 9C The configuration described in the document.

[0104] Next, as Figures 21A to 21C As described herein, the execution is the same as that in the first embodiment. Figures 10A to 10C The described process is similar to that of a process. For example... Figure 21C As explained in the diagram, in the longitudinal section view along line BB, by using... Figure 16A and 16C The protrusion 32a described herein serves as a model for transferring protrusion 10e. Therefore, the protrusion length 10f of protrusion 10e is formed to reflect... Figure 16A and 16C The protrusion length described in the document is 32b.

[0105] The rest of the configuration is similar to that of the first embodiment. Figures 10A to 10C The configuration described in the document.

[0106] Next, as Figures 22A to 22C As described herein, the execution is the same as that in the first embodiment. Figures 11A to 11C The process described is similar to that described. Figures 22A to 22C The configuration described herein is the same as that in the first embodiment. Figures 11A to 11C The configurations described in the document are largely the same.

[0107] Next, as Figures 23A to 23D As described herein, the execution is the same as that in the first embodiment. Figures 12A to 12E The described process is similar to that of a process. For example... Figure 23A and 23D As described, the resist 60 has a protrusion 60a that protrudes outward in the direction of the memory cell region M with a protrusion length 60b. The rest of the configuration is substantially the same as that of the first embodiment. Figure 23A The configuration of the line DD section and Figure 12E The configurations described in the document are largely the same.

[0108] Next, as Figures 24A to 24D As described herein, the execution is the same as that in the first embodiment. Figures 13A to 13D The process described is similar. Anisotropic dry etching forms straight trenches 62 in areas not covered by the resist 60 with protrusions 60a and the hard mask 59. Conductive material is embedded in the trenches 62 in a later step, and the embedded conductive material acts as DRAM word lines 4 (e.g., word lines 4 are embedded in the trenches 62). Next, the resist 60 and the 17th insulating film 54, 18th insulating film 56, 19th insulating film 58, and 14th insulating film 48 on the top surface of the semiconductor substrate 10 in the area are removed.

[0109] like Figures 24B to 24D As explained, trenches 62 with the shape of resist 60 transferred thereto are formed in the peripheral region N by dry etching. Furthermore, as... Figure 24C As explained, protrusion 10e extends outward by a length 10f further than edge 10b at position BB along line BB. Therefore, the length L2 of protrusion 10e is longer than... Figure 24B The length L3 of the edge 10b described herein. In other words, since the protrusion 10e is relatively long, the surface of the protrusion 10e does not recede due to the above dry etching, the top surface of the protrusion 10e is formed at a position that is higher than the top surface of the active region 10a by a height difference T, and the protrusion 10e protrudes upward.

[0110] The height difference T depends on the length L4 of the protrusion 10e. For example, the optimal value of the length L4 of the protrusion 10e sufficient to obtain the necessary height difference T can be found by using a test element group (TEG) chip to test protrusions 10e in which various lengths L4 are formed.

[0111] And, as Figure 24D As explained in the text, along Figure 24A In the part of line CC, Figure 23A The protrusions 60a of the resist 60 described herein are transferred and patterned onto the 16th insulating film 52, etc., to obtain a coating with the resist. Figure 13D The configuration is similar to that of the previous one.

[0112] Next, as Figures 25A to 25E As described herein, the execution is the same as that in the first embodiment. Figures 14A to 14E The process described is similar to that described. Figures 25A to 25E The configuration described herein is the same as that in the first embodiment. Figures 14A to 14E The configurations described in the document are largely the same.

[0113] Next, as Figures 26A to 26F As described herein, the execution is the same as that in the first embodiment. Figures 15A to 15F The process described is similar to that described. Figures 26A to 26F The configuration described herein is the same as that in the first embodiment. Figures 15A to 15F The configurations described in the document are largely the same.

[0114] According to the semiconductor device 1B and the method of forming therewith according to the second embodiment, effects similar to those of the semiconductor device 1A and the method of forming therewith according to the first embodiment can be obtained.

[0115] Furthermore, according to the semiconductor device 1B and its formation method according to the second embodiment, the first portion 4a without word lines 4 is formed by the presence of protrusions 10e. This is achieved by using the semiconductor device 1B provided with... Figure 16A and 16C The protrusions 32a in the resist 32 described herein are used as a model for transfer to form the protrusion 10e. In other words, the first part 4a is formed by using the protrusions 32a of the resist 32 as a model.

[0116] On the other hand, the second part 4b, in which the word line 4 is not formed, is provided by using Figure 23A and 23D The protrusions 60a in the resist 60 described herein are formed as a mask to transfer the pattern to the underlying material. In other words, the second portion 4b is formed by using the protrusions 60a of the resist 60 as a model. Therefore, even if the first portion 4a and the second portion 4b are closer to each other than the lithographic resolution limit, since the portions are formed in separate lithographic steps, phenomena such as the inability to achieve patterning are avoided.

[0117] Furthermore, according to the semiconductor device 1B and its formation method according to the second embodiment, as described above, a first portion 4a in which word lines 4 are not formed is formed by using the protrusions 32a of the resist 32 as a model. Three word lines 4 are arranged between two points in the first portion 4a, and sufficient distance is provided between the two points in the first portion 4a. Therefore, since sufficient distance is provided between the multiple protrusions 32a that serve as a model for the pattern of the first portion 4a, it is possible to maintain a resolution at or below the lithographic resolution limit and avoid phenomena such as the inability to achieve patterning.

[0118] Furthermore, according to the semiconductor device 1B and its formation method according to the second embodiment, as described above, a second portion 4b in which word lines 4 are not formed is formed by using the protrusions 60a of the resist 60 as a model. Three word lines 4 are arranged, and sufficient distance is provided between the two in the second portion 4b. Therefore, since sufficient distance is provided between the plurality of protrusions 60a that serve as a model for the patterning of the second portion 4b, it is possible to maintain at or below the lithographic resolution limit and avoid phenomena such as the inability to achieve patterning.

[0119] As described above, DRAM is described as an example of semiconductor device 1 (1A, 1B) according to the embodiments; however, the above description is merely an example and is not intended to limit it to DRAM. For example, memory devices other than DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase-change memory, can also be used as semiconductor device 1.

[0120] While the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the invention itself and its obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also possible and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form variations of the disclosed invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. A semiconductor device comprising: Substrate; A memory cell region is provided above the substrate; A peripheral region is provided above the substrate and adjacent to the memory cell region; Multiple word lines extend across the memory cell region and the peripheral region; and Multiple contacts, each connected to the edge portion of an even-numbered word line among the multiple word lines in the peripheral area; The edge portion of each of the even-numbered word lines in the plurality of word lines is adjacent to the portion lacking the odd-numbered word lines; and In the plurality of word lines, the other side of each of the edge portions of the even-numbered word lines is adjacent to the cut-off portion of another odd-numbered word line, wherein the cut-off portion of the other odd-numbered word line is physically and electrically isolated from the other odd-numbered word line.

2. The semiconductor device according to claim 1, further comprising: An additional peripheral region is provided above the substrate, such that the memory cell region is disposed between the peripheral region and the additional peripheral region, and the plurality of word lines extend above the additional peripheral region; and Multiple additional contacts, which are respectively connected to the edge portions of the odd-numbered word lines among the multiple word lines in the additional peripheral area; The edge portion of each of the even-numbered word lines in the plurality of word lines is adjacent to the portion lacking the even-numbered word line on one side; and The other side of each of the edge portions of the odd-numbered word lines is adjacent to an additional cut-off portion of another even-numbered word line, wherein the additional cut-off portion of the other even-numbered word line is physically and electrically isolated from the other even-numbered word line.

3. The semiconductor device according to claim 1, wherein the cut-off portion is electrically floating.

4. The semiconductor device of claim 2, wherein the additional cut-off portion is electrically floating.

5. The semiconductor device of claim 1, wherein the memory cell region comprises a plurality of memory cells.

6. The semiconductor device of claim 5, wherein each of the plurality of word lines is coupled to a corresponding memory cell among the plurality of memory cells to control access to the corresponding memory cell among the plurality of memory cells.

7. The semiconductor device of claim 1, wherein each of the plurality of word lines is embedded in a trench in the substrate.

8. The semiconductor device of claim 7, wherein each of the plurality of word lines comprises a conductive material.

9. A semiconductor device comprising: Substrate; A memory cell region is provided above the substrate; A peripheral region is provided above the substrate and adjacent to the memory cell region; and The first, second and third word lines extend across the memory cell area and the peripheral area; The first character line is provided adjacent to the second character line and the third character line; The first length of the first character line in the outer perimeter area is longer than the second length of the second character line in the outer perimeter area; and Wherein the second length of the second character line in the outer perimeter area is longer than the third length of the third character line in the outer perimeter area, Wherein, one side of the edge portion of the first character line is adjacent to the portion lacking the second character line; and The edge portion of the first character line is adjacent to the cut-off portion of the third character line on the other side, wherein the cut-off portion of the third character line is physically and electrically isolated from the third character line.

10. The semiconductor device of claim 9, further comprising a contact connected to an edge portion of the first word line in the peripheral region.

11. The semiconductor device of claim 9, further comprising: A fourth word line is arranged adjacent to the third word line, the fourth word line having the same length as the first word line and extending across the memory cell area and the peripheral area.

12. The semiconductor device of claim 11, further comprising: A fifth word line is arranged adjacent to the second word line, the fifth word line having the same length as the first word line and extending across the memory cell area and the peripheral area.

13. The semiconductor device of claim 9, wherein the memory cell region comprises a plurality of memory cells and a plurality of word lines, each of the plurality of word lines being connected to a corresponding memory cell among the plurality of memory cells.

14. The semiconductor device of claim 9, wherein each word line is embedded in a trench provided in the substrate.

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