Semiconductor structure and method of forming the same
By forming a cap layer and a hard mask layer with grooves on the metal layer and the interlayer dielectric layer, the metal layer is protected from etching, which solves the damage problem caused by metal gate etching and improves the electrical performance and process reliability of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-03-12
- Publication Date
- 2026-06-05
AI Technical Summary
In the semiconductor manufacturing process, the etching of metal gates leads to particle defects and damage to the work function layer, affecting the electrical performance and threshold voltage stability of the device.
A grooved cap layer is formed on the metal layer and the interlayer dielectric layer, and a hard mask layer is covered to protect the metal layer from etching. The intermediate layer is etched through an oxide layer as a mask to avoid damage to the work function layer.
It improves the electrical performance of semiconductor structures, prevents damage to metal gates, reduces process difficulty and alignment errors, and enhances device reliability and performance.
Smart Images
Figure CN115083891B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] In semiconductor manufacturing, with the rapid development of integrated circuit (IC) technology, while the geometric size of the smallest component that can be formed using manufacturing processes is decreasing, its functional density, i.e., the number of interconnect devices per chip area, is generally increasing. Due to the reduction in device size, gate polysilicon depletion, substrate quantum effects, and gate leakage current become increasingly severe, significantly impacting the power consumption and reliability of integrated circuits. Therefore, to reduce gate leakage, high-k (high dielectric constant) dielectric materials are often used as the gate dielectric layer. This allows for a larger physical gate dielectric layer with the same equivalent gate oxide thickness, thereby improving gate leakage current.
[0003] In addition, in some integrated circuit designs, as technology nodes shrink, metal gate (MG) electrodes are used to replace typical polysilicon gate electrodes to improve the performance of existing devices. The process of forming metal gate electrodes is called the "Gate-Last" process, also known as the Replacement Metal Gate (RMG) process.
[0004] Currently, metal gates are connected to other devices via a zero-level gate metal layer (MOG). Etching the zero-level gate metal layer exposes the metal gate, making it susceptible to sufferr particle defects. Furthermore, patterning the zero-level gate metal layer damages the work function (WF) layer, which is removed in subsequent processes. Since the work function layer is primarily used to regulate the device's threshold voltage, the processes involving the zero-level gate metal layer significantly impact the threshold voltage shift. Summary of the Invention
[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the device.
[0006] First, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:
[0007] A substrate is provided, the substrate including a substrate, a gate structure on the substrate, a metal layer on top of the gate structure, a source / drain doped layer on the side of the gate structure, and an interlayer dielectric layer covering the source / drain doped layer;
[0008] A cap layer with grooves is formed over the metal layer and the interlayer dielectric layer, wherein the grooves expose at least a portion of the metal layer;
[0009] A hard mask layer is formed on the groove and the cap layer, the hard mask layer covering the metal layer exposed in the groove;
[0010] The metal layer is etched to form a first opening;
[0011] Remove the hard mask layer;
[0012] An intermediate layer and an oxide layer are sequentially formed above the metal layer and the interlayer dielectric layer, and the oxide layer has a second opening that exposes the intermediate layer.
[0013] Using the oxide layer as a mask, the intermediate layer is etched to form a third opening;
[0014] A gate plug is formed in the third opening, the characteristic dimension of the gate plug being larger than the characteristic dimension of the metal layer.
[0015] Optionally, the groove may also expose a portion of the interlayer dielectric layer.
[0016] Optionally, the width of the groove is greater than the width of the second opening.
[0017] Optionally, the step of forming a cap layer with grooves on the metal layer and the interlayer dielectric layer, wherein the grooves expose at least a portion of the metal layer, includes:
[0018] A cap layer is formed on the metal layer and the interlayer dielectric layer;
[0019] A first anti-reflective coating and a first photoresist layer are sequentially formed on the cap layer, wherein the first photoresist layer has a first patterned opening that exposes a portion of the first anti-reflective coating.
[0020] Using the first photoresist layer as a mask, the first anti-reflective coating and the cap layer are sequentially etched along the first pattern opening. Part of the cap layer is removed to form a groove, which exposes part of the metal layer and part of the interlayer dielectric layer.
[0021] Optionally, the cap layer may be formed using atomic layer deposition or chemical vapor deposition.
[0022] Optionally, the material of the cap layer includes one or more of silicon carbonitride, silicon nitride, silicon oxide, silicon carbide, and silicon boron nitride.
[0023] Optionally, forming a hard mask layer on the groove and the cap layer, the hard mask layer covering the metal layer exposed by the groove, includes:
[0024] A hard mask layer is formed in the groove and on the cap layer using atomic layer deposition or chemical vapor deposition processes.
[0025] The hard mask layer on the cap layer is removed using a planarization process, so that the groove is flush with the top of the cap layer, and the hard mask layer covers the metal layer exposed by the groove.
[0026] Optionally, after removing the hard mask layer on the cap layer using a planarization process, the method further includes: removing the cap layer.
[0027] Optionally, the material of the hard mask layer is titanium nitride.
[0028] Optionally, removing the hard mask layer includes:
[0029] A capping layer is formed on the first opening, the hard mask layer, and the interlayer dielectric layer using atomic layer deposition or chemical vapor deposition.
[0030] The capping layer and hard mask layer on the metal layer, as well as the capping layer above the first opening and on the interlayer dielectric layer, are removed using a planarization process.
[0031] Optionally, the material of the capping layer includes one or more of silicon carbonitride, silicon nitride, silicon oxide, silicon carbide, and silicon boron nitride.
[0032] Optionally, an intermediate layer and an oxide layer are sequentially formed over the metal layer and the interlayer dielectric layer, the oxide layer having a second opening that exposes the intermediate layer, including:
[0033] The intermediate layer and the oxide layer are sequentially formed over the metal layer and the interlayer dielectric layer using atomic layer deposition or chemical vapor deposition processes.
[0034] A second anti-reflective coating and a second photoresist layer are sequentially formed on the oxide layer, wherein the second photoresist layer has a second patterned opening that exposes a portion of the second anti-reflective coating.
[0035] Using the second photoresist layer as a mask, the second photoresist layer and the oxide layer are sequentially etched along the second pattern opening to form a second opening, which exposes a portion of the intermediate layer.
[0036] Optionally, the material of the intermediate layer includes one or more of silicon carbonitride, silicon nitride, silicon oxide, silicon carbide, and silicon boron nitride.
[0037] Optionally, a gate plug is formed in the third opening, including:
[0038] A gate plug is formed in the third opening using atomic layer deposition or chemical vapor deposition.
[0039] The gate plug exposing the third opening is removed using a planarization process.
[0040] Optionally, the gate plug may be made of one or more of tungsten, magnesium-tungsten alloy, ruthenium, and cobalt.
[0041] Accordingly, embodiments of the present invention provide a semiconductor structure, including: a substrate; a gate structure located on the substrate; a source / drain doped layer located on the side of the gate structure; an interlayer dielectric layer covering the source / drain doped layer; an intermediate layer located above the interlayer dielectric layer and the gate structure; an oxide layer located above the intermediate layer; and a gate plug located above the metal layer, penetrating the openings of the intermediate layer and the oxide layer, and connected to the metal layer, wherein the feature size of the gate plug is larger than the feature size of the metal layer.
[0042] Optionally, the material of the intermediate layer includes one or more of silicon carbonitride, silicon nitride, silicon oxide, silicon carbide, and silicon boron nitride.
[0043] Optionally, the gate plug may be made of one or more of tungsten, magnesium-tungsten alloy, ruthenium, and cobalt.
[0044] The semiconductor structure formation method of this invention involves forming a cap layer with grooves above the metal layer and the interlayer dielectric layer before etching the metal layer to form the first opening. The grooves expose at least a portion of the metal layer. Then, a hard mask layer is formed on the grooves and the cap layer, covering the exposed metal layer. Because the metal layer above the metal gate is covered by the hard mask layer, it is not removed during subsequent etching. Furthermore, during the etching of the intermediate layer using the oxide layer as a mask to form the third opening, the gate structure is not damaged. Specifically, the work function layer in the gate structure is not damaged, preventing the damaged work function layer from being removed in subsequent processes, thus improving the electrical performance of the semiconductor device.
[0045] Furthermore, an intermediate layer and an oxide layer are sequentially formed above the metal layer and the interlayer dielectric layer. The oxide layer has a second opening that exposes the intermediate layer. Since the width of the groove formed in the aforementioned process is greater than the width of the second opening, the process window for subsequent photolithography processes is expanded. This makes it easier to align the second opening with the metal layer during the second photolithography process, reducing the difficulty of the process. Attached Figure Description
[0046] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0047] Figures 7 to 19 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0048] The devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.
[0049] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0050] Reference Figure 1 A substrate is provided, the substrate including a substrate 10, a gate structure 11 on the substrate 10, a metal layer 12 on top of the gate structure 11, a source / drain doped layer 13 on the side of the gate structure 11, and an interlayer dielectric layer 14 covering the source / drain doped layer 13. The gate structure 11 includes a work function layer 111 and a gate layer 112 on the work function layer.
[0051] Reference Figure 2 The metal layer 12 on the top of the gate structure 11 is removed by a back etching process to form an opening 15, which exposes the top of the gate structure 11.
[0052] Reference Figure 3 A capping layer 16 is formed in the opening 15, and the capping layer 16 covers the opening 15.
[0053] Reference Figure 4 An intermediate layer 17 and an oxide layer 18 are sequentially formed above the interlayer dielectric layer 14 and the capping layer 16. The oxide layer 18 has an opening ( Figure 4 (Not shown), the opening exposes the intermediate layer 17.
[0054] Using the oxide layer 18 as a mask, the opening is removed to expose the intermediate layer 17, forming an opening 19, which exposes the top of the cap layer 16.
[0055] Reference Figure 5 and Figure 6 ,like Figure 5 As shown, the opening 19 is removed by an etching process to expose the cap layer 16, forming an opening 20, which exposes the top of the gate structure 11.
[0056] likeFigure 6 As shown, a gate plug 21 is formed in the opening 20.
[0057] During the formation of the aforementioned semiconductor structure, such as Figure 5 As shown in circle I, the etching process used to remove the sacrificial material layer to form the capping layer 16 will damage the work function layer 111. In subsequent processes, the damaged work function layer 111 will be removed, causing a change in the work function value of the work function layer 111. Since the work function layer 111 is mainly used to adjust the threshold voltage of the device, this will lead to an increase or decrease in the threshold voltage, thus affecting the electrical performance of the semiconductor device.
[0058] To address the aforementioned issues, in this embodiment of the invention, before etching the metal layer, a cap layer with grooves is first formed. The grooves expose a portion of the metal layer and a portion of the interlayer dielectric layer hard mask layer. Then, a hard mask layer is formed to cover the portion of the metal layer exposed by the grooves. This prevents the metal layer on the metal gate from being etched away during the etching process, thus ensuring that subsequent processes do not damage the work function layer, preventing the work function layer from being removed, and improving the electrical performance of the semiconductor structure.
[0059] To enable those skilled in the art to better understand and implement the embodiments of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the following drawings describe the embodiments of the present invention from two perspectives.
[0060] Figures 7 to 19 This is a schematic diagram of the structure corresponding to each step in an embodiment of the semiconductor structure formation method of the present invention, wherein... Figures 7 to 19 Subfigure number (a) is a cross-sectional view perpendicular to the fin, and subfigure number (b) is a cross-sectional view along the fin direction.
[0061] Reference Figure 7 Provides a base. For example... Figure 7 As shown in (a), the substrate includes a substrate 100, a gate structure 101 on the substrate 100, a metal layer 102 on top of the gate structure 101, a source / drain doped layer 103 on the side of the gate structure 101, and an interlayer dielectric layer 104 covering the source / drain doped layer 103, wherein the interlayer dielectric layer 104 is exposed on top of the gate structure 101.
[0062] The substrate provides a process platform for the subsequent formation of semiconductor structures.
[0063] In this embodiment of the invention, the semiconductor structure formed is a fin field-effect transistor (Fin FET) as an example, such as... Figure 7As shown in (b). Accordingly, the substrate includes a substrate 100 and fins 200 located on the substrate 100, and a source / drain doped layer covering the substrate. Figure 7 (b) Interlayer dielectric layer 104 (not shown), located in the gate structure ( Figure 7 (b) The upper metal layer 102 (not shown) and the work function layer 1011 located below the metal layer 102. In other embodiments, the semiconductor structure may also be a planar transistor (MOSFET).
[0064] In this embodiment of the invention, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0065] When the semiconductor structure is in operation, the gate structure 101 is used to turn the channel on or off.
[0066] Specifically, the gate structure 101 may include a work function layer 1011 and a gate layer 1012 located on the work function layer 1011. The work function layer 1011 is used to adjust the threshold voltage of the transistor.
[0067] In this embodiment of the invention, the gate layer 1012 is made of tungsten. In other embodiments, the gate layer 1012 is made of one or more of cobalt, ruthenium, and magnesium-tungsten alloys.
[0068] In this embodiment of the invention, the steps for forming the gate structure 101 and the metal layer 102 typically include: forming a gate opening (not shown in the figure) between the interlayer dielectric layers 104; conformally covering the bottom surface and sidewalls of the gate opening with work function material layers (not shown in the figure), wherein the work function material layers have trenches (not shown in the figure) between them; removing the work function material layer at the top of the gate opening, leaving the remaining work function material layer as work function layer 1011; forming conductive material layers on the trenches and the work function layer 1011, wherein the conductive material layer in the trenches serves as gate layer 1012, and the conductive material layer above the top surface of the work function layer 1011 serves as metal layer 102.
[0069] In the step of forming the gate structure 101 and the metal layer 102, the work function material layer at the top of the gate opening is removed to form a work function layer 1011. This reduces the aspect ratio of the trenches between the work function layers 1011, reduces the difficulty of filling the conductive material layer in the trenches, and makes it less likely for pores to exist in the conductive material layer formed between the work function layers 1011, which is beneficial to improving the formation quality of the gate layer 1012.
[0070] It should be noted that the substrate may further include a sidewall layer 106. The sidewall layer 106 is located on the sidewall of the gate structure 101, protecting the sidewall of the gate structure 101 from damage.
[0071] In this embodiment, the material of the sidewall layer 106 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.
[0072] When the semiconductor structure is in operation, the source and drain doped layers 103 are used to provide stress to the channel and improve the migration rate of carriers in the channel.
[0073] In this embodiment of the invention, the semiconductor structure can be used to form an N-channel metal-oxide-semiconductor (NMOS), and the source / drain doped layer 103 is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, by doping silicon carbide or silicon phosphide with N-type ions, the N-type ions replace the positions of silicon atoms in the crystal lattice. The more N-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. In this embodiment of the invention, the N-type ion material includes phosphorus, arsenic, or antimony.
[0074] In other embodiments, the semiconductor structure is used to form a P-channel metal-oxide-semiconductor (PMOS), and the source / drain doping layer is silicon germanide doped with P-type ions. By doping silicon germanide with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice. The more P-type ions incorporated, the higher the majority carrier concentration and the stronger the conductivity. The P-type ion material may include boron, gallium, or indium.
[0075] In this embodiment, the material of the interlayer dielectric layer 104 is an insulating material. Specifically, the material of the interlayer dielectric layer 104 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 104.
[0076] It should be noted that the substrate may further include an etch-resistant layer 105, which protects the source / drain doped layer 103 from damage. In this embodiment, the etch-resistant layer 105 is made of silicon nitride. In other embodiments, the etch-resistant layer 105 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and boron silicon carbide.
[0077] Reference Figure 8 and Figure 9A cap layer 107 with a groove 110 is formed above the metal layer 102 and the interlayer dielectric layer 104, the groove 110 exposing at least a portion of the metal layer 102.
[0078] In embodiments of the present invention, such as Figure 8 As shown in (a), the metal layer 102 is formed on top of the gate structure 101, the cap layer 107 is formed on top of the metal layer 102, and the groove 110 formed by etching the cap layer 107 provides process space for the subsequent formation of the hard mask layer.
[0079] In specific implementation, such as Figure 8 As shown in (a), the step of forming a cap layer 107 with a groove 110 above the metal layer 102 and the interlayer dielectric layer 104, wherein the groove 110 exposes at least a portion of the metal layer 102, includes: forming the cap layer 107 on the metal layer 102 and the interlayer dielectric layer 104, and then sequentially forming a first anti-reflective coating 108 and a first photoresist layer 109 on the cap layer 107. The first photoresist layer 109 has a first patterned opening that exposes a portion of the first anti-reflective coating 108. Figure 8 (Not shown), using the first photoresist layer 109 as a mask, the first anti-reflective coating 108 and the cap layer 107 are sequentially etched along the first pattern opening. The cap layer 107 exposed by the first pattern opening is removed, forming a groove 110. The groove 110 exposes a portion of the metal layer 102, such as... Figure 9 As shown.
[0080] In this embodiment of the invention, the cap layer 107 can be formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which helps improve the thickness uniformity of the cap layer 107, enabling it to conformally cover the top of the metal layer 102 and the interlayer dielectric layer 104. Furthermore, ALD offers good gap-filling performance and step coverage, correspondingly improving the conformal coverage capability of the cap layer 107. In other embodiments, the cap layer 107 can be formed using chemical vapor deposition (CVD).
[0081] In this embodiment of the invention, the cap layer 107 is made of silicon carbonitride. In other embodiments, the cap layer 107 material further includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and boron nitride silicon carbide.
[0082] It should be noted that, in cases such as Figure 9In the step of forming the groove 110, the groove 110 can expose not only the metal layer 102, but also a portion of the interlayer dielectric layer 104, such as... Figure 10 As shown in (a), the width of the formed groove 110 is greater than the width of the metal layer 102.
[0083] It should be noted that after forming the cap layer 107 with the groove 110, it is also necessary to remove the first anti-reflective coating 108 and the first photoresist layer 109.
[0084] In this embodiment of the invention, the material of the first anti-reflective coating 108 includes: a dielectric anti-reflective coating (DARC) material or a bottom anti-reflective coating (BARC) material.
[0085] Reference Figure 10 and Figure 11 A hard mask layer 111 is formed on the groove 110 and the cap layer 107, and the hard mask layer 111 covers the metal layer 102 exposed in the groove 110.
[0086] like Figure 10 As shown, the step of forming a hard mask layer 111 on the groove 110 and the cap layer 107 includes: forming a hard mask layer 111 in the groove 110 and on the cap layer 107 using an atomic layer deposition process or a chemical vapor deposition process.
[0087] It should be noted that the hard mask layer 111 completely covers the groove 110 and the cap layer 107.
[0088] In this embodiment of the invention, the hard mask layer 111 is formed using atomic layer deposition (ALD). ALD improves the uniformity and density of the hard mask layer 111's thickness, allowing for precise control of its thickness. In other embodiments, the hard mask layer can also be formed using chemical vapor deposition (CVD).
[0089] In a specific implementation, the hard mask layer 111 is made of titanium nitride. In other embodiments, the hard mask layer material also includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and boron carbide.
[0090] It should be noted that the use of titanium nitride in this embodiment of the invention can solve the problem of polysilicon gate depletion in the metal-embedded polysilicon gate process, thereby improving the electrical performance of the device. In subsequent processes, the hard mask layer 111 also needs to be removed.
[0091] like Figure 11As shown, a planarization process is used to remove the hard mask layer 111 on the cap layer 107, and the cap layer 107 is used as an etching stop layer. The hard mask layer 111 covers the metal layer 102 exposed in the groove 110. Therefore, the hard mask layer 111 can serve as a protective layer for the metal layer, preventing the metal layer 102 from being removed in subsequent etching processes.
[0092] In this embodiment of the invention, chemical mechanical planarization (CMP) is used for the planarization process. During the planarization process, the top of the cap layer 107 is used as the etching stop position. Chemical mechanical planarization is a global surface planarization technique. After the chemical mechanical planarization process, the cap layer is flush with the top of the mask layer 111, and the groove 110 is completely filled by the hard mask layer 111.
[0093] It should be noted that after removing the hard mask layer 111 on the cap layer 107 using a planarization process, the remaining cap layer 107 also needs to be removed to expose the metal layer 102 to be removed in subsequent etching processes, such as... Figure 12 As shown in (a).
[0094] In this embodiment of the invention, an ashing process can be used to remove the cap layer 107. The material of the cap layer 107 includes organic materials. The ashing process can remove the cap layer 107 in a timely manner, making it less likely for the organic materials in the cap layer 107 to contaminate the machine.
[0095] Through the above process, a cap layer with grooves is first formed, and then a hard mask layer is used to fill the grooves, covering the metal layer exposed by the grooves. The hard mask layer formed can protect the metal layer on the metal gate from being etched during the etching process. Subsequent processes will not damage the work function layer, and the work function layer will not be removed, which can improve the electrical performance of the semiconductor structure device.
[0096] Reference Figure 13 The metal layer 102 is etched to form the first opening 120.
[0097] In this embodiment of the invention, a dry etching process is used to etch back the metal layer 102, forming a first opening 120 above the gate structure 101, such as... Figure 13 As shown in (a) or as... Figure 13 As shown in (b), a first opening 120 is formed above the work function layer 1011. The dry etching process can precisely control the removal thickness of the metal layer 102, reducing damage to other film structures. Since the hard mask layer 111 formed in the aforementioned process covers the metal layer 102 located on the metal gate, the metal layer 102 located below the hard mask layer 111 will not be removed.
[0098] Reference Figure 14 and Figure 15 Remove the hard mask layer 111.
[0099] The step of removing the hard mask layer 111 includes: as follows Figure 14 As shown, a capping layer 112 is formed on the first opening 120, the hard mask layer 111, and the interlayer dielectric layer 104 using atomic layer deposition (ALD) or chemical vapor deposition (CVD). Then, a planarization process is used to remove the capping layer 112 and the hard mask layer 111 on the metal layer 102, as well as the capping layer 112 on the first opening 120 and the interlayer dielectric layer 104. Figure 15 As shown.
[0100] In this embodiment of the invention, the capping layer 112 is formed using an atomic layer deposition (ALD) process. Using ALD improves the uniformity and density of the capping layer 112's thickness, allowing for precise control of its thickness.
[0101] In a specific implementation, during the planarization process, the top of the interlayer dielectric layer 104 is used as the etching stop position, so that the capping layer 112 can completely cover the substrate. Figure 13 The first opening 120 is formed.
[0102] In this embodiment of the invention, the material of the capping layer 112 is the same as the material of the anti-etching layer 105, which is silicon nitride. In other embodiments, the material of the capping layer 112 may also include one or more of silicon oxide, silicon nitride, silicon oxynitride, and boron carbide.
[0103] Reference Figure 16 and Figure 17 An intermediate layer 113 and an oxide layer 114 are sequentially formed above the metal layer 102 and the interlayer dielectric layer 104. The oxide layer 114 has a second opening 130 that exposes the intermediate layer 113.
[0104] In embodiments of the present invention, such as Figure 16 As shown, an intermediate layer 113 and an oxide layer 114 are sequentially formed on the metal layer 102 and the interlayer dielectric layer 104 using atomic layer deposition or chemical vapor deposition processes.
[0105] It should be noted that the material of the intermediate layer 113 is the same as that of the capping layer 112, both being silicon nitride. To distinguish between the intermediate layer and the capping layer in the semiconductor structure, different designations are used in this embodiment of the invention. In other embodiments, the material of the intermediate layer 113 may also be one or more of silicon carbonitride, silicon oxide, silicon carbide, and silicon boron nitride.
[0106] In this embodiment of the invention, the oxide layer 114 is made of plasma-enhanced oxide.
[0107] like Figure 17 As shown, a second anti-reflective coating 115 and a second photoresist layer 116 are sequentially formed on the surface, wherein the second photoresist layer 116 forms a second patterned opening that exposes a portion of the second anti-reflective coating 115. Figure 17 (Not shown), and then using the second photoresist layer 116 as a mask, the second anti-reflective coating 115 and the oxide layer 114 are sequentially etched along the second pattern opening, forming a second opening 130 in the oxide layer 114, with the second opening 130 exposing a portion of the intermediate layer 113.
[0108] It should be noted that after the second opening 130 is formed, the second anti-reflective coating 115 and the second photoresist layer 116 need to be removed.
[0109] In the implementation of this invention, as shown in Figure 10 The width of the formed groove 110 is greater than the width of the second opening 130, which expands the process window for subsequent photolithography processes. This makes it easier for the second opening 130 to align with the metal layer 102 during the second photolithography process, thereby reducing the difficulty of the process.
[0110] Reference Figure 18 Using the oxide layer 114 as a mask, the second opening 130 is etched to expose a portion of the intermediate layer 113, forming a third opening 140, which exposes the metal layer 102. The third opening 140 provides process space for the subsequent formation of the gate plug.
[0111] In this embodiment of the invention, the intermediate layer 113 is etched using a dry etching process, with the oxide layer 114 as a mask, to form the third opening 140. Dry etching has anisotropic etching characteristics and good control over the etching profile, ensuring that the morphology of the third opening 140 meets the process requirements.
[0112] Reference Figure 19 A gate plug 150 is formed in the third opening 140, and the feature size of the gate plug 150 is larger than the feature size of the metal layer 102.
[0113] In this embodiment of the invention, the step of forming a gate plug 150 in the third opening 140 includes: forming the gate plug 150 in the third opening 140 using an atomic layer deposition process or a chemical vapor deposition process; removing the gate plug 150 exposed in the third opening 140 using a planarization process, and using the oxide layer 114 as an etch stop layer to make the gate plug 150 flush with the oxide layer 114.
[0114] It should be noted that since the feature size of the formed groove 110 is larger than the feature size of the second opening 130, the feature size of the third opening 140 can be larger than the feature size of the metal layer 102 when the third opening 140 is formed. Therefore, when the gate plug 150 is formed in the third opening 140 using atomic layer deposition or chemical vapor deposition, the feature size of the gate plug 150 is larger than the feature size of the metal layer 102.
[0115] In this embodiment of the invention, the gate plug 150 is made of tungsten. In other embodiments, the gate plug 150 may also be made of one or more of cobalt, ruthenium, and magnesium-tungsten alloys.
[0116] Accordingly, embodiments of the present invention also provide a semiconductor structure. (Refer to...) Figure 19 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.
[0117] The semiconductor structure includes: a substrate 100; a gate structure 101 located on the substrate 100; a metal layer 102 located on top of the gate structure 101; a source / drain doped layer 103 located on the side portion 101 of the gate structure; an interlayer dielectric layer 104 covering the source / drain doped layer 101; an intermediate layer 113 located above the interlayer dielectric layer 104 and the gate structure 101; an oxide layer 114 located above the intermediate layer 113; and a gate plug 150 located above the metal layer 102, penetrating through openings in the intermediate layer 113 and the oxide layer 114, and connected to the metal layer 102, wherein the feature size of the gate plug 150 is larger than the feature size of the metal layer 102.
[0118] In this embodiment of the invention, the semiconductor structure formed is a fin field-effect transistor (Fin FET) as an example, such as... Figure 19 As shown in (b). Accordingly, the substrate includes a substrate 100 and fins 200 located on the substrate 100. In other embodiments, the semiconductor structure may also be a planar transistor (MOSFET).
[0119] In this embodiment of the invention, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0120] When the semiconductor structure is in operation, the gate structure 101 is used to turn the channel on or off.
[0121] Specifically, the gate structure 101 may include a work function layer 1011 and a gate layer 1012 located on the work function layer 1011. The work function layer 1011 is used to adjust the threshold voltage of the transistor.
[0122] In this embodiment of the invention, the gate layer 1012 is made of tungsten. In other embodiments, the gate layer 1012 is made of one or more of cobalt, ruthenium, and magnesium-tungsten alloys.
[0123] It should be noted that the substrate may further include a sidewall layer 106. The sidewall layer 106 is located on the sidewall of the gate structure 101, protecting the sidewall of the gate structure 101 from damage.
[0124] In this embodiment, the material of the sidewall layer 106 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.
[0125] When the semiconductor structure is in operation, the source and drain doped layers 103 are used to provide stress to the channel and improve the migration rate of carriers in the channel.
[0126] In this embodiment of the invention, the semiconductor structure can be used to form an N-channel metal-oxide-semiconductor (NMOS), and the source / drain doped layer 103 is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, by doping silicon carbide or silicon phosphide with N-type ions, the N-type ions replace the positions of silicon atoms in the crystal lattice. The more N-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. In this embodiment of the invention, the N-type ion material includes phosphorus, arsenic, or antimony.
[0127] In other embodiments, the semiconductor structure is used to form a P-channel metal-oxide-semiconductor (PMOS), and the source / drain doping layer is silicon germanide doped with P-type ions. By doping silicon germanide with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice. The more P-type ions incorporated, the higher the majority carrier concentration and the stronger the conductivity. The P-type ion material may include boron, gallium, or indium.
[0128] In this embodiment of the invention, the metal layer 102 is made of tungsten. Tungsten has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of semiconductor structures and improving the semiconductor formation rate.
[0129] In this embodiment of the invention, the intermediate layer 113 is made of silicon nitride. In other embodiments, the intermediate layer 113 is made of one or more of silicon carbonitride, silicon oxide, silicon carbide, and silicon boron nitride.
[0130] In this embodiment of the invention, the gate plug 150 is made of tungsten. In other embodiments, the gate plug 150 may be one or more of cobalt, ruthenium, and magnesium-tungsten alloys.
[0131] It should be noted that since the feature size of the formed groove 110 is larger than the feature size of the second opening 130, when forming the third opening 140, the feature size of the third opening 140 can be larger than the feature size of the metal layer 102. Therefore, an atomic layer deposition process or a chemical vapor deposition process is used to form a gate plug 150 in the third opening 140, and the feature size of the formed gate plug 150 is larger than the feature size of the metal layer 102.
[0132] The semiconductor structure described in this embodiment of the invention can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.
[0133] It should be noted that the terms "first," "second," etc., used in the embodiments of this specification are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with terms such as "first," "second," etc., may explicitly or implicitly include one or more of that feature. Furthermore, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or indicate importance.
[0134] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a gate structure on the substrate, a metal layer on top of the gate structure, a source / drain doped layer on the side of the gate structure, and an interlayer dielectric layer covering the source / drain doped layer; A cap layer with grooves is formed above the metal layer and the interlayer dielectric layer, wherein the grooves expose a portion of the metal layer and the remaining portion of the metal layer is covered by the cap layer; A hard mask layer is formed on the groove and the cap layer, the hard mask layer covering the portion of the metal layer exposed in the groove; Remove the cap layer to expose the remaining portion of the metal layer, and etch the remaining portion of the metal layer to form a first opening; Remove the hard mask layer; An intermediate layer and an oxide layer are sequentially formed above the metal layer and the interlayer dielectric layer, and the oxide layer has a second opening that exposes the intermediate layer. Using the oxide layer as a mask, the intermediate layer is etched to form a third opening; A gate plug is formed in the third opening, the characteristic dimension of the gate plug being larger than the characteristic dimension of the metal layer, and the bottom of the gate plug being flush with the top of the gate structure.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The groove also exposes a portion of the interlayer dielectric layer.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The width of the groove is greater than the width of the second opening.
4. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The step of forming a cap layer with grooves over the metal layer and the interlayer dielectric layer, wherein the grooves at least partially expose the metal layer, includes: A cap layer is formed on the metal layer and the interlayer dielectric layer; A first anti-reflective coating and a first photoresist layer are sequentially formed on the cap layer, wherein the first photoresist layer forms a first patterned opening that exposes a portion of the first anti-reflective coating. Using the first photoresist layer as a mask, the first anti-reflective coating and the cap layer are sequentially etched along the first pattern opening. Part of the cap layer is removed to form a groove, which exposes part of the metal layer and part of the interlayer dielectric layer.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, The cap layer is formed using atomic layer deposition or chemical vapor deposition.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, The cap layer is made of one or more of silicon carbonitride, silicon nitride, silicon oxide, silicon carbon oxynitride, and silicon boron nitride.
7. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The process of forming a hard mask layer on the groove and the cap layer, the hard mask layer covering the exposed metal layer in the groove, includes: A hard mask layer is formed in the groove and on the cap layer using atomic layer deposition or chemical vapor deposition processes. A planarization process is used to remove the hard mask layer on the cap layer, so that the hard mask layer is flush with the top of the groove, and the hard mask layer covers the metal layer exposed in the groove.
8. The method for forming a semiconductor structure according to claim 7, characterized in that, The material of the hard mask layer is titanium nitride.
9. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The removal of the hard mask layer includes: A capping layer is formed on the first opening, the hard mask layer, and the interlayer dielectric layer using atomic layer deposition or chemical vapor deposition. The capping layer and hard mask layer on the metal layer, as well as the capping layer above the first opening and on the interlayer dielectric layer, are removed using a planarization process.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The capping layer is made of one or more of silicon carbonitride, silicon nitride, silicon oxide, silicon carbon oxynitride, and silicon boron nitride.
11. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, An intermediate layer and an oxide layer are sequentially formed above the metal layer and the interlayer dielectric layer, wherein the oxide layer has a second opening that exposes the intermediate layer, including: The intermediate layer and the oxide layer are sequentially formed over the metal layer and the interlayer dielectric layer using atomic layer deposition or chemical vapor deposition processes. A second anti-reflective coating and a second photoresist layer are sequentially formed on the oxide layer, wherein the second photoresist layer forms a second patterned opening that exposes a portion of the second anti-reflective coating. Using the second photoresist layer as a mask, the second photoresist layer and the oxide layer are sequentially etched along the second pattern opening to form a second opening, which exposes a portion of the intermediate layer.
12. The method for forming a semiconductor structure according to claim 11, characterized in that, The material of the intermediate layer includes one or more of silicon carbonitride, silicon nitride, silicon oxide, silicon carbon oxynitride, and silicon boron nitride.
13. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The formation of the gate plug in the third opening includes: A gate plug is formed in the third opening using atomic layer deposition or chemical vapor deposition. A planarization process is used to remove the gate plug that exposes the third opening.
14. The method for forming a semiconductor structure according to claim 13, characterized in that, The gate plug is made of one or more of tungsten, magnesium-tungsten alloy, ruthenium, and cobalt.
15. A semiconductor structure obtained by the method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that, include: Substrate; A gate structure is located on the substrate; A metal layer is located on top of the gate structure; Source and drain doped layers are located on the side of the gate structure; An interlayer dielectric layer covers the source / drain doped layer; An intermediate layer is located above the interlayer dielectric layer and the gate structure; An oxide layer is located above the intermediate layer; A gate plug is located above the metal layer, through an opening in the intermediate layer and the oxide layer, and connected to the metal layer. The characteristic dimension of the gate plug is larger than the characteristic dimension of the metal layer, and the bottom of the gate plug is flush with the top of the gate structure.
16. The semiconductor structure according to claim 15, characterized in that, The material of the intermediate layer includes one or more of silicon carbonitride, silicon nitride, silicon oxide, silicon carbon oxynitride, and silicon boron nitride.
17. The semiconductor structure according to claim 15 or 16, characterized in that, The gate plug is made of one or more of tungsten, magnesium-tungsten alloy, ruthenium, and cobalt.