Method of manufacturing a semiconductor device and corresponding semiconductor device

Abstract

Embodiments of the present disclosure relate to methods of manufacturing semiconductor devices and corresponding semiconductor devices. A semiconductor device, such as a quad flat no-lead (QFN) package, includes a semiconductor die disposed on a die pad of a leadframe. The leadframe has an array of conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad and recessed portions in upper surfaces of the leads. A resilient material, such as a low modulus of elasticity material, is present on the upper surfaces of the leads and fills the recessed portions. An insulating encapsulation is molded over the semiconductor die. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. Such a resilient material facilitates the flexibility of the leads to make them suitable for reliable soldering to an insulating metal substrate.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102020000005759, filed on March 11, 2021, the contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This specification relates to semiconductor devices.

[0004] One or more embodiments can be advantageously applied to semiconductor devices used in the automotive and consumer mass markets. Background Technology

[0005] So-called insulating metal substrates (IMS) are often used to replace conventional printed circuit boards (PCBs) as insulating metal cards (IMCs) in applications that require heat dissipation through semiconductor device packages, such as the automotive industry.

[0006] It is important to note that packages such as quad flat-no-lead (QFN) modules on IMS can exhibit a high coefficient of thermal expansion (CTE) and generate high stress transmitted to the QFN module solder joints. Thin organic layers are insufficient to alleviate this stress.

[0007] Therefore, large QFN modules (e.g., 7x7mm or 10x10mm) may not meet reliability standards (weld joint failures during BLR / thermal cycling or thermal shock and card bending).

[0008] This suggests that quad flat package (QFP) modules should be used instead of QFN modules, which may result in a larger footprint on the circuit board.

[0009] The problems discussed above need to be addressed in this field. Summary of the Invention

[0010] One or more embodiments may relate to a method.

[0011] One or more embodiments may relate to corresponding semiconductor products.

[0012] One or more embodiments may relate to a QFN manufacturing method that helps increase lead flexibility.

[0013] In one or more embodiments, a low-modulus mass block is inserted between the lead and the molded part at the lead end.

[0014] One or more embodiments facilitate the use of large QFN packages (e.g., 10x10mm) on an insulating metal substrate (IMS).

[0015] Those skilled in the art will understand that while particularly advantageous results can be achieved by combining with a QFN package, the embodiments discussed herein are not limited to use with a QFN package. Attached Figure Description

[0016] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0017] Figure 1 This is an exemplary arrangement of a conventional quad flat no-lead (QFN) package mounted on an insulated metal card (IMC).

[0018] Figure 2 This is a cross-sectional view of the lead frame that can be used in the embodiments according to this description.

[0019] Figure 3 It is roughly along Figure 3 Enlarged perspective view of arrow III.

[0020] Figure 4 and Figure 5 Possible method steps according to embodiments described herein are shown.

[0021] Figure 6 It is roughly along Figure 5 Enlarged perspective view of arrow VI (center arrow).

[0022] Figure 7 and Figure 8 Possible method steps according to embodiments described herein are shown.

[0023] Figure 9 It is roughly along Figure 8 Perspective view of the middle arrow IX.

[0024] Figure 10 yes Figure 8 A magnified view of the middle arrow X.

[0025] Figure 11 Possible method steps according to embodiments described herein are shown.

[0026] Figure 12A , Figure 12B and Figure 12C These are illustrations of possible variations of the method steps in the embodiments described herein.

[0027] Figure 13 It's a perspective view, illustrating... Figures 12A to 12C Possible results of the variation,

[0028] Figures 14A to 14L This is an illustration of another possible sequence of method steps according to the embodiments described herein.

[0029] Figure 15 and Figure 16 These are illustrative diagrams illustrating possible features of embodiments according to this description, and

[0030] Figure 17 and Figure 18 The possible different features of the embodiments according to this description are explained.

[0031] It should be understood that, for the sake of simplicity and ease of interpretation, different figures may not be drawn at the same scale. Detailed Implementation

[0032] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more of these specific details, or using other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described in order not to obscure certain aspects of the embodiments.

[0033] References to "embodiment" or "one embodiment" within the framework of this description are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0034] Furthermore, specific conformations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0035] The titles and references used herein are provided for convenience only and therefore do not define the scope of protection or the scope of the embodiments.

[0036] It should be understood that, unless the context otherwise indicates, similar parts or elements are indicated by similar reference numerals throughout the drawings, and for the sake of brevity, detailed descriptions will not be repeated for each drawing.

[0037] One drawback that Quad Flat Leadless (QFN) modules may encounter when connecting to Insulated Metal Cards (IMCs) is related to the card material. To achieve high heat dissipation, thick cards are required, such as those made of copper with a thin dielectric layer.

[0038] Figure 1 An example of such an arrangement is a QFN package 10 mounted on an IMC 100, which has a layered structure including a base copper layer (1100H1 / 2) 102, a dielectric layer 104, a top copper layer 106, and a solder mask 108 in which pads BP are formed to provide solder joints 110 for the package 10.

[0039] Such a thick copper card inevitably exhibits a high coefficient of thermal expansion (CTE) and high stress, which is transmitted to the solder joints 110 through the QFN package 10. The thin organic layer 104 is insufficient to alleviate the stress.

[0040] For example, board-level reliability (BLR) simulations performed on QFN 7x7 modules show that the lifetime of QFN 7x7 modules may drop to a maximum of 279 cycles, compared to 1368 cycles on FR4 multilayer boards.

[0041] One approach to addressing these issues could involve using thin quad flat package (TQFP) modules with flexible contacts that can mitigate thermomechanical stress.

[0042] Another approach could involve using copper cards with thicker PCB inserters to alleviate stress.

[0043] These methods also have drawbacks. For example, TQFP packages may take up more card space compared to QFN; and thicker PCB inserters can unnecessarily increase card costs.

[0044] Summary: Figure 1 As shown, compared to multilayer PCB card assemblies, the QFN package 10 assembled on the IMS copper card 100 has (worse) on-board temperature cycling (TCoB) performance; and the “critical” solder joint 110 may end up located at the corner of the package, because the corner lead design in the QFN package helps to improve the TCoB reliability of the critical solder joint.

[0045] Now for reference Figure 2 One or more embodiments may involve providing (in a semiconductor device package, such as 10) a half-etched lead frame 12.

[0046] The currently used term lead frame (or lead frame) (see, for example, the USPC Uniform Glossary) indicates that it provides support for a semiconductor chip or die (at the die pads or baffles, 12A) and a metal frame that couples the semiconductor chip or die and electrical leads 12B to other electrical components or contacts.

[0047] Basically, the lead frame 12 includes an array of conductive structures (leads) 12B extending inward from a peripheral location in the direction of a semiconductor chip or die, thereby forming an array of conductive structures from a die pad 12A on which at least one semiconductor chip or die is attached.

[0048] Otherwise, it should be understood that the “leadless” specification applicable to QFN packages does not contradict the provision of lead frames that include leads: in fact, a key feature of QFN packages is that the leads do not protrude radially from the package, so that (iv) the package will not have “leads” protruding from it.

[0049] like Figure 3 As shown in the enlarged partial view, in one or more embodiments, the outer leads 12B in the lead frame have grooves (recesses, openings) 120B formed near their distal ends. These grooves 120B can be provided during the formation of the lead frame 12 from a sheet or reel of material such as copper via a conventional etching process.

[0050] Using current terminology in etching techniques, slot 120B can be described as a “semi-etch” in the lead frame material. However, this does not necessarily mean that the depth of slot 120B is equal to half the thickness of lead frame 12.

[0051] Furthermore, it should be understood that, from Figure 2 The initial diagram may refer to multiple devices 10 that are manufactured simultaneously and ultimately divided in the "segmentation" step.

[0052] like Figure 4 As shown, a semiconductor device like 10 includes one or more semiconductor chips or dies 14 in a manner known to those skilled in the art, which are arranged (attached via die attachment material) on die pads 12A of leadframe 12.

[0053] Electrical coupling between the lead 12B in the lead frame 12B and the semiconductor chip or die 14 can be achieved via wires forming a lead bonding pattern 16 around the chip or die 14.

[0054] The device package can then be completed by molding an insulating encapsulation 18, such as epoxy resin, onto the lead frame 12 and the semiconductor chip 14 attached thereto (plus lead bonding pattern 16).

[0055] In one or more embodiments, such as Figure 7 The steps or actions shown are in Figure 5 and Figure 6 Prior to the steps or actions shown, the low elastic modulus (LEM) material 1200 is dispensed into the groove 120B.

[0056] The elastic modulus (or elastic modulus) is a physical entity—expressed in Nm. 2 Or measured in Pa, even if megapascals (MPa or N / mm) are frequently used. 2 or gigapascals (GPa or kN / mm) 2Elasticity (or non-permanent elasticity) represents the resistance of an object or material to deformation under stress. Therefore, harder materials have a higher elastic modulus, and softer materials have a lower elastic modulus.

[0057] In one or more embodiments, the modified polyurethane derivative material, commercially known as DELO DUALBOND BS3770, is provided by DELO Industrie Klebstoffe GmbH & Co. KGaA, located at KGaA of Gewerbegebiet. DELO-Allee 1,86949 Windach, Germany - (see delo-adhesives.com) and has a Young's modulus close to (i.e., + / - 3-5%) 2MPa (rheometer | 400nm | 200mW / cm). 2 |10s|plus|150℃|40min) is sufficient for use as an elastic material 1200.

[0058] Other materials exhibiting similar properties, and more generally, other materials that those skilled in the art would consider to have a low modulus of elasticity (i.e., easily deformable under pressure) in the use environments considered herein, may be satisfactorily used in the embodiments.

[0059] Examples of possible alternative materials include Master Bond Supreme 10HT epoxy insulating adhesive supplied by Master Bond Inc. of Hackensack, New Jersey, USA (see masterbond.com) or Dymax 9037F acrylic insulating adhesive supplied by Dymax Inc. of Torrington, USA, CT06790 (see dymax.com).

[0060] The above materials can be obtained through, for example Figure 5 The dispensing pin shown in N is fully applied to the groove 120B, and then curing is performed via, for example, ultraviolet (UV) curing.

[0061] like Figure 6 As shown, the thickness of material 1200 can be 0.1-0.2 mm, and a pad or liner is provided to cover the front or top surface of lead 12B (at its distal end), and possibly the sides—see Figure 17 and Figure 18 We'll discuss that later.

[0062] like Figure 7As shown, the insulating encapsulation 18 is formed by molding a compound such as epoxy resin onto the lead frame 12 and one or more semiconductor chips 14 attached thereto (plus lead bonding pattern 16) and material 1200.

[0063] If not completed in advance, the polymerization (curing) of material 1200 can be completed together with the curing of insulating encapsulation 18 (e.g., at a temperature of 170°C).

[0064] Figure 8 The possibility that the (or conventional) back-side etching applied at BE and the bottom plating area 24 at lead 12B stops before the top bonding area (see...). Figure 9 and Figure 10 Example of ). It should be noted that the back-side etching does not reach the material 1200 of the filling groove 120B.

[0065] Figure 11 This is an example of a conventional partitioning step (e.g., performed by blade B) that results in the formation of a single (e.g., QFN) package 10.

[0066] Otherwise, those skilled in the art will understand that Figures 3 to 11 The order of steps or actions is exemplary only in the following ways: one or more steps shown may be omitted and / or replaced by other steps; other steps may be added; and one or more steps may be performed in an order different from that shown.

[0067] Now we will combine Figure 12A , Figure 12B , Figure 12C and Figure 13 as well as Figures 14A to 14L and Figure 15 and Figure 16 Various possible alternatives to the embodiments are discussed.

[0068] For simplicity and ease of understanding, unless the context otherwise requires, [the following has been] combined Figures 1 to 11 The components or elements discussed are indicated by similar reference numerals in the following figures, and for the sake of brevity, detailed descriptions will not be repeated.

[0069] For simplicity, Figures 1 to 11 Some details that may be described in the diagram below may not be reproduced.

[0070] Figure 12A , Figure 12B and Figure 12C The steps illustrated in the diagram take into account the half-cut 12C formed on the back or bottom side of the lead frame 12 (in a manner known per se). Figure 12A (For simplicity, only the central part of the figure is shown), then at 120°C (also conventional - Figure 12B Electroplating, after separation ( Figure 12C Electroplated solder makes the wettable lead sides usable, such as... Figure 13 As shown.

[0071] Figures 14A to 14L This is an example of the possibility of applying one or more embodiments to (other conventional) QFNs in tape manufacturing processes.

[0072] Those skilled in the art will once again recognize that Figures 14A to 14L The order of steps is illustrative only in the following respects: one or more steps shown may be omitted and / or replaced by other steps; additional steps may be added; one or more steps may be performed in a different order than that shown in the diagram.

[0073] Figures 14A to 14L The steps include:

[0074] Figure 14A —A “semi-etched” groove or notch 120B is provided on the support strip T of the lead frame 12 (again, this does not necessarily mean that the depth of the groove 120B is equal to half the thickness of the lead frame 12).

[0075] Figure 14B —The chip or die 14 is attached to the lead frame; the lead bonding 16 provides bonding between the chip or die 14 and the lead 12B of the lead frame 12.

[0076] Figure 14C —Low elastic modulus material 1200 distributed at groove or opening 120B;

[0077] Figure 14D —Packaging molding materials 18 molding;

[0078] Figure 14E — Tape T has been removed;

[0079] Figure 14F -Will Figure 14E The components are flipped (upside down);

[0080] Figure 14G —Apply a water-soluble mask to the contact lead portion corresponding to the bonding area (e.g., by jet printing, as shown in JP);

[0081] Figure 14H —A partial cut at 12C (see also) Figure 12A );

[0082] Figure 14I —Tin plating at 120°C (see also) Figure 12B );

[0083] Figure 14J—Remove water-soluble mask;

[0084] Figure 14K —Splitter (blade B); and

[0085] Figure 14L —A single device package 10 (e.g., QFN) with flexible flat contacts is provided at the distal end of lead 12B.

[0086] like Figure 15 and Figure 16 As shown, the low modulus material 1200 embedded between the lead 12B and the molding material 18 effectively alleviates the thermomechanical stress caused by the (high) CTE mismatch between the module 10 and the substrate 100 (e.g., IMS card), which would otherwise be transferred to the solder joint 110.

[0087] The low modulus material 1200 contributes to a certain sealing effect of the module due to improved adhesion to the substrate material (e.g., copper), which can be further improved by chemical compatibility with the molding material 14 and / or the design of the groove 120B.

[0088] On the latter point, Figure 17 and Figure 18 Examples of the possibility of "soft" pads or solder pads provided by the low modulus material 1200: (only) in lead 12B ( Figure 17 The top or front surface of the lead 12B, i.e., the surface opposite the solder joint 110 and the substrate 100; and also on the side of the lead 12B. Figure 18 This provides a groove-shaped pad or solder pad to accommodate lead 12B.

[0089] The standardized solder life simulation results based on temperature cycling TC (-40 / +125°C) modeled using finite element analysis (FEA) show that when applied to QFNmr 10x10mm packages, as... Figure 17 and 18 The package shown with flexible contacts can increase solder life by nearly 17% and 42%.

[0090] The methods illustrated in this article may include:

[0091] At least one semiconductor chip (e.g., 14) is disposed on a (first) surface of a lead frame (e.g., 12), wherein at least one semiconductor chip is disposed at a die pad (e.g., 12A) of the lead frame, and the lead frame has an array of conductive leads (e.g., 12B) around the die pad, the leads in the array having a distal end opposite to the die pad and a recessed portion (e.g., 120B) of the (first) surface of the lead frame at the distal end of the leads in the array.

[0092] The recessed portion at the distal end of the lead in the array is formed with an elastic material (e.g., N) (e.g., 1200); and

[0093] An insulating encapsulation (e.g., 18) of at least one semiconductor chip disposed on a lead frame is molded onto at least one semiconductor chip disposed on a lead frame, wherein an elastic material is sandwiched between the insulating encapsulation and the distal end of the leads in the array in the recessed portion, wherein the elastic material promotes the flexibility of the leads at the distal end.

[0094] The method described herein may include forming a groove in the recessed portion at the distal end.

[0095] In the method illustrated herein, the slot may be open at the (first) surface of the lead frame.

[0096] In the method illustrated herein, the recessed portion may include a half-etched portion of the lead frame.

[0097] Methods exemplified herein may include:

[0098] An elastic material is formed only at the recessed portion at the distal end of the lead in the array on the surface of the lead frame (e.g., see...). Figure 17 );or

[0099] An elastic material is formed in the recessed portion at the distal end of the lead in the array on both the surface of the lead frame and the side of the lead (e.g., see...). Figure 18 ).

[0100] In the method illustrated herein, the elastic material may have a low elastic modulus, i.e., it may be composed essentially of a low elastic modulus material, optionally with an elastic modulus around 2 MPa.

[0101] For materials applied in a flowable (molten) state and subsequently cured, such as curable (polymerizable) resin materials, the elastic modulus and Young's modulus values ​​are intended to refer to the material after curing (polymerization).

[0102] The methods described herein may include:

[0103] An electrical bonding pattern (e.g., 16) is provided on the (first) surface of the lead frame between the bonding regions of the at least one semiconductor chip and the leads in the array; and

[0104] An electroplating area is provided on the second surface of the lead frame opposite to the (first) surface (e.g., Figure 9 (24) The electroplated area is located at the far end of the lead in the array and stops before the bonding area of ​​the lead in the array at the (first) surface of the lead frame.

[0105] The device (e.g., 10) illustrated herein may include:

[0106] At least one semiconductor chip (e.g., 14) is disposed on the surface of a lead frame (e.g., 12), wherein at least one semiconductor chip is disposed on a die pad (e.g., 12A) of the lead frame, and the lead frame has an array of conductive leads (e.g., 12B) around the die pad, the leads in the array having a distal end opposite to the die pad and a recessed portion (e.g., 120B) on the surface of the lead frame at the distal end of the leads in the array.

[0107] An elastic material (e.g., 1200) formed in the recessed portion at the distal end of the lead in the array; and

[0108] An insulating encapsulation (e.g., 18) of at least one semiconductor chip disposed on a lead frame, wherein an elastic material is sandwiched between the recessed portion and the distal end of a lead in an array of insulating encapsulations, wherein the elastic material promotes the flexibility of the lead at the distal end.

[0109] In the device as illustrated herein, the recessed portion may include a groove in the distal end, or alternatively, a groove that opens on the surface of the lead frame.

[0110] In the device as illustrated herein, the recessed portion may include a half-etched portion of the lead frame.

[0111] The devices shown in this document may include:

[0112] The elastic material formed only on the surface of the lead frame at the recessed portion at the distal end of the lead in the array (e.g., see...). Figure 17 );or

[0113] The elastic material formed in the recessed portion at the distal end of the lead in the array includes both the surface of the lead frame and the side surface of the lead (e.g., see...). Figure 18 ).

[0114] In the device as shown herein, the elastic material may have a low elastic modulus, i.e., it may be composed essentially of a low elastic modulus material, optionally with an elastic modulus around 2 MPa.

[0115] As mentioned earlier, for materials that are coated in a flowable (molten) state and then cured, such as curable (polymerizable) resin materials, the elastic modulus and Young's modulus values ​​refer to the cured (polymerized) material.

[0116] The devices shown in this document may include:

[0117] An electrical bonding pattern (e.g., 16) between bonding regions of leads in an array at least one semiconductor chip and a lead frame at the (first) surface; and

[0118] An electroplated area (e.g., 24) on the (second) surface of the lead frame (12) opposite to the (first) surface, the electroplated area being located at the distal end of the leads in the array and stopping before the bonding area of ​​the leads in the array at the (first) surface of the lead frame.

[0119] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, only with respect to what has been described by example, without departing from the scope of protection.

[0120] The claims are an integral part of the technical instruction provided herein.

[0121] The scope of protection is determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: At least one semiconductor chip is disposed on a die pad of a lead frame, the lead frame including an array of leads surrounding the die pad, the leads having a distal end opposite to the die pad and a recessed portion in the upper surface of the leads. An elastic material is formed on the upper surface and fills the recessed portion of the lead wire; as well as An insulating encapsulation is molded onto at least one semiconductor chip disposed on the lead frame; The elastic material is sandwiched between the insulating encapsulation and the distal end of the lead at the recessed portion, and the elastic material promotes the flexibility of the lead at the distal end.

2. The method of claim 1, further comprising forming the recessed portion in the distal end into a groove.

3. The method of claim 2, wherein the groove is open on the side surface of the lead.

4. The method of claim 1, wherein the recessed portion comprises a half-etched portion of the lead frame.

5. The method according to claim 4, further comprising: Etching is performed on the lower surface of the lead frame to define the lead, wherein the etching is not performed on the lower surface opposite the location of the recessed portion.

6. The method of claim 1, wherein forming the elastic material includes not providing the elastic material on the side of the lead.

7. The method of claim 1, wherein forming the elastic material comprises distributing the elastic material on the side of the lead.

8. The method according to claim 1, wherein the elastic material has an elastic modulus of around 2 MPa.

9. The method according to claim 1, further comprising: The at least one semiconductor chip is electrically bonded to the bonding region on the upper surface of the lead.

10. The method of claim 9, further comprising: An electroplating area is provided on the lower surface of the lead wire opposite to the upper surface.

11. A semiconductor device, comprising: A lead frame having a die pad and an array of conductive leads surrounding the die pad, the leads having a distal end opposite to the die pad and a recessed portion in the upper surface of the lead. At least one semiconductor chip is disposed at the die pad; An elastic material is placed on the upper surface and fills the recessed portion of the lead wire; as well as Insulating encapsulation is provided on the at least one semiconductor chip disposed on the lead frame; The elastic material is sandwiched between the insulating encapsulation and the distal end of the lead at the recessed portion, and the elastic material promotes the flexibility of the lead at the distal end.

12. The semiconductor device of claim 11, wherein the recessed portion includes a groove in the distal end.

13. The semiconductor device of claim 12, wherein the trench is open at the side surface of the lead.

14. The semiconductor device of claim 11, wherein the recessed portion comprises a half-etched portion of the lead frame.

15. The semiconductor device of claim 11, wherein the elastic material is not disposed on the side of the lead.

16. The semiconductor device of claim 11, wherein the elastic material is disposed on the side of the lead.

17. The semiconductor device of claim 11, wherein the elastic material has an elastic modulus of approximately 2 MPa.

18. The semiconductor device of claim 11, further comprising an electrical connection between the at least one semiconductor chip and the bonding region of the lead at the upper surface.

19. The semiconductor device of claim 18, further comprising an electroplated region on the lower surface of the lead opposite the upper surface.

Images