Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The present application provides a semiconductor storage device and a manufacturing method of the semiconductor storage device, which can achieve improvement of electrical characteristics. The semiconductor storage device of the embodiment has a first substrate, a second substrate, a first laminate, and a second laminate. The first laminate is provided between the first substrate and the second substrate, and includes a first wiring, a first pad connected to the first wiring, and a first insulator. The second laminate is provided between the first laminate and the second substrate, and includes a second wiring, a second pad connected to the second wiring, and a second insulator. The first pad includes a plurality of first electrode portions connected to the first wiring, respectively. The first insulator is provided between the plurality of first electrode portions. The plurality of first electrode portions are joined to the second pad.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-042688 (filed on March 16, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0003] Semiconductor memory devices are known to be manufactured by bonding multiple wafers together. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device that can achieve improved electrical characteristics and a method for manufacturing the semiconductor memory device.

[0005] The semiconductor memory device of this embodiment includes a first substrate, a second substrate, a first laminate, and a second laminate. The second substrate is separated from the first substrate in the thickness direction, i.e., a first direction, of the first substrate. The first laminate is disposed between the first substrate and the second substrate and includes a first wiring, a first pad connected to the first wiring, and a first insulator. The second laminate is disposed between the first laminate and the second substrate and includes a second wiring, a second pad connected to the second wiring, and a second insulator. The first pad includes a plurality of first electrode portions that are separated from each other in a second direction intersecting the first direction and are respectively connected to the first wiring. The first insulator is disposed between the plurality of first electrode portions. The plurality of first electrode portions are bonded to the second pad. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view showing the configuration of a semiconductor memory device according to an embodiment.

[0007] Figure 2 This is a cross-sectional view near the storage pillars of the storage element array in the embodiment.

[0008] Figure 3 This is a cross-sectional view showing multiple bonding pads in an embodiment.

[0009] Figure 4 This is a diagram showing the bonding pads in the implementation method.

[0010] Figure 5 This is a cross-sectional view showing the state of the electrode portions of the first laminate and the second laminate when the first laminate and the second laminate are bonded together according to the embodiment.

[0011] Figure 6 This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0012] Figure 7 This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0013] Figure 8 This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0014] Figure 9 This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Figure 10 This is a cross-sectional view of a semiconductor memory device illustrating a variation of the implementation method.

[0016] Figure 11 It is Figure 10 The enlarged cross-sectional view of the area enclosed by line F11 is shown.

[0017] Figure 12 This is a cross-sectional view showing the shape of the plurality of electrode portions in the first embodiment of the implementation.

[0018] Figure 13 This is a cross-sectional view showing the shape of the plurality of electrode portions in the second embodiment of the implementation.

[0019] Figure 14 This is a cross-sectional view showing the shape of the plurality of electrode portions in the third embodiment of the implementation.

[0020] Figure 15 This is a cross-sectional view showing the shape of the plurality of electrode portions in the fourth embodiment of the implementation.

[0021] Figure 16 This is a cross-sectional view showing the shape of the plurality of electrode portions in the fifth embodiment of the implementation.

[0022] Figure 17 This is a cross-sectional view showing the shape of the plurality of electrode portions in the sixth embodiment of the implementation.

[0023] Figure 18 This is a cross-sectional view showing the shape of the plurality of electrode portions in the seventh embodiment of the implementation.

[0024] Figure 19 This is a cross-sectional view showing the shape of the plurality of electrode portions in the eighth embodiment of the implementation.

[0025] Figure 20 This is a cross-sectional view showing the shape of the plurality of electrode portions in the ninth embodiment of the implementation.

[0026] Explanation of symbols

[0027] 1: Semiconductor memory device; 10: First substrate; 30: First laminate; 35: First insulator; 37: Wiring (first wiring); 38: Bonding pad (first pad); 40: Second laminate; 45: Second insulator; 47: Wiring (second wiring); 48: Bonding pad (second pad); 81: Electrode portion (first electrode portion); 82: Electrode portion (second electrode portion); 101: Protective layer; R: Pad area. Detailed Implementation

[0028] Hereinafter, a semiconductor memory device according to an embodiment will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions will be labeled with the same symbols. Furthermore, repeated descriptions of these components will sometimes be omitted. "Connection" is not limited to physical connection, but also includes electrical connection. That is, "connection" is not limited to direct connection, but also includes cases where other components are sandwiched between the components. "Ring-shaped" is not limited to a circular ring shape, but also includes rectangular ring shapes. "Parallel," "orthogonal," and "same" also include cases of "approximately parallel," "approximately orthogonal," and "approximately same," respectively.

[0029] First, define the X direction, Y direction, +Z direction, and -Z direction. The X and Y directions are along the first substrate 10 (see below) described later. Figure 1 The direction of surface 10a of the first substrate 10. The Y direction is a direction that intersects (e.g., is orthogonal) the X direction. The +Z direction and -Z direction are directions that intersect (e.g., are orthogonal) the X and Y directions, and are the thickness directions of the first substrate 10. The +Z direction is from the first substrate 10 toward the second substrate 60 (refer to...). Figure 1 The direction of gravity is Z. The -Z direction is the opposite of the +Z direction. Without distinguishing between the +Z and -Z directions, it is simply referred to as the "Z direction". In the following explanations, the "+Z direction" is sometimes called "up" and the "-Z direction" is sometimes called "down". However, these interpretations are for ease of explanation and do not define the direction of gravity. The Z direction is an example of the "first direction". Either the X or Y direction is an example of the "second direction". The other of the X and Y directions is an example of the "third direction".

[0030] (Implementation Method)

[0031] <1. Overall Structure of Semiconductor Memory Devices>

[0032] First, the overall configuration of the semiconductor memory device 1 according to the embodiment will be described. The semiconductor memory device 1 is a non-volatile semiconductor memory device, such as a NAND flash memory.

[0033] Figure 1This is a cross-sectional view showing the configuration of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a three-dimensional memory formed by bonding a circuit chip 2 and an array chip 3 together via an adhesive surface S. The circuit chip 2 is an example of a "first chip." The array chip 3 is an example of a "second chip." The circuit chip 2 includes a control circuit (logic circuit) that controls the operation of the array chip 3. The semiconductor memory device 1 will now be described in detail.

[0034] The semiconductor memory device 1 includes, for example, a first substrate 10, a laminate 20, a second substrate 60, and insulating layers 72 and 73.

[0035] The first substrate 10 is a substrate included in the circuit chip 2. The first substrate 10 is, for example, a silicon substrate. The first substrate 10 has a surface 10a for stacking the laminate 20. The source region and drain region of the transistor 31 (described later) included in the laminate 20 are provided on the first substrate 10.

[0036] The stack 20 is located between the first substrate 10 and the second substrate 60 in the Z direction. The stack 20 includes a first stack 30 and a second stack 40. The first stack 30 is disposed on the first substrate 10. The first stack 30 is located between the first substrate 10 and the second stack 40 in the Z direction. In this embodiment, the first substrate 10 and the first stack 30 constitute a circuit chip 2. The first stack 30 includes a plurality of transistors 31 (in Figure 1 (Only one is shown in the figure), multiple contact plugs 32, multiple wirings 33, multiple pads 34, and a first insulator 35.

[0037] Transistor 31 is disposed on the first substrate 10. Transistor 31 is connected to contact plug 32. Transistor 31 is electrically connected to memory element array 41 or external connection pad 71 via contact plugs 32, 42, wiring 33, 43 and pads 34, 44 included in the stack 20. Transistor 31 controls memory element array 41, for example.

[0038] Contact plugs 32, wiring 33, and pads 34 electrically connect multiple transistors 31 to the second-layer stack 40. Contact plugs 32, wiring 33, and pads 34 are formed of a conductive material such as copper (Cu) or aluminum (Al). Contact plugs 32 are wiring extending along the Z-direction that electrically connects different layers within the first-layer stack 30. Wiring 33 is wiring extending along the X-direction or Y-direction.

[0039] Pad 34 is a connection electrode disposed on the first layer stack 30. Pad 34 includes an internal pad disposed inside the first layer stack 30 and a bonding pad 38 exposed on the surface (adhesive surface S) of the first layer stack 30. The bonding pad 38 is an example of a "first pad". The wiring 37 of the multiple wirings 33 connected to the bonding pad 38 is an example of a "first wiring". The bonding pad 38 will be described in detail later.

[0040] A first insulator 35 is disposed between a plurality of contact plugs 32, a plurality of wirings 33, and a plurality of pads 34, electrically insulating these elements from each other. The first insulator 35 is formed, for example, from TEOS (tetraethyl orthosilicate (Si(OC2H5)4), silicon oxide (SiO2), or silicon nitride (SiN).

[0041] The second stack 40 is disposed on the first stack 30. The second stack 40 is located between the first stack 30 and the second substrate 60 in the Z direction. In this embodiment, the array chip 3 is formed by the second substrate 60 and the second stack 40. The second stack 40 includes a memory element array 41, a plurality of contact plugs 42, a plurality of wirings 43, a plurality of pads 44, and a second insulator 45.

[0042] The memory element array 41 is disposed below the second substrate 60. The memory element array 41 is laminated on the second substrate 60 during manufacturing (see reference). Figure 8 The storage element array 41 has multiple conductive layers 51 and multiple memory pillars P. The multiple conductive layers 51 and multiple memory pillars P are respectively connected to contact plugs 42.

[0043] Multiple conductive layers 51 are formed, for example, from polycrystalline silicon (Poly-Si) doped with tungsten (W) or other impurities. The multiple conductive layers 51 sandwich an interlayer insulating film 45b (see reference) included in the second insulator 45. Figure 2 The layers are stacked in the Z direction. One or two conductive layers 51 on the first stack 30 side (-Z direction side) of the plurality of conductive layers 51 function as drain-side selected gate lines (SGD). One or two conductive layers 51 on the second substrate 60 side (+Z direction side) of the plurality of conductive layers 51 function as source-side selected gate lines (SGS). The remaining conductive layers 51 located between the drain-side selected gate lines (SGD) and the source-side selected gate lines (SGS) of the plurality of conductive layers 51 function as multiple word lines (WL).

[0044] Multiple memory pillars P extend along the Z-direction and pass through the drain-side select gate line SGD, multiple word lines WL, and the source-side select gate line SGS. Memory elements MC are formed at the intersections between the multiple word lines WL and the multiple memory pillars P. Thus, the multiple memory elements MC are spaced apart in the X, Y, and Z directions and arranged in a three-dimensional configuration. The memory elements MC will be described in detail later.

[0045] Contact plugs 42, wiring 43, and pads 44 electrically connect the memory element array 41 or the external connection pads 71 ​​(described later) to the first layer stack 30. Contact plugs 42, wiring 43, and pads 44 are formed of a conductive material such as copper or aluminum. Contact plugs 42 are wiring extending along the Z-direction that electrically connects different layers within the second layer stack 40. Wiring 43 is wiring extending along the X-direction or Y-direction.

[0046] The pad 44 is a connection electrode provided on the second laminate 40. The pad 44 includes an internal pad located inside the second laminate 40 and a bonding pad 48 exposed on the surface (adhesive surface S) of the second laminate 40. In the state after the first laminate 30 and the second laminate 40 are stacked, the bonding pad 48 of the second laminate 40 is located on and bonded to the bonding pad 38 of the first laminate 30. The bonding pad 48 is an example of a "second pad". The wiring 47 among the multiple wirings 43 that connects to the bonding pad 48 is an example of a "second wiring". The bonding pad 48 will be described in detail later.

[0047] A second insulator 45 is disposed between the plurality of contact plugs 42, the plurality of wirings 43, and the plurality of pads 44, electrically insulating these elements from each other. The second insulator 45 is formed, for example, of TEOS, silicon oxide, or silicon nitride.

[0048] The second substrate 60 is disposed above the second laminate 40. The second substrate 60 is located at a position separated from the first substrate 10 in the Z direction. The second substrate 60 is the substrate included in the array chip 3. The second substrate 60 is, for example, a silicon substrate. Conductive regions that function as source lines of the memory element array 41 are provided on the second substrate 60. The second substrate 60 has a first surface 60a facing the memory element array 41 and a second surface 60b located on the opposite side of the first surface 60a. An external connection pad 71 is provided on the second surface 60b. The external connection pad 71 is provided with an external connection terminal (e.g., solder ball) not shown, and is electrically connected to the external semiconductor memory device 1 via the external connection terminal.

[0049] An insulating layer 72 is disposed on the second substrate 60. An insulating layer 73 is disposed on the insulating layer 72. Insulating layers 72 and 73 are passivation films protecting the laminate 20. The insulating layer 72 is, for example, a silicon oxide film. The insulating layer 73 is, for example, a polyimide film.

[0050] Figure 2 This is a cross-sectional view showing the vicinity of memory pillar P in memory element array 41. For example... Figure 2 As shown, multiple word lines WL are stacked in the Z direction, sandwiching an interlayer insulating film 45b. The multiple word lines WL extend along the X direction. The memory element array 41 has a memory aperture MH with a memory pillar P. The memory pillar P extends along the Z direction inside the memory aperture MH and penetrates the multiple word lines WL.

[0051] Viewed from the Z-direction, the storage column P is, for example, circular or elliptical. From the inside, the storage column P has a core insulator 52, a semiconductor body 53, and a storage film 54 in sequence.

[0052] The core insulator 52 is a columnar body extending along the Z direction. The core insulator 52 may contain, for example, silicon oxide. The core insulator 52 is located inside the semiconductor body 53.

[0053] The semiconductor body 53 extends along the Z-direction and functions as a channel. The semiconductor body 53 is connected to a conductive region of the second substrate 60 that functions as a source line. The semiconductor body 53 covers the outer peripheral surface of the core insulator 52. The semiconductor body 53 may contain silicon, for example. The silicon may be, for example, polycrystalline silicon formed by crystallizing amorphous silicon.

[0054] The storage film 54 extends along the Z-direction. The storage film 54 covers the outer peripheral surface of the semiconductor body 53. The storage film 54 is located between the inner surface of the storage via MH and the outer surface of the semiconductor body 53. The storage film 54 may include, for example, a tunnel insulating film 55 and a charge storage film 56.

[0055] The tunnel insulating film 55 is located between the charge storage film 56 and the semiconductor substrate 53. The tunnel insulating film 55 may comprise, for example, silicon oxide or silicon oxide and silicon nitride. The tunnel insulating film 55 acts as a potential barrier between the semiconductor substrate 53 and the charge storage film 56.

[0056] A charge storage film 56 is disposed between the word line WL and the interlayer insulating film 45b, respectively, and the tunnel insulating film 55. The charge storage film 56 may contain, for example, silicon nitride. The intersection between the charge storage film 56 and the word line WL functions as a storage element MC. The storage element MC retains data based on the presence or absence of charge or the amount of charge stored in the intersection between the charge storage film 56 and the word line WL (charge storage section). The charge storage section is located between the word line WL and the semiconductor body 53 and is surrounded by an insulating material.

[0057] A block insulating film 57 and a barrier film 58 may also be provided between the word line WL and the interlayer insulating film 45b, and between the word line WL and the storage film 54. The block insulating film 57 is an insulating film that suppresses the reverse tunneling effect. The reverse tunneling effect is the phenomenon of charge returning from the word line WL to the storage film 54. The block insulating film 57 is, for example, a silicon oxide film, a metal oxide film, or a laminated film composed of multiple insulating films. An example of a metal oxide is aluminum oxide. The barrier film 58 is, for example, a titanium nitride film, or a laminated film of titanium nitride and titanium.

[0058] A cover insulating film 59 may also be provided between the interlayer insulating film 45b and the charge storage film 56. The cover insulating film 59 may contain, for example, silicon oxide. The cover insulating film 59 protects the charge storage film 56 from etching during processing. The cover insulating film 59 may be absent, or a portion may remain between the conductive layer 51 and the charge storage film 56 as a block insulating film.

[0059] <2. Composition of bonding pads>

[0060] Next, the configuration of the bonding pads 38 and 48 will be explained. Figure 3 This is a cross-sectional view showing multiple bonding pads 38 and 48. (Example) Figure 3 As shown, the wiring 37 of the first layer stack 30 includes electrically independent wirings 37A, 37B, and 37C. A first insulator 35 is provided between wirings 37A, 37B, and 37C in both the X and Y directions. Thus, wirings 37A, 37B, and 37C are electrically insulated from each other. Wirings 37A, 37B, and 37C can be at different potentials. Hereinafter, without distinguishing between wirings 37A, 37B, and 37C, they will be referred to as "wiring 37".

[0061] The bonding pads 38 of the first layer stack 30 include bonding pad 38A connected to wiring 37A, bonding pad 38B connected to wiring 37B, and bonding pad 38C connected to wiring 37C. A first insulator 35 is provided between bonding pads 38A, 38B, and 38C in both the X and Y directions. Bonding pads 38A, 38B, and 38C can be at different potentials. Hereinafter, bonding pads 38A, 38B, and 38C will be referred to as "bonding pad 38" without distinguishing them from each other.

[0062] In this embodiment, bonding pads 38A, 38B, and 38C each have a plurality of electrode portions 81 that are separated from each other in at least one of the X and Y directions. In one example described here, bonding pads 38A, 38B, and 38C each have a plurality of electrode portions 81 that are separated from each other in both the X and Y directions (see reference). Figure 4A first insulator 35 is provided between multiple electrode portions 81 in both the X and Y directions. In other words, when viewed along the Z direction, a first insulator 35 is provided between multiple electrode portions 81 in the adhesive surface S. The electrode portion 81 is an example of a "first electrode portion".

[0063] Multiple electrode portions 81 are independent of each other and are each connected to wiring 37. That is, multiple electrode portions 81 contained in the same bonding pad 38 are connected to the same wiring 37. The multiple electrode portions 81 contained in the same bonding pad 38 are at the same potential. Figure 3 In the example shown, the plurality of electrode portions 81 included in bonding pad 38A are connected to wiring 37A. The plurality of electrode portions 81 included in bonding pad 38B are connected to wiring 37B. The plurality of electrode portions 81 included in bonding pad 38C are connected to wiring 37C.

[0064] Similarly, the wiring 47 of the second layer stack 40 includes electrically independent wirings 47A, 47B, and 47C. A second insulator 45 is provided between wirings 47A, 47B, and 47C in both the X and Y directions. Thus, wirings 47A, 47B, and 47C are electrically insulated from each other. Wirings 47A, 47B, and 47C can be at different potentials. Hereinafter, without distinguishing between wirings 47A, 47B, and 47C, they will be referred to as "wiring 47".

[0065] The bonding pads 48 of the second layer stack 40 include bonding pad 48A connected to wiring 47A, bonding pad 48B connected to wiring 47B, and bonding pad 48C connected to wiring 47C. A second insulator 45 is provided between bonding pads 48A, 48B, and 48C in both the X and Y directions. Bonding pads 48A, 48B, and 48C can be at different potentials. Hereinafter, bonding pads 48A, 48B, and 48C will be referred to as "bonding pad 48" without distinguishing them from each other.

[0066] In this embodiment, similar to the bonding pads 38A, 38B, and 38C of the first laminate 30, the bonding pads 48A, 48B, and 48C each have a plurality of electrode portions 82 that are separated from each other in at least one of the X and Y directions. In one example described here, the bonding pads 48A, 48B, and 48C each have a plurality of electrode portions 82 that are separated from each other in both the X and Y directions. A second insulator 45 is provided between the plurality of electrode portions 82 in both the X and Y directions. In other words, when viewed along the Z direction, a second insulator 45 is provided between the plurality of electrode portions 82 in the bonding surface S. The electrode portion 82 is an example of a "second electrode portion".

[0067] Multiple electrode portions 82 are independent of each other and are each connected to wiring 47. That is, multiple electrode portions 82 contained in the same bonding pad 48 are connected to the same wiring 47. The multiple electrode portions 82 contained in the same bonding pad 48 are at the same potential. Figure 3 In the example shown, the plurality of electrode portions 82 included in bonding pad 48A are connected to wiring 47A. The plurality of electrode portions 82 included in bonding pad 48B are connected to wiring 47B. The plurality of electrode portions 82 included in bonding pad 48C are connected to wiring 47C.

[0068] The plurality of electrode portions 81 of the bonding pads 38 of the first laminate 30 and the plurality of electrode portions 82 of the bonding pads 48 of the second laminate 40 are bonded to each other through the adhesive surface S. Thus, the bonding pads 38 of the first laminate 30 and the bonding pads 48 of the second laminate 40 are bonded to each other. Figure 3 In the example shown, the plurality of electrode portions 81 of the bonding pads 38 of the first stack 30 and the plurality of electrode portions 82 of the bonding pads 48 of the second stack 40 are arranged in the same manner. "In the same manner" means that the plurality of electrode portions 81 and 82 have the same shape. In this case, the plurality of electrode portions 81 of the bonding pads 38 of the first stack 30 and the plurality of electrode portions 82 of the bonding pads 48 of the second stack 40 are bonded to each other in a one-to-one correspondence.

[0069] In this embodiment, the plurality of electrode portions 81 of the bonding pad 38A of the first laminate 30 are bonded to the plurality of electrode portions 82 of the bonding pad 48A of the second laminate 40, thereby electrically connecting wiring 37A and wiring 47A. Similarly, the plurality of electrode portions 81 of the bonding pad 38B of the first laminate 30 are bonded to the plurality of electrode portions 82 of the bonding pad 48B of the second laminate 40, thereby electrically connecting wiring 37B and wiring 47B. The plurality of electrode portions 81 of the bonding pad 38C of the first laminate 30 are bonded to the plurality of electrode portions 82 of the bonding pad 48C of the second laminate 40, thereby electrically connecting wiring 37C and wiring 47C.

[0070] In this embodiment, bonding pads 38A, 38B, 38C, 48A, 48B, and 48C have the same shape. Therefore, in the following, one bonding pad 38 of the first laminate 30 will be described in detail. The bonding pad 48 of the second laminate 40 also has the same structure as described below.

[0071] Figure 4 This is a diagram showing the bonding pad 38. Figure 4The bonding pad 38 indicates the state before the first laminate 30 and the second laminate 40 are bonded. In this embodiment, the plurality of electrode portions 81 includes, for example, nine electrode portions 81 separated in the X and Y directions and arranged in a 3×3 matrix. That is, the plurality of electrode portions 81 includes a plurality of electrode portions 81 separated from each other and arranged at equal intervals in the X direction. Similarly, the plurality of electrode portions 81 includes a plurality of electrode portions 81 separated from each other and arranged at equal intervals in the Y direction. However, the number and arrangement of the electrode portions 81 are not limited to the above example.

[0072] The electrode portion 81 is, for example, a quadrilateral shape along the X and Y directions. Figure 4 In the example shown, the width W1 of the electrode portion 81 in the X direction is the same as the distance L1 between two adjacent electrode portions 81 in the X direction. Similarly, the width W2 of the electrode portion 81 in the Y direction is the same as the distance L2 between two adjacent electrode portions 81 in the Y direction. The distances L1 and L2 between two adjacent electrode portions 81 are smaller than the distance L3 between two adjacent bonding pads 38 (see reference). Figure 3 ).

[0073] Viewed along the Z direction, when the inner region of the imaginary line IL is defined as the "pad region R", the total area of ​​the plurality of electrode portions 81 in the pad region R is less than the area of ​​the first insulator 35 in the pad region R. The imaginary line IL integrally surrounds the plurality of electrode portions 81 along the edge of the plurality of electrode portions 81A located at the outermost part of the plurality of electrode portions 81 relative to the center of the bonding pad 38. In other words, the plurality of electrode portions 81 are arranged apart from each other with a relatively large spacing.

[0074] In this embodiment, each electrode portion 81 includes an electrode body 91 and a connecting portion 92. The electrode body 91 has an adhesive surface S (refer to...) Figure 3 The electrode body 91 is exposed and bonded to the bonding pad 48 of the second layer stack 40. A connection portion 92 is located between the electrode body 91 and the wiring 37, connecting the electrode body 91 and the wiring 37. The connection portion 92 is thinner than the electrode body 91. For example, the width W4 of the connection portion 92 in the X direction is smaller than the width W3 of the electrode body 91 in the X direction. Similarly, the width of the connection portion 92 in the Y direction is smaller than the width of the electrode body 91 in the Y direction. The electrode body 91 of each electrode portion 81 is connected to the wiring 37 via the corresponding connection portion 92.

[0075] In another viewpoint, each electrode portion 81 has a conductive body 95 and a blocking metal layer 96. The conductive body 95 forms the main part of each electrode portion 81. The blocking metal layer 96 is disposed between the conductive body 95 and the first insulator 35 in the X and Y directions. The blocking metal layer 96 is a metal layer that inhibits the diffusion of conductive material (e.g., copper or aluminum) contained in the conductive body 95 into the first insulator 35. The conductive body 95 and the blocking metal layer 96 are respectively disposed on both sides of the electrode body 91 and the connecting portion 92.

[0076] like Figure 4 As shown, before the first laminate 30 and the second laminate 40 are bonded, the end E of each electrode portion 81 protrudes in the +Z direction relative to the surface 35a of the first insulator 35. The end E of each electrode portion 81 has a recess RS that is cup-shaped and recessed in the -Z direction.

[0077] The bonding pads 38 of the first layer stack 30 have been described above. Regarding the bonding pads 48 of the second layer stack 40, simply replace "bonding pad 38" with "bonding pad 48", "routing 37" with "routing 47", "+Z direction" with "-Z direction", and "-Z direction" with "+Z direction" in the above description.

[0078] Figure 5 This is a cross-sectional view showing the state of the electrode portion 81 of the first laminate 30 and the electrode portion 82 of the second laminate 40 when the first laminate 30 and the second laminate 40 are bonded together. In this embodiment, when bonding the first laminate 30 and the second laminate 40, the first laminate 30 and the second laminate 40 are heated, and the second laminate 40 is pressed toward the first laminate 30. That is, with the electrode portion 81 of the first laminate 30 and the electrode portion 82 of the second laminate 40 in contact with each other, the second laminate 40 is pressed toward the first laminate 30.

[0079] As a result, the electrode portion 81 of the first laminate 30 and the electrode portion 82 of the second laminate 40 are deformed. Specifically, the electrode portion 81 of the first laminate 30 is deformed so that it no longer protrudes from the surface 35a of the first insulator 35. Furthermore, the recess RS at the end E of the electrode portion 81 of the first laminate 30 is filled in and disappears (or becomes smaller). Similarly, the electrode portion 82 of the second laminate 40 is deformed so that it no longer protrudes from the surface 45a of the second insulator 45. Furthermore, the recess RS at the end of the electrode portion 82 of the second laminate 40 is filled in and disappears (or becomes smaller).

[0080] <3. Manufacturing Method of Semiconductor Memory Devices>

[0081] Next, the manufacturing method of semiconductor memory device 1 will be described. Figures 6 to 9 This is a cross-sectional view showing the manufacturing method of semiconductor memory device 1.

[0082] Figure 6 This indicates the manufacturing stage of circuit chip 2. Circuit chip 2 is manufactured as part of a circuit wafer CW. The circuit wafer CW includes multiple circuit chips 2. The circuit wafer CW is obtained by forming a first layer stack 30 on a first substrate 10. The first layer stack 30 includes transistors 31, contact plugs 32, wiring 33, pads 34, and a first insulator 35. These are formed for each layer. The circuit wafer CW is formed by repeatedly performing film deposition and photolithography-based processing on these layers. Film deposition methods and processing methods other than bonding pads 38 can use known methods. Multiple bonding pads 38 are exposed on the bonding surface S1 of the circuit wafer CW opposite to the first substrate 10. Thus, the circuit wafer CW is completed.

[0083] Here, the method for forming the bonding pad 38 is described in detail. Figure 7 This describes the detailed manufacturing stages of the bonding pad 38. First, as... Figure 7 As shown in (a), a portion of a first insulator 35 is provided on the wiring 37. The first insulator 35 provided on the wiring 37 is formed, for example, from silicon oxide (SiO2).

[0084] Next, a protective layer 101 is formed on the first insulator 35. The protective layer 101 is formed of a material different from the first insulator 35. For example, the protective layer 101 is formed of silicon nitride (SiN). The thickness T1 of the protective layer 101 is, for example, set to be greater than the amount of depression K of the depression RS caused by chemical mechanical polishing (see reference). Figure 7 (c)). For example, the thickness T1 of the protective layer 101 (e.g., the thickness in the Z direction) is greater than the thickness T2 of the blocking metal layer 96 (e.g., the thickness in the X direction).

[0085] Next, as Figure 7 As shown in (b), a resist pattern is formed by a photo etching process (PEP), and the protective layer 101 and the first insulator 35 are etched by reactive ion etching (RIE). As a result, a plurality of holes 102 are formed at the locations where a plurality of electrode portions 81 will be provided in subsequent processes.

[0086] Next, as Figure 7As shown in (c), a conductive layer 103a, which forms the basis of the blocking metal layer 96, is formed on the inner surface of the hole 102. Then, by filling the interior of the hole 102 with a conductive material (such as a metal material like copper or aluminum), a conductive portion 103b, which forms the basis of the conductive portion body 95, is formed. Thus, a conductive portion 103 is formed that fills the hole 102. The conductive portion 103 forms the basis of the plurality of electrode portions 81.

[0087] Next, the conductive portion 103 is planarized by chemical mechanical polishing (CMP) with the protective layer 101 as a stop layer. For example, CMP is performed at the endpoint of polishing by inspecting the surface of the protective layer 101. As a result, a plurality of electrode portions 81 are formed from the conductive portion 103. At this time, a recess RS caused by dishing is formed on the surface of the upper end of each electrode portion 81.

[0088] Next, as Figure 7 As shown in (d), the protective layer 101 is removed. If the protective layer 101 is a silicon nitride, phosphoric acid is used, for example, to remove it. This exposes the surface 35a of the first insulator 35. The surface 35a of the first insulator 35 forms an adhesive surface S1 for bonding to the array chip 3. The upper end portion, or end portion E, of each electrode portion 81 protrudes upward from the surface 35a (adhesive surface S1) of the first insulator 35. This completes the bonding pad 38.

[0089] Figure 8 This indicates the manufacturing stage of array chip 3. Array chip 3 is manufactured as part of array wafer AW. Array wafer AW comprises multiple array chips 3. Figure 8 The array chip AW shown is in its state before being bonded to the circuit chip CW, relative to Figure 1 The array chip 3 shown is flipped vertically.

[0090] An array wafer AW is obtained by forming a second layer stack 40 on a second substrate 60. The second layer stack 40 includes a memory element array 41, contact plugs 42, wiring 43, pads 44, and a second insulator 45. These are formed for each layer. The array wafer AW is formed by repeatedly performing film deposition and photolithography-based processing on these layers. Film deposition methods and processing methods other than bonding pads 48 can be used using known methods. A plurality of bonding pads 48 are exposed on the bonding surface S2 of the array wafer AW opposite to the second substrate 60. The method for forming the bonding pads 48 is, for example, the same as described in Reference Figure 7 The method for forming the bonding pad 38 described above is the same. Thus, the circuit chip CW is completed.

[0091] Figure 9This describes the bonding stage between the circuit chip CW and the array chip AW. Specifically, the circuit chip CW and the array chip AW are heated, and the bonding surface S1 of the circuit chip CW and the bonding surface S2 of the array chip AW are brought face to face (i.e., the bonding pads 38 of the first laminate 30 and the bonding pads 48 of the second laminate 40 are brought face to face). The circuit chip CW and the array chip AW are then bonded together by mechanical pressure. As a result, the first insulator 35 and the second insulator 45 are bonded together.

[0092] At this time, as referenced Figure 5 As described above, with the end E of the electrode portion 81 of the bonding pad 38 protruding from the surface 35a of the first insulator 35 and the end E of the electrode portion 82 of the bonding pad 48 protruding from the surface 45a of the second insulator 45, the bonding pad 38 of the circuit chip CW and the bonding pad 48 of the array chip AW abut against each other. Then, by mechanical pressure, the electrode portions 81 of the bonding pad 38 and 82 of the bonding pad 48 that abut against each other are deformed, and the recesses RS formed in the electrode portions 81 and 82 due to the depression in the previous process are filled in and disappear (or become smaller).

[0093] Next, the array wafer AW and the circuit wafer CW are annealed at 400°C. As a result, the electrode portion 81 of the bonding pad 38 and the electrode portion 82 of the bonding pad 48 are bonded together. Thus, an adhesive body 111 is formed, which bonds the circuit wafer CW and the array wafer AW together.

[0094] Next, the second substrate 60 is thinned. The thinning of the second substrate 60 is performed, for example, by CMP. Then, external connection pads 71 ​​and insulating layers 72 and 73 are provided on the second substrate 60 using a known method. Then, the adhesive 111 is cut along a cutting line (not shown). Thus, the adhesive 111 is divided into multiple chips (semiconductor memory devices 1). Thus, the semiconductor memory device 1 is obtained.

[0095] <4. Advantages>

[0096] For comparison, we consider the case where the bonding pads are configured with a relatively large electrode portion. In such a comparative example, when a large indentation occurs at the end of the bonding pad due to CMP or other reasons, space may remain between the two bonded bonding pads. In this case, a void is formed on the bonding surface of the two bonding pads. The resistance of the bonding pads becomes high in this situation.

[0097] Furthermore, this gap may sometimes move (condense) towards the connection between the bonding pad and the wiring due to stress migration caused by room temperature. In this case, there is a possibility that the bonding pad and the wiring may become disconnected. On the other hand, when the annealing temperature is increased to increase thermal expansion in order to make the two bonding pads bond more reliably, the metal contained in the barrier metal layer diffuses into the interior of the insulator, and there is a possibility that the barrier metal layer's barrier properties may decrease.

[0098] On the other hand, in this embodiment, the bonding pad 38 includes a plurality of electrode portions 81 that are separated from each other in the X direction and are respectively connected to the wiring 37. A first insulator 35 is provided between the plurality of electrode portions 81. According to this configuration, the bonding pad 38 is divided into a plurality of smaller electrode portions 81, so it is difficult to generate large depressions in each electrode portion 81, and the depression amount K of the depression RS is reduced. Therefore, it is difficult for space to remain between the two bonded bonding pads 38, 48, and it is difficult for gaps to be generated on the bonding surfaces of the two bonding pads. As a result, the resistance of the bonding pads 38, 48 is less likely to become high. Thus, the electrical characteristics of the semiconductor memory device 1 can be improved.

[0099] Furthermore, in this embodiment, the multiple electrode portions 81 are independent of each other and are each connected to the wiring 37. With this configuration, the stress acting on the bonding pad 38 can be dispersed through the multiple electrode portions 81. This reduces the probability of wire breakage caused by stress migration.

[0100] In this embodiment, during the manufacture of the semiconductor memory device 1, a protective layer 101 is provided on the first insulator 35. Then, a plurality of electrode portions 81 are formed by chemical mechanical polishing using the protective layer 101 as a stop layer. Afterwards, the protective layer 101 is removed. This causes the ends E of the plurality of electrode portions 81 to protrude from the first insulator 35. Then, with the ends E of the plurality of electrode portions 81 protruding from the first insulator 35, the plurality of electrode portions 81 of the bonding pad 38 are brought into contact with the bonding pad 48. With this configuration, the two bonding pads 38 and 48 are bonded with the ends E of the electrode portions 81 protruding from the first insulator 35, thus filling the recess RS caused by the depression by the ends E of the electrode portions 81 protruding from the first insulator 35. Therefore, it is difficult for space to remain between the two bonded bonding pads 38 and 48, and it is difficult for gaps to form on the bonding surfaces of the two bonding pads 38 and 48. This improves the electrical characteristics of the semiconductor memory device 1.

[0101] Furthermore, when the protective layer 101 is used as a stop layer for chemical mechanical polishing, a recess RS is formed at a higher position relative to the surface 35a of the first insulator 35, compared to the case where the protective layer 101 is not provided. That is, multiple electrode portions 81 are formed with the interface where the recess is formed raised. Therefore, when viewed with the surface 35a of the first insulator 35 as a reference, it is difficult for a large recess to be formed in the electrode portions 81, and the amount of recess K of the recess RS becomes smaller. For this reason, it is also difficult for space to remain between the two bonded pads 38 and 48, and it is difficult for gaps to be formed on the bonding surfaces of the two bonded pads 38 and 48. As a result, the electrical characteristics of the semiconductor memory device 1 can be improved.

[0102] In this embodiment, viewed along the Z-direction, when the area integrally surrounded by the edges of the outermost electrode portions 81A relative to the center of the bonding pad 38 is defined as the pad region R, the total area of ​​the electrode portions 81 in the pad region R is less than the area of ​​the first insulator 35 in the pad region R. With this configuration, the bonding pad 38 is divided into multiple smaller electrode portions 81, making it less likely for large depressions to form in each electrode portion 81. This improves the electrical characteristics of the semiconductor memory device 1.

[0103] In this embodiment, the plurality of electrode portions 81 include a plurality of electrode portions 81 separated in the X direction and a plurality of electrode portions 81 separated in the Y direction. With this configuration, the bonding pad 38 is divided into smaller electrode portions 81 in multiple directions, thus making it less likely for large depressions to form in each electrode portion 81. This, in turn, enables the improvement of the electrical characteristics of the semiconductor memory device 1.

[0104] In this embodiment, each of the plurality of electrode portions 81 has an electrode body 91 and a connecting portion 92 located between the electrode body 91 and the wiring 37. The width W4 of the connecting portion 92 in the X direction is smaller than the width W3 of the electrode body 91 in the X direction. With this configuration, even if the connection portion 92 is thinner, which could easily lead to wire breakage due to stress migration, the probability of wire breakage due to stress migration can be reduced because the plurality of electrode portions 81 are independent of each other and each is connected to the wiring 37.

[0105] <5. Variations>

[0106] Hereinafter, a modified example will be described. In this modified example, the configuration is the same as that of the embodiment described above, except as described below.

[0107] Figure 10 This is a cross-sectional view of a modified semiconductor memory device 1. Figure 11 It is Figure 10 The diagram shows an enlarged cross-sectional view of the area enclosed by line F11. In this modified example, the width W1A of each electrode portion 81 of the bonding pad 38 of the first stack 30 in the X direction is greater than the distance L1B between two adjacent electrode portions 82 of the bonding pad 48 of the second stack 40 in the X direction. Similarly, the width W1B of each electrode portion 82 of the bonding pad 48 of the second stack 40 in the X direction is greater than the distance L1A between two adjacent electrode portions 81 of the bonding pad 38 of the first stack 30 in the X direction. The same applies in the Y direction.

[0108] In this modified example, even if the bonding pad 48 of the second stack 40 is offset relative to the bonding pad 38 of the first stack 30, a portion of the electrode portion 81 of the bonding pad 38 and a portion of the electrode portion 82 of the bonding pad 48 reliably face each other in the Z direction, and the electrode portion 81 of the bonding pad 38 and the electrode portion 82 of the bonding pad 48 are reliably connected. Therefore, the electrical characteristics of the semiconductor memory device 1 can be improved.

[0109] <6. Examples>

[0110] Hereinafter, several embodiments relating to the shapes of the electrode portions 81 and 82 of the bonding pads 38 and 48 will be described. The shape of the electrode portion 81 of the bonding pad 38 of the first laminate 30 will be used as an example for description. The shape of the electrode portion 82 of the bonding pad 48 of the second laminate 40 is also the same. However, the shapes of the electrode portions 81 and 82 are not limited to the embodiments described below.

[0111] <6.1 First Embodiment>

[0112] Figure 12 This is a cross-sectional view showing the shape of the plurality of electrode portions 81 in the first embodiment. In the first embodiment, the plurality of electrode portions 81 are separated in the X and Y directions and arranged in a matrix. Figure 12 In the example shown, there are 64 electrode sections 81 in an 8×8 configuration.

[0113] <6.2 Example 2>

[0114] Figure 13This is a cross-sectional view showing the shape of the plurality of electrode portions 81 in the second embodiment. In the second embodiment, the bonding pad 38 includes a frame portion 121, a plurality of first straight portions 122, and a plurality of second straight portions 123. The plurality of first straight portions 122 and the plurality of second straight portions 123 are disposed inside the frame portion 121. The plurality of first straight portions 122 are separated from each other in the X direction and extend along the Y direction respectively. A first insulator 35 is disposed between the plurality of first straight portions 122 in the X direction. On the other hand, the plurality of second straight portions 123 are separated from each other in the Y direction and extend along the X direction respectively. A first insulator 35 is disposed between the plurality of second straight portions 123 in the Y direction. The plurality of first straight portions 122 and the plurality of second straight portions 123 intersect each other.

[0115] In this embodiment, a plurality of electrode portions 81 that are separated from each other in the X direction are formed by a plurality of first straight sections 122. Similarly, a plurality of electrode portions 81 that are separated from each other in the Y direction are formed by a plurality of second straight sections 123. In this specification, "separated from each other" is not limited to the case of being completely independent as in the first embodiment, but also includes the case of being interconnected via other parts (e.g., frame portions 121).

[0116] In the second embodiment, the first straight section 122 has a length that spans at least two of the plurality of second straight sections 123 in its extending direction (Y direction). With this configuration, even if a positional offset occurs in the Y direction between the bonding pad 38 and the bonding pad 48, the bonding pad 38 and the bonding pad 48 can be connected more reliably. Similarly, the second straight section 123 has a length that spans at least two of the plurality of first straight sections 122 in its extending direction (X direction). With this configuration, even if a positional offset occurs in the X direction between the bonding pad 38 and the bonding pad 48, the bonding pad 38 and the bonding pad 48 can be connected more reliably.

[0117] <6.3 Third Embodiment>

[0118] Figure 14 This is a cross-sectional view showing the shape of the plurality of electrode portions 81 in the third embodiment. In the third embodiment, the bonding pad 38 includes a plurality of straight portions 131. The plurality of straight portions 131 are separated from each other in the Y direction and extend along the X direction respectively. A first insulator 35 is provided between the plurality of straight portions 131 in the Y direction. In this embodiment, the plurality of electrode portions 81 separated from each other in the Y direction are formed by the plurality of straight portions 131. According to this configuration, even if a positional offset occurs in the X direction between the bonding pad 38 and the bonding pad 48, the bonding pad 38 and the bonding pad 48 can be connected more reliably.

[0119] <6.4 Example 4>

[0120] Figure 15 This is a cross-sectional view showing the shape of the plurality of electrode portions 81 in the fourth embodiment. In the third embodiment, the bonding pad 38 includes a plurality of straight portions 141. The plurality of straight portions 141 are separated from each other in the X direction and extend along the Y direction respectively. A first insulator 35 is provided between the plurality of straight portions 141 in the X direction. In this embodiment, the plurality of electrode portions 81 separated from each other in the X direction are formed by the plurality of straight portions 141. According to this configuration, even if a positional offset in the Y direction occurs between the bonding pad 38 and the bonding pad 48, the bonding pad 38 and the bonding pad 48 can be connected more reliably.

[0121] <6.5 Example 5>

[0122] Figure 16 This is a cross-sectional view showing the shape of the plurality of electrode portions 81 in the fifth embodiment. In the fifth embodiment, the bonding pad 38 includes a frame portion 151 and a plurality of straight portions 152. The plurality of straight portions 152 are disposed inside the frame portion 151. The plurality of straight portions 152 are separated from each other in the Y direction and extend along the X direction respectively. A first insulator 35 is disposed between the plurality of straight portions 152 in the Y direction. In this embodiment, the plurality of electrode portions 81 separated from each other in the Y direction are formed by the plurality of straight portions 152.

[0123] <6.6 Example 6>

[0124] Figure 17 This is a cross-sectional view showing the shape of the plurality of electrode portions 81 in the sixth embodiment. In the sixth embodiment, the bonding pad 38 includes a frame portion 161 and a plurality of straight portions 162. The plurality of straight portions 162 are disposed inside the frame portion 161. The plurality of straight portions 162 are separated from each other in the X direction and extend along the Y direction respectively. A first insulator 35 is disposed between the plurality of straight portions 162 in the X direction. In this embodiment, the plurality of electrode portions 81 separated from each other in the X direction are formed by the plurality of straight portions 162.

[0125] <6.7 Example 7>

[0126] Figure 18This is a cross-sectional view showing the shape of the plurality of electrode portions 81 in the seventh embodiment. In the seventh embodiment, the bonding pad 38 includes a plurality of frame portions 171. The plurality of frame portions 171 are annular rings of similar shapes of different sizes and are arranged concentrically. A first insulator 35 is provided between the plurality of frame portions 171 in the X and Y directions. In this embodiment, the plurality of annular electrode portions 81 are formed by the plurality of frame portions 171. From another viewpoint, the plurality of electrode portions 81 separated from each other in the X direction are formed by the linear portions 171a included in the plurality of frame portions 171 along the Y direction. Similarly, the plurality of electrode portions 81 separated from each other in the Y direction are formed by the linear portions 171b included in the plurality of frame portions 171 along the X direction. When the bonding pad 38 includes both a portion extending along the Y direction and a portion extending along the X direction, the bonding pad 38 and the bonding pad 48 can be more easily and reliably connected even if there is a positional offset in either the X or Y direction between the bonding pad 38 and the bonding pad 48.

[0127] <6.8 Example 8>

[0128] Figure 19 This is a cross-sectional view of the shapes of the plurality of electrode portions 81, 82 in the eighth embodiment. Figure 19 In the diagram, (a) represents the plurality of electrode portions 81 of the bonding pads 38 of the first layer 30. Figure 19 In the diagram, (b) represents the plurality of electrode portions 82 of the bonding pad 48 of the second layer stack 40.

[0129] In this embodiment, the plurality of electrode portions 81 of the bonding pads 38 of the first laminate 30 are arranged in a first manner. This first manner is, for example, similar to that of the third embodiment (…). Figure 14 The same method. On the other hand, the plurality of electrode portions 82 of the bonding pads 48 of the second laminate 40 are arranged in a second manner, different from the first manner described above. "Different manner" means that the shapes of the plurality of electrode portions 81, 82 are different. The second manner of this embodiment is, for example, the same as that of the fourth embodiment ( Figure 15 In the same way.

[0130] Figure 19 In the diagram, (c) indicates a state where the plurality of electrode portions 81 of the bonding pad 38 overlap (bond) with the plurality of electrode portions 82 of the bonding pad 48. Figure 19 In the example shown, the direction (Y direction) in which the plurality of electrode portions 81 of the bonding pad 38 are separated from each other is different from the direction (X direction) in which the plurality of electrode portions 82 of the bonding pad 48 are separated from each other.

[0131] At least a portion of each electrode portion 81 of the bonding pad 38 extends in a straight line across two or more electrode portions 82 in the direction (X direction) in which the plurality of electrode portions 82 of the bonding pad 48 are separated from each other. On the other hand, at least a portion of each electrode portion 82 of the bonding pad 48 extends in a straight line across two or more electrode portions 81 in the direction (Y direction) in which the plurality of electrode portions 81 of the bonding pad 38 are separated from each other. With this configuration, even if a positional offset occurs between the bonding pad 38 and the bonding pad 48 in any direction in the X and Y directions, the bonding pad 38 and the bonding pad 48 are connected more reliably.

[0132] <6.9 Example 9>

[0133] Figure 20 This is a cross-sectional view showing the shapes of the plurality of electrode portions 81, 82 in the 9th embodiment. Figure 20 In the diagram, (a) represents the plurality of electrode portions 81 of the bonding pads 38 of the first layer 30. Figure 20 In the diagram, (b) represents the plurality of electrode portions 82 of the bonding pad 48 of the second layer stack 40.

[0134] In this embodiment, the plurality of electrode portions 81 of the bonding pads 38 of the first laminate 30 are arranged in a first manner. The first manner of this embodiment is, for example, similar to the first embodiment (…). Figure 12 The same method. On the other hand, the plurality of electrode portions 82 of the bonding pads 48 of the second laminate 40 are arranged in a second manner, different from the first manner described above. The second manner of this embodiment is, for example, the same as that of the seventh embodiment ( Figure 18 In the same way.

[0135] Figure 20 In the diagram, (c) indicates a state where the plurality of electrode portions 81 of the bonding pad 38 overlap (bond) with the plurality of electrode portions 82 of the bonding pad 48. Figure 20 In the example shown, the plurality of electrode portions 81 of the bonding pad 38 are separated from each other in the X and Y directions. On the other hand, at least a portion (e.g., line portion 171b) of each electrode portion 82 of the bonding pad 48 extends in a straight line across (spanning) two or more electrode portions 81 in the direction in which the plurality of electrode portions 81 of the bonding pad 38 are separated from each other (X direction). At least a portion (e.g., line portion 171a) of each electrode portion 82 of the bonding pad 48 extends in a straight line across (spanning) two or more electrode portions 81 in the direction in which the plurality of electrode portions 81 of the bonding pad 38 are separated from each other (Y direction). With this configuration, even if a positional offset occurs between the bonding pad 38 and the bonding pad 48 in any direction in the X and Y directions, the bonding pad 38 and the bonding pad 48 are connected more reliably.

[0136] The embodiments, modifications, and several examples have been described above. However, the embodiments, modifications, and examples are not limited to the examples described above. For example, the electrode portion 81 of the bonding pad 38 in any of the first to seventh embodiments described above can also be bonded to the electrode portion 82 of the bonding pad 48 in any other embodiment of the first to seventh embodiments described above. In all the above descriptions, the shapes of the bonding pad 38 and the bonding pad 48 can also be opposite. In the above embodiments, the bonding pad 38 is divided into multiple electrode portions 81, and the bonding pad 48 is divided into multiple electrode portions 82. Alternatively, the bonding pad 38 may be divided into multiple electrode portions 81, and the bonding pad 48 may be a single large pad, or the bonding pad 48 may be divided into multiple electrode portions 82, and the bonding pad 38 may be a single large pad.

[0137] According to at least one embodiment described above, a semiconductor memory device has a first laminate and a second laminate. The first laminate includes a first wiring, a first pad connected to the first wiring, and a first insulator. The second laminate includes a second wiring, a second pad connected to the second wiring, and a second insulator. The first pad includes a plurality of first electrode portions that are separated from each other and respectively connected to the first wiring. A first insulator is disposed between the plurality of first electrode portions. The plurality of first electrode portions are bonded to the second pad. According to this configuration, a semiconductor memory device capable of achieving improved electrical characteristics and a method for manufacturing a semiconductor memory device can be provided.

[0138] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: 1st substrate; The second substrate is separated from the first substrate in the thickness direction, i.e., the first direction; A first laminate, disposed between the first substrate and the second substrate, includes a first wiring, a first pad connected to the first wiring, and a first insulator; and The second layer stack, disposed between the first layer stack and the second substrate, includes a second wiring, a second pad connected to the second wiring, and a second insulator. The first pad mentioned above includes: Frame; A plurality of first straight sections are disposed inside the frame portion, separated from each other in a second direction intersecting the first direction, and extend linearly in a third direction intersecting both the first and second directions to connect with the frame portion; and Multiple second straight sections are disposed inside the frame portion, are separated from each other in the third direction, extend linearly in the second direction, intersect with the multiple first straight sections, and connect with the frame portion. The first insulator is provided between the plurality of first straight sections and between the plurality of second straight sections. The aforementioned plurality of first straight sections and the aforementioned plurality of second straight sections are bonded to the aforementioned second pad.

2. The semiconductor memory device according to claim 1, wherein, The aforementioned second pad includes a plurality of second electrode portions that are separated from each other in the aforementioned second direction or the aforementioned third direction and are respectively connected to the aforementioned second wiring. The aforementioned second insulator is disposed between the plurality of second electrode portions. The aforementioned plurality of second electrode portions are engaged with the aforementioned plurality of first linear portions and the aforementioned plurality of second linear portions.

3. The semiconductor memory device according to claim 2, wherein, Viewed from the first direction, when the area enclosed by the frame along the frame is defined as the pad area, the total area of ​​the plurality of first straight sections and the plurality of second straight sections in the pad area is less than the area of ​​the first insulator in the pad area.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein, The second pad mentioned above includes multiple electrode portions that are separated from each other in the second direction and the third direction mentioned above. The plurality of first straight portions and the plurality of second straight portions of the first pad are joined with the plurality of electrode portions of the second pad.

5. The semiconductor memory device according to any one of claims 1 to 3, wherein, The second pad mentioned above includes multiple electrode portions in a concentric ring shape. The plurality of first straight portions and the plurality of second straight portions of the first pad are joined with the plurality of electrode portions of the second pad.

6. A method for manufacturing a semiconductor memory device, wherein, A first laminate including a first wiring, a first pad connected to the first wiring, and a first insulator is formed on the first substrate. A second laminate, including a second wiring, a second pad connected to the second wiring, and a second insulator, is formed on the second substrate. By making the first pad and the second pad face each other, the first laminate and the second laminate are bonded together, thus joining the first pad and the second pad. The first pad mentioned above includes: Frame; A plurality of first straight sections are disposed inside the frame portion, and are separated from each other in a second direction intersecting the thickness direction (i.e., the first direction) of the first substrate, and extend linearly in a third direction intersecting both the first and second directions to connect with the frame portion; and Multiple second straight sections are disposed inside the frame portion, are separated from each other in the third direction, extend linearly in the second direction, intersect with the multiple first straight sections, and connect with the frame portion. The first insulator is provided between the plurality of first straight sections and between the plurality of second straight sections. The aforementioned plurality of first straight sections and the aforementioned plurality of second straight sections are bonded to the aforementioned second pad.

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