Semiconductor storage device

Abstract

A semiconductor storage device according to the present invention comprises a first memory cell transistor, a second memory cell transistor, a sense amplifier, and a control unit. In a first operation mode, the control unit, via the sense amplifier, senses data stored at the first memory cell transistor. In the first operation mode, the control unit adjusts a first prescribed number of first read voltages to the first prescribed number of third read voltages that include a second prescribed number that is smaller than the first prescribed number of second read voltages that correspond to a plurality of second threshold voltage distributions, applies the first prescribed number of third read voltages to a gate of the second memory cell transistor via a word line, and, via the sense amplifier, senses data stored at the second memory cell transistor.

Description

Semiconductor memory device

[0001] The embodiment relates to a semiconductor memory device.

[0002] As a semiconductor memory device, a NAND type flash memory is known.

[0003] Japanese Patent Application Laid-Open No. 2023-86292

[0004] According to the disclosed embodiment, a semiconductor memory device capable of improving the speed of the read operation is provided.

[0005] The semiconductor memory device of the embodiment includes a first memory cell transistor, a second memory cell transistor, a sense amplifier, and a control unit. Data is stored in the first memory cell transistor using a plurality of first threshold voltage distributions. Data is stored in the second memory cell transistor using a plurality of second threshold voltage distributions that are fewer than the plurality of first threshold voltage distributions. The sense amplifier senses the data stored in the first memory cell transistor and the second memory cell transistor via bit lines connected to the first memory cell transistor and the second memory cell transistor during a read operation. The control unit controls the voltages applied to the gates of the first memory cell transistor and the second memory cell transistor from a word line. In a first operation mode in which the control unit reads data from the first memory cell transistor, the control unit applies a first predetermined number of first read voltages corresponding to the plurality of first threshold voltage distributions to the gate of the first memory cell transistor via the word line, and senses the data stored in the first memory cell transistor by the sense amplifier. In the first operation mode, the control unit adjusts the first predetermined number of first read voltages to a first predetermined number of third read voltages including a second predetermined number of second read voltages that are fewer than the first predetermined number and correspond to the plurality of second threshold voltage distributions, and applies the first predetermined number of third read voltages to the gate of the second memory cell transistor via the word line to sense the data stored in the second memory cell transistor by the sense amplifier.

[0006] A block diagram showing the schematic configuration of the memory system of the first embodiment. A block diagram showing the schematic configuration of the semiconductor memory device of the first embodiment. (A) to (D) are diagrams schematically showing an example of the operating mode of the semiconductor memory device of the first embodiment. A circuit diagram showing the configuration of the semiconductor memory device of the first embodiment. A cross-sectional view showing the cross-sectional structure of the semiconductor memory device of the first embodiment. A block diagram showing the configuration of the sense amplifier unit of the first embodiment. A diagram showing an example of the threshold voltage distribution of the memory cell transistors of the TLC of the first embodiment. A diagram showing an example of the read voltage corresponding to the memory cell transistors of the TLC of the first embodiment. (A) to (C) are diagrams showing the potential change of each wiring during the read operation of the upper page of the TLC of the first embodiment. A diagram showing an example of data sensing and latching operations during the read operation of the upper page of the TLC of the first embodiment. (A) to (C) are diagrams showing the potential change of each wiring during the read operation of the middle page of the TLC of the first embodiment. (A) to (C) are diagrams showing the potential change of each wiring during the read operation of the lower page of the TLC of the first embodiment. Figure showing an example of the threshold voltage distribution of the memory cell transistors of the QLC in the first embodiment. Figure showing an example of the read voltage corresponding to the memory cell transistors of the QLC in the first embodiment. Figures (A) to (C) show the potential change of each wiring during the read operation of the top page of the TLC in the first embodiment. Figures showing an example of data sensing and latching operations during the read operation of the top page of the QLC in the first embodiment. Figures (A) to (C) show the potential change of each wiring during the read operation of the upper pages of the TLC in the first embodiment. Figures (A) to (C) show the potential change of each wiring during the read operation of the middle pages of the TLC in the first embodiment. Figures (A) to (C) show the potential change of each wiring during the read operation of the lower pages of the TLC in the first embodiment. Figure showing an example of the transition of signals transmitted and received between the semiconductor memory device and the memory controller in the first embodiment. Block diagram showing the functional configuration of the sequencer in the first embodiment. Figure showing an example of the voltage shift amount when reading the TLC in QLC mode in the first embodiment. This figure shows an example of the adjusted read voltage when reading out the TLC in QLC mode in the first embodiment.Figures (A) to (C) show the potential change of each wire during the read operation of the upper page of the TLC in the QLC mode of the first embodiment. Figures showing an example of data sensing and latching operations during the read operation of the upper page of the TLC in the QLC mode of the first embodiment. Figures (A) to (C) show the potential change of each wire during the read operation of the middle page of the TLC in the QLC mode of the first embodiment. Figures showing an example of data sensing and latching operations during the read operation of the middle page of the TLC in the QLC mode of the first embodiment. Figures (A) to (C) show the potential change of each wire during the read operation of the lower page of the TLC in the QLC mode of the first embodiment. Figures showing an example of data sensing and latching operations during the read operation of the lower page of the TLC in the QLC mode of the first embodiment. Figures showing an example of the transition of signals etc. transmitted and received between the semiconductor memory device and the memory controller of the first embodiment. Figures showing an example of the transition of signals etc. transmitted and received between the semiconductor memory device and the memory controller of the first embodiment. Figures showing an example of the transition of signals etc. transmitted and received between the semiconductor memory device and the memory controller of the first embodiment. Figures (A) to (C) show the potential change of each wire during the read operation of the upper page of the TLC in the QLC mode of the first modified example of the first embodiment. Figures showing an example of data sensing and latching operations during the read operation of the upper page of the TLC in the QLC mode of the first modified example of the first embodiment. Figures (A) to (C) show the potential change of each wire during the read operation of the upper page of the TLC in the QLC mode of the first modified example of the first embodiment. Figures (A) to (C) show the potential change of each wire during the read operation of the middle page of the TLC in the QLC mode of the first modified example of the first embodiment. Figures (A) to (C) show the potential change of each wire during the read operation of the middle page of the TLC in the QLC mode of the first modified example of the first embodiment. Figures showing an example of the read voltage corresponding to the memory cell transistor of the PLC in the second modified example of the first embodiment. Figures showing an example of the adjusted read voltage when reading the top page of the QLC in the PLC mode of the second modified example of the first embodiment.A figure showing an example of the adjusted read voltage when reading the upper pages of a QLC in the PLC mode of the second modification of the first embodiment. A figure showing an example of the adjusted read voltage when reading the lower pages of a QLC in the PLC mode of the second modification of the first embodiment. A figure showing an example of the adjusted read voltage when reading the middle pages of a QLC in the PLC mode of the second modification of the first embodiment. A figure showing an example of data sensing and latching operations during the reading operation of the upper pages of a TLC in the QLC mode of the second embodiment.

[0007] The embodiments will be described below with reference to the drawings. To facilitate understanding of the explanation, the same reference numerals are used for identical components in each drawing whenever possible, and redundant explanations are omitted.

[0008] 1. The semiconductor memory device of the embodiment will be described. The semiconductor memory device according to this embodiment is a non-volatile memory device configured as a NAND flash memory.

[0009] 1.1 Memory System Configuration First, the configuration of the memory system of this embodiment will be described.

[0010] As shown in Figure 1, the memory system 3 of this embodiment comprises a memory controller 1 and a semiconductor memory device 2. The semiconductor memory device 2 is a non-volatile memory device configured as a NAND flash memory. The memory system 3 is connectable to a host. The host is an electronic device such as a personal computer or a mobile terminal.

[0011] The memory controller 1 controls the writing of data to the semiconductor storage device 2 in accordance with write requests from the host. The memory controller 1 also controls the reading of data from the semiconductor storage device 2 in accordance with read requests from the host.

[0012] The following signals are transmitted and received between the memory controller 1 and the semiconductor memory device 2: chip enable signal / CE, ready busy signal R / B, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE, RE, write protect signal / WP, signal DQ<7:0>, and data strobe signals DQS, / DQS.

[0013] The chip enable signal / CE is transmitted from the memory controller 1 to the semiconductor memory device 2. The chip enable signal / CE is a signal to enable the semiconductor memory device 2. The ready / busy signal R / B is transmitted from the semiconductor memory device 2 to the memory controller 1. The ready / busy signal R / B is a signal to indicate whether the semiconductor memory device 2 is in a ready state or a busy state. "Ready state" is, for example, a state in which it is ready to accept commands from the outside. "Busy state" is a state in which it is not ready to accept commands from the outside.

[0014] The command latch enable signal CLE is transmitted from the memory controller 1 to the semiconductor storage device 2. The command latch enable signal CLE indicates that signal DQ<7:0> is a command. The address latch enable signal ALE is transmitted from the memory controller 1 to the semiconductor storage device 2. The address latch enable signal ALE indicates that signal DQ<7:0> is an address. The write enable signal / WE is transmitted from the memory controller 1 to the semiconductor storage device 2. The write enable signal / WE is a signal for capturing the received signal in the semiconductor storage device 2, and is asserted by the memory controller 1 each time a command, address, or data is received. The memory controller 1 instructs the semiconductor storage device 2 to capture signal DQ<7:0> while signal / WE is at the "L (Low)" level.

[0015] The read enable signal / RE is transmitted from the memory controller 1 to the semiconductor memory device 2. Signal RE is the complementary signal to signal / RE. The read enable signals / RE and RE are signals for the memory controller 1 to read data from the semiconductor memory device 2. The read enable signals / RE and RE are used to control the operating timing of the semiconductor memory device 2 when, for example, outputting signal DQ<7:0>. Signal DQ<7:0> is the actual data transmitted and received between the semiconductor memory device 2 and the memory controller 1, and includes commands, addresses, and data. The data strobe signal DQS is a timing control signal transmitted and received between the semiconductor memory device 2 and the memory controller 1 in conjunction with signal DQ<7:0>. Signal / DQS is the complementary signal to signal DQS. The data strobe signals DQS and / DQS are signals for controlling the input and output timing of signal DQ<7:0>.

[0016] The memory controller 1 comprises a RAM 11, a processor 12, a host interface 13, an ECC circuit 14, and a memory interface 15. These are connected to each other by an internal bus 16.

[0017] The host interface 13 outputs requests and user data (write data), etc., received from the host to the internal bus 16. The host interface 13 also transmits user data read from the semiconductor memory device 2 and responses from the processor 12, etc., to the host.

[0018] The memory interface 15 controls the process of writing user data, etc., to the semiconductor storage device 2 and the process of reading data from the semiconductor storage device 2, based on instructions from the processor 12.

[0019] The processor 12 comprehensively controls the memory controller 1. The processor 12 is a CPU, MPU, etc. When the processor 12 receives a request from the host via the host interface 13, it performs control according to that request. For example, the processor 12 instructs the memory interface 15 to write user data and parity to the semiconductor storage device 2 according to a request from the host. The processor 12 also instructs the memory interface 15 to read user data and parity from the semiconductor storage device 2 according to a request from the host.

[0020] The processor 12 determines the storage area (memory area) on the semiconductor memory device 2 for the user data stored in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data in page units (page data), which are the writing units. User data stored in one page of the semiconductor memory device 2 will also be referred to as "unit data" below. Unit data is generally encoded and stored in the semiconductor memory device 2 as a codeword. In this embodiment, encoding is not mandatory. The memory controller 1 may store the unit data in the semiconductor memory device 2 without encoding, but Figure 1 shows a configuration in which encoding is performed as an example. If the memory controller 1 does not perform encoding, the page data will match the unit data. Also, one codeword may be generated based on one unit data, or one codeword may be generated based on divided data obtained by dividing the unit data. Furthermore, one codeword may be generated using multiple unit data.

[0021] The processor 12 determines the memory area of ​​the semiconductor storage device 2 to which each unit data should be written. A physical address is assigned to the memory area of ​​the semiconductor storage device 2. The processor 12 manages the memory area to which the unit data should be written using the physical address. The processor 12 instructs the memory interface 15 to write the user data to the semiconductor storage device 2 by specifying the determined memory area (physical address). The processor 12 manages the correspondence between the logical address (logical address managed by the host) and the physical address of the user data. When the processor 12 receives a read request from the host that includes a logical address, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0022] The ECC circuit 14 encodes user data stored in the RAM 11 to generate codewords. The ECC circuit 14 also decodes codewords read from the semiconductor memory device 2.

[0023] The RAM 11 temporarily stores user data received from the host before storing it in the semiconductor memory device 2, and also temporarily stores data read from the semiconductor memory device 2 before sending it to the host. The RAM 11 is a general-purpose memory such as SRAM or DRAM.

[0024] Figure 1 shows an example configuration in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be built into the memory interface 15. Alternatively, the ECC circuit 14 may be built into the semiconductor memory device 2. The specific configuration and arrangement of each element shown in Figure 1 are not particularly limited.

[0025] When a write request is received from the host, the memory system 3 in Figure 1 operates as follows: The processor 12 temporarily stores the data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the semiconductor memory device 2.

[0026] When a read request is received from the host, the memory system 3 in Figure 1 operates as follows: The memory interface 15 inputs the codeword read from the semiconductor memory device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13.

[0027] 1.2 Outline Configuration of Semiconductor Memory Device Next, the outline configuration of the semiconductor memory device 2 will be described.

[0028] As shown in Figure 2, the semiconductor memory device 2 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a sequencer 24, a register 25, a voltage generation circuit 26, a row decoder 27, a sense amplifier 28, a group of input / output pads 30, a group of logic control pads 31, and a group of power input terminals 32.

[0029] The memory cell array 21 is the part that stores data. The memory cell array 21 includes multiple memory cell transistors associated with multiple word lines and multiple bit lines. In the memory cell array 21, both the TLC (triple-level cell) method and the QLC (quad-level cell) method are used as methods for writing data to the memory cell transistors. The TLC method assigns 3 bits of data to one memory cell transistor. The threshold voltage of each memory cell transistor is set to correspond to one of eight threshold voltage distributions, for example, as shown in the middle of Figure 7. The QLC method assigns 4 bits of data to one memory cell transistor. The threshold voltage of each memory cell transistor is set to correspond to one of 16 threshold voltage distributions, for example, as shown in the middle of Figure 13. The QLC method can achieve a higher storage density than the TLC method, but the time required to perform read and write operations is longer.

[0030] For example, as shown in Figure 3(A), in the initial state of the semiconductor memory device 2, where the used area of ​​the memory cell array 21 is small and the unused area is large, the semiconductor memory device 2 operates in TLC mode, and data is written to and read from the memory cell array 21 using the TLC method. As shown in Figure 3(B), when the used area of ​​the memory cell array 21 increases and the unused area decreases, the semiconductor memory device 2 switches to QLC mode, and data is written to and read from the memory cell array 21 using the QLC method. In this case, for example, as shown in Figure 3(C), there is a mixture of areas written using the TLC method (first block group) 211 and areas written using the QLC method (second block group) 212. In the state shown in Figure 3(C), the area 212 written using the QLC method increases as data is written to the memory cell array 21 using the QLC method, while data is read from the area 211 written using the TLC method using the TLC method. By continuing to operate the semiconductor memory device 2 in QLC mode, once data has been written to the entire memory cell array 21 using the QLC method, as shown in Figure 3(D), subsequent data writing and reading to the memory cell array 21 will be performed using the QLC method.

[0031] As shown in Figure 2, the memory cell array 21 has multiple block BLKs, each composed of multiple memory cell transistors. The multiple block BLKs include a first block group 211, a second block group 212, and a ROM block 213. The first block group 211 consists of multiple block BLKs included in the memory cell array 21 on which data has been written using the TLC method. The second block group 212 consists of multiple block BLKs included in the memory cell array 21 on which data has been written using the QLC method. In other words, the memory cell array 21 shown in Figure 2 represents an example of the state shown in Figure 3(C). The ROM block 213 is one of the multiple block BLKs included in the memory cell array 21 and stores data necessary for the operation of the semiconductor memory device 2, such as various operating parameters. The operating parameters stored in the ROM block 213 include mode parameters necessary to operate the semiconductor memory device 2 in accordance with the method of writing data to the memory cell array 21 (e.g., TLC method or QLC method). Mode parameters include, for example, TLC parameters for performing data writing and reading in the TLC method and QLC parameters for performing data writing and reading in the QLC method. In this embodiment, the QLC memory cell transistors included in the second block group 212 are an example of first memory cell transistors, and the TLC memory cell transistors included in the first block group 211 are an example of second memory cell transistors. Multiple ROM blocks 213 may be provided and function as a group of ROM blocks. In this case, for example, one ROM block 213 may be configured to hold information to be read by the power-on read process described later, and the other ROM blocks 213 may be configured to hold mode parameters.

[0032] The input / output circuit 22 transmits and receives the signal DQ<7:0> and the data strobe signals DQS, / DQS to and from the memory controller 1. The input / output circuit 22 also transfers the command and address within the signal DQ<7:0> to the register 25. Furthermore, the input / output circuit 22 transmits and receives write data and read data to and from the sense amplifier 28.

[0033] The logic control circuit 23 receives the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE, RE, and write protect signal / WP from the memory controller 1. The logic control circuit 23 also forwards the ready busy signal R / B to the memory controller 1 to notify the outside of the state of the semiconductor memory device 2.

[0034] Register 25 temporarily holds various types of data. For example, register 25 holds commands that instruct write, read, and erase operations. These commands are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to register 25 for storage. Register 25 also holds the addresses corresponding to the above commands. These addresses are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to register 25 for storage.

[0035] The sequencer 24 controls the operation of each part, including the memory cell array 21, based on control signals input from the memory controller 1 to the input / output circuit 22 and the logic control circuit 23.

[0036] The voltage generation circuit 26 is the part that generates the voltages necessary for the data writing, reading, and erasing operations in the memory cell array 21. These voltages include, for example, the voltages applied to multiple word lines and multiple bit lines of the memory cell array 21. The operation of the voltage generation circuit 26 is controlled by the sequencer 24.

[0037] The row decoder 27 is a circuit composed of a group of switches for applying voltage to multiple word lines of the memory cell array 21. The row decoder 27 receives a block address and a row address from the register 25, selects a block based on the block address, and selects a word line based on the row address. The row decoder 27 switches the open / closed state of the group of switches so that a voltage from the voltage generation circuit 26 is applied to the selected word line. The operation of the row decoder 27 is controlled by the sequencer 24.

[0038] The sense amplifier 28 is a circuit for adjusting the voltage applied to the bit lines of the memory cell array 21 and for reading the voltage from the bit lines and converting it into data. When reading data, the sense amplifier 28 acquires the data read from the memory cell transistors of the memory cell array 21 onto the bit lines and transfers the acquired read data to the input / output circuit 22. When writing data, the sense amplifier 28 transfers the data to be written to the memory cell transistors via the bit lines. The operation of the sense amplifier 28 is controlled by the sequencer 24.

[0039] Both the input / output circuit 22 and the logic control circuit 23 are circuits configured to receive and receive signals from the memory controller 1. In other words, the input / output circuit 22 and the logic control circuit 23 are provided as interface circuits for the semiconductor memory device 2.

[0040] The input / output pad group 30 is a section provided with multiple terminals (pads) for transmitting and receiving signals between the memory controller 1 and the input / output circuit 22. Each terminal is individually provided to correspond to the signal DQ<7:0> and the data strobe signals DQS, / DQS, respectively.

[0041] The logic control pad group 31 is a part provided with a plurality of terminals (pads) for transmitting and receiving each signal between the memory controller 1 and the logic control circuit 23. Each terminal is individually provided corresponding to each of the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, RE, write protect signal / WP, and ready busy signal R / B.

[0042] The power input terminal group 32 is a part provided with a plurality of terminals for receiving the application of each voltage necessary for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltages VCC, VCCQ, VPP, and the ground voltage VSS. The power supply voltage VCC is a circuit power supply voltage externally supplied as an operating power supply, for example, a voltage of about 2.5V. The power supply voltage VCC is a voltage for generating, for example, the voltage VDD which is the internal power supply voltage of the semiconductor memory device 2. The voltage VDD is, for example, a voltage of about 1.5V. The power supply voltage VCCQ is a power supply voltage lower than the power supply voltage VCC, for example, a voltage of 1.2V. The power supply voltage VCCQ is an input / output power supply voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage VCCQ is supplied to at least the driver circuit and the receiver circuit (not shown) of the input / output circuit 22. The power supply voltage VPP is a power supply voltage higher than the power supply voltage VCC, for example, a voltage of 12V.

[0043] 1.3 Circuit Configuration of Memory Cell Array Next, the circuit configuration of the memory cell array 21 will be described.

[0044] As shown in FIG. 4, the memory cell array 21 is composed of a plurality of blocks BLK. In FIG. 4, only one of the plurality of blocks BLK is shown. The configuration of the other blocks BLK that the memory cell array 21 has is also the same as that shown in FIG. 4.

[0045] As shown in FIG. 4, the block BLK includes, for example, four string units SU (SU0 to SU3). Each string unit SU includes a plurality of NAND strings NS. Each NAND string NS includes, for example, eight memory cell transistors MT (MT0 to MT7), and selection transistors ST1 and ST2.

[0046] The memory cell transistors MT are arranged to be connected in series between the selection transistor ST1 and the selection transistor ST2. The memory cell transistor MT7 on one end side is connected to the source of the selection transistor ST1, and the memory cell transistor MT0 on the other end side is connected to the drain of the selection transistor ST2.

[0047] The gates of the selection transistors ST1 of the string units SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. The gates of the selection transistors ST2 are commonly connected to the same select gate line SGS among the plurality of string units SU within the same block BLK. The gates of the memory cell transistors MT0 to MT7 within the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. That is, the word lines WL0 to WL7 and the select gate line SGS are common among the plurality of string units SU0 to SU3 within the same block BLK, whereas the select gate line SGD is provided individually for each of the string units SU0 to SU3 even within the same block BLK.

[0048] The memory cell array 21 is provided with m bit lines BL (BL0, BL1,..., BL(m - 1)). "m" is an integer corresponding to the number of NAND strings NS included in one string unit SU. The drain of each selection transistor ST1 of the NAND string NS is connected to the corresponding bit line BL. The source of each selection transistor ST2 of the NAND string NS is connected to the source line SL. The source line SL is common to the sources of the plurality of selection transistors ST2 included in the block BLK.

[0049] In the following explanation, a "page" refers to a set of 1-bit data stored by multiple memory cell transistors MT connected to a single word line WL and belonging to a single string unit SU. In Figure 4, one of the sets of multiple memory cell transistors MT described above is denoted with the code "MG".

[0050] Data stored in multiple memory cell transistors MT within the same block BLK is erased collectively. On the other hand, data reading and writing are performed collectively on multiple memory cell transistors MT connected to a single word line WL and belonging to a single string unit SU.

[0051] 1.4 Cross-sectional structure of semiconductor memory device Next, the structure of the memory cell array 21 and its surroundings will be described.

[0052] As shown in Figure 5, in the memory cell array 21, multiple NAND strings NS are formed on the conductive layer 320. The conductive layer 320 is also called the embedded source line (BSL) and corresponds to the source line SL shown in Figure 4.

[0053] Above the conductive layer 320, multiple wiring layers 333 functioning as select gate lines (SGS), multiple wiring layers 332 functioning as word lines (WL), and multiple wiring layers 331 functioning as select gate lines (SGD) are stacked. An insulating layer (not shown) is placed between each of the stacked wiring layers 333, 332, and 331.

[0054] Multiple memory holes 334 are formed in the memory cell array 21. The memory holes 334 penetrate vertically through the wiring layers 333, 332, 331 and the insulating layer (not shown) between them, and reach the conductive layer 320. Block insulating film 335, charge storage layer 336, and gate insulating film 337 are sequentially formed on the side surface of the memory hole 334, and a conductive column 338 is embedded further inside. The conductive column 338 is made of polysilicon, for example, and functions as a region where a channel is formed when the memory cell transistor MT and selection transistors ST1, ST2 included in the NAND string NS are in operation. Hereinafter, the columnar body formed by the block insulating film 335, charge storage layer 336, gate insulating film 337, and conductive column 338 inside the memory hole 334 will also be referred to as a memory pillar MP.

[0055] In the memory pillar MP, each portion that intersects with the stacked wiring layers 333, 332, and 331 functions as a transistor. Of these multiple transistors, the portion that intersects with wiring layer 331 functions as a selection transistor ST1. Of these multiple transistors, the portions that intersect with wiring layer 332 function as memory cell transistors MT (MT0 to MT7). Of these multiple transistors, the portion that intersects with wiring layer 333 functions as a selection transistor ST2. With this configuration, the memory pillar MP functions as a NAND string NS as shown in Figure 4. The conductive pillar 338 inside the memory pillar MP is the portion that functions as the channel for the memory cell transistors MT and selection transistors ST1 and ST2.

[0056] Above the conductive column 338, a wiring layer that functions as a bit line BL is formed. At the upper end of the conductive column 338, a contact plug 339 is formed to connect the conductive column 338 and the bit line BL.

[0057] Multiple configurations similar to the one shown in Figure 5 are arranged along the depth direction of the page in Figure 5. A single string unit SU is formed by a collection of multiple NAND strings NS arranged in a line along the depth direction of the page in Figure 5.

[0058] In the semiconductor memory device 2 of this embodiment, a peripheral circuit PER is provided below the memory cell array 21, that is, at a position between the memory cell array 21 and the semiconductor substrate 300. The peripheral circuit PER is a circuit provided to realize data writing, reading, and erasing operations in the memory cell array 21. The sense amplifier 28, row decoder 27, and voltage generation circuit 26 shown in Figure 2 are part of the peripheral circuit PER. The peripheral circuit PER includes various transistors and RC circuits. In the example shown in Figure 5, a transistor TR formed on the semiconductor substrate 300 and a bit line BL located above the memory cell array 21 are electrically connected via a contact 924.

[0059] 1.5 Sense Amplifier Configuration Next, the circuit configuration of the sense amplifier 28 will be explained.

[0060] The sense amplifier 28 includes multiple sense amplifier units, each associated with one of the multiple bit lines BL. Figure 6 shows an extracted circuit configuration of one of these sense amplifier units, SAU.

[0061] As shown in Figure 6, the sense amplifier unit SAU includes a sense amplifier section SA and latch circuits SDL, ADL, BDL, CDL, DDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, DDL, and XDL are connected by a bus LBUS to enable them to send and receive data from each other.

[0062] The sense amplifier unit SA senses the data read to the corresponding bit line BL during a read operation, for example, and determines whether the read data is "0" or "1". The sense amplifier unit SA includes, for example, a p-channel MOS transistor TR1, n-channel MOS transistors TR2 to TR9, and a capacitor C10.

[0063] One end of transistor TR1 is connected to the power line, and the other end of transistor TR1 is connected to transistor TR2. The gate of transistor TR1 is connected to node INV in the latch circuit SDL. One end of transistor TR2 is connected to transistor TR1, and the other end of transistor TR2 is connected to node COM. The signal BLX is input to the gate of transistor TR2. One end of transistor TR3 is connected to node COM, and the other end of transistor TR3 is connected to transistor TR4. The signal BLC is input to the gate of transistor TR3. Transistor TR4 is a high-voltage MOS transistor. One end of transistor TR4 is connected to transistor TR3. The other end of transistor TR4 is connected to the corresponding bit line BL. The signal BLS is input to the gate of transistor TR4.

[0064] One end of transistor TR5 is connected to node COM, and the other end of transistor TR5 is connected to node SRC. The gate of transistor TR5 is connected to node INV. One end of transistor TR6 is connected between transistors TR1 and TR2, and the other end of transistor TR6 is connected to node SEN. The signal HLL is input to the gate of transistor TR6. One end of transistor TR7 is connected to node SEN, and the other end of transistor TR7 is connected to node COM. The signal XXL is input to the gate of transistor TR7.

[0065] One end of transistor TR8 is grounded, and the other end of transistor TR8 is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end of transistor TR9 is connected to bus LBUS. The signal STB is input to the gate of transistor TR9. One end of capacitor C10 is connected to node SEN. The clock CLK is input to the other end of capacitor C10.

[0066] Signals BLX, BLC, BLS, HLL, XXL, and STB are generated, for example, by the sequencer 24. In addition, a voltage VDD, which is the internal power supply voltage of the semiconductor memory device 2, is applied to the power line connected to one end of transistor TR1, and a voltage VSS, which is the ground voltage of the semiconductor memory device 2, is applied to node SRC.

[0067] The latch circuits SDL, ADL, BDL, CDL, DDL, and XDL temporarily hold the read data. Latch circuit XDL is connected to the input / output circuit 22 and is used for data input and output between the sense amplifier unit SAU and the input / output circuit 22. By being held in latch circuit XDL, the read data becomes ready to be output from the input / output circuit 22 to the memory controller 1. For example, data read by the sense amplifier unit SAU is stored in one of the latch circuits ADL, BDL, CDL, or DDL, then transferred to latch circuit XDL, and output from latch circuit XDL to the input / output circuit 22. Also, for example, data input from the memory controller 1 to the input / output circuit 22 is transferred from the input / output circuit 22 to latch circuit XDL, and then transferred from latch circuit XDL to one of the latch circuits ADL, BDL, CDL, or DDL.

[0068] The latch circuit SDL includes, for example, inverters IV11 and IV12 and n-channel MOS transistors TR13 and TR14. The input node of inverter IV11 is connected to node LAT. The output node of inverter IV11 is connected to node INV. The input node of inverter IV12 is connected to node INV. The output node of inverter IV12 is connected to node LAT. One end of transistor TR13 is connected to node INV, and the other end of transistor TR13 is connected to bus LBUS. The signal STI is input to the gate of transistor TR13. One end of transistor TR14 is connected to node LAT, and the other end of transistor TR14 is connected to bus LBUS. The signal STL is input to the gate of transistor TR14. For example, the data held at node LAT corresponds to the data held in the latch circuit SDL. Also, the data held at node INV corresponds to the inverted data of the data held at node LAT. The circuit configurations of latch circuits ADL, BDL, CDL, DDL, and XDL are the same as those of latch circuit SDL, for example, so their explanation will be omitted.

[0069] 1.6 Threshold Voltage Distribution of Memory Cell Transistors in TLC Next, the threshold voltage distribution of the memory cell transistors MT in the first block group 211, where data is written using the TLC method, will be described. Figure 7 is a diagram showing an example of the threshold voltage distribution of the memory cell transistors MT in TLC and the data coding of TLC. The diagram in the middle of Figure 7 shows the correspondence between the threshold voltage of the memory cell transistors MT (horizontal axis) and the number of memory cell transistors MT (vertical axis). The data coding of TLC in this embodiment is called 3-2-2 coding.

[0070] When data is written using the TLC method, multiple memory cell transistors (MTs) form eight threshold voltage distributions, as shown in the middle section of Figure 7. These eight threshold voltage distributions (write levels) are referred to as "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from the lowest threshold voltage.

[0071] The table in the upper part of Figure 7 shows examples of data assigned to each of the threshold voltage levels mentioned above. As shown in the table, different 3-bit data are assigned to the "ER," "A," "B," "C," "D," "E," "F," and "G" levels, for example, as shown below.

[0072] "ER" level: "111" ("lower bit / middle bit / upper bit") "A" level: "110" "B" level: "010" "C" level: "000" "D" level: "100" "E" level: "101" "F" level: "001" "G" level: "011" As described above, the threshold voltage of the memory cell transistor MT in this embodiment can take one of eight preset candidate levels, and data is assigned to each candidate level as shown above.

[0073] Between pairs of adjacent threshold voltage distributions, a verify voltage used in the write operation is set. Specifically, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set corresponding to the "A", "B", "C", "D", "E", "F", and "G" levels, respectively.

[0074] The verify voltage VfyA is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level. When the verify voltage VfyA is applied to the word line WL, memory cell transistors MT connected to the word line WL whose threshold voltage falls within the "ER" level turn ON, and memory cell transistors MT whose threshold voltage falls within the threshold voltage distribution of the "A" level or higher turn OFF. Hereinafter, memory cell transistors MT in the ON state will also be referred to as ON cells, and memory cell transistors MT in the OFF state will also be referred to as OFF cells.

[0075] Other verify voltages VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set in the same way as the verify voltage VfyA described above. The verify voltage VfyB is set between the "A" level and the "B" level, the verify voltage VfyC is set between the "B" level and the "C" level, the verify voltage VfyD is set between the "C" level and the "D" level, the verify voltage VfyE is set between the "D" level and the "E" level, the verify voltage VfyF is set between the "E" level and the "F" level, and the verify voltage VfyG is set between the "F" level and the "G" level.

[0076] Furthermore, a read voltage used in the read operation is set between adjacent threshold distributions. The "read voltage" is the voltage applied to the word line WL connected to the memory cell transistor MT to be read, i.e., the selected word line, during the read operation. In the read operation, the data is determined based on whether or not the threshold voltage of the memory cell transistor MT to be read is higher than the applied read voltage.

[0077] As schematically shown in the lower part of Figure 7, specifically, the read voltage AR used to determine whether the threshold voltage of the memory cell transistor MT falls within the "ER" level or above the "A" level is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level.

[0078] Other read voltages BR, CR, DR, ER, FR, and GR are set in the same way as the read voltage AR described above. Read voltage BR is set between level "A" and level "B", read voltage CR is set between level "B" and level "C", read voltage DR is set between level "C" and level "D", read voltage ER is set between level "D" and level "E", read voltage FR is set between level "E" and level "F", and read voltage GR is set between level "F" and level "G". Read voltages AR, BR, CR, DR, ER, FR, and GR are set as shown in Figure 8, for example.

[0079] The read path voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (e.g., "G" level). When the read path voltage VPASS_READ is applied to the gate of a memory cell transistor MT, it turns ON regardless of the data being stored. The read path voltage VPASS_READ is set to, for example, 5.0V.

[0080] Furthermore, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set to higher voltages than, for example, the read voltages AR, BR, CR, DR, ER, FR, and GR. In other words, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set near the lower tail of the threshold distributions for the "A," "B," "C," "D," "E," "F," and "G" levels, respectively.

[0081] 1.7 Readout Operation of Memory Cell Transistors in TLC Next, the readout operation of the memory cell transistor MT in the first block group 211 of the TLC will be described. Figures 9(A) to (C) show the potential changes of each wiring during the readout operation of the upper page of the memory cell transistor MT in the first block group 211. In the readout operation, the NAND string NS containing the memory cell transistor MT to be read out is selected. Alternatively, the string unit SU containing the page to be read out is selected.

[0082] First, as shown in Figure 9(A), a voltage of, for example, 5V is applied to the select gate line SGDsel, the non-select select gate line SGDusel, and the select gate line SGS from the voltage generation circuit 26 via the row decoder 27. This turns on the select transistors ST1 and ST2 included in the select block BLK. Also, as shown in Figure 9(B), a read path voltage VPASS_READ is applied to the word line WL (select word line WLsel) connected to the memory cell transistor MT that is the target of the read operation, and to the other word lines (non-select word line WLusel) from the voltage generation circuit 26 via the row decoder 27. The read path voltage VPASS_READ is a voltage that can turn on the memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT, and does not change the threshold voltage. As a result, current conducts in all NAND strings NS included in the select block BLK, regardless of whether they are select string units SU or non-select string units SU.

[0083] Next, as shown in Figure 9(B), a read voltage ER is applied to the selected word line WLsel from the voltage generation circuit 26 via the row decoder 27 for a predetermined time, and then a read voltage AR is applied for a predetermined time. In addition, a read path voltage VPASS_READ is applied to the non-selected word line WLusel.

[0084] Furthermore, as shown in Figure 9(A), while the voltages applied to the select gate line SGDsel and the select gate line SGS are maintained, a voltage VSS is applied to the non-selected select gate line SGDusel from the voltage generation circuit 26 via the raw decoder 27. As a result, the select transistor ST1 included in the select string unit SU remains ON, while the select transistor ST1 included in the non-selected string unit SU is OFF. Regardless of whether it is a select string unit SU or a non-selected string unit SU, the select transistor ST2 included in the select block BLK remains ON.

[0085] As a result, in the NAND string NS included in the non-selected string unit SU, at least the selection transistor ST1 is in the off state, and therefore no current path is formed. On the other hand, in the NAND string NS included in the selected string unit SU, a current path is formed or not formed depending on the relationship between the read voltages ER and AR applied to the selected word line WLsel and the threshold voltage of the memory cell transistor MT.

[0086] The sense amplifier 28 applies a predetermined voltage (e.g., 0.7V) to the bit line BL connected to the selected NAND string NS. In this state, the sense amplifier 28 reads data based on the value of the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT that is the target of the read operation is higher than the read voltage applied to the memory cell transistor MT. Alternatively, data reading may be performed based on the time change of the potential in the bit line BL, rather than based on the value of the current flowing through the bit line BL. In the latter case, the bit line BL is pre-charged to a predetermined potential.

[0087] As shown in Figure 9(B), during the period in which the voltage applied to the selection word line WLsel changes, the sequencer 24 inputs a control signal STB to the sense amplifier unit SAU, as shown in Figure 9(C). The control signal STB is a control signal that causes the sense amplifier unit SAU to read data based on the value of the current flowing through the bit line BL corresponding to it. That is, when the control signal STB is raised at times t10 and t11, respectively, data corresponding to the determination result of whether the threshold voltage of the memory cell transistor MT is higher than the read voltages ER and AR is latched to one of the latch circuits ADL, BDL, CDL, or DDL of the sense amplifier unit SAU.

[0088] For example, if the threshold voltage of the memory cell transistor MT is within the "F" level shown in Figure 7, the sense amplifier unit SAU operates as shown by the dashed line in Figure 10.

[0089] Specifically, when the control signal STB is activated at time t10 shown in Figure 9(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage ER. If the threshold voltage of the memory cell transistor MT is within the "F" level, the threshold voltage of the memory cell transistor MT is higher than the read voltage ER, and as shown in the "ER Sense" section of Figure 10, the sense amplifier unit SAU determines that the memory cell transistor MT is an off-cell and senses the data "1". At this time, for example, as shown in the "First Latch Operation" section of Figure 10, the latch circuit ADL stores the bit-inverted value of the sensed "1" data, i.e., the data "0".

[0090] Next, when the control signal STB is activated at time t11 shown in Figure 9(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage AR. If the threshold voltage of the memory cell transistor MT is within the "F" level, the threshold voltage of the memory cell transistor MT is higher than the read voltage AR, and as shown in the "AR Sense" section of Figure 10, the sense amplifier unit SAU determines that the memory cell transistor MT is an off-cell and senses the data "1". At this time, for example, as shown in the "Second Latch Operation" section of Figure 10, the latch circuit ADL stores the value of the negative logical AND (NAND) of the sensed "1" data and the already stored "0" data, i.e., the data "1".

[0091] When the threshold voltage of the memory cell transistor MT is included in the "F" level, the sense amplifier unit SAU reads out the data "1" as the data stored in the memory cell transistor MT during the read operation of the upper page, as shown in Figure 7. When the threshold voltage of the memory cell transistor MT is included in the "Er", "A", "B", "C", "D", "E", and "G" levels, the sense amplifier unit SAU senses the data, and the latch circuit ADL stores the calculated data, as shown in Figure 10. Hereafter, "storage of calculated data in the latch circuit ADL" will also be referred to as "latch operation".

[0092] Figures 11(A) to (C) show the potential changes of each wiring during the read operation of the middle page of the TLC memory cell transistor MT. During the read operation of the middle page, as shown in Figure 11(B), the read voltage GR and read voltage CR are sequentially applied to the selected word line WLsel from the voltage generation circuit 26 via the row decoder 27.

[0093] Figures 12(A) to (C) show the potential changes of each wiring during the read operation of the lower pages of the TLC memory cell transistor MT. During the read operation of the lower pages, as shown in Figure 12(B), the read voltage FR, read voltage DR, and read voltage BR are sequentially applied to the selected word line WLsel from the voltage generation circuit 26 via the row decoder 27.

[0094] The operation of the sense amplifier unit SAU during the read operation of the middle and lower pages of the TLC memory cell transistor MT will be omitted.

[0095] 1.8 Threshold Voltage Distribution of QLC Memory Cell Transistors Next, the threshold voltage distribution of the memory cell transistors MT in the second block group 212, where data is written using the QLC method, will be described. Figure 13 is a diagram showing an example of the threshold voltage distribution of the QLC memory cell transistors MT and the QLC data coding. The diagram in the middle of Figure 13 shows the correspondence between the threshold voltage of the memory cell transistors MT (horizontal axis) and the number of memory cell transistors MT (vertical axis). Note that the verification voltage used in the writing operation is not shown in Figure 13. The QLC data coding in this embodiment is called 3-4-4-4 coding.

[0096] When data is written using the QLC method, multiple memory cell transistors (MTs) form 16 threshold voltage distributions, as shown in the middle section of Figure 13. These 16 threshold voltage distributions (write levels) are referred to as "S0" level, "S1" level, "S2" level, "S3" level, "S4" level, "S5" level, "S6" level, "S7" level, "S8" level, "S9" level, "S10" level, "S11" level, "S12" level, "S13" level, "S14" level, and "S15" level, in order from lowest to highest threshold voltage.

[0097] The table in the upper part of Figure 13 shows examples of data assigned to each of the threshold voltage levels mentioned above. As shown in the table, each level is assigned different 4-bit data, such as shown below.

[0098] "S0" level: "1111" ("Lower bit / Middle bit / Upper bit / Most significant bit") "S1" level: "1110" "S2" level: "1100" "S3" level: "1101" "S4" level: "1001" "S5" level: "0001" "S6" level: "0101" "S7" level: "0100" "S8" level: "0110" "S9" level: "0010" "S10" level: "0000" "S11" level: "1000" "S12" level: "1010" "S13" level: "1011" "S14" level: "0011" "S15" level: "0111" Thus, the threshold voltage of the QLC memory cell transistor MT in this embodiment can take one of 16 preset candidate levels, and data is assigned to each candidate level as described above.

[0099] Between adjacent threshold distributions, a read voltage used in the read operation is set. Specifically, as schematically shown in the lower part of Figure 13, the read voltage S1R, which determines whether the threshold voltage of the memory cell transistor MT is included in the "S0" level or in the "S1" level or higher, is set between the maximum threshold voltage in the "S0" level and the minimum threshold voltage in the "S1" level.

[0100] Other read voltages S2R, S3R, S4R, S5R, S6R, S7R, S8R, S9R, S10R, S11R, S12R, S13R, S14R, and S15R are set in the same way as the read voltage S1R mentioned above. Read voltages S1R, S2R, S3R, S4R, S5R, S6R, S7R, S8R, S9R, S10R, S11R, S12R, S13R, S14R, and S15R are set as shown in Figure 14, for example. The read path voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (e.g., the "S15" level). The read path voltage VPASS_READ is set to 5.0V, for example.

[0101] 1.9 Readout Operation of QLC Memory Cell Transistors Next, the readout operation of the memory cell transistor MT in the second block group 212 of the QLC will be described. Figures 15(A) to (C) show the potential change of each wiring during the readout operation of the top page of the memory cell transistor MT in the second block group 212. In the readout operation, the NAND string NS containing the memory cell transistor MT to be read out is selected. Alternatively, the string unit SU containing the page to be read out is selected.

[0102] First, as shown in Figure 15(A), the same or similar voltages as in Figure 9(A) are applied to the selected gate line SGDsel, the non-selected gate line SGDusel, and the selected gate line SGS. Also, as shown in Figure 15(B), the same or similar voltages as in Figure 9(B) are applied to the non-selected word line WLusel.

[0103] As shown in Figure 15(B), the read path voltage VPASS_READ is applied to the selected word line WLsel, and then the read voltages S13R, S7R, S3R, and S1R are applied sequentially for predetermined periods of time.

[0104] As shown in Figure 15(B), during the period in which the voltage applied to the selected word line WLsel changes, the sequencer 24 inputs a control signal STB to the sense amplifier unit SAU, as shown in Figure 15(C). That is, when the control signal STB is raised at times t20, t21, t22, and t23, data corresponding to the determination result of whether the threshold voltage of the memory cell transistor MT is higher than the readout voltages S13R, S7R, S3R, and S1R is latched to one of the latch circuits ADL, BDL, CDL, or DDL of the sense amplifier unit SAU.

[0105] For example, if the threshold voltage of the memory cell transistor MT is within the “S1” level shown in Figure 13, the sense amplifier unit operates as shown by the dashed line in Figure 16.

[0106] Specifically, when the control signal STB is activated at time t20 as shown in Figure 15(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage S13R. If the threshold voltage of the memory cell transistor MT is included in the "S1" level, the threshold voltage of the memory cell transistor MT is lower than the read voltage S13R, so as shown in the "S13R Sense" section of Figure 16, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example as shown in the "First Latch Operation" section of Figure 16, the latch circuit ADL stores the bit-inverted value of the sensed "0" data, i.e., the data "1".

[0107] Next, when the control signal STB is activated at time t21 shown in Figure 15(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage S7R. If the threshold voltage of the memory cell transistor MT is included in the "S1" level, the threshold voltage of the memory cell transistor MT is lower than the read voltage S7R, and as shown in the "S7R Sense" section of Figure 16, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example, as shown in the "Second Latch Calculation" section of Figure 16, the latch circuit ADL stores the value obtained by taking the NAND of the sensed "0" data and the already stored "1" data, i.e., the data "1".

[0108] Next, when the control signal STB is activated at time t22 as shown in Figure 15(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage S3R. If the threshold voltage of the memory cell transistor MT is included in the "S1" level, the threshold voltage of the memory cell transistor MT is lower than the read voltage S3R, and as shown in the "S3R Sense" section of Figure 16, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example, as shown in the "Third Latch Operation" section of Figure 16, the latch circuit ADL stores the value obtained by taking the NAND of the sensed "0" data and the already stored "1" data, i.e., the data "1".

[0109] Next, when the control signal STB is activated at time t23 as shown in Figure 15(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage S1R. If the threshold voltage of the memory cell transistor MT is included in the "S1" level, the threshold voltage of the memory cell transistor MT is higher than the read voltage S1R, and as shown in the "S1R Sense" section of Figure 16, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "1". At this time, for example, as shown in the "Fourth Latch Operation" section of Figure 16, the latch circuit ADL stores the value obtained by taking the NAND of the sensed "1" data and the already stored "1" data, i.e., the data "0".

[0110] When the threshold voltage of the memory cell transistor MT is included in the "S1" level, the sense amplifier unit SAU reads out the data "0" as the data stored in the memory cell transistor MT during the read operation of the top page, as shown in Figure 13. When the threshold voltage of the memory cell transistor MT is included in the "S0", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "S12", "S13", "S14", and "S15" levels, the sense amplifier unit SAU performs data sensing and latching operations, similarly as shown in Figure 16.

[0111] Figures 17(A) to (C) show the potential changes of each wiring during the read operation of the upper page of the QLC memory cell transistor MT. During the read operation of the upper page, as shown in Figure 17(B), the read voltages S12R, S10R, S8R, and S2R are applied sequentially to the selected word line WLsel from the voltage generation circuit 26 via the row decoder 27 for a predetermined time.

[0112] Figures 18(A) to (C) show the potential changes of each wiring during the read operation of the middle page of the QLC memory cell transistor MT. During the read operation of the middle page, as shown in Figure 18(B), the read voltages S15R, S9R, S6R, and S4R are applied sequentially to the selected word line WLsel from the voltage generation circuit 26 via the row decoder 27 for a predetermined time.

[0113] Figures 19(A) to (C) show the potential changes of each wiring during the read operation of the lower pages of the QLC memory cell transistor MT. During the read operation of the lower pages, as shown in Figure 19(B), the read voltage S14R, read voltage S11R, and read voltage S5R are applied sequentially for a predetermined time from the voltage generation circuit 26 to the selected word line WLsel via the row decoder 27.

[0114] The operation of the sense amplifier unit SAU during the read operation of the upper, middle, and lower pages of the QLC memory cell transistor MT will be omitted.

[0115] 1.10 Signal Exchange During Read Operation Next, we will explain the specific signals exchanged between the semiconductor memory device 2 and the memory controller 1 during read operation.

[0116] As shown in Figure 20, during a read operation, the memory controller 1 first switches the chip enable signal / CE corresponding to the semiconductor memory device 2 from the "H" level to the "L" level at time t30, causing the semiconductor memory device 2 to transition to the enabled state. As a result, the semiconductor memory device 2 becomes capable of receiving signals from the memory controller 1.

[0117] Next, the memory controller 1 sequentially inputs a signal DQ<7:0> to the semiconductor memory device 2, consisting of "00h", multiple "ADD" signals, and "30h". "00h" is a command to execute a data read operation from the memory cell array 21. "ADD" is a signal that specifies the address from which the data will be read. "30h" is a command to start the read operation. In Figure 20, the time at which the memory controller 1 begins inputting the signal DQ<7:0> to the semiconductor memory device 2 is shown as t31.

[0118] From time t31 onward, the memory controller 1 begins to toggle the write enable signal / WE. As mentioned earlier, the write enable signal / WE is a signal used to capture signals from the memory controller 1 to the semiconductor memory device 2. The write enable signal / WE is switched alternately (toggled) between the "H" level and the "L" level. The write enable signal / WE, which is switched in this manner, is used as an "acquisition signal" for capturing data.

[0119] When the memory controller 1 receives "00h" and "30h" from the signal DQ<7:0>, it switches the command latch enable signal CLE from the "L" level to the "H" level, thereby taking "00h" and "30h" as commands into the semiconductor memory device 2. Also, when the memory controller 1 receives multiple "ADD" from the signal DQ<7:0>, it switches the address latch enable signal ALE from the "L" level to the "H" level, thereby taking multiple "ADD" as address information of the data source into the semiconductor memory device 2. The address information taken into the semiconductor memory device 2 is stored in register 25. The address information includes block addresses and row addresses.

[0120] In Figure 20, the time at which "30h" is entered into the semiconductor memory device 2 is shown as t32. After time t32, the semiconductor memory device 2 begins internal operation. Specifically, the sequencer 24 operates the row decoder 27 based on the address information of the data source stored in the register 25. The row decoder 27 receives the address information from the register 25 and selects a block in the memory cell array 21 based on the block address included in the address information, and also selects a word line WL based on the row address included in the address information. The row decoder 27 then switches the open / closed state of the switch group so that a voltage from the voltage generation circuit 26 is applied to the selected word line WL. This completes the preparation for reading data from the memory cell array 21. Subsequently, the sense amplifier 28 acquires the data read from the memory cell transistor MT of the memory cell array 21 to the bit line BL, and transfers the acquired read data to the input / output circuit 22. With the above, the preparation for reading data from the semiconductor memory device 2 is complete. In Figure 20, the time reserved for this internal operation of the semiconductor memory device 2 is shown as tR. In other words, at time t33, after a predetermined time tR has elapsed from time t32, preparations for reading data from the semiconductor memory device 2 are complete. The predetermined time tR is, for example, 50 μsec to 100 μsec.

[0121] From time t33 onward, the memory controller 1 alternately switches the read enable signal / RE between the "H" level and the "L" level, and the semiconductor memory device 2 switches the data strobe signal DQS between the "H" level and the "L" level, causing the semiconductor memory device 2 to output data as signal DQ<7:0> to the memory controller 1. In this way, the memory controller 1 reads data from the semiconductor memory device 2.

[0122] 1.11 As shown in the sequencer configuration diagram 21, the sequencer 24 includes a parameter register 240, a control unit 241, and a feature register 242. The parameter register 240, control unit 241, and feature register 242 included in the sequencer 24 are implemented by hardware such as electronic circuits.

[0123] The parameter register 240 holds information read from the ROM block 213 of the memory cell array 21, for example, by a power-on read operation. Specifically, when a power supply voltage is applied to the memory system 3, the processor 12 of the memory controller 1 shown in Figure 1 instructs the semiconductor storage device 2 to execute a power-on read operation via the memory interface 15. As a result, the semiconductor storage device 2 reads data including the operating mode from the ROM block 213 of the memory cell array 21, and this data is stored in the parameter register 240 of the sequencer 24. In this embodiment, the parameter register 240 stores either the TLC mode parameter P10 or the QLC mode parameter P20 as the operating mode.

[0124] When the TLC mode parameter P10 is stored in the parameter register 240, the semiconductor memory device 2 operates in TLC mode. In this case, for example, data writing and reading operations to the memory cell transistors MT of the first block group 211 of the memory cell array 21 can be performed in TLC mode.

[0125] When the QLC mode parameter P20 is stored in the parameter register 240, the semiconductor memory device 2 operates in QLC mode. In this case, for example, data writing and reading operations to the memory cell transistors MT of the second block group 212 of the memory cell array 21 can be performed in the QLC manner.

[0126] The TLC mode parameter P10 includes, for example, waveform information of the voltage applied to the selection word line WLsel during readout, and the calculation method for latching data in the latch circuits ADL, BDL, CDL, and DDL of the sense amplifier unit SAU during readout. The waveform information of the voltage applied to the selection word line WLsel includes voltage waveform information corresponding to the upper page, middle page, and lower page, as shown in Figures 9, 11, and 12, for example, information on the number of times the voltage is applied to the selection word line WLsel. For example, the number of times the voltage is applied to the selection word line WLsel of the upper page is set to 2. The calculation method for the latch circuits ADL, BDL, CDL, and DDL in the sense amplifier unit SAU during readout is, for example, as shown in Figure 10, to bit-invert the data first sensed by the sense amplifier unit SAU, and then to perform a NAND with the data already stored for the data sensed thereafter.

[0127] Similarly, the QLC mode parameter P20 also includes information such as the voltage waveform of the selected word line WLsel during readout, and the calculation method used when latching data to the latch circuits ADL, BDL, CDL, and DDL of the sense amplifier unit SAU during readout.

[0128] The control unit 241 controls the voltage generation circuit 26, the row decoder 27, and the sense amplifier 28 according to the mode parameter (TLC mode parameter P10 or QLC mode parameter P20) stored in the parameter register 240, for example, during write and read operations. For example, when the memory controller 1 inputs a parameter switching command to the semiconductor storage device 2 along with an address indicating an area in the ROM block 213 where the TLC mode parameter P10 is stored, the semiconductor storage device 2 reads the TLC mode parameter P10 from the ROM block 213 of the memory cell array 21 and stores it in the parameter register 240 of the sequencer 24. Similarly, when the memory controller 1 inputs a parameter switching command to the semiconductor storage device 2 along with an address indicating an area in the ROM block 213 where the QLC mode parameter P20 is stored, the semiconductor storage device 2 reads the QLC mode parameter P20 from the ROM block 213 of the memory cell array 21 and stores it in the parameter register 240 of the sequencer 24.

[0129] For example, as shown in Figures 3(A) and (B), if the memory cell array 21 contains only TLC memory cell transistors MT, the parameter register 240 stores the TLC mode parameter P10, and the control unit 241 operates in TLC mode.

[0130] For example, as shown in Figure 3(D), if the memory cell array 21 contains only QLC memory cell transistors MT, the parameter register 240 stores the QLC mode parameter P20, and the control unit 241 operates in QLC mode.

[0131] Incidentally, as shown in Figure 3(C), when the operating mode of the semiconductor memory device 2 transitions from TLC mode to QLC mode, as shown in Figure 2, a first block group 211 including TLC memory cell transistors MT and a second block group 212 including QLC memory cell transistors MT are mixed together. In the state shown in Figure 3(C), the control unit 241 basically operates in QLC mode in order to write to the memory cell transistors MT included in the second block group 212 using the QLC method. However, for example, if the host requests to read data from the memory cell transistors MT included in the first block group 211, the control unit 241 needs to read the data from the memory cell transistors MT of the first block group 211 using the TLC method. Furthermore, in garbage collection, even when data is read from the memory cell transistors MT included in the first block group 211, which have been written using the TLC method, and written to the memory cell transistors MT included in the second block group 212 using the QLC method, the control unit 241 also needs to read the data from the memory cell transistors MT in the first block group 211 using the TLC method. Thus, in the semiconductor memory device 2, there is a need to read data from the memory cell transistors MT included in the first block group 211, which have been written using the TLC method, while operating in QLC mode.

[0132] One possible solution to this requirement is to change the operating mode of the control unit 241 from QLC mode to TLC mode by sending a parameter switching command from the memory controller 1 to the semiconductor memory device 2. However, in this case, the semiconductor memory device 2 needs to read the TLC mode parameter P10 from the ROM block 213 of the memory cell array 21 and store it in the parameter register 240 of the sequencer 24. In particular, the operation of the semiconductor memory device 2 to read the TLC mode parameter P10 from the ROM block 213 of the memory cell array 21 involves internal operations such as applying voltage to word lines and bit lines. These internal operations to read data from the memory cell array 21 require, for example, several tens of microseconds. Therefore, switching the operating mode using a parameter switching command may become cumbersome.

[0133] Alternatively, the capacity of the parameter register 240 could be expanded to store both the TLC mode parameter P10 and the QLC mode parameter P20. In this case, the control unit 241 can access both the TLC mode parameter P10 and the QLC mode parameter P20 without reading data from the ROM block 213 of the memory cell array 21. However, in this case, the area required to configure the parameter register 240 would increase.

[0134] Here, the memory controller 1 may instruct the semiconductor storage device 2 to perform a normal read operation (see, for example, Figure 30) or a shift read operation (see, for example, Figure 31A). When the memory controller 1 instructs the semiconductor storage device 2 to perform a shift read operation, the voltage applied to the word line to read the data is shifted by the instructed voltage shift amount compared to the case of a normal read operation. More specifically, when a shift read operation is instructed, the control unit 241 refers to the voltage shift amount data stored in the feature register 242 and performs the read operation while controlling, for example, the voltage generation circuit 26 so that the voltage applied to the word line is shifted.

[0135] In the semiconductor memory device 2 of this embodiment, when the control unit 241 is operated in QLC mode by storing the QLC mode parameter P20 in the parameter register 240, it is possible to read data in the TLC method without reading the TLC mode parameter P10 from the ROM block 213 and storing it in the parameter register 240. Specifically, by using the waveform of the read voltage applied to the selection word line WLsel shown in Figures 15(B), 18(B), and 19(B) used in QLC mode as a reference, and using the waveform of the voltage obtained by shifting the value of the read voltage at each level as the waveform of the read voltage of the TLC memory cell transistor MT, it is possible to read data in the TLC method in QLC mode. In other words, in the semiconductor memory device 2 of this embodiment, the shift read operation is reused for switching the operating mode. By using this method, it is possible to simulate a TLC-style data read operation by setting appropriate voltage shift amount data in the feature register 242 and then performing a shift read operation, thereby maintaining the state in which the QLC mode parameter P20 is stored in the parameter register 240.

[0136] 1.12 Data Readout Operation of TLC in QLC Mode Next, the data readout operation of TLC in QLC mode will be described. Figure 22 shows the voltage shift amount value stored in the feature register 242 as one of the QLC mode parameters for performing data readout operation on TLC.

[0137] When performing a TLC method data readout operation under QLC mode, the waveform of the readout voltage of the upper page in QLC mode is not used. Therefore, as shown in Figure 22, voltage shift amounts ΔVr1, ΔVr3, ΔVr4, ΔVr5, ΔVr6, ΔVr7, ΔVr9, ΔVr11, ΔVr13, ΔVr14, and ΔVr15 are set for the readout voltages S1R, S3R, S4R, S5R, S6R, S7R, S9R, S11R, S13R, S14R, and S15R of the other pages, respectively. These voltage shift amounts are set to the values ​​shown in Figure 22, for example.

[0138] Figure 23 shows the relationship between the read voltage after adjusting the read voltage by the voltage shift amount and the corresponding TLC read voltage. As shown in Figure 23, the adjusted read voltage "S1R + ΔVr1" is used as read voltage AR, the adjusted read voltage "S5R + ΔVr5" is used as read voltage BR, the adjusted read voltage "S9R + ΔVr9" is used as read voltage CR, the adjusted read voltage "S11R + ΔVr11" is used as read voltage DR, the adjusted read voltage "S13R + ΔVr13" is used as read voltage ER, the adjusted read voltage "S14R + ΔVr14" is used as read voltage FR, and the adjusted read voltage "S15R + ΔVr15" is used as read voltage GR.

[0139] The other adjusted read voltages "S3R+ΔVr3", "S4R+ΔVr4", "S6R+ΔVr6", and "S7R+ΔVr7" are not necessary for reading TLC data, but are voltages that are consequently applied to the selected word line WLsel by using the waveform of the QLC mode read voltage. In this embodiment, the adjusted read voltages "S3R+ΔVr3", "S4R+ΔVr4", "S6R+ΔVr6", and "S7R+ΔVr7" are set so that when the sense amplifier 28 senses the data stored in the memory cell transistor MT using these read voltages, the sensed data does not affect the TLC data read result.

[0140] Figure 24 shows the change in potential applied to each wire when performing a read operation on the upper pages of a TLC using the adjusted read voltage of the top page shown in Figure 23.

[0141] As shown in Figure 24(A), the same or similar voltages as in Figure 15(A) are applied to the selected gate line SGDsel, the non-selected gate line SGDusel, and the selected gate line SGS. Also, as shown in Figure 24(B), the same or similar voltages as in Figure 15(B) are applied to the non-selected word line WLusel.

[0142] As shown in Figure 24(B), the read path voltage VPASS_READ is applied to the selected word line WLsel, and then the adjusted read voltages "S13R+ΔVr13", "S7R+ΔVr7", "S3R+ΔVr3", and "S1R+ΔVr1" are applied sequentially for a predetermined time. The read voltage "S13R+ΔVr13" is the voltage corresponding to the TLC read voltage ER. The read voltage "S7R+ΔVr7" is lower than the read voltage "S13R+ΔVr13" and lower than the read voltage "S3R+ΔVr3". The read voltage "S3R+ΔVr3" is lower than the read voltage "S13R+ΔVr13" and higher than the read voltage "S7R+ΔVr7". The read voltage "S1R+ΔVr1" is the voltage corresponding to the TLC read voltage AR. Figure 24(B) shows the waveform of the voltage applied to the selected word line WLsel before adjustment, indicated by a dashed line. The following figures also show the waveform of the voltage before adjustment using a dashed line.

[0143] As shown in Figure 24(B), during the period in which the voltage applied to the selected word line WLsel changes, the sequencer 24 inputs a control signal STB to the sense amplifier unit SAU, as shown in Figure 24(C). That is, when the control signal STB is raised at times t20, t21, t22, and t23, data corresponding to the determination result of whether the threshold voltage of the memory cell transistor MT is higher than the adjusted readout voltages "S13R + ΔVr13", "S7R + ΔVr7", "S3R + ΔVr3", and "S1R + ΔVr1" is stored in one of the latch circuits ADL, BDL, CDL, or DDL of the sense amplifier unit SAU.

[0144] Next, we will explain an example of how the sense amplifier unit (SAU) operates when reading higher-level data from the TLC memory cell transistor (MT).

[0145] First, we will explain the case where the threshold voltage of the TLC memory cell transistor MT is set to one of the "E" level, "F" level, or "G" level shown in Figure 25.

[0146] In this case, as shown in Figure 24(C), when the control signal STB is activated at time t20, it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S13R + ΔVr13". The threshold voltage of the memory cell transistor MT is determined to be higher than the read voltage "S13R + ΔVr13". Therefore, as shown in the "S13R + ΔVr13 Sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is an off-cell and senses the data "1". At this time, for example, as shown in the "First Latch Operation" section of Figure 25, the latch circuit ADL stores the bit-inverted value of the sensed "1" data, i.e., the data "0".

[0147] Next, when the control signal STB is activated at time t21 shown in Figure 24(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7". It is determined that the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7". Therefore, as shown in the "S7R + ΔVr7 Sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is an off-cell and senses the data "1". At this time, for example, as shown in the "Second Latch Operation" section of Figure 25, the latch circuit ADL stores the value obtained by taking the NAND of the sensed "1" data and the already stored "0" data, i.e., the data "1".

[0148] Subsequently, when the control signal STB is raised at times t22 and t23 as shown in Figure 24(C), the sense amplifier unit SAU similarly determines that the memory cell transistor MT is an off-cell and senses the data "1", as shown in the respective items "S3R + ΔVr3 sense" and "S1R + ΔVr1 sense" in Figure 25. Then, as shown in the respective items "Third latch operation" and "Fourth latch operation" in Figure 25, the latch circuit ADL stores the NAND value obtained by taking the data sensed by the sense amplifier unit SAU and the data already stored. As a result, the latch circuit ADL stores the data "1". In other words, the data "1" is read out as the data stored in the memory cell transistor MT.

[0149] Next, we will explain the case where the threshold voltage of the TLC memory cell transistor MT is set to the "Er" level shown in Figure 25.

[0150] In this case, as shown in Figure 24(C), when the control signal STB is raised at time t20, it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S13R + ΔVr13". If the threshold voltage of the memory cell transistor MT is determined to be lower than the read voltage "S13R + ΔVr13", then, as shown in the "S13R + ΔVr13 sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example, as shown in the "First latch operation" section of Figure 25, the latch circuit ADL stores the bit-inverted value of the sensed "0" data, i.e., the data "1".

[0151] Next, when the control signal STB is activated at time t21 shown in Figure 24(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7". If it is determined that the threshold voltage of the memory cell transistor MT is lower than the read voltage "S7R + ΔVr7", then, as shown in the "S7R + ΔVr7 sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example, as shown in the "Second latch operation" section of Figure 25, the latch circuit ADL stores the value obtained by taking the NAND of the sensed "0" data and the already stored "1" data, i.e., the data "1".

[0152] Subsequently, when the read voltages "S3R + ΔVr3" and "S1R + ΔVr1" are used at times t22 and t23 as shown in Figure 24(C), the sense amplifier unit SAU similarly determines that the memory cell transistor MT is on-cell and senses the data "0", as shown in the respective items for "S3R + ΔVr3 sense" and "S1R + ΔVr1 sense" in Figure 25. Then, as shown in the respective items for "Third latch operation" and "Fourth latch operation" in Figure 25, the latch circuit ADL stores the NAND value obtained by taking the data sensed by the sense amplifier unit SAU and the data already stored. As a result, the latch circuit ADL stores the data "1". In other words, the data "1" is read out as the data stored in the memory cell transistor MT.

[0153] Next, we will explain the case where the threshold voltage of the TLC memory cell transistor MT is set to one of the levels "A", "B", "C", and "D" shown in Figure 25.

[0154] First, if the threshold voltage of the TLC memory cell transistor MT is greater than or equal to the read voltage "S3R + ΔVr3" and less than the read voltage "S13R + ΔVr13", the sense amplifier unit SAU operates as follows.

[0155] In this case, as shown in Figure 24(C), when the control signal STB is raised at time t20, it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S13R + ΔVr13". If the threshold voltage of the memory cell transistor MT is determined to be lower than the read voltage "S13R + ΔVr13", then, as shown in the "S13R + ΔVr13 sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example, as shown in the "First latch operation" section of Figure 25, the latch circuit ADL stores the bit-inverted value of the sensed "0" data, i.e., the data "1".

[0156] Next, when the control signal STB is activated at time t21 as shown in Figure 24(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7". It is determined that the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7". Therefore, as shown in the "S7R + ΔVr7 Sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is an off-cell and senses the data "1". At this time, for example, as shown in the "Second Latch Operation" section of Figure 25, the latch circuit ADL stores the NAND value of the sensed "1" data and the already stored "1" data, i.e., the data "0".

[0157] Subsequently, when the read voltages "S3R + ΔVr3" and "S1R + ΔVr1" are used at times t22 and t23 as shown in Figure 24(C), the sense amplifier unit SAU similarly determines that the memory cell transistor MT is an off-cell and senses the data "1", as shown in the respective items for "S3R + ΔVr3 sense" and "S1R + ΔVr1 sense" in Figure 25. Then, as shown in the respective items for "Third latch operation" and "Fourth latch operation" in Figure 25, the latch circuit ADL stores the NAND value obtained by taking the data sensed by the sense amplifier unit SAU and the data already stored. As a result, the latch circuit ADL stores the data "0". In other words, the data "0" is read out as the data stored in the memory cell transistor MT.

[0158] Next, we will describe an example of the operation of the sense amplifier unit SAU when the threshold voltage of the TLC memory cell transistor MT is less than the read voltage "S7R + ΔVr7" and greater than or equal to the read voltage "S1R + ΔVr1".

[0159] In this case, as shown in Figure 24(C), when the control signal STB is raised at time t20, it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S13R + ΔVr13". If the threshold voltage of the memory cell transistor MT is determined to be lower than the read voltage "S13R + ΔVr13", then, as shown in the "S13R + ΔVr13 sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example, as shown in the "First latch operation" section of Figure 25, the latch circuit ADL stores the bit-inverted value of the sensed "0" data, i.e., the data "1".

[0160] Next, when the read voltages "S7R + ΔVr7" and "S3R + ΔVr3" are used at times t21 and t22 shown in Figure 24(C), the sense amplifier unit SAU similarly determines that the memory cell transistor MT is on-cell and senses the data "0", as shown in the respective items "S7R + ΔVr7 sense" and "S3R + ΔVr3 sense" in Figure 25. Then, as shown in the respective items "second latch operation" and "third latch operation" in Figure 25, the latch circuit ADL stores the NAND value obtained by taking the data sensed by the sense amplifier unit SAU and the data already stored. Therefore, the latch circuit ADL stores the data "1" as the result of the "third latch operation".

[0161] Next, when the control signal STB is activated at time t23 as shown in Figure 24(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S1R + ΔVr1". It is determined that the threshold voltage of the memory cell transistor MT is higher than the read voltage "S1R + ΔVr1". Therefore, as shown in the "S1R + ΔVr1 Sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is an off-cell and senses the data "1". At this time, for example, as shown in the "Fourth Latch Operation" section of Figure 25, the latch circuit ADL stores the NAND value of the sensed "1" data and the already stored "1" data, i.e., the data "0". As a result, the data "0" is read out as the data stored in the memory cell transistor MT.

[0162] Next, we will describe an example of the operation of the sense amplifier unit SAU when the threshold voltage of the TLC memory cell transistor MT is greater than or equal to the read voltage "S7R + ΔVr7" and less than the read voltage "S3R + ΔVr3".

[0163] In this case, as shown in Figure 24(C), when the control signal STB is raised at time t20, it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S13R + ΔVr13". If the threshold voltage of the memory cell transistor MT is determined to be lower than the read voltage "S13R + ΔVr13", then, as shown in the "S13R + ΔVr13 sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example, as shown in the "First latch operation" section of Figure 25, the latch circuit ADL stores the bit-inverted value of the sensed "0" data, i.e., the data "1".

[0164] Next, when the control signal STB is activated at time t21 as shown in Figure 24(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7". It is determined that the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7". Therefore, as shown in the "S7R + ΔVr7 Sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is an off-cell and senses the data "1". At this time, for example, as shown in the "Second Latch Operation" section of Figure 25, the latch circuit ADL stores the NAND value of the sensed "1" data and the already stored "1" data, i.e., the data "0".

[0165] Next, when the control signal STB is activated at time t22 as shown in Figure 24(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S3R + ΔVr3". If it is determined that the threshold voltage of the memory cell transistor MT is lower than the read voltage "S3R + ΔVr3", then, as shown in the "S3R + ΔVr3 sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is on-cell and senses the data "0". At this time, for example, as shown in the "Third latch operation" section of Figure 25, the latch circuit ADL stores the value obtained by taking the NAND of the sensed "0" data and the already stored "0" data, i.e., the data "1".

[0166] Next, when the control signal STB is activated at time t23 as shown in Figure 24(C), it is determined whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S1R + ΔVr1". It is determined that the threshold voltage of the memory cell transistor MT is higher than the read voltage "S1R + ΔVr1". Therefore, as shown in the "S1R + ΔVr1 Sense" section of Figure 25, the sense amplifier unit SAU determines that the memory cell transistor MT is an off-cell and senses the data "1". At this time, for example, as shown in the "Fourth Latch Operation" section of Figure 25, the latch circuit ADL stores the NAND value of the sensed "1" data and the already stored "1" data, i.e., the data "0". As a result, the data "0" is read out as the data stored in the memory cell transistor MT.

[0167] As described above, when the read voltage shown in Figure 24(B) is applied to the selection word line WLsel, the sense amplifier unit SAU reads out the data "1" if the threshold voltage of the TLC memory cell transistor MT is at the "E", "F", or "G" level. Also, the sense amplifier unit SAU reads out the data "1" if the threshold voltage of the TLC memory cell transistor MT is at the "Er" level. Furthermore, the sense amplifier unit SAU reads out the data "0" if the threshold voltage of the TLC memory cell transistor MT is at the "A", "B", "C", or "D" level. Since this is the same as the data of the upper page of the TLC shown in Figure 7, it indicates that the upper page of the TLC can be read by applying the read voltage shown in Figure 24(B) to the selection word line WLsel.

[0168] Comparing the data trends at the upper levels of the TLC shown in Figure 25 with the data trends at the highest level of the QLC shown in Figure 16, the data trends in the area enclosed by the dashed line in Figure 25 differ from those in Figure 16. This is because the read voltages "S7R + ΔVr7" and "S3R + ΔVr3" are deliberately set so that "(S7R + ΔVr7) < (S3R + ΔVr3)". In other words, by setting the read voltages "S7R + ΔVr7" and "S3R + ΔVr3" to have such a relationship, the data trends enclosed by the dashed line in Figure 25 can be achieved. As a result, when the threshold voltage of the TLC memory cell transistor MT is greater than or equal to the read voltage "S7R + ΔVr7" and less than the read voltage "S3R + ΔVr3", the data read by the sense amplifier unit SAU can be changed to data obtained by bit-inverting the QLC read data, thereby enabling the reading of higher-level data from the TLC. In the upper-page readout of the TLC method under QLC mode in this embodiment, the sense operation performed with the voltage "S13R + ΔVr13" applied functions as the first real sense operation, the sense operation performed with the voltage "S7R + ΔVr7" applied functions as the first imaginary sense operation, the sense operation performed with the voltage "S3R + ΔVr3" applied functions as the second imaginary sense operation, and the sense operation performed with the voltage "S1R + ΔVr1" applied functions as the second real sense operation.

[0169] Figure 26 shows the change in potential applied to each wire when performing a TLC middle page readout operation using the adjusted middle page readout voltage shown in Figure 23.

[0170] As shown in Figure 26(A), the same or similar voltages as in Figure 18(A) are applied to the selected gate line SGDsel, the non-selected gate line SGDusel, and the selected gate line SGS. Also, as shown in Figure 26(B), the same or similar voltages as in Figure 18(B) are applied to the non-selected word line WLusel.

[0171] As shown in Figure 26(B), the read path voltage VPASS_READ is applied to the selected word line WLsel, and then the adjusted read voltages "S15R+ΔVr15", "S9R+ΔVr9", "S6R+ΔVr6", and "S4R+ΔVr4" are applied in sequence for a predetermined time. The read voltage "S15R+ΔVr15" is the voltage corresponding to the TLC read voltage GR. The read voltage "S9R+ΔVr9" is lower than the read voltage "S15R+ΔVr15" and is the voltage corresponding to the TLC read voltage CR. The read voltage "S6R+ΔVr6" is lower than the read voltage "S9R+ΔVr9" and lower than the read voltage "S4R+ΔVr4". The read voltage "S4R + ΔVr4" is lower than the read voltage "S9R + ΔVr9" and higher than the read voltage "S6R + ΔVr6".

[0172] When these adjusted readout voltages, "S15R + ΔVr15", "S9R + ΔVr9", "S6R + ΔVr6", and "S4R + ΔVr4", are used, the sense amplifier unit SAU senses the mid-level data of the TLC memory cell transistor MT as shown in Figure 27. As shown in Figure 27, when the threshold voltage of the TLC memory cell transistor MT is at the "G" level, the sense amplifier unit SAU reads out the data "1". Also, when the threshold voltage of the TLC memory cell transistor MT is at the "Er", "A", or "B" levels, the sense amplifier unit SAU reads out the data "1". Furthermore, when the threshold voltage of the TLC memory cell transistor MT is at the "C", "D", "E", or "F" levels, the sense amplifier unit SAU reads out the data "0". Since this is identical to the data of the middle page of the TLC shown in Figure 7, it is shown that the middle page of the TLC can be read by applying a read voltage as shown in Figure 26(B) to the selected word line WLsel. In the middle page readout of the TLC system under QLC mode in this embodiment, the sense operation performed with the voltage "S15R + ΔVr15" applied functions as the first real sense operation, the sense operation performed with the voltage "S9R + ΔVr9" applied functions as the second real sense operation, the sense operation performed with the voltage "S6R + ΔVr6" applied functions as the first imaginary sense operation, and the sense operation performed with the voltage "S4R + ΔVr4" applied functions as the second imaginary sense operation.

[0173] Figure 28 shows the change in potential applied to each wire when performing a lower page read operation on a TLC using the adjusted read voltage of the lower page shown in Figure 23.

[0174] As shown in Figure 28(A), the same or similar voltages as in Figure 19(A) are applied to the selected gate line SGDsel, the non-selected gate line SGDusel, and the selected gate line SGS. Also, as shown in Figure 28(B), the same or similar voltages as in Figure 19(B) are applied to the non-selected word line WLusel.

[0175] As shown in Figure 28(B), the read path voltage VPASS_READ is applied to the selected word line WLsel, and then the adjusted read voltages "S14R+ΔVr14", "S11R+ΔVr11", and "S5R+ΔVr5" are applied sequentially for a predetermined time. The read voltage "S14R+ΔVr14" is the voltage corresponding to the TLC read voltage FR. The read voltage "S11R+ΔVr11" is the voltage corresponding to the TLC read voltage DR. The read voltage "S5R+ΔVr5" is the voltage corresponding to the TLC read voltage BR.

[0176] When these adjusted readout voltages "S14R + ΔVr14", "S11R + ΔVr11", and "S5R + ΔVr5" are used, the sense amplifier unit SAU senses lower-level data from the TLC memory cell transistor MT as shown in Figure 29. As shown in Figure 29, when the threshold voltage of the TLC memory cell transistor MT is at the "F" level and the "G" level, the sense amplifier unit SAU reads out "0" data. Similarly, when the threshold voltage of the TLC memory cell transistor MT is at the "B" level and the "C" level, the sense amplifier unit SAU also reads out "0" data. Furthermore, when the threshold voltage of the TLC memory cell transistor MT is at the "D" level and the "E" level, the sense amplifier unit SAU reads out "1" data. Also, when the threshold voltage of the TLC memory cell transistor MT is at the "Er" level and the "A" level, the sense amplifier unit SAU also reads out "1" data. Since this is identical to the data of the lower pages of the TLC shown in Figure 7, it indicates that the lower pages of the TLC can be read by applying a read voltage as shown in Figure 26(B) to the selected word line WLsel.

[0177] 1.13 Operation of the PLC Next, the operation of the PLC 24 in this embodiment will be described.

[0178] When the semiconductor memory device 2 is operating in QLC mode and data is being read from the QLC memory cell transistor MT, the memory controller 1 sends a signal DQ<7:0> consisting of "01h", "00h", multiple "ADD", and "30h", as shown in Figure 30, to the semiconductor memory device 2. Figure 30 shows an example where the number of "ADD" cycles sent from the memory controller 1 to the semiconductor memory device 2 is 5, but it is not limited to this. The number of "ADD" cycles may be 6, for example, and can be set according to the size of the address space representing the memory cell array 21. "01h" is a command to instruct the reading of a lower page. When reading a middle page, "02h" is used instead of "01h", when reading a higher page, "03h" is used instead of "01h", and when reading the most important page, "04h" is used instead of "01h". When the control unit 241 of the sequencer 24 shown in Figure 21 receives the signal DQ<7:0> consisting of "01h", "00h", multiple "ADD", and "30h", it reads the lower page data from the QLC memory cell transistor MT using the read voltages S5R, S11R, and S14R directly, without using the voltage shift amounts ΔVr5, ΔVr11, and ΔVr14. In other words, the control unit 241 of the sequencer 24 reads the lower page data from the QLC memory cell transistor MT by applying the voltages shown in Figure 19 to each wire. The same applies when reading the top page, upper page, and middle page data from the QLC memory cell transistor MT.

[0179] On the other hand, when the memory controller 1 reads data from a memory cell transistor MT that has been written using the TLC method while the semiconductor memory device 2 is operating in QLC mode, it first sends a signal DQ<7:0> consisting of "D5h", "C_ADD", "F_ADD", and multiple "F_DAT" signals to the semiconductor memory device 2, as shown in Figure 31A. This causes the semiconductor memory device 2 to perform a SetFeature operation, which stores the voltage shift amount data in the feature register 242. "D5h" is, for example, a second command, which is a command to instruct the SetFeature operation. "C_ADD" is the chip address that indicates the semiconductor memory device 2 that is the target of the SetFeature operation. "F_ADD" is the address (feature address) that indicates the setting information to be set by the SetFeature operation. In this embodiment, "F_ADD" indicates the address in the feature register 242 where the voltage shift amount data will be stored. "F_DAT" is data indicating the voltage shift amount as feature data. When a set feature operation is instructed, for example, data indicating voltage shift amounts ΔVr5, ΔVr11, and ΔVr14 is stored in the feature register 242 of the sequencer 24 shown in Figure 21.

[0180] When the semiconductor memory device 2 receives a set feature operation, it sets the ready busy signal R / B output to the memory controller 1 to the "L" level to indicate that the setting information has been reflected, and then sets it to the "H" level after a predetermined period (e.g., tFeat) has elapsed. Alternatively, the semiconductor memory device 2 may maintain the ready busy signal R / B at the "H" level after receiving the set feature operation without setting it to the "L" level.

[0181] After a predetermined period has elapsed since the semiconductor memory device 2 accepted the set feature operation, the memory controller 1 transmits a signal DQ<7:0> consisting of "A3h", "5Dh", "01h", "00h", a plurality of "ADD", and "30h" to the semiconductor memory device 2. "A3h" is, for example, the first command and is a prefix command for instructing the reading of data written using the TLC method when the semiconductor memory device 2 is set to QLC mode. "5Dh" is a command for instructing reading using a voltage shift amount.

[0182] When the semiconductor memory device 2 receives the signal DQ<7:0> consisting of "A3h", "5Dh", "01h", "00h", multiple "ADD", and "30h", the control unit 241 of the sequencer 24 shown in Figure 21 performs a shift read operation while referring to the data stored in the feature register 242. As a result, the control unit 241 adjusts the read voltages S5R, S11R, and S14R using voltage shift amounts ΔVr5, ΔVr11, and ΔVr14 to obtain the voltages "S5R + ΔVr5", "S11R + ΔVr11", and "S14R + ΔVr14", and reads the lower page data from the memory cell transistor MT that was written using the TLC method. In other words, the control unit 241 of the sequencer 24 realizes a pseudo-TLC read operation by applying the voltages shown in Figure 28 to each wire as a shift read operation in QLC mode, and reads the lower page data from the memory cell transistor MT that was written using the TLC method. The same applies when reading data from the upper and middle pages of a memory cell transistor MT that has been written to using the TLC method. Note that when reading data from the middle page of a memory cell transistor MT written to using the TLC method, "02h" is used instead of "01h". Also, when reading data from the upper page of a memory cell transistor MT written to using the TLC method, "04h" is used instead of "01h".

[0183] When reading data from a memory cell transistor MT that has been written using the TLC method while the semiconductor memory device 2 is operating in QLC mode, the memory controller 1 may send the signal DQ<7:0> shown in Figure 31B instead of the signal DQ<7:0> shown in Figure 31A. Specifically, the controller first sends the signal DQ<7:0>, consisting of "CEh", "C_ADD", "F_ADD", and multiple "F_DAT", to the semiconductor memory device 2, causing it to perform a set feature operation to store the voltage shift amount data in the feature register 242. In this case, "CEh" functions as the second command. When the set feature operation is instructed by "CEh", the semiconductor memory device 2 reflects the setting information while maintaining the ready busy signal R / B at the "H" level. In this state, when the memory controller 1 transmits the signal DQ<7:0> consisting of "A3h", "5Dh", "01h", "00h", multiple "ADD", and "30h" to the semiconductor memory device 2, the control unit 241 performs a shift read operation while referring to the data stored in the feature register 242.

[0184] 1.14 Operation and Effects of Semiconductor Memory Devices The control unit 241 of the sequencer 24 has a QLC mode for reading data from the QLC memory cell transistor MT (first memory cell transistor) included in the second block group 212. The control unit 241 of the sequencer 24 also has a TLC mode (second operating mode) for reading data from the TLC memory cell transistor MT (second memory cell transistor) included in the first block group 211. In the QLC mode, the control unit 241 senses the data stored in the memory cell transistor MT by applying four read voltages S13R, S7R, S3R, S1R (a first predetermined number of first read voltages), such as those shown in Figure 15, corresponding to the multiple threshold voltage distributions (first threshold voltage distribution) of the QLC shown in Figure 13, to the gate of the memory cell transistor MT via the word line WL, as shown by the sense amplifier 28. Furthermore, in QLC mode, the control unit 241 changes the four read voltages S13R, S7R, S3R, and S1R to four read voltages "S13R + ΔVr13", "S7R + ΔVr7", "S3R + ΔVr3", and "S1R + ΔVr1" (first predetermined number of third read voltages), which include two read voltages AR and ER (second predetermined number of second read voltages) corresponding to the multiple threshold voltage distributions (second threshold voltage distributions) of the TLC shown in Figure 7. The control unit 241 applies the read voltages "S13R + ΔVr13", "S7R + ΔVr7", "S3R + ΔVr3", and "S1R + ΔVr1" to the gate of the memory cell transistor MT of the TLC via the word line WL, and senses the data of the upper pages stored in the memory cell transistor MT of the TLC using the sense amplifier 28. The same applies when sensing the data of the middle and lower pages of the memory cell transistor MT of the TLC using the sense amplifier 28.

[0185] With this configuration, it becomes possible to read data from the TLC memory cell transistor MT while the sequencer 24 is operating in QLC mode. Therefore, it is not necessary to update the mode parameter of the parameter register 240 with data read from the ROM block 213 to change from QLC mode to TLC mode. As a result, the read operation speed of the semiconductor memory device 2 can be improved.

[0186] In QLC mode, the control unit 241 of the sequencer 24 applies four read voltages S13R, S7R, S3R, and S1R to the word line WL in sequence, as shown in Figure 15. The control unit 241 also applies the read voltages "S13R + ΔVr13", "S7R + ΔVr7", "S3R + ΔVr3", and "S1R + ΔVr1" to the word line WL in sequence, as shown in Figure 24. The read voltages "S13R + ΔVr13" and "S1R + ΔVr1" correspond to two read voltages ER and AR (a second predetermined number of second read voltages) corresponding to the threshold voltage distribution of the TLC, respectively. The read voltages "S7R + ΔVr7" and "S3R + ΔVr3" are voltages applied to the word line WL separately from the two read voltages ER and AR. Among these, the read voltage "S7R + ΔVr7" is an example of a first adjusted read voltage that is lower than the read voltage ER. Also, the read voltage "S3R + ΔVr3" is an example of a second adjusted read voltage that is higher than the first adjusted read voltage.

[0187] With this configuration, for example, as shown in Figure 25, when the threshold voltage of the TLC memory cell transistor MT is greater than or equal to the read voltage "S7R + ΔVr7" and less than the read voltage "S3R + ΔVr3", the data finally sensed by the sense amplifier unit SAU can be changed to data obtained by bit-inverting the QLC read data, thereby enabling the reading of higher-level data from the TLC.

[0188] When the control unit 241 of the sequencer 24 receives a signal DQ<7:0> from the memory controller 1 and includes the command "A3h" (first command) which instructs the sequencer 24 to sense data from the TLC memory cell transistor MT in QLC mode, it changes the read voltages S1R, S3R, S4R, S5R, S6R, S7R, S9R, S11R, S13R, S14R, S15R using the voltage shift amounts ΔVr1, ΔVr3, ΔVr4, ΔVr5, ΔVr6, ΔVr7, ΔVr9, ΔVr11, ΔVr13, ΔVr14, ΔVr15.

[0189] This configuration makes it possible to easily generate a read voltage that allows data to be read from the TLC memory cell transistor MT.

[0190] 1.15 First Modification Next, a first modification of the semiconductor memory device 2 of the above embodiment will be described.

[0191] The voltage shift amount shown in Figure 22, or in other words, the adjusted readout voltage shown in Figure 23, can be changed as appropriate.

[0192] Figure 32 shows an example of changes to the adjusted read voltages "S13R + ΔVr13", "S7R + ΔVr7", "S3R + ΔVr3", and "S1R + ΔVr1". In this example, the voltage shift amounts ΔVr13 and ΔVr1 remain unchanged. That is, the read voltages "S13R + ΔVr13" and "S1R + ΔVr1" are unchanged. On the other hand, the voltage shift amount ΔVr7 is set to "-0.8V", and the voltage shift amount ΔVr3 is set to "0.8V". As a result, as shown in Figure 32(B), the read voltages "S7R + ΔVr7" and "S3R + ΔVr3" are set to the same "0.8V". That is, in the upper page readout of the TLC method under QLC mode in this modified example, the first imaginary sense operation and the second imaginary sense operation are performed with the same voltage applied to the word line.

[0193] Thus, the readout voltages "S7R + ΔVr7" and "S3R + ΔVr3" may be the same voltage value.

[0194] Figure 33 shows an example of data sensing and latching operations performed by the sense amplifier unit SAU when a voltage waveform as shown in Figure 32(B) is applied to the selected word line WLsel.

[0195] Furthermore, for example, if the threshold voltage of the memory cell transistor MT in a TLC is at the "B" level, when determining whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7", it is possible that it should be determined as an off-cell, but due to the influence of some noise, it may be determined as an on-cell. In this case, as shown in parentheses in Figure 33, the data ultimately latched may become an incorrect "1" data.

[0196] In this regard, if the voltage waveform of the above embodiment, as shown in Figure 24(B), is applied to the selection word line WLsel, that is, if the condition that "S7R + ΔVr7" is lower than "S3R + ΔVr3" is guaranteed, then when determining whether the threshold voltage of the memory cell transistor MT is higher than the read voltage "S7R + ΔVr7", the determination that it is an off-cell becomes more reliable. Therefore, the possibility of incorrect data being read in the end can be reduced.

[0197] Figure 34 shows another example of modification of the read voltages "S13R + ΔVr13", "S7R + ΔVr7", "S3R + ΔVr3", and "S1R + ΔVr1". In this modification example, the voltage shift amounts ΔVr13 and ΔVr1 remain unchanged. On the other hand, the voltage shift amount ΔVr7 is set to "-2.0V", and the voltage shift amount ΔVr3 is set to "0.4V". As a result, as shown in Figure 34(B), the read voltage "S7R + ΔVr7" is set to "-1.0V", and the read voltage "S3R + ΔVr3" is set to "-0.2V". For example, the voltage applied to the word line in the first imaginary sense operation (S7R + ΔVr7 = -1.0V) is set slightly lower than the voltage applied to the word line in the second real sense operation (S1R + ΔVr1 = -0.6V). Furthermore, the voltage applied to the word line during the second imaginary sense operation (S3R + ΔVr3 = -0.2V) is set slightly higher than the voltage applied to the word line during the second real sense operation (S1R + ΔVr1 = -0.6V).

[0198] Generally, it is preferable to perform data sensing by the sense amplifier unit SAU after the voltage of the selected word line WLsel has stabilized. On the other hand, if the voltage of the selected word line WLsel is left to stabilize for a long time, the time required for the read operation will increase. Here, high precision is required for the first real sense operation, which is performed with the voltage "S13R + ΔVr13" applied to the selected word line WLsel, and the second real sense operation, which is performed with the voltage "S1R + ΔVr1" applied to the selected word line WLsel, while high precision is not required for the first imaginary sense operation, which is performed with the voltage "S7R + ΔVr7" applied to the selected word line WLsel, and the second imaginary sense operation, which is performed with the voltage "S3R + ΔVr3" applied to the selected word line WLsel. Therefore, the first real sense operation and the second real sense operation are required to be performed after the voltage of the selected word line WLsel has stabilized, but the first imaginary sense operation and the second imaginary sense operation are not required to be performed after the voltage of the selected word line WLsel has stabilized. In this modified example, the voltage applied to the selected word line WLsel in the first imaginary sense operation and the voltage applied to the selected word line WLsel in the second imaginary sense operation are adjusted so that the time required for the voltage of the selected word line WLsel to stabilize in the second real sense operation is shortened.

[0199] This configuration allows for a smaller difference between the read voltage "S3R + ΔVr3" and the read voltage "S1R + ΔVr1". As a result, when the voltage applied to the selected word line WLsel is changed from "S3R + ΔVr3" to "S1R + ΔVr1" at time t24, the voltage of the selected word line WLsel stabilizes at "S1R + ΔVr1" more quickly. Consequently, when the sense amplifier unit SAU senses the data stored in the memory cell transistor MT based on the read voltage "S1R + ΔVr1", it becomes possible to sense the data more appropriately.

[0200] Figure 35 shows another example of modifying the read voltages "S15R + ΔVr15", "S9R + ΔVr9", "S6R + ΔVr6", and "S4R + ΔVr4". In this modification example, the voltage shift amount ΔVr15 remains unchanged. On the other hand, the voltage shift amount ΔVr9 is set to "0V", the voltage shift amount ΔVr6 is set to "1.6V", and the voltage shift amount ΔVr4 is set to "1.2V". As a result, the read voltage "S9R + ΔVr9" is set to "1.8V", the read voltage "S6R + ΔVr6" is set to "2.2V", and the read voltage "S4R + ΔVr4" is set to "1.0V". In this modification example, the read voltage "S4R + ΔVr4" is used as the TLC read voltage CR. In other words, in this modified example, the sense operation performed with the voltage "S15R + ΔVr15" applied functions as the first real sense operation, the sense operation performed with the voltage "S9R + ΔVr9" applied functions as the first imaginary sense operation, the sense operation performed with the voltage "S6R + ΔVr6" applied functions as the second imaginary sense operation, and the sense operation performed with the voltage "S4R + ΔVr4" applied functions as the second real sense operation. In this case, the voltage applied to the selected word line WLsel in the first imaginary sense operation is set lower than the voltage applied to the selected word line WLsel in the first real sense operation, and the voltage applied to the selected word line WLsel in the second imaginary sense operation is set lower than the voltage applied to the selected word line WLsel in the first imaginary sense operation and higher than the voltage applied to the selected word line WLsel in the second real sense operation. In other words, the first and second imaginary sense operations may be performed before the second real sense operation.

[0201] Furthermore, the read voltages "S15R + ΔVr15", "S9R + ΔVr9", "S6R + ΔVr6", and "S4R + ΔVr4" may be changed as shown in Figure 36. In this example of modification, unlike the example shown in Figure 35, the voltage shift amount ΔVr9 is set to "-1.6V", and the voltage shift amount ΔVr6 is set to "0.8V". As a result, the read voltage "S9R + ΔVr9" is set to "0.2V", and the read voltage "S6R + ΔVr6" is set to "1.4V". In other words, the voltage applied to the word line in the first imaginary sense operation (S9R + ΔVr9 = 0.2V) is set slightly lower than the voltage applied to the word line in the second real sense operation (S4R + ΔVr4 = 1.2V). Furthermore, the voltage applied to the word line during the second imaginary sense operation (S6R + ΔVr6 = 1.4V) is set slightly higher than the voltage applied to the word line during the second real sense operation (S4R + ΔVr4 = 1.2V).

[0202] With this configuration, as in the example shown in Figure 34, the difference between the read voltage "S6R + ΔVr6" and the read voltage "S4R + ΔVr4" can be reduced. As a result, when the sense amplifier unit SAU senses the data stored in the memory cell transistor MT based on the read voltage "S4R + ΔVr4", it becomes possible to sense the data more appropriately.

[0203] 1.17 Second Modification Next, a second modification of the semiconductor memory device 2 of the above embodiment will be described.

[0204] In this modified example, the semiconductor memory device 2 employs both the QLC method and the PLC (pentalevel cell) method as data writing methods to the memory cell transistors. In this modified example, the semiconductor memory device 2 is provided with QLC mode and PLC mode as operating modes. When operating in PLC mode, the semiconductor memory device 2 reads data from the QLC memory cell transistor MT.

[0205] Figure 37 shows an example of PLC data coding and read voltage. The data coding of the PLC in this modified example is called 6-6-7-6-6 coding. By matching the data coding and read voltage of the PLC shown in Figure 37 with the data coding and read voltage of the QLC shown in Figure 13, it becomes possible to read data from the memory cell transistor MT of the QLC in PLC mode. Specifically, the data coding and read voltage of the PLC shown in Figure 37 are changed as follows.

[0206] First, the data coding and read voltages of the second, third, fourth, and fifth pages of the PLC shown in Figure 37, excluding the first page, are matched to the data coding and read voltages of the top, upper, middle, and lower pages of the QLC, respectively.

[0207] Specifically, as shown in Figure 38, the data coding and read voltage of the PLC's 5th page are matched to the data coding and read voltage of the QLC's top-level page. In this case, for example, the read voltage "S1R + ΔVr1" obtained by adjusting the PLC's read voltage S1R by a voltage shift amount ΔVr1 is matched to the QLC's read voltage S1R. Also, the read voltage "S5R + ΔVr5" obtained by adjusting the PLC's read voltage S5R by a voltage shift amount ΔVr5 is matched to the QLC's read voltage S3R. Furthermore, the read voltage "S13R + ΔVr13" obtained by adjusting the PLC's read voltage S13R by a voltage shift amount ΔVr13 is matched to the QLC's read voltage S7R. In addition, the read voltage "S21R + ΔVr21" obtained by adjusting the PLC's read voltage S21R by a voltage shift amount ΔVr21 is matched to the QLC's read voltage S13R.

[0208] Furthermore, the read voltage "S27R + ΔVr27", obtained by adjusting the PLC read voltage S27R with a voltage shift amount ΔVr27, is set to a higher voltage than the adjusted read voltage "S21R + ΔVr21". Also, the read voltage "S31R + ΔVr31", obtained by adjusting the PLC read voltage S31R with a voltage shift amount ΔVr31, is set to a lower voltage than the adjusted read voltage "S27R + ΔVr27". By setting the adjusted read voltages "S27R + ΔVr27" and "S31R + ΔVr31" to "(S27R + ΔVr27) > (S31R + ΔVr31)", as explained in the area enclosed by the dashed line in Figure 25, when the sense amplifier unit SAU senses the data of the QLC memory cell transistor MT which has a threshold voltage between these read voltages, the data that is ultimately sensed can be changed to data obtained by bit-inverting the PLC read data. Specifically, the sense data in section Da on page 5 of Figure 38 can be changed from "0" to "1". As a result, the data coding of the top-level page of QLC can be simulated.

[0209] Furthermore, as shown in Figure 39, the data coding and read voltage of the PLC's fourth page are matched to the data coding and read voltage of the higher-level pages of the QLC. In this case, for example, the read voltage "S2R + ΔVr2" obtained by adjusting the PLC's read voltage S2R by a voltage shift amount ΔVr2 is matched to the QLC's read voltage S2R. Also, the read voltage "S14R + ΔVr14" obtained by adjusting the PLC's read voltage S14R by a voltage shift amount ΔVr14 is matched to the QLC's read voltage S8R. Furthermore, the read voltage "S17R + ΔVr17" obtained by adjusting the PLC's read voltage S17R by a voltage shift amount ΔVr17 is matched to the QLC's read voltage S10R. Also, the read voltage "S25R + ΔVr25" obtained by adjusting the PLC's read voltage S25R by a voltage shift amount ΔVr25 is matched to the QLC's read voltage S12R.

[0210] Furthermore, the PLC read voltage S6R is adjusted by the voltage shift amount ΔVr6 to obtain the read voltage "S6R + ΔVr6", which is set to a higher voltage than the adjusted read voltage "S2R + ΔVr2". Also, the PLC read voltage S10R is adjusted by the voltage shift amount ΔVr10 to obtain the read voltage "S10R + ΔVr10", which is set to a lower voltage than the adjusted read voltage "S6R + ΔVr6". By setting the adjusted read voltages "S6R + ΔVr6" and "S10R + ΔVr10" to "(S6R + ΔVr6) > (S10R + ΔVr10)", the sense data in section Db on page 4 of Figure 39 can be changed from "1" data to "0" data. As a result, data coding of the higher-level pages of the QLC can be simulated.

[0211] Furthermore, as shown in Figure 40, the data coding and read voltage of the third page of the PLC are matched to the data coding and read voltage of the lower pages of the QLC. In this case, for example, the read voltage "S3R + ΔVr3" obtained by adjusting the PLC read voltage S3R by a voltage shift amount ΔVr3 is matched to the QLC read voltage S5R. Also, the read voltage "S16R + ΔVr16" obtained by adjusting the PLC read voltage S16R by a voltage shift amount ΔVr16 is matched to the QLC read voltage S11R. Furthermore, the read voltage "S29R + ΔVr29" obtained by adjusting the PLC read voltage S29R by a voltage shift amount ΔVr29 is matched to the QLC read voltage S14R.

[0212] Furthermore, the PLC read voltage S9R is adjusted by the voltage shift amount ΔVr9 to obtain the read voltage "S9R + ΔVr9", which is set to a higher voltage than the adjusted read voltage "S3R + ΔVr3". In addition, the PLC read voltage S12R is adjusted by the voltage shift amount ΔVr12 to obtain the read voltage "S12R + ΔVr12", which is set to a lower voltage than the adjusted read voltage "S9R + ΔVr9". By setting the adjusted read voltages "S9R + ΔVr9" and "S12R + ΔVr12" to "(S9R + ΔVr9) > (S12R + ΔVr12)", the sense data of part Dc on page 3 of Figure 40 can be changed from "1" data to "0" data.

[0213] Furthermore, the PLC read voltage S20R is adjusted by the voltage shift amount ΔVr20 to obtain the read voltage "S20R + ΔVr20", which is set to a higher voltage than the adjusted read voltage "S16R + ΔVr16". Furthermore, the PLC read voltage S23R is adjusted by the voltage shift amount ΔVr23 to obtain the read voltage "S23R + ΔVr23", which is set to a lower voltage than the adjusted read voltage "S20R + ΔVr20". By setting the adjusted read voltages "S20R + ΔVr20" and "S23R + ΔVr23" to "(S20R + ΔVr20) > (S23R + ΔVr23)", the sense data of part Dd on page 3 of Figure 40 can be changed from "0" data to "1" data.

[0214] As a result, it is possible to simulate data coding for lower-level pages of QLC.

[0215] Furthermore, as shown in Figure 41, the data coding and read voltage of the second page of the PLC are matched to the data coding and read voltage of the middle page of the QLC. In this case, for example, the read voltage "S4R + ΔVr4" obtained by adjusting the PLC read voltage S4R by a voltage shift amount ΔVr4 is matched to the QLC read voltage S4R. Also, the read voltage "S8R + ΔVr8" obtained by adjusting the PLC read voltage S8R by a voltage shift amount ΔVr8 is matched to the QLC read voltage S6R. Furthermore, the read voltage "S11R + ΔVr11" obtained by adjusting the PLC read voltage S11R by a voltage shift amount ΔVr11 is matched to the QLC read voltage S9R. Also, the read voltage "S28R + ΔVr28" obtained by adjusting the PLC read voltage S28R by a voltage shift amount ΔVr28 is matched to the QLC read voltage S15R.

[0216] Furthermore, the PLC read voltage S19R is adjusted by the voltage shift amount ΔVr19 to obtain the read voltage "S19R + ΔVr19", which is set to a higher voltage than the adjusted read voltage "S11R + ΔVr11". Also, the PLC read voltage S24R is adjusted by the voltage shift amount ΔVr24 to obtain the read voltage "S24R + ΔVr24", which is set to a lower voltage than the adjusted read voltage "S19R + ΔVr19". By setting the adjusted read voltages "S19R + ΔVr19" and "S24R + ΔVr24" to "(S19R + ΔVr19) > (S24R + ΔVr24)", the sense data of part De on page 4 of Figure 41 can be changed from "1" data to "0" data. As a result, data coding of the middle page of the QLC can be simulated.

[0217] As described above, by appropriately changing the PLC read voltage, it is possible to read data from the QLC memory cell transistor MT in PLC mode.

[0218] In the semiconductor memory device 2 of the above embodiment, a QLC with 3-4-4-4 coding was used as a TLC with 3-2-2 coding. To achieve this, in the semiconductor memory device 2 of the above embodiment, the sense operations of the upper and middle pages of the TLC were simulated by changing the four sense operations of the uppermost and middle pages of the QLC to two sense operations.

[0219] On the other hand, in the semiconductor memory device 2 of this modified version, the PLC with 6-6-7-6-6 coding is also used with 3-4-4-4 coding. To this end, in the semiconductor memory device 2 of this modified version, the sense operation of the lower pages of the QLC is simulated by changing the seven sense operations of the third page of the PLC to three sense operations. Furthermore, in the semiconductor memory device 2 of this modified version, the sense operation of the top-level, upper-level, and middle-level pages of the QLC is simulated by changing the six sense operations of the second, fourth, and fifth pages of the PLC to four sense operations each.

[0220] Based on the above, the configuration of the semiconductor memory device 2 is not limited to the configuration shown in the above embodiments and modifications, but is broadly applicable to semiconductor memory devices that can use a mode in which each memory cell transistor MT can store p bits (where p is a natural number of 2 or more) (e.g., TLC mode) and a mode in which each memory cell transistor MT can store q bits (where q is a natural number greater than p) (e.g., QLC mode), where the difference in the number of sense operations for each page is even (0, 2, 4, ...).

[0221] 2. Second Embodiment Next, a second embodiment of the semiconductor memory device 2 of the second embodiment will be described. The following description will focus on the differences from the semiconductor memory device 2 of the first embodiment.

[0222] In the semiconductor memory device 2 of this embodiment, as shown in Figure 42, when the control unit 241 of the sequencer 24 reads data from the upper pages of the TLC memory cell transistor MT in QLC mode, it applies the adjusted read voltages "S13R + ΔVr13" and "S1R + ΔVr1" corresponding to the read voltages AR and ER to the selection word line WLsel, while skipping the application of the adjusted read voltages "S7R + ΔVr7" and "S3R + ΔVr3" to the selection word line WLsel. Even with this configuration, as shown in Figure 42, it is possible to appropriately read data from the upper pages of the TLC memory cell transistor.

[0223] Furthermore, when reading data from the middle pages of the TLC memory cell transistors MT in QLC mode, the control unit 241 of the sequencer 24 applies the adjusted read voltages "S15R + ΔVr15" and "S9R + ΔVr9" corresponding to the read voltages CR and GR to the selection word line WLsel, while skipping the application of the adjusted read voltages "S6R + ΔVr6" and "S4R + ΔVr4" to the selection word line WLsel. When reading data from the lower pages of the TLC memory cell transistors MT in QLC mode, the control unit 241 of the sequencer 24 applies the adjusted read voltages "S14R + ΔVr14", "S11R + ΔVr11", and "S5R + ΔVr5" corresponding to the read voltages BR, DR, and FR to the selection word line WLsel.

[0224] Thus, in the QLC mode (first operating mode), the control unit 241 of the sequencer 24 of this embodiment adjusts two of the four read voltages S13R, S7R, S3R, S1R (a first predetermined number of first read voltages), S13R and S1R, to two read voltages "S13R + ΔVr13" and "S1R + ΔVr1" (a second predetermined number of third read voltages) corresponding to two read voltages ER and AR (a second predetermined number of second read voltages) of the TLC. The control unit 241 also applies the two read voltages "S13R + ΔVr13" and "S1R + ΔVr1" to the memory cell transistor MT of the TLC via the word line WL, and senses the data stored in the memory cell transistor MT of the TLC using the sense amplifier unit SAU.

[0225] Even with this configuration, the same or similar functions and effects as those of the semiconductor memory device 2 of the first embodiment can be obtained.

[0226] 3. Other Embodiments: This disclosure is not limited to the above-described examples.

[0227] For example, when the sequencer 24 reads the data of the upper page stored in the TLC memory cell transistor MT, instead of applying voltage to the selection word line WLsel in the order of "S13R+ΔVr13", "S7R+ΔVr7", "S3R+ΔVr3", and "S1R+ΔVr1" as shown in Figure 24, it may apply voltage in the order of "S1R+ΔVr1", "S3R+ΔVr3", "S7R+ΔVr7", and "S13R+ΔVr13". The same applies when reading the data of the middle and lower pages stored in the TLC memory cell transistor MT.

[0228] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention and are included in the claims of the invention and its equivalents.

Claims

1. A first memory cell transistor in which data is stored using a plurality of first threshold voltage distributions; a second memory cell transistor in which data is stored using a plurality of second threshold voltage distributions which are fewer than the plurality of first threshold voltage distributions; a sense amplifier that senses the data stored in the first memory cell transistor and the second memory cell transistor, respectively, via bit lines connected to the first memory cell transistor and the second memory cell transistor during a read operation; and a control unit that controls the voltages applied from a word line to the gate of the first memory cell transistor and the gate of the second memory cell transistor, respectively, wherein in a first operation mode for reading data from the first memory cell transistor, the control unit senses the data stored in the first memory cell transistor by applying a first predetermined number of first read voltages corresponding to the plurality of first threshold voltage distributions to the gate of the first memory cell transistor via the word line, the sense amplifier senses the data stored in the first memory cell transistor. In the first operating mode, the semiconductor memory device adjusts the first predetermined number of first read voltages to a first predetermined number of third read voltages, which include a second predetermined number of second read voltages that are fewer than the first predetermined number and correspond to the plurality of second threshold voltage distributions, and applies the first predetermined number of third read voltages to the gate of the second memory cell transistor via the word line to sense the data stored in the second memory cell transistor using the sense amplifier.

2. The semiconductor memory device according to claim 1, wherein the control unit has a second operating mode in which it senses data stored in the second memory cell transistor by applying a second predetermined number of second readout voltages to the gate of the second memory cell transistor via the word line, thereby allowing the sense amplifier to sense the data stored in the second memory cell transistor.

3. The semiconductor memory device according to claim 1, wherein the control unit, in the first operating mode, applies a first predetermined number of first read voltages to the word line in order from highest to lowest, applies a second predetermined number of second read voltages to the word line as a first predetermined number of third read voltages, and applies a first adjustment read voltage lower than at least one of the second predetermined number of second read voltages, and a second adjustment read voltage higher than the first adjustment read voltage, separately from the second predetermined number of second read voltages, to the word line.

4. The semiconductor memory device according to claim 1, wherein the control unit changes a first predetermined number of first read voltages to a first predetermined number of third read voltages when the signal transmitted from the memory controller includes a first command instructing the control unit to sense data from the second memory cell transistor in the first operating mode.

5. The semiconductor memory device according to claim 4, further comprising: a parameter register storing a first predetermined number of first read voltages; and a feature register storing a voltage shift amount for changing from the first predetermined number of first read voltages to a first predetermined number of third read voltages, wherein the control unit, when the signal transmitted from the memory controller includes the first command, reads the first predetermined number of first read voltages from the parameter register and reads the voltage shift amount from the feature register to generate the first predetermined number of third read voltages.

6. The semiconductor memory device according to claim 5, wherein the control unit stores the voltage shift amount transmitted together with the second command in the feature register when the signal transmitted from the memory controller includes a second command.

7. The semiconductor memory device according to claim 1, wherein the first memory cell transistor is a quad-level cell and the second memory cell transistor is a triple-level cell.

8. The semiconductor memory device according to claim 1, wherein the first memory cell transistor is a pentalevel cell and the second memory cell transistor is a quadlevel cell.

9. A first memory cell transistor in which data is stored using a plurality of first threshold voltage distributions; a second memory cell transistor in which data is stored using a plurality of second threshold voltage distributions which are fewer than the plurality of first threshold voltage distributions; a sense amplifier that senses the data stored in the first memory cell transistor and the second memory cell transistor, respectively, via bit lines connected to the first memory cell transistor and the second memory cell transistor during a read operation; and a control unit that controls the voltages applied from a word line to the gate of the first memory cell transistor and the gate of the second memory cell transistor, respectively, wherein in a first operation mode for reading data from the first memory cell transistor, the control unit senses the data stored in the first memory cell transistor by applying a first predetermined number of first read voltages corresponding to the plurality of first threshold voltage distributions to the gate of the first memory cell transistor via the word line, the sense amplifier senses the data stored in the first memory cell transistor. In a second operating mode for reading data from the second memory cell transistor, a second predetermined number of second read voltages, fewer than the first predetermined number, corresponding to the plurality of second threshold voltage distributions, are applied to the gate of the second memory cell transistor via the word line to sense the data stored in the second memory cell transistor using the sense amplifier. In the first operating mode, at least one of the first predetermined number of first read voltages is adjusted to a second predetermined number of third read voltages corresponding to the second predetermined number of second read voltages, and the second predetermined number of third read voltages are applied to the gate of the second memory cell transistor via the word line to sense the data stored in the second memory cell transistor using the sense amplifier.

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