Semiconductor memory device and method of manufacturing the same

Abstract

The embodiment relates to a semiconductor memory device and a method for manufacturing the same. The semiconductor memory device includes: a semiconductor substrate; a first stacked body having a plurality of first insulating layers and a plurality of first conductive layers alternately stacked in a first direction intersecting the surface of the semiconductor substrate; a second stacked body disposed in a first direction of the first stacked body, and having a plurality of second insulating layers and a plurality of second conductive layers alternately stacked in the first direction; a third insulating layer disposed between the first stacked body and the second stacked body, and having a thickness greater than that of the first and second insulating layers; and a columnar portion having a semiconductor layer and a charge storage layer, the semiconductor layer penetrating the first stacked body. The charge storage layer is disposed between a plurality of first conductive layers and a semiconductor layer, and between a plurality of second conductive layers and a semiconductor layer, and extends in a first direction; the columnar body portion has a first region facing one of the plurality of first conductive layers and a connecting portion facing the third insulating layer, and the width of the connecting portion in a second direction orthogonal to the first direction is greater than the width of the first region in the second direction, and the thickness of the semiconductor layer in the connecting portion is greater than the thickness of the semiconductor layer in the first region.

Description

[0001] Related applications

[0002] This application enjoys priority to Japanese Patent Application No. 2021-42801 (filed on March 16, 2021). This application includes all contents of the said basic application by reference. Technical Field

[0003] The embodiments disclosed herein relate to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0004] Semiconductor packages using NAND (Not-AND) flash memory as semiconductor storage devices are known. To increase the capacity of this type of NAND flash memory, 3D NAND flash memory composed of multiple stacked storage cells has become practical. The challenge of this stacked 3D NAND flash memory lies in improving reliability and manufacturing yield. Summary of the Invention

[0005] The embodiments disclosed herein provide a semiconductor memory device and a method for manufacturing the same, which improves reliability and manufacturing yield.

[0006] A semiconductor memory device according to one embodiment includes: a semiconductor substrate; a first stacked body having a plurality of first insulating layers and a plurality of first conductive layers alternately stacked in a first direction intersecting the surface of the semiconductor substrate; a second stacked body disposed in a first direction of the first stacked body, and having a plurality of second insulating layers and a plurality of second conductive layers alternately stacked in the first direction; a third insulating layer disposed between the first stacked body and the second stacked body, and having a thickness greater than that of the first insulating layers and the second insulating layers; and a columnar portion having: a semiconductor layer penetrating the first stacked body and the first insulating layer. The three insulating layers and the second stacked body are disposed and extend in the first direction; and the charge storage layer is disposed between the plurality of first conductive layers and the semiconductor layer and between the plurality of second conductive layers and the semiconductor layer, and extends in the first direction; the columnar body portion has a first region facing one of the plurality of first conductive layers and a connecting portion facing the third insulating layer, and the width of the connecting portion in the second direction orthogonal to the first direction is greater than the width in the second direction of the first region, and the film thickness in the connecting portion of the semiconductor layer is greater than the film thickness of the first region. Attached Figure Description

[0007] Figure 1 This is a perspective view showing the overall configuration of a semiconductor memory device according to one embodiment.

[0008] Figure 2 This is a cross-sectional view showing the overall configuration of a semiconductor memory device according to one embodiment.

[0009] Figure 3 This is a cross-sectional view showing the configuration of a memory cell in a semiconductor memory device according to one embodiment.

[0010] Figures 4 to 15 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to one embodiment.

[0011] Figure 16 This is a cross-sectional view showing the configuration of a memory cell in a semiconductor memory device according to one embodiment.

[0012] Figure 17 This is a cross-sectional view showing the configuration of a memory cell in a modified semiconductor memory device.

[0013] Figure 18 This is a cross-sectional view showing the configuration of a memory cell in a modified semiconductor memory device. Detailed Implementation

[0014] Hereinafter, the semiconductor memory device and its manufacturing method according to this embodiment will be described in detail with reference to the accompanying drawings. In the following description, elements having substantially the same function and structure are indicated by the same symbols or symbols followed by letters, and will be repeated only where necessary. The embodiments shown below illustrate apparatus or methods for embodying the technical concept of the embodiments. The technical concept of the embodiments does not specify the materials, shapes, structures, arrangements, etc., of the constituent parts as described below. Various modifications can be made to the scope of the claims based on the technical concept of the embodiments.

[0015] The accompanying drawings are provided to clarify the description and may schematically represent the width, thickness, shape, etc., of various parts compared to the actual form. However, these are merely examples and are not intended to limit the interpretation of the invention. In this specification and the accompanying drawings, elements that have the same function as those described in the previous drawings are sometimes labeled with the same symbols, omitting redundant descriptions.

[0016] Multilayer films formed using the same process have the same layer structure and are made of the same material. In this specification, even if the multilayer films perform different functions or roles, these multilayer films formed using the same process are treated as films existing in the same layer.

[0017] In various embodiments of the present invention, the direction from the substrate toward the memory cell is referred to as "upper". Conversely, the direction from the memory cell toward the substrate is referred to as "lower". Thus, although the terms "upper" or "lower" are used for ease of explanation, the substrate and memory cell may be arranged in a manner opposite to that shown in the figures, for example. Furthermore, in the following description, the description of "memory cell on substrate" only illustrates the vertical relationship between the substrate and the memory cell as described above; other components may also be arranged between the substrate and the memory cell.

[0018] In this specification, unless otherwise expressly stated, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes a group selected from A, B, and C" do not exclude the possibility that α includes multiple combinations of A to C. Furthermore, these expressions do not exclude the possibility that α includes other elements.

[0019] The following implementation methods can be combined with each other as long as they do not create technical contradictions.

[0020] In the following embodiments, although the memory cell array is illustrated as a semiconductor memory device, the technology disclosed herein can be applied to semiconductor memory devices other than memory cell arrays (e.g., CPU (Central Processing Unit), display, interpolator, etc.).

[0021] Furthermore, the configuration of the peripheral (CMOS, Complementary Metal-Oxide Semiconductor) circuitry is not specifically mentioned in the following embodiments. The semiconductor memory device may also have CMOS circuitry partitioned in other areas on the semiconductor substrate. Furthermore, the semiconductor memory device may also have CMOS circuit chips and memory cell array chips formed separately on different semiconductor substrates. In this case, the upper surface of the memory cell array chip may be bonded to the upper surface of the CMOS circuit chip. Alternatively, the semiconductor memory device may have the memory cell array integrally formed on the CMOS circuit chip.

[0022] <First Embodiment>

[0023] [Composition of a memory cell array]

[0024] The configuration of the storage cell array in this embodiment uses... Figure 1 Please provide an explanation. Figure 1 This is a schematic perspective view showing the configuration of each element of the storage cell array 1 in this embodiment.

[0025] exist Figure 1 In this context, the two directions that are parallel to and orthogonal to each other relative to the main surface of the substrate 10 are referred to as the X direction and the Y direction, and the surface that is parallel to the main surface of the substrate 10 is referred to as the XY plane. The direction that is orthogonal to the X and Y directions is referred to as the Z direction (lamination direction).

[0026] like Figure 1 As shown, the memory cell array 1 has a substrate 10, a stack 100 disposed on the substrate 10, a plurality of columnar portions CL, and a plurality of bit lines BL disposed on the stack 100.

[0027] The substrate 10 is, for example, a P-type silicon (Si) semiconductor substrate containing P-type impurities such as boron (B). A P-type well region containing P-type impurities is provided on the surface of the substrate 10, for example.

[0028] The laminate 100 includes a lower laminate 120 disposed on a substrate 10, and an upper laminate 140 disposed on the lower laminate 120 on the opposite side (Z direction) from the substrate 10 (here, without distinguishing between the lower laminate 120 and the upper laminate 140, it is referred to as laminate 100). A plurality of mutually insulating conductive layers 70 and openings ST and MH shared by the plurality of conductive layers 70 are formed on the laminate 100. Openings ST and MH extend in the lamination direction (Z direction), penetrating the laminate 100 to reach the substrate 10. Opening ST extends in the X direction and separates the laminate 100 into multiple blocks in the Y direction. Details will be described later, but a columnar portion CL is formed in the opening MH (see reference). Figure 2 ).

[0029] The columnar portions CL are formed as cylinders extending along the lamination direction within the laminate 100. Multiple columnar portions CL may be arranged in an alternating pattern, for example. Alternatively, multiple columnar portions CL may be arranged in a square lattice along the X and Y directions.

[0030] Multiple bit lines BL are separated from each other in the X direction, and each bit line BL extends in the Y direction.

[0031] Semiconductor layer 20 of columnar body CL (described later) (reference) Figure 2 The upper end of the ) is connected to the bit line BL via the contact part Cb. Multiple columnar parts CL, which are selected one by one from the blocks separated in the Y direction due to the opening ST, are connected to a common bit line BL.

[0032] Additionally, an insulating layer 40 is formed at the opening ST, and an insulating layer 41 is formed on the laminate 100. However, for ease of explanation, in Figure 1 The insulating layer is omitted from the text.

[0033] Figure 2 This is a schematic cross-sectional view of storage cell array 1. Figure 2 The X and Z directions shown are... Figure 1 The X and Z directions are shown in the diagram.

[0034] The laminate 100 has a plurality of conductive layers 70 deposited on a substrate 10. The plurality of conductive layers 70, separated by a plurality of insulating layers 40, are periodically deposited in a direction perpendicular to the main surface of the substrate 10 (deposition direction, Z-direction). Each conductive layer 70 is a single layer. That is, when viewing the cross-sectional shape of a single conductive layer 70, a single material can be continuous in the thickness direction (Z-direction) of the conductive layer 70. Furthermore, interfaces may not exist within a single conductive layer 70. The material of the conductive layer 70 may also be, for example, tungsten.

[0035] An insulating layer 40 is formed between adjacent conductive layers 70 in the stacking direction. Multiple conductive layers 70 and multiple insulating layers 40 are alternately arranged. An insulating layer 40 is also formed between the substrate 10 and the bottommost conductive layer 70. An insulating layer 40a (here, when not distinguished from other insulating layers 40) is disposed at the boundary between the lower stacked layer 120 and the upper stacked layer 140. The film thickness of the insulating layer 40a disposed at the boundary between the lower stacked layer 120 and the upper stacked layer 140 in the stacking direction is greater than the film thickness of the insulating layer 40 between other conductive layers 70 in the stacking direction. The insulating layer 40a disposed at the boundary between the lower stacked layer 120 and the upper stacked layer 140 may have a film thickness in the stacking direction that is, for example, greater than the film thickness in the stacking direction of the insulating layer 40b on the bottommost conductive layer 70 (the control gate of the source-side select transistor STS) (here, the insulating layer 40b is referred to as the insulating layer 40 when it is not distinguished from other insulating layers 40). Adjacent conductive layers 70 in the stacking direction only need to be mutually insulated, and the material of the insulating layer 40 may also be silicon oxide such as silicon dioxide (SiO2) or TEOS (Tetraethoxysilane). The insulating layer 40 is deposited using, for example, a CVD (Chemical Vapor Deposition) apparatus.

[0036] A columnar portion CL is formed in the opening MH. The columnar portion CL includes an epitaxial growth layer 60, a memory layer 30, a semiconductor layer 20, and an insulating core layer 50. The columnar portion CL includes the epitaxial growth layer 60 near the substrate 10. The epitaxial growth layer 60 is formed, for example, by epitaxial growth of single-crystal silicon on the substrate 10 including single-crystal silicon.

[0037] On the epitaxial growth layer 60, a memory layer 30, a semiconductor layer 20, and an insulating core layer 50 extending in the stacking direction are formed. The core layer 50 is columnarly disposed near the center of the opening MH. The semiconductor layer 20 is disposed in a bottomed cylindrical shape around the core layer 50. The lower end of the semiconductor layer 20 is connected to the epitaxial growth layer 60. The memory layer 30 is cylindrically disposed around the semiconductor layer 20. The memory layer 30 is in contact with the inner surface of the opening MH (alternatingly stacked conductive layer 70 and insulating layer 40). The memory layer 30 is in contact with the semiconductor layer 20. In other words, the semiconductor layer 20 penetrates the stacked body 100. The memory layer 30 (including the charge storage layer 32 described later) is disposed between the conductive layer 70 and the semiconductor layer 20.

[0038] The columnar portion CL has a first narrow portion A at the boundary between the lower laminate 120 and the upper laminate 140, where its width (diameter, distance between outer surfaces) in the X direction is relatively small. The first narrow portion A is adjacent to a second region facing the conductive layer 70 of the upper laminate 140. The first narrow portion A is also adjacent to the insulating layer 40a at the boundary between the lower laminate 120 and the upper laminate 140. Alternatively, in the columnar portion CL, the width of the first narrow portion A in the X direction may be smaller than the width of the second region facing the conductive layer 70 of the upper laminate 140 in the X direction. Similarly, in the columnar portion CL, the width of the first narrow portion A in the X direction may be smaller than the width of the first region facing the conductive layer 70 of the lower laminate 120 in the X direction.

[0039] The columnar portion CL has a first widened portion a, which is wider in the X direction at the boundary between the lower laminate 120 and the upper laminate 140. The first widened portion a is adjacent to the first narrowed portion A. The first widened portion a and the insulating layer 40a at the boundary between the lower laminate 120 and the upper laminate 140 face each other. In the columnar portion CL, the width of the first widened portion a in the X direction is greater than the width of the first narrowed portion A in the X direction. In the columnar portion CL, the width of the first widened portion a in the X direction is greater than the width of the second region facing the conductive layer 70 of the upper laminate 140 in the X direction. In the columnar portion CL, the width of the first widened portion a in the X direction is greater than the width of the first region facing the conductive layer 70 of the lower laminate 120 in the X direction.

[0040] The columnar portion CL has a third region (connection portion) that is adjacent to the first widened portion a and has a larger width in the X direction on the substrate 10 side of the first widened portion a. The third region and the insulating layer 40a at the boundary between the lower laminate 120 and the upper laminate 140 face each other. In the columnar portion CL, the width of the third region in the X direction is approximately the same as the width of the first widened portion a in the X direction. In the columnar portion CL, the width of the third region in the X direction is larger than the width of the second region facing the conductive layer 70 of the upper laminate 140 in the X direction. In the columnar portion CL, the width of the third region in the X direction is larger than the width of the first region facing the conductive layer 70 of the lower laminate 120 in the X direction.

[0041] The columnar portion CL has a second widened portion b, which is adjacent to the third region and has a larger width in the X direction on the substrate 10 side of the third region. The second widened portion b is adjacent to the third region and is disposed on the opposite side of the first widened portion a. The second widened portion b and the insulating layer 40a at the boundary between the lower laminate 120 and the upper laminate 140 face each other. In the columnar portion CL, the width of the second widened portion b in the X direction is approximately the same as the width of the third region in the X direction. In the columnar portion CL, the width of the second widened portion b in the X direction is larger than the width of the second region facing the conductive layer 70 of the upper laminate 140 in the X direction. In the columnar portion CL, the width of the second widened portion b in the X direction is larger than the width of the first region facing the conductive layer 70 of the lower laminate 120 in the X direction.

[0042] The columnar portion CL has a second narrow portion B, which is adjacent to the second widened portion b and is located on the substrate 10 side of the third region, and has a smaller width in the X direction. The second narrow portion B is adjacent to a first region facing the conductive layer 70 of the lower laminate 120. The second narrow portion B faces the insulating layer 40a at the boundary between the lower laminate 120 and the upper laminate 140. In the columnar portion CL, the width of the second narrow portion B in the X direction is smaller than the width of the third region in the X direction. In the columnar portion CL, the width of the second narrow portion B in the X direction may also be larger than the width of the second region facing the conductive layer 70 of the upper laminate 140 in the X direction. In the columnar portion CL, the width of the second narrow portion B in the X direction may also be larger than the width of the first region facing the conductive layer 70 of the lower laminate 120 in the X direction.

[0043] The memory layer 30 is cylindrically disposed on the side of the columnar portion CL. The outer surface of the memory layer 30 (the surface in contact with the alternately stacked conductive layer 70 and insulating layer 40) reflects the shape of the CL side surface. The inner surface of the memory layer 30 (the surface in contact with the semiconductor layer 20) also reflects the shape of the CL side surface. That is, the memory layer 30 has a first narrow portion A at the boundary between the lower stacked layer 120 and the upper stacked layer 140, with a smaller outer width (outer diameter, distance between opposing outer surfaces) in the X direction. The memory layer 30 has a first widened portion a at the boundary between the lower stacked layer 120 and the upper stacked layer 140, with a larger outer width in the X direction. The memory layer 30 has a third region adjacent to the first widened portion a and on the substrate 10 side of the first widened portion a, with a larger outer width in the X direction. The memory layer 30 has a second widened portion b adjacent to the third region and on the substrate 10 side of the third region, with a larger outer width in the X direction. The memory layer 30 has a second narrow portion B adjacent to the second widened portion b and located on the substrate 10 side of the third region, with a smaller outer width in the X direction. The size relationship of the outer width of the first widened portion a, the second widened portion b, the first narrow portion A, the second narrow portion B, the first region, the second region, and the third region of the memory layer 30 in the X direction is the same as the size relationship of the width of the first widened portion a, the second widened portion b, the first narrow portion A, the second narrow portion B, the first region, the second region, and the third region of the columnar portion CL in the X direction, and therefore, the description is omitted here.

[0044] The shortest distance (film thickness) between the outer surface of the memory layer 30 (the surface in contact with the alternately stacked conductive layer 70 and insulating layer 40) and the inner surface of the memory layer 30 (the surface in contact with the semiconductor layer 20) is approximately the same across the entire surface. In other words, the film thickness of the memory layer 30 is formed with a substantially uniform thickness, regardless of the shape of the opening MH and the columnar portion CL.

[0045] Semiconductor layer 20 is disposed in a bottom cylindrical shape, in contact with the inner side surface of memory layer 30 and epitaxial growth layer 60. The outer side surface of semiconductor layer 20 (the surface in contact with memory layer 30) reflects the shape of the CL side surface. The inner side surface of semiconductor layer 20 (the surface in contact with core layer 50) also reflects the shape of the CL side surface. That is, semiconductor layer 20 has a first narrow portion A at the boundary between lower stacked layer 120 and upper stacked layer 140, with a smaller outer width (outer diameter, distance between opposing outer sides) in the X direction. Semiconductor layer 20 has a first widened portion a at the boundary between lower stacked layer 120 and upper stacked layer 140, with a larger outer width in the X direction. Semiconductor layer 20 has a third region adjacent to the first widened portion a and on the substrate 10 side of the first widened portion a, with a larger outer width in the X direction. Semiconductor layer 20 has a second widened portion b adjacent to the third region and on the substrate 10 side of the third region, with a larger outer width in the X direction. Semiconductor layer 20 has a second narrow portion B adjacent to the second widened portion b and located on the substrate 10 side of region III, with a smaller outer width in the X direction. The size relationship of the outer width of the first widened portion a, the second widened portion b, the first narrow portion A, the second narrow portion B, region I, region II, and region III of semiconductor layer 20 in the X direction is the same as the size relationship of the width of the first widened portion a, the second widened portion b, the first narrow portion A, the second narrow portion B, region I, region II, and region III of columnar body portion CL in the X direction, and therefore, the description is omitted here.

[0046] The shortest distance (film thickness) between the outer surface (the surface in contact with the memory layer 30) and the inner surface (the surface in contact with the core layer 50) of the semiconductor layer 20 differs in the first widened portion a, the second widened portion b, the first narrowed portion A, the second narrowed portion B, the first region, the second region, and the third region. The film thickness of the semiconductor layer 20 in the first and second regions is smaller than that in the first widened portion a, the second widened portion b, the first narrowed portion A, the second narrowed portion B, and the third region. The minimum film thickness of the semiconductor layer 20 in the first widened portion a, the second widened portion b, the first narrowed portion A, the second narrowed portion B, and the third region can also be larger than that in the first and second regions. By making the film thickness of the semiconductor layer 20 in the first and second regions smaller, the characteristics of the memory cell MC formed by the semiconductor layer 20 together with the opposing memory layer 30 and the conductive layer 70 can be improved. Because the semiconductor layer 20 in the first widened portion a, the second widened portion b, the first narrowed portion A, the second narrowed portion B, and the third region has a larger film thickness, it can suppress the discontinuity of the semiconductor layer 20 and improve reliability and manufacturing yield.

[0047] In this embodiment, the following example is shown: the film thickness of the semiconductor layer 20 facing all conductive layers 70 in regions I and II is smaller than the film thickness of the semiconductor layer 20 in regions I, II, III, and the first widening portion a, the second widening portion b, the first narrowing portion A, the second narrowing portion B, and the third region. However, this is not a limitation; in variations, as described later, the film thickness of the semiconductor layer 20 facing the conductive layer 70 above the uppermost layer of region I and / or below the lowermost layer of region II, which is close to region III, may be approximately the same as the film thickness of the semiconductor layer 20 in region III.

[0048] The core layer 50 is cylindrically disposed in contact with the inner surface of the semiconductor layer 20. The outer surface of the core layer 50 (the surface in contact with the semiconductor layer 20) reflects the shape of the CL side surface. That is, the core layer 50 has a first narrow portion A with a smaller outer width (outer diameter, distance between opposing outer surfaces) in the X direction at the boundary between the lower laminate 120 and the upper laminate 140. The core layer 50 has a first widened portion a with a larger outer width in the X direction at the boundary between the lower laminate 120 and the upper laminate 140. The core layer 50 has a third region with a larger outer width in the X direction adjacent to the first widened portion a and on the substrate 10 side of the first widened portion a. The core layer 50 has a second widened portion b with a larger outer width in the X direction adjacent to the third region and on the substrate 10 side of the third region. The core layer 50 has a second narrow portion B with a smaller outer width in the X direction adjacent to the second widened portion b and on the substrate 10 side of the third region. The width relationship in the X direction of the first widened portion a, the second widened portion b, the first narrowed portion A, the second narrowed portion B, the I region, the II region, and the III region of the core layer 50 is the same as the width relationship in the X direction of the first widened portion a, the second widened portion b, the first narrowed portion A, the second narrowed portion B, the I region, the II region, and the III region of the columnar body portion CL, therefore, the description is omitted here.

[0049] An insulating layer 40 is disposed on the uppermost conductive layer 70, and an insulating layer 41 is disposed on the insulating layer 40.

[0050] Figure 3 yes Figure 2 An enlarged sectional view of a portion of the structure.

[0051] The columnar portion CL is a structure having a memory layer 30, a semiconductor layer 20, and an insulating core layer 50. The semiconductor layer 20 extends continuously in the stacking direction within the stacked body 100. The material of the semiconductor layer 20 includes, for example, amorphous silicon or polycrystalline silicon. The core layer 50 is disposed inside the cylindrical semiconductor layer 20. The material of the core layer 50 includes, for example, silicon oxide. The memory layer 30 is disposed between the conductive layer 70 and the semiconductor layer 20, and surrounds the semiconductor layer 20 from its outer periphery.

[0052] The memory layer 30 includes a tunnel insulating layer 31, a charge storage layer 32, and a barrier insulating layer 33 (here, without distinguishing between the tunnel insulating layer 31, charge storage layer 32, and barrier insulating layer 33, it is referred to as the memory layer 30). The barrier insulating layer 33, charge storage layer 32, and tunnel insulating layer 31 extend continuously in the stacking direction of the stacked body 100 together with the semiconductor layer 20. Between the conductive layer 70 and the semiconductor layer 20, the barrier insulating layer 33, charge storage layer 32, and tunnel insulating layer 31 are sequentially disposed from the conductive layer 70 side. The tunnel insulating layer 31 is in contact with the semiconductor layer 20. The barrier insulating layer 33 is in contact with the conductive layer 70. The charge storage layer 32 is disposed between the barrier insulating layer 33 and the tunnel insulating layer 31.

[0053] Semiconductor layer 20, memory layer 30, and conductive layer 70 constitute the memory cell MC. Figure 3 In the diagram, a memory cell MC is schematically represented by a dashed line. The memory cell MC has a vertical transistor structure that separates the memory layer 30 from the conductive layer 70 and surrounds the semiconductor layer 20.

[0054] In the memory cell MC constructed with the vertical transistor, the semiconductor layer 20 functions as a channel, and the conductive layer 70 functions as a control gate. The charge storage layer 32 functions as a data storage layer that accumulates the charge injected from the semiconductor layer 20.

[0055] As described above, multiple memory cells MC are arranged in the stacking direction of multiple conductive layers 70, and the multiple conductive layers 70 are respectively connected to the multiple memory cells MC. The conductive layer 70 near the barrier insulating layer 33 in the conductive layer 70 functions as a control gate. By controlling the voltage of the conductive layer 70 connected to the memory cell MC, the writing or erasing of the memory cell MC is controlled.

[0056] The semiconductor memory device of the embodiment is a non-volatile semiconductor memory device that can electrically and freely write or erase data in the memory cell MC, and can retain the stored content even when the power is cut off.

[0057] The storage cell MC is, for example, a charge trapping type storage cell. The charge storage layer 32 has multiple well fields that trap charge in the insulating layer. The material of the charge storage layer 32 includes, for example, silicon nitride.

[0058] The tunnel insulating layer 31 acts as a potential barrier when charge is injected from the semiconductor layer 20 into the charge storage layer 32, or when the charge accumulated in the charge storage layer 32 diffuses toward the semiconductor layer 20. The material of the tunnel insulating layer 31 includes, for example, silicon oxide.

[0059] The barrier insulating layer 33 prevents the charge accumulated in the charge storage layer 32 from diffusing toward the conductive layer 70. The material of the barrier insulating layer 33 includes, for example, silicon oxide.

[0060] like Figure 1 As shown, a source-side selection transistor (STS) and multiple memory cells (MCs) are disposed on the lower stacked layer 120. A drain-side selection transistor (STD) and multiple memory cells (MCs) are disposed on the upper stacked layer 140. For example, the bottommost conductive layer 70 functions as the control gate of the source-side selection transistor (STS). For example, the topmost conductive layer 70 functions as the control gate of the drain-side selection transistor (STD).

[0061] Between the drain-side selection transistor (STD) and the source-side selection transistor (STS), multiple memory cells (MCs) are disposed. These multiple memory cells (MCs), the drain-side selection transistor (STD), and the source-side selection transistor (STS) are connected in series via a semiconductor layer 20, forming a memory string. The memory string is arranged, for example, in an alternating manner in a plane direction parallel to the XY plane, and the multiple memory cells (MCs) are arranged in three dimensions in the X, Y, and Z directions.

[0062] Figure 17 This illustrates a variation where a conductive layer 70a is disposed between the lowest conductive layer 70 in region II and region III, and a conductive layer 70b is disposed between the uppermost conductive layer 70 in region I and region III. The memory cell array in this variation is identical to the memory cell array of the first embodiment, except for the inclusion of conductive layers 70a and 70b. In the following description, descriptions of configurations and manufacturing methods identical to those of the first embodiment are omitted; the description primarily focuses on configurations different from those of the first embodiment.

[0063] In this variation, a conductive layer 70a (third conductive layer) is disposed between the bottommost conductive layer 70 of region II and region III. The thickness of the semiconductor layer 20 opposite to the conductive layer 70a is approximately the same as the thickness of the semiconductor layer 20 in region III. The thickness of the semiconductor layer 20 opposite to the conductive layer 70a is greater than the thickness of the semiconductor layer 20 opposite to the conductive layer 70 in region I and region II. In this case, the first narrow portion A may also face the conductive layer 70a below the bottommost layer of region II. The memory cell MC including the semiconductor layer 20 opposite to the conductive layer 70a may not be intended to function as a memory cell MC.

[0064] In this variation, a conductive layer 70b is disposed between the uppermost conductive layer 70 in region I and region III. The thickness of the semiconductor layer 20 opposite to the conductive layer 70b is approximately the same as the thickness of the semiconductor layer 20 in region III. The thickness of the semiconductor layer 20 opposite to the conductive layer 70b is greater than the thickness of the semiconductor layer 20 opposite to the conductive layer 70 in region I and region II. In this case, the second narrow portion B may also face the conductive layer 70 above the uppermost layer in region I. The memory cell MC including the semiconductor layer 20 opposite to the conductive layer 70b may not be intended to function as a memory cell MC. This variation shows a memory cell array comprising conductive layers 70a and 70b. However, it is not limited to this and may also be configured to include only either conductive layer 70a or conductive layer 70b.

[0065] [Manufacturing Method of Memory Cell Array]

[0066] Next, refer to Figures 4 to 15 The manufacturing method of the storage cell array 1 according to the first embodiment will be described.

[0067] like Figure 4 As shown, firstly, an insulating layer 40 (TEOS film) and a sacrificial layer 71 (SiN film) are alternately deposited on a substrate 10 to form a lower stack 120. The insulating layer 40 and the sacrificial layer 71 are deposited using, for example, a CVD apparatus. The alternately deposited insulating layer 40 and sacrificial layer 71 are formed in a manner that they are in contact with each other. The thickness of the uppermost insulating layer 40a formed in the lower stack 120 may be greater than the thickness of the lower insulating layer 40. The thickness of the uppermost insulating layer 40a formed in the lower stack 120 in the stacking direction may, for example, be greater than the thickness of the insulating layer 40b above the lowermost sacrificial layer 71 in the stacking direction. In this embodiment, the material of the insulating layer 40 is exemplified as a TEOS film, but the material of the insulating layer 40 is not limited to this, and may also be, for example, silicon dioxide (SiO2). In this embodiment, although the material of the sacrificial layer 71 is illustrated as silicon nitride film (SiN), the material of the sacrificial layer 71 is not limited to this, and may also be, for example, silicon.

[0068] Next, as Figure 5 As shown, multiple memory holes MH are formed in the lower stack 120, which includes multiple insulating layers 40 and multiple sacrificial layers 71. The memory holes MH are formed by RIE (Reactive Ion Etching) using a mask not shown. The memory holes MH penetrate the lower stack 120 in the stacking direction, exposing the substrate 10.

[0069] like Figure 6As shown, the substrate 10 exposed inside the memory hole MH is used as a seed for epitaxial growth of single-crystal silicon. The epitaxial growth of single-crystal silicon is also performed using a CVD apparatus to form an epitaxial growth layer 60. Furthermore, the surface of the epitaxial growth layer 60 is subsequently oxidized (e.g., thermal oxidation). A silicon oxide film 61 is formed on the surface of the epitaxial growth layer 60. A sacrificial film 90 is formed above the silicon oxide film 61 of the memory hole MH. The material of the sacrificial film 90 may also be, for example, amorphous silicon. The sacrificial film 90 is filled to form the upper stack 140 and is intended to be removed later.

[0070] Next, for example Figure 7 As shown, a portion of the insulating layer 40 is removed, and the width (inner diameter, distance between opposing inner surfaces) of the upper end of the memory hole MH of the lower laminate 120 is enlarged to form a junction J. The junction J is formed, for example, by a method such as wet etching. The junction J is formed on the insulating layer 40, which is formed on the uppermost layer of the lower laminate 120. That is, the junction J is formed above the first region, which is opposite to the sacrificial layer 71 of the lower laminate 120. In the memory hole MH, a third region, wider in the X direction than the first region, is formed. Adjacent to the third region, a second widening portion b is formed on the substrate 10 side of the third region, and a first widening portion a is formed on the opposite side of the third region from the substrate 10. Adjacent to the second widening portion b, on the substrate 10 side of the third region, a second narrowing portion B, narrower in the X direction than the third region, is formed. A sacrificial film 90 is also formed in the junction J of the memory hole MH.

[0071] Next, as Figure 8 As shown, an insulating layer 40 (TEOS film) and a sacrificial layer 71 (SiN film) are alternately deposited on the lower laminate 120 to form an upper laminate 140. The insulating layer 40 and the sacrificial layer 71 are deposited using, for example, a CVD apparatus. The alternately deposited insulating layer 40 and sacrificial layer 71 are formed in a manner that they are in contact with each other. The film thickness of the bottommost and topmost insulating layers 40 formed on the upper laminate 140 may also be greater than the film thickness of the other insulating layers 40. The film thickness of the insulating layers 40 in the upper laminate 140 may also be smaller than the film thickness of the topmost insulating layer 40a formed on the lower laminate 120.

[0072] Subsequently, multiple memory holes MH are formed on the upper laminate 140, which includes multiple insulating layers 40 and multiple sacrificial layers 71. The memory holes MH are formed by the Reactive Ion Etching (RIE) method using a mask (not shown). The memory holes MH of the upper laminate 140 are formed in such a way that they are connected to the junction J of the memory holes MH of the lower laminate 120. The width (inner diameter, distance between opposing inner surfaces) of the memory holes MH of the upper laminate 140 is smaller than that of the junction J. In the memory holes MH, a second region is formed, which is smaller in width in the X direction than the third region and faces the sacrificial layer 71 of the upper laminate 140. Adjacent to the third region and on the opposite side of the third region from the substrate 10, a first narrow portion A is formed, which is smaller in width in the X direction than the third region. The memory holes MH penetrate the upper laminate 140 in the stacking direction, exposing the sacrificial film 90 that fills the junction J of the memory holes MH of the lower laminate 120.

[0073] The sacrificial film 90 and silicon oxide film 61 remaining in the memory hole MH of the lower stack 120 are removed via the memory hole MH of the upper stack 140. This step is performed, for example, by wet etching and RIE. As a result, a memory hole MH connecting the lower stack 120 and the upper stack 140 is formed. Alternatively, the silicon oxide film 61 may not be removed.

[0074] Next, as Figure 9 As shown, a memory layer 30 is formed on the side and bottom surfaces of the memory hole MH. The memory layer 30 is deposited, for example, on the upper surface of the laminate 100 and the inner surface (side and bottom surfaces) of the memory hole MH using a CVD apparatus.

[0075] Next, the memory layer 30 on the upper surface of the stacked layer 100 and the bottom surface of the memory hole MH is removed. The memory layer 30 on the upper surface of the stacked layer 100 and the bottom surface of the memory hole MH is removed, for example, by the RIE method. By removing the memory layer 30 on the bottom surface of the memory hole MH, the epitaxial growth layer 60 near the substrate 10 is exposed.

[0076] After removing the memory layer 30 from the bottom surface of the memory hole MH, a semiconductor layer 20 is formed on the side and bottom surfaces of the memory hole MH. The semiconductor layer 20 is deposited, for example, on the upper surface of the laminate 100 and the inner surfaces (side and bottom surfaces) of the memory hole MH using a CVD apparatus. The semiconductor layer 20 is formed in contact with the side surface of the memory layer 30 and the epitaxial growth layer 60 exposed at the bottom of the memory hole MH. The semiconductor layer 20 is formed, for example, as an amorphous silicon layer, and then crystallized into a polycrystalline silicon layer through heat treatment.

[0077] Figures 10-13 It is near the junction J of the memory hole MH ( Figure 9An enlarged sectional view of the dashed area. Next, as... Figure 10 and Figure 11 As shown, a protective film 80 is formed at the junction J of the memory hole MH.

[0078] like Figure 10 As shown, plasma treatment is first performed on the second region, which faces the sacrificial layer 71 of the upper stacked body 140, from the upper end of the memory hole MH. A passivation layer 22 is formed on the inner wall of the semiconductor layer 20 in the second region through plasma treatment. By controlling the type, proportion, and flow rate of the plasma treatment gas, the passivation layer is not formed on the inner wall of the semiconductor layer 20 in the third and first regions. In other words, a gradient of the passivation layer is formed in the stacking direction of the semiconductor layer 20. Preferably, at least one gas selected from the group consisting of N2, Ar, He, H2, NH3, or F is used for the plasma treatment.

[0079] like Figure 11 As shown, film deposition is performed on regions II and III from the upper end of the memory hole MH. The film deposition process is carried out by supplying reactant gas to regions II and III from the upper end of the memory hole MH. The type, proportion, and flow rate of the reactant gas are controlled to a flow rate that selectively forms the protective film in regions II and III. A protective film 80 is formed on the inner walls of the semiconductor layer 20 in regions III, the first widening portion a, the second widening portion b, the first narrowing portion A, and the second narrowing portion B by film deposition. The protective film 80 may be, for example, silicon oxide or silicon nitride. The protective film 80 is deposited, for example, using a CVD apparatus. Because a passivation layer 22 is formed on the semiconductor layer 20 in region II, nucleation of the protective film 80 is suppressed. Therefore, the protective film 80 is not formed on the semiconductor layer 20 in region II. By controlling the type, proportion, and flow rate of the CVD gas, reactant gas is not supplied to region I. Because the reactant gas is insufficient, the protective film 80 is also not formed on the semiconductor layer 20 in region I. In other words, a protective film 80 is selectively formed on the inner wall of the semiconductor layer 20 in a specific region (the region other than the I region and the II region) including the III region, the first widened portion a, the second widened portion b, the first narrowed portion A, and the second narrowed portion B.

[0080] In the method for manufacturing the memory cell array of this embodiment, by controlling the type or ratio and flow rate of the plasma processing and CVD gases, film formation in the first and second regions can be suppressed, and a protective film 80 can be formed in a specific region (the region other than the first and second regions) including the third region, the first widening portion a, the second widening portion b, the first narrowing portion A, and the second narrowing portion B.

[0081] exist Figure 11The diagram shows that the protective film 80 is formed with a generally uniform film thickness. However, it is not limited to this, and the film thickness of the protective film 80 may also be formed to be thinner as it approaches the first region and the second region.

[0082] Next, as Figure 12 As shown, a portion of the semiconductor layer 20 is oxidized to form an oxide film 24. The oxide film 24 is formed, for example, by an oxidation process. In the semiconductor layer 20 covered by the protective film 80, including the third region, the first widening portion a, the second widening portion b, the first narrowing portion A, and the second narrowing portion B, the oxide film 24 is not formed. Therefore, the oxide film 24 is formed on the surface of the semiconductor layer 20 exposed from the protective film 80 in the first and second regions.

[0083] Next, as Figure 13 As shown, a portion of the inner wall of the semiconductor layer, namely the oxide film 24, is selectively removed. The oxide film 24 is removed, for example, by wet etching. The oxide film 24 is etched under conditions with a selectivity higher than that of the semiconductor layer 20. Through etching of the oxide film 24, the thickness of the semiconductor layer 20 in regions I and II is smaller than the thickness of the semiconductor layer 20 in the region covered by the protective film 80, including region III, the first widening portion a, the second widening portion b, the first narrowing portion A, and the second narrowing portion B. Figure 13 In this process, a portion of the protective film 80 is etched away, leaving residue. However, this is not the only possibility; the protective film 80 may also be completely etched along with the oxide film 24.

[0084] In the method for manufacturing a memory cell array according to this embodiment, by covering a specific region (the region other than the first and second regions) of the semiconductor layer 20 including the third region with a protective film 80, the formation and etching of the oxide film 24 in the specific region including the third region (the region other than the first and second regions) can be suppressed. Therefore, the thickness of the semiconductor layer 20 including the third region is formed to be greater than the thickness of the semiconductor layer 20 in the first and second regions. By making the thickness of the semiconductor layer 20 in the first and second regions smaller, the characteristics of the memory cell MC formed together with the opposing memory layer 30 and conductive layer 70 can be improved. Because the thickness of the semiconductor layer 20 in the third region is larger, the discontinuity of the semiconductor layer 20 at the first narrow portion A and the second narrow portion B can be suppressed, thereby improving reliability and manufacturing yield.

[0085] like Figure 14 As shown, a core layer 50 is formed inside the memory aperture MH. The core layer 50 is formed by embedding it inside the semiconductor layer 20. The core layer 50 is formed, for example, by deposition using a CVD apparatus. The stacking of the memory layer 30, the semiconductor layer 20, and the core layer 50 within the memory aperture MH constitutes a columnar portion CL.

[0086] like Figure 15 As shown, the semiconductor layer 20 and core layer 50 deposited on the multilayer 100 are removed by CMP (Chemical Mechanical Polishing) or etching. Then, an insulating layer 41 is formed on the insulating layer 40. The insulating layer 41 covers the upper end of the multilayer constituting the columnar portion CL.

[0087] Next, using a RIE method with a mask (not shown), a plurality of openings ST are formed in the laminate 100, which includes an insulating layer 41, a plurality of insulating layers 40, and a plurality of sacrificial layers 71. The openings ST are shared by the plurality of insulating layers 40 and the plurality of sacrificial layers 71. The openings ST penetrate the laminate 100 near the columnar portion CL and reach the substrate 10.

[0088] Next, the sacrificial layer 71 is removed using an etchant supplied via the ST aperture. Removal of the sacrificial layer 71 creates voids between adjacent insulating layers 40 in the stacking direction. The epitaxial growth layer 60 exposed in the voids of the bottommost layer is then subjected to oxidation or similar processes to form an insulating layer 62. A conductive layer 70 is formed in the voids between adjacent insulating layers 40, thereby enabling the fabrication of… Figure 2 The storage cell array 1 shown.

[0089] As described above, according to the semiconductor memory device manufacturing method of this embodiment, by making the film thickness of the semiconductor layer 20 in the first region and the second region smaller, the characteristics of the memory cell MC formed by the semiconductor layer 20 together with the opposing memory layer 30 and conductive layer 70 can be improved. Because the film thickness of the semiconductor layer 20 in the first narrow portion A and the second narrow portion B is larger, the discontinuity of the semiconductor layer 20 can be suppressed, thereby improving reliability and manufacturing yield.

[0090] <Second Implementation>

[0091] [Composition of a memory cell array]

[0092] use Figure 16 The storage cell array 1A of the second embodiment and its manufacturing method will be described. Except for the shape of the columnar body portion CL, the storage cell array 1A of the second embodiment is the same as the storage cell array 1 of the first embodiment. In the following description, the configuration and manufacturing method that are the same as those of the first embodiment will be omitted; the configuration and manufacturing method that are different from those of the first embodiment will be mainly described.

[0093] Figure 16 This is a schematic cross-sectional view of the storage cell array 1A according to the second embodiment. (See attached image.) Figure 16 As shown, the columnar body portion CL of this embodiment does not have the second widened portion b and the second narrowed portion B.

[0094] The columnar portion CL has a first narrow portion A at the boundary between the lower laminate 120 and the upper laminate 140, which has a smaller width (diameter, distance between outer surfaces) in the X direction. The first narrow portion A is adjacent to a second region facing the conductive layer 70 of the upper laminate 140. The first narrow portion A faces the insulating layer 40a at the boundary between the lower laminate 120 and the upper laminate 140. In the columnar portion CL, the width of the first narrow portion A in the X direction may also be smaller than the width of the second region facing the conductive layer 70 of the upper laminate 140 in the X direction. In the columnar portion CL, the width of the first narrow portion A in the X direction may also be smaller than the width of the first region facing the conductive layer 70 of the lower laminate 120 in the X direction.

[0095] The columnar portion CL has a first widened portion a, which is wider in the X direction at the boundary between the lower laminate 120 and the upper laminate 140. The first widened portion a is adjacent to the first narrowed portion A. The first widened portion a and the insulating layer 40a at the boundary between the lower laminate 120 and the upper laminate 140 face each other. In the columnar portion CL, the width of the first widened portion a in the X direction is greater than the width of the first narrowed portion A in the X direction. In the columnar portion CL, the width of the first widened portion a in the X direction is greater than the width of the second region facing the conductive layer 70 of the upper laminate 140 in the X direction. In the columnar portion CL, the width of the first widened portion a in the X direction is greater than the width of the first region facing the conductive layer 70 of the lower laminate 120 in the X direction.

[0096] The columnar portion CL has a third region (connection portion) that is adjacent to the first widened portion a and has a larger width in the X direction on the substrate 10 side of the first widened portion a. The third region and the insulating layer 40a at the boundary between the lower laminate 120 and the upper laminate 140 face each other. In the columnar portion CL, the width of the third region in the X direction is greater than the width of the first narrow portion A in the X direction. In the columnar portion CL, the width of the third region in the X direction is greater than the width of the second region facing the conductive layer 70 of the upper laminate 140 in the X direction. In the columnar portion CL, the width of the third region in the X direction is greater than the width of the first region facing the conductive layer 70 of the lower laminate 120 in the X direction.

[0097] The memory layer 30 is cylindrically disposed on the side of the columnar portion CL. The outer surface of the memory layer 30 (the surface in contact with the alternately stacked conductive layer 70 and insulating layer 40) reflects the shape of the CL side. The inner surface of the memory layer 30 (the surface in contact with the semiconductor layer 20) also reflects the shape of the CL side. That is, the memory layer 30 has a first narrow portion A with a smaller outer width (outer diameter, distance between opposing outer surfaces) in the X direction at the boundary between the lower stacked layer 120 and the upper stacked layer 140. The memory layer 30 has a first widened portion a with a larger outer width in the X direction at the boundary between the lower stacked layer 120 and the upper stacked layer 140. The memory layer 30 has a third region adjacent to the first widened portion a and with a larger outer width in the X direction on the substrate 10 side of the first widened portion a. The size relationship of the outer width of the first widened portion a, the first narrowed portion A, the first region, the second region, and the third region of the memory layer 30 in the X direction is the same as the size relationship of the width of the first widened portion a, the first narrowed portion A, the first region, the second region, and the third region of the columnar portion CL in the X direction, so the description is omitted here.

[0098] The shortest distance (film thickness) between the outer surface of the memory layer 30 (the surface in contact with the alternately stacked conductive layer 70 and insulating layer 40) and the inner surface of the memory layer 30 (the surface in contact with the semiconductor layer 20) is approximately the same across the entire surface. In other words, the film thickness of the memory layer 30 is formed with a substantially uniform thickness, regardless of the shape of the opening MH and the columnar portion CL.

[0099] Semiconductor layer 20 is disposed in a bottomed cylindrical shape, in contact with the inner side of memory layer 30 and epitaxial growth layer 60. The outer side of semiconductor layer 20 (the side in contact with memory layer 30) reflects the shape of the CL side. The inner side of semiconductor layer 20 (the side in contact with core layer 50) also reflects the shape of the CL side. That is, semiconductor layer 20 has a first narrow portion A at the boundary between lower stacked layer 120 and upper stacked layer 140, with a smaller outer width (outer diameter, distance between opposing outer sides) in the X direction. Semiconductor layer 20 has a first widened portion a at the boundary between lower stacked layer 120 and upper stacked layer 140, with a larger outer width in the X direction. Semiconductor layer 20 has a third region adjacent to the first widened portion a and on the substrate 10 side of the first widened portion a, with a larger outer width in the X direction. The size relationship of the outer width of the first widened portion a, the first narrowed portion A, the first region, the second region, and the third region of the semiconductor layer 20 in the X direction is the same as the size relationship of the width of the first widened portion a, the first narrowed portion A, the first region, and the second region of the columnar body portion CL in the X direction, so the description is omitted here.

[0100] The shortest distance (film thickness) between the outer surface (the surface in contact with the memory layer 30) and the inner surface (the surface in contact with the core layer 50) of the semiconductor layer 20 differs in the first widening portion a, the first narrowing portion A, the first region, the second region, and the third region. The film thickness of the semiconductor layer 20 in the first region and the second region is smaller than that in the first widening portion a, the first narrowing portion A, and the third region. The minimum film thickness of the semiconductor layer 20 in the first widening portion a, the first narrowing portion A, and the third region can also be larger than that in the first region and the second region. By making the film thickness of the semiconductor layer 20 in the first region and the second region smaller, the semiconductor layer 20 can improve the characteristics of the memory cell MC formed together with the opposing memory layer 30 and the conductive layer 70. Because the semiconductor layer 20 in the first widened portion a, the first narrow portion A, and the third region has a larger film thickness, it can suppress the discontinuity of the semiconductor layer 20, thereby improving reliability and manufacturing yield.

[0101] In this embodiment, the following example is shown: the film thickness of the semiconductor layer 20 facing all conductive layers 70 in regions I and II is smaller than the film thickness of the semiconductor layer 20 in regions I widening a, I narrowing A, and III. However, this is not a limitation; in variations, as described later, the film thickness of the semiconductor layer 20 facing the conductive layer 70 above the uppermost layer of region I and / or below the lowermost layer of region II near the first narrowing A may be approximately the same as the film thickness of the semiconductor layer 20 in region I narrowing A.

[0102] The core layer 50 is cylindrically disposed in contact with the inner surface of the semiconductor layer 20. The outer surface of the core layer 50 (the surface in contact with the semiconductor layer 20) reflects the shape of the CL side surface. That is, the core layer 50 has a first narrow portion A with a small outer width (outer diameter, distance between opposing outer surfaces) in the X direction at the boundary between the lower laminate 120 and the upper laminate 140. The core layer 50 has a first widened portion a with a larger outer width in the X direction at the boundary between the lower laminate 120 and the upper laminate 140. The core layer 50 has a third region adjacent to the first widened portion a and with a larger outer width in the X direction on the substrate 10 side of the first widened portion a. The width relationship of the first widened portion a, the first narrowed portion A, the first region, the second region, and the third region in the X direction of the core layer 50 is the same as that of the first widened portion a, the first narrowed portion A, the first region, the second region, and the third region in the X direction of the columnar body portion CL, so the description is omitted here.

[0103] Figure 18The following variation is illustrated: a conductive layer 70a is disposed between the lowest conductive layer 70 in region II and region III, and a conductive layer 70b is disposed between the uppermost conductive layer 70 in region I and region III. The memory cell array in this variation is identical to the memory cell array of the second embodiment, except for the conductive layers 70a and 70b. In the following description, descriptions of configurations and manufacturing methods identical to those of the second embodiment are omitted; the descriptions of configurations different from those of the second embodiment are primarily provided.

[0104] In this variation, a conductive layer 70a (third conductive layer) is disposed between the bottommost conductive layer 70 of region II and region III. The thickness of the semiconductor layer 20 opposite to the conductive layer 70a is approximately the same as the thickness of the semiconductor layer 20 in region III. The thickness of the semiconductor layer 20 opposite to the conductive layer 70a is greater than the thickness of the semiconductor layer 20 opposite to the conductive layers 70 in regions I and II. In this case, the first narrow portion A may also face the conductive layer 70a below the bottommost layer of region II. The memory cell MC including the semiconductor layer 20 opposite to the conductive layer 70a may not be intended to function as a memory cell MC.

[0105] In this variation, a conductive layer 70b is disposed between the uppermost conductive layer 70 in region I and region III. The thickness of the semiconductor layer 20 opposite to the conductive layer 70b is approximately the same as the thickness of the semiconductor layer 20 in region III. The thickness of the semiconductor layer 20 opposite to the conductive layer 70b is greater than the thickness of the semiconductor layer 20 opposite to the conductive layers 70 in regions I and II. The memory cell MC including the semiconductor layer 20 opposite to the conductive layer 70b may not necessarily function as a memory cell MC. This variation shows a memory cell array comprising conductive layers 70a and 70b. However, it is not limited to this and may also be configured to include only either conductive layer 70a or conductive layer 70b.

[0106] [Manufacturing Method of Memory Cell Array]

[0107] The manufacturing method of the memory cell array 1A in the second embodiment is the same as that of the memory cell array 1 in the first embodiment, except that the joint J is not formed, so it is omitted here.

[0108] According to the semiconductor memory device manufacturing method of this embodiment, by making the film thickness of the semiconductor layer 20 in the first region and the second region smaller, the semiconductor layer 20 can improve the characteristics of the memory cell MC formed together with the opposing memory layer 30 and conductive layer 70. Because the film thickness of the semiconductor layer 20 in the first widened portion a, the first narrowed portion A, and the third region is larger, the discontinuity of the semiconductor layer 20 can be suppressed, thereby improving reliability and manufacturing yield.

[0109] The above has been referenced in the appendix. Figure 1 While this invention is being described, it is not limited to the embodiments described herein. Appropriate modifications can be made without departing from the spirit of the invention. For example, those skilled in the art can add, delete, or modify constituent elements or designs based on the semiconductor memory device of this embodiment; such modifications are also included within the scope of the invention as long as they retain the spirit of the invention. Furthermore, the various embodiments can be appropriately combined as long as they do not contradict each other. Technical matters common to all embodiments, even if not explicitly described, are included in each embodiment.

[0110] It should be understood that any effect other than that brought about by the various embodiments described herein, as long as it is clear from the description in this specification or can be reasonably conceived by those skilled in the art, is of course brought about by the present invention.

Claims

1. A semiconductor memory device comprising: Semiconductor substrate; The first stacked body is formed by alternately stacking a plurality of first insulating layers and a plurality of first conductive layers in a first direction intersecting with the surface of the semiconductor substrate; The second laminate is disposed in the first direction of the first laminate, and is formed by alternately depositing a plurality of second insulating layers and a plurality of second conductive layers in the first direction; A third insulating layer is disposed between the first laminate and the second laminate, and its thickness is greater than that of the first insulating layer and the second insulating layer. The columnar body has a semiconductor layer and a charge storage layer. The semiconductor layer is disposed through the first stacked body, the third insulating layer, and the second stacked body, and extends in the first direction. The charge storage layer is disposed between the plurality of first conductive layers and the semiconductor layer, and between the plurality of second conductive layers and the semiconductor layer, and extends in the first direction. The columnar portion has a first region facing one of the plurality of first conductive layers, and a connecting portion facing the third insulating layer; and The width of the connecting portion in the second direction, which is orthogonal to the first direction, is greater than the width in the second direction in the first region; The thickness of the semiconductor layer at the connection is greater than that in the first region.

2. The semiconductor memory device according to claim 1, wherein The columnar portion has a second region facing one of the plurality of second conductive layers; and The width of the connecting portion in the second direction is greater than the width of the second region in the second direction.

3. The semiconductor memory device according to claim 2, wherein... The thickness of the semiconductor layer at the connection is greater than that in the second region.

4. The semiconductor memory device according to claim 3, wherein The minimum thickness of the semiconductor layer at the connection is greater than the thickness in the first region and the thickness in the second region.

5. The semiconductor memory device according to claim 2, wherein... The second laminate further includes a third conductive layer disposed between the lowest layer of the plurality of second conductive layers and the third insulating layer; and The thickness of the semiconductor layer in the third region opposite to the third conductive layer is greater than the thickness in the first region and the thickness in the second region.

6. The semiconductor memory device according to claim 1, wherein The columnar portion, together with the first conductive layer and the second conductive layer, functions as a non-volatile memory string.

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