A low dark current image sensor pixel structure

Abstract

The present invention discloses a low dark current image sensor pixel structure, which includes a photodiode, a transfer transistor, a floating diffusion node, a reset transistor, a source follower transistor, a row selection transistor, a power supply, and a pixel output disposed in a semiconductor substrate; a reverse PN junction isolation 301 is adopted between adjacent photodiodes, and a trapezoidal shallow trench isolation 205 is added between the photodiodes, so that stress is concentrated in the obtuse angle structure formed at the four corners of the photodiode. By optimizing the pixel layout design, and in the pixel process, a low-stress silicon nitride film is used to replace the high-stress silicon nitride film and the thickness of the silicon nitride film is reduced to reduce the stress on the photodiode. The dislocation defects caused by high stress in the active region of the photodiode are reduced, thereby reducing the dark current generated by the pixel and improving the performance of the image sensor.

Description

Technical Field

[0001] The present invention relates to a CMOS image sensor, and more particularly to a pixel structure of a low dark current image sensor. Background Art

[0002] CMOS image sensors are widely used in portable digital cameras, mobile phones, intelligent vehicles, security, and medical fields. In most of these applications, advanced performance such as wide dynamic range, high speed, and high sensitivity is required.

[0003] As Figure 1 shown, an image sensor pixel is composed of a photodiode (PD), a transfer transistor (TX), a floating diffusion node (FD), a reset transistor (RESET), a source follower transistor (SF), a row selection transistor (SELECT), a power supply (VDD), and a pixel output (VOUT) in a semiconductor substrate. Multiple photodiodes and each transistor need to adopt a STI (Shallow Trench Isolation) isolation structure or a reverse PN junction isolation structure to reduce the leakage current and crosstalk between each device circuit.

[0004] When using the STI (Shallow Trench Isolation) isolation structure to isolate adjacent photodiodes, during the STI trench etching process, silicon will be damaged, and the formed defects will generate a relatively high dark current, reducing the dynamic range of the image sensor.

[0005] Using partial STI (Partial Shallow Trench Isolation) and a reverse PN junction isolation structure between adjacent photodiodes can reduce the area of STI trench etching. However, the partial STI isolation structure will form a high stress region between the photodiode and other transistors.

[0006] As Figure 5 shown, when there are lattice defects caused by, for example, ion implantation or silicon itself mismatch in the high stress region, dislocation defects will be formed, and continuous high stress regions will form more dislocation defects, generating a relatively high dark current and reducing the dynamic range of the image sensor.

[0007] In view of this, the present invention is specifically proposed. Summary of the Invention

[0008] The object of the present invention is to provide a pixel structure of a low dark current image sensor to solve the above technical problems existing in the prior art.

[0009] The object of the present invention is achieved by the following technical solutions:

[0010] The pixel structure of the low dark current image sensor of the present invention includes a photodiode 101, a transfer transistor 102, a floating diffusion node 103, a reset transistor 104, a source follower transistor 106, a row select transistor 107, a power supply 105, and a pixel output 108 disposed in a semiconductor substrate;

[0011] There are multiple photodiodes. Reverse PN junction isolation 301 is used between adjacent photodiodes, and a trapezoidal shallow trench isolation 205 is added between the photodiodes, so that stress is concentrated in the obtuse angle structure formed at the four corners of the photodiode.

[0012] Compared with the prior art, the pixel structure of the low dark current image sensor provided by the present invention reduces the stress generated by STI etching, reduces the stress around the photodiode, and reduces the dislocation defects of the photodiode. Description of the Drawings

[0013] Figure 1 It is a circuit diagram of a 4-transistor active pixel (4T-APS) for a CMOS image sensor

[0014] 101: Photodiode (PD)

[0015] 102: Transfer gate transistor (TX)

[0016] 103: Floating diffusion node (FD)

[0017] 104: Reset transistor (RESET)

[0018] 105: Power supply (VDD)

[0019] 106: Source follower transistor (SF)

[0020] 107: Row select transistor (SEL)

[0021] 108: Pixel output (Vout)

[0022] Figure 2 It is a stress distribution diagram of a shallow trench isolated photodiode

[0023] 201: Photodiode 1 (PD1)

[0024] 202: Photodiode 2 (PD2)

[0025] 203: Photodiode 3 (PD3)

[0026] 204: Photodiode 4 (PD4)

[0027] 205: Shallow trench isolation (STI)

[0028] 206: High stress region

[0029] Figure 3 Is the stress distribution diagram of the reverse PN junction isolated photodiode

[0030] 201: Photodiode 1 (PD1)

[0031] 202: Photodiode 2 (PD2)

[0032] 203: Photodiode 3 (PD3)

[0033] 204: Photodiode 4 (PD4)

[0034] 206: High stress region

[0035] 301: Reverse PN junction isolation

[0036] Figure 4 Is the stress distribution diagram of the photodiode in this embodiment

[0037] 201: Photodiode 1 (PD1)

[0038] 202: Photodiode 2 (PD2)

[0039] 203: Photodiode 3 (PD3)

[0040] 204: Photodiode 4 (PD4)

[0041] 206: High stress region

[0042] 301: Reverse PN junction isolation

[0043] Figure 5 Is the schematic diagram of dislocation defects; (a) continuous high stress region, (b) discontinuous high stress region;

[0044] 206: High stress region

[0045] 501: Silicon substrate

[0046] 502: Lattice defect

[0047] 503: Low stress region

[0048] 504: Dislocation defect

[0049] Figure 6 Is the schematic diagram of the shallow trench isolation etching mask layer; (a) shallow trench isolation etching mask layer of the traditional process, (b) shallow trench isolation etching mask layer of the process of this embodiment;

[0050] 501 Silicon substrate

[0051] 601. Buffer Oxide

[0052] 602 High stress hard mask

[0053] 603 Buffer Poly Silicon

[0054] 604 Low stress hard mask;

[0055] Figure 7 is a schematic cross - section view of shallow trench isolation etching; (a) Cross - section view of shallow trench isolation etching in traditional process, (b) Cross - section view of shallow trench isolation etching in this embodiment;

[0056] 205 Shallow Trench Isolation (STI);

[0057] 501 Silicon Substrate

[0058] 601. Buffer Oxide

[0059] 602 High stress hard mask

[0060] 603 Buffer Poly Silicon

[0061] 604 Low stress hard mask Detailed implementation manners

[0062] Next, in combination with the accompanying drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described; Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments, which does not constitute a limitation to the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0063] First, the terms that may be used in this article are described as follows:

[0064] The term "and / or" means that either one of the two or both can be realized. For example, X and / or Y means that it includes both the case of "X" or "Y" and the three cases of "X and Y".

[0065] Descriptions with terms such as "comprising", "including", "containing", "having" or other similar semantics shall be construed as non-exclusive inclusion. For example: including a certain technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article, etc.) shall be construed as not only including the explicitly listed certain technical feature element, but also including other technical feature elements well-known in the art that are not explicitly listed.

[0066] The term "consisting of" means excluding any technical feature element that is not explicitly listed. If this term is used in a claim, then this term will make the claim a closed type, making it not contain technical feature elements other than the explicitly listed ones, except for conventional impurities related thereto. If this term only appears in a certain clause of a claim, then it only limits the elements explicitly listed in that clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0067] Unless otherwise explicitly specified or limited, terms such as "installed", "connected", "joined", "fixed", etc. shall be understood in a broad sense. For example: it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this article can be understood according to specific circumstances.

[0068] The orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of description and simplification of the description, rather than explicitly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to this article.

[0069] The content not described in detail in the embodiments of the present invention belongs to the prior art well-known to those of ordinary skill in the art. For those conditions not specified in the embodiments of the present invention, they shall be carried out according to the conventional conditions in the art or the conditions recommended by the manufacturer. For the reagents or instruments not indicating the manufacturer in the embodiments of the present invention, they are all conventional products that can be obtained through commercial purchase.

[0070] The pixel structure of the low dark current image sensor of the present invention includes a photodiode 101, a transfer transistor 102, a floating diffusion node 103, a reset transistor 104, a source follower transistor 106, a row select transistor 107, a power supply 105, and a pixel output 108 disposed in a semiconductor substrate;

[0071] There are multiple photodiodes, and reverse PN junction isolation 301 is used between adjacent photodiodes, and trapezoidal shallow trench isolation 205 is added between the photodiodes to concentrate stress in the obtuse angle structure formed at the four corners of the photodiode.

[0072] In the isolation structure between adjacent photodiodes, reverse PN junction isolation 301 is used in the middle, and trapezoidal shallow trench isolation 205 is used at both ends. The trapezoidal shallow trench isolation 205 at both ends forms an obtuse angle structure at the four corners of the photodiode.

[0073] During the process of shallow trench isolation etching, a hard mask layer process is used. The hard mask layer is a chemical vapor deposited silicon nitride thin film, including a buffer oxide layer 601, a buffer polysilicon layer 603, and a low stress hard mask layer 604 sequentially covering a silicon substrate 501.

[0074] During the deposition of the low stress hard mask layer 604, by adjusting the ratio of reaction gases, the ratio of DSC to NH3 is 5:1 to obtain a low stress silicon nitride thin film with a stress of 200 MPa.

[0075] The thickness of the buffer oxide layer 601 is 11 nm, the thickness of the buffer polysilicon layer 603 is 50 nm, and the thickness of the low stress hard mask layer 604 is 75 nm.

[0076] In summary, the pixel structure of the low dark current image sensor in the embodiment of the present invention reduces the stress generated by STI etching, reduces the stress around the photodiode, and reduces the dislocation defects of the photodiode.

[0077] In order to more clearly show the technical solutions provided by the present invention and the technical effects produced, the following uses specific embodiments to describe in detail what is provided in the embodiments of the present invention.

[0078] Embodiment 1

[0079] The pixel structure design and its preparation method of the low dark current of the present invention are as Figure 1 shown:

[0080] The pixel structure at least includes a photodiode (PD), a transfer transistor (TX), a floating diffusion node (FD), a reset transistor (RESET), a source follower transistor (SF), a row selection transistor (SELECT), a power supply (VDD), and a pixel output (VOUT) disposed in a semiconductor substrate. In this embodiment, by optimizing the pixel layout design and using a low-stress silicon nitride (SiN) thin film to replace the high-stress silicon nitride thin film and reducing the thickness of the silicon nitride thin film in the pixel manufacturing process, the stress on the photodiode (PD) is reduced. The dislocation defects caused by the high stress in the active area of the photodiode are reduced, thereby reducing the dark current generated by the pixel and improving the performance of the image sensor.

[0081] As Figure 2 shown, using shallow trench isolation for adjacent photodiodes only forms high-stress regions at the four corners, but the shallow trench isolation in the middle of the photodiode will be damaged during the etching process, forming defects that cause a relatively high dark current in the pixel circuit.

[0082] As Figure 3 shown, using reverse PN junction isolation for adjacent photodiodes avoids the damage caused during the shallow trench isolation etching process, but a continuous high-stress region is formed around the photodiode. After ion implantation and high-temperature annealing, dislocation defects are more likely to form, resulting in a relatively high dark current in the pixel circuit.

[0083] As Figure 4 shown, in this embodiment, reverse PN junction isolation is still used between adjacent photodiodes to avoid the damage caused during the shallow trench isolation etching process. And a trapezoidal shallow trench isolation is added in the middle of the photodiode to concentrate the stress in the obtuse-angle structure formed at the four corners of the photodiode, avoiding the formation of a continuous high-stress region, reducing the formation of dislocation defects, and reducing the dark current generated by the pixel circuit.

[0084] As Figure 6 、 Figure 7 shown, a hard mask layer process will be used during the shallow trench isolation etching process. The hard mask layer is a silicon nitride thin film deposited by chemical vapor deposition. In the traditional process, the ratio of the reaction gases DSC (dichlorosilane) and NH3 for generating the silicon nitride thin film is 1:4, and its stress is about 1200 MPa. In this embodiment, by adjusting the ratio of the reaction gases, the ratio of DSC (dichlorosilane) and NH3 is changed to 5:1 to obtain a low-stress silicon nitride thin film with a stress of about 200 MPa.

[0085] Due to the large lattice difference between silicon nitride (SiN) and the silicon substrate, significant stress will be formed on the surfaces of silicon nitride and silicon. Usually, an 11-nm buffer oxide layer is grown between the silicon nitride and the silicon substrate to reduce the stress on the silicon substrate. However, the buffer oxide layer is not sufficient to offset the stress brought by the hard mask layer, and the stress increases with the increase in the thickness of the hard mask layer. In this embodiment, the thickness of the silicon nitride is reduced to 75 nm to reduce the generation of stress. However, in order to avoid changes in the height of the shallow trench isolation after filling the oxide, which may cause changes in the electrical characteristics of each transistor. In this embodiment, on the 11-nm buffer oxide layer, 50 nm of polysilicon is first grown, and then 75 nm of low-stress silicon nitride is deposited. Without changing the overall thickness of the mask layer, the thickness of the hard mask layer is reduced, the stress on the photodiode is reduced, dislocation defects are reduced, and the dark current generated by the pixel circuit is reduced.

[0086] As described above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art.

Claims

1. A low dark current image sensor pixel structure, characterized in that, It includes a photodiode (101), a transfer transistor (102), a floating diffusion node (103), a reset transistor (104), a source follower transistor (106), a row strobe transistor (107), a power supply (105), and a pixel output (108) disposed in a semiconductor substrate; There are multiple photodiodes (101), and reverse PN junction isolation (301) is used between adjacent photodiodes, and trapezoidal shallow trench isolation (205) is added between the photodiodes, so that stress is concentrated in the obtuse angle structure formed at the four corners of the photodiode; In the isolation structure between adjacent photodiodes, reverse PN junction isolation (301) is used in the middle, and trapezoidal shallow trench isolation (205) is used at both ends. The trapezoidal shallow trench isolation (205) at both ends forms an obtuse angle structure at the four corners of the photodiode.

2. The low dark current image sensor pixel structure according to claim 1, wherein During the process of shallow trench isolation etching, a hard mask layer process is used. The hard mask layer is a chemically vapor deposited silicon nitride thin film, including a buffer oxide layer (601), a buffer polysilicon layer (603), and a low stress hard mask layer (604) sequentially covering a silicon substrate (501).

3. The low dark current image sensor pixel structure according to claim 2, wherein During the deposition of the low stress hard mask layer (604), by adjusting the ratio of reaction gases, the ratio of DSC to NH3 is 5:1 to obtain a low stress silicon nitride thin film with a stress of 200 MPa.

4. The low dark current image sensor pixel structure according to claim 3, characterized in that, The thickness of the buffer oxide layer (601) is 11 nm, the thickness of the buffer polysilicon layer (603) is 50 nm, and the thickness of the low stress hard mask layer (604) is 75 nm.

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