Semiconductor structure, manufacturing method of semiconductor structure and image sensor

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method of the semiconductor structure and an image sensor. The semiconductor structure comprises a substrate; a transmission gate formed on the surface of the substrate; the floating diffusion region and the transition doping region are formed in the substrate; wherein the transition doped region is located between the projection of the transmission gate on the substrate and the floating diffusion region; the doping concentration of the transition doping region is smaller than that of the floating diffusion region; the transition doped region comprises a first doped region and a second doped region which are formed based on an ion implantation process; the doping type of the first doping region is different from that of the floating diffusion region; the doping type of the second doped region is the same as that of the floating diffusion region; in the normal direction of the substrate, the ion implantation depth of the second doped region is larger than that of the first doped region. According to the embodiment of the invention, the occurrence of gate-induced drain leakage is reduced, and the imaging quality of the CMOS image sensor is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and specifically to a semiconductor structure, a method for manufacturing a semiconductor structure, and an image sensor. Background Art

[0002] A CMOS image sensor (CIS) is an image sensor device that integrates a photosensor, amplifier, analog-to-digital converter, memory, digital signal processor, and computer interface circuitry on a single silicon substrate. Due to its low power consumption, high performance, and ease of integration, CMOS image sensors are widely used in a variety of fields, including consumer electronics, security monitoring, driver assistance, and medical equipment.

[0003] The pixel array is a key component of a CMOS image sensor. The performance of each pixel in the pixel array has a significant impact on the overall imaging quality and resolution of the CMOS image sensor. Among the various pixel structures that make up the pixel array, the 4-transistor active pixel sensor (4T-APS) structure has been widely used in the design and manufacture of CMOS image sensors due to its advantages such as high integration, fast response, low power consumption, and low cost.

[0004] However, in a pixel array composed of an existing four-transistor active pixel structure, when the transistors are in an off or standby state, white pixels may be generated, thereby reducing the imaging quality of the CMOS image sensor. Summary of the Invention

[0005] In view of this, various embodiments of the present application provide a semiconductor structure, a method for manufacturing the semiconductor structure, and an image sensor to improve the imaging quality of a CMOS image sensor.

[0006] In one aspect, an embodiment of the present application provides a semiconductor structure comprising: a substrate; a transfer gate formed on the surface of the substrate; a floating diffusion region and a transition doping region formed within the substrate; wherein the transition doping region is located between a projection of the transfer gate on the substrate and the floating diffusion region; the doping concentration of the transition doping region is less than the doping concentration of the floating diffusion region; the transition doping region comprises a first doping region and a second doping region formed based on an ion implantation process; the doping type of the first doping region is different from the doping type of the floating diffusion region; the doping type of the second doping region is the same as the doping type of the floating diffusion region; along the normal direction of the substrate, the ion implantation depth of the second doping region is greater than the ion implantation depth of the first doping region.

[0007] Optionally, the semiconductor structure also includes: a first gate sidewall formed on the side of the transfer gate and the surface of the substrate; wherein the first gate sidewall is made of a different material from the substrate; a second gate sidewall formed on a side of the first gate sidewall away from the transfer gate and away from the substrate; and the first doped region exists between the projection of the second gate sidewall on the substrate and the floating diffusion region.

[0008] Optionally, the transmission gate includes a first gate doping region and a second gate doping region; wherein, the direction perpendicular to the normal direction of the substrate is used as the width direction of the transmission gate, and along the width direction of the transmission gate, the first gate doping region is located between the second gate doping region and the first gate side wall; the doping type of the first gate doping region is different from the doping type of the second gate doping region.

[0009] Optionally, the transmission gate includes a third gate doping region; in the third gate doping region, the doping concentration of a region closer to the first gate sidewall is lower.

[0010] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method for manufacturing the semiconductor structure comprising: providing a substrate; forming a transfer gate on the surface of the substrate; performing ion implantation on the substrate to form a floating diffusion region and a transition doping region in the substrate to obtain the semiconductor structure; wherein the transition doping region is located between a projection of the transfer gate on the substrate and the floating diffusion region; the doping concentration of the floating diffusion region is greater than the doping concentration of the transition doping region; the transition doping region comprises a first doping region and a second doping region formed based on an ion implantation process; the doping type of the first doping region is different from the doping type of the floating diffusion region; the doping type of the second doping region is the same as the doping type of the floating diffusion region; along the normal direction of the substrate, the ion implantation depth of the second doping region is greater than the ion implantation depth of the first doping region.

[0011] Optionally, the semiconductor structure further includes a first gate sidewall and a second gate sidewall; ion implantation is performed on the substrate to form a floating diffusion region and a transition doping region in the substrate, and the steps of obtaining the semiconductor structure include: performing a first ion implantation on the substrate; forming the first gate sidewall on the surface of the transfer gate and the surface of the substrate; wherein the material of the first gate sidewall is different from that of the substrate; performing at least two second ion implantations on the substrate; wherein the implanted ion type of the second ion implantation is different from the implanted ion type of the first ion implantation; the implantation depth of the second ion implantation is greater than the implantation depth of the first ion implantation; and the at least two second ion implantations are performed. The implantation depths of the sub-implantations are different; the substrate is annealed; the second gate sidewall is formed on the side of the first gate sidewall away from the transfer gate and away from the substrate; a third ion implantation is performed on the substrate to form the floating diffusion region on the side of the projection of the second gate sidewall away from the projection of the transfer gate on the substrate, and a first doped region and a second doped region are formed between the floating diffusion region and the projection of the transfer gate on the substrate to obtain the semiconductor structure; wherein the implantation ion type of the third ion implantation is the same as the implantation ion type of the second ion implantation; and the implantation dose of the third ion implantation is greater than the implantation dose of the second ion implantation.

[0012] Optionally, the method further includes: after the floating diffusion region is formed, performing a fourth ion implantation into the substrate so that the second doping region exists between the projection of the second gate side wall on the substrate and the floating diffusion region; wherein the implantation ion type of the fourth ion implantation is the same as the implantation ion type of the third ion implantation; and the implantation energy of the fourth ion implantation is less than the implantation energy of the second ion implantation and greater than the implantation energy of the first ion implantation.

[0013] Optionally, the step of forming a transfer gate on the surface of the substrate includes: forming a first transition gate on the surface of the substrate; performing a first gate ion implantation on the first transition gate to form a first gate doping region; wherein the first gate ion implantation on the first transition gate and the first ion implantation on the substrate are completed in the same process step; performing a second gate ion implantation on the first transition gate to form a second gate doping region to obtain the transfer gate; wherein the implantation ion type of the second gate ion implantation is different from the implantation ion type of the first gate ion implantation; taking the direction perpendicular to the normal direction of the substrate as the width direction of the transfer gate, along the width direction of the transfer gate, the first gate doping region is located between the second gate doping region and the first gate side wall.

[0014] Optionally, the step of forming a transfer gate on the surface of the substrate includes: forming a gate material layer on the surface of the substrate; performing a third gate ion implantation into the gate material layer based on a gate ion implantation mask; etching and removing a portion of the gate material layer based on a gate etch mask to form a second transition gate; wherein the etching barrier size of the gate etch mask is larger than the injection opening size of the gate ion implantation mask; annealing the second transition gate to form the transfer gate; wherein the transfer gate includes a third gate doping region; in the third gate doping region, the closer the region is to the first gate side wall, the lower the doping concentration.

[0015] In yet another aspect, an embodiment of the present application provides an image sensor, comprising the semiconductor structure as described in the above embodiment or a semiconductor structure manufactured according to the method for manufacturing the semiconductor structure as described in the above embodiment.

[0016] In multiple embodiments provided in the present application, a transition doping region is formed between a projection of the substrate and a floating diffusion region by a transfer gate on the surface of the substrate, wherein the doping concentration of the transition doping region is less than the doping concentration of the floating diffusion region, and the transition doping region includes a first doping region and a second doping region formed based on an ion implantation process, the doping type of the first doping region is different from the doping type of the floating diffusion region, the doping type of the second doping region is the same as the doping type of the floating diffusion region, and, along the normal direction of the substrate, the ion implantation depth of the second doping region is greater than the ion implantation depth of the first doping region, and the unexpected effects achieved include: since in the transition doping region, the ion implantation depth of the first doping region, which is different from the doping type of the floating diffusion region, is less than the ion implantation depth of the second doping region, which is the same as the doping type of the floating diffusion region, the first doping region can be used to push the depletion region from the substrate surface to the interior of the substrate, thereby optimizing the electric field distribution on the substrate surface, thereby reducing the occurrence of gate-induced drain leakage, and improving the imaging quality of the CMOS image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A circuit connection diagram of a four-tube active pixel structure provided for related technology.

[0019] Figure 2 A schematic diagram of the structure of the transmission part in the existing four-tube active pixel structure provided in the related technology.

[0020] Figure 3 A schematic diagram of the structure of the transmission part in the improved four-tube active pixel structure provided in the related technology.

[0021] Figure 4 A schematic diagram of forming an N-type ion implantation region provided in the related art.

[0022] Figure 5 A schematic diagram of forming a lightly doped region provided for related technology.

[0023] Figure 6 for Figure 2 Enlarged schematic diagram of the local electric field distribution in the area within the dotted circle.

[0024] Figure 7 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0025] Figure 8 A schematic structural diagram of the substrate provided in an embodiment of the present application.

[0026] Figure 9 A schematic diagram of a process for forming a transmission gate on a substrate surface is provided for one embodiment of the present application.

[0027] Figure 10 A schematic diagram of forming a first transition gate on a substrate surface according to an embodiment of the present application.

[0028] Figure 11 A schematic diagram of performing a first ion implantation on a substrate according to an embodiment of the present application.

[0029] Figure 12 A schematic diagram of forming a second gate doping region and a first ion implantation region provided in one embodiment of the present application.

[0030] Figure 13 A schematic diagram of a process for forming a transmission gate on a substrate surface according to another embodiment of the present application is provided.

[0031] Figure 14 A schematic diagram of forming a gate material layer on a substrate surface according to another embodiment of the present application.

[0032] Figure 15 A schematic diagram of forming a gate injection region in a gate material layer according to another embodiment of the present application is provided.

[0033] Figure 16 A schematic diagram of forming a second transition gate according to another embodiment of the present application.

[0034] Figure 17 A schematic diagram of forming a second transmission gate according to another embodiment of the present application.

[0035] Figure 18 A schematic diagram of a process for performing ion implantation on a substrate to form a floating diffusion region and a transition doping region in the substrate is provided in accordance with one embodiment of the present application.

[0036] Figure 19 A schematic diagram of performing a first ion implantation into a substrate according to another embodiment of the present application.

[0037] Figure 20 A schematic diagram of forming a first gate sidewall spacer based on a first transfer gate according to an embodiment of the present application.

[0038] Figure 21 A schematic diagram of forming a first gate spacer based on a second transfer gate according to another embodiment of the present application.

[0039] Figure 22 A schematic diagram of forming a second ion implantation region according to an embodiment of the present application.

[0040] Figure 23 A schematic diagram of forming a second ion implantation region according to another embodiment of the present application.

[0041] Figure 24 A schematic diagram of annealing a substrate having a second ion implantation region formed therein is provided in accordance with an embodiment of the present application.

[0042] Figure 25 A schematic diagram of annealing a substrate having a second ion implantation region formed therein is provided in accordance with another embodiment of the present application.

[0043] Figure 26 A schematic diagram of forming a second gate spacer based on a first transfer gate according to an embodiment of the present application.

[0044] Figure 27 A schematic diagram of forming a second gate spacer based on a second transfer gate according to another embodiment of the present application.

[0045] Figure 28 A schematic diagram of forming a floating diffusion region according to an embodiment of the present application.

[0046] Figure 29 A schematic diagram of forming a floating diffusion region according to another embodiment of the present application.

[0047] Figure 30 A schematic diagram of forming a first doping region and a second doping region provided in one embodiment of the present application.

[0048] Figure 31 A schematic diagram of forming a first doping region and a second doping region provided in another embodiment of the present application.

[0049] Figure 32 A schematic structural diagram of a first semiconductor structure provided in one embodiment of the present application.

[0050] Figure 33 A schematic structural diagram of a second semiconductor structure provided in another embodiment of the present application.

[0051] Figure 34 A schematic diagram of forming a second ion implantation region according to an embodiment of the present application.

[0052] Figure 35 A schematic diagram of forming a transitional doping region provided in one embodiment of the present application.

[0053] Figure 36 for Figure 32 Enlarged schematic diagram of the local electric field distribution in the area within the dotted circle.

[0054] Structural label description 1. Clamped photodiode; 2. Floating diffusion region; 3. Reset transistor; 4. Transfer transistor; 5. Source follower transistor; 6. Select transistor; 7. P-type heavily doped region; 100. Transfer portion of existing four-tube active pixel structure; 100a. Transfer portion of improved four-tube active pixel structure; 101. P-type doped silicon substrate; 102. P-type well region; 103. Floating diffusion doped region; 104. Photodiode doped region; 105. Shallow trench isolation structure; 106. Pinning layer; 107. Lightly doped region; 107a. N-type ion implantation region; 111. First sidewall spacer; 112. Second sidewall spacer; 113. Gate; 114. Oxide layer; 200. First semiconductor structure; 201. Substrate; 202. Doped well region; 203. Photodiode; 204. Isolation structure ; 205, heavily doped region; 2061, first ion implantation region; 2062, second ion implantation region; 207, floating diffusion region; 208, transition doped region; 2081, first doped region; 2082, second doped region; 211, gate oxide layer; 212, first transition gate; 213, first transfer gate; 2131, first gate doped region; 2132, second gate doped region; 2133, gate implantation region; 214, gate material layer; 215, third gate doped region; 216, first gate sidewall; 217, second gate sidewall; 221, gate etching mask; 222, gate ion implantation mask; 223, second ion implantation mask; 224, third ion implantation mask; 224', fourth ion implantation mask; 300, second semiconductor structure. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0056] The drawings provided in the embodiments of the present application are only for schematic illustration of the basic concept of the present application. The drawings only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of its components may also be more complicated.

[0057] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0058] See also Figure 1 . In the related art, a four-tube active pixel structure may generally include two ion-doped regions for realizing photoelectric signal conversion and four transistors. Specifically, the two ion-doped regions may include a pinned photodiode (PPD) 1 for generating a photoelectric signal and a floating diffusion region (FD) 2 for temporarily storing the charge generated by the photodiode and converting the charge signal into a voltage signal. The four transistors may include a reset transistor 3 for resetting the photodiode and the floating diffusion region, a transfer transistor 4 for controlling the switch of the photogenerated charge transfer channel, that is, a transfer gate (TG), a source follower transistor 5 for caching and reading out the voltage signal of the floating diffusion region, and a select transistor 6 for realizing row selection output. A P-type heavily doped region 7 for stabilizing the working state of the clamped photodiode 1 is formed on one side of the clamped photodiode 1 close to the transfer transistor 4.

[0059] The working process of the four-tube active pixel structure can be decomposed into four stages: reset stage, integration stage, transfer stage and reading stage. In the reset stage, the reset transistor 3 is turned on, and the floating diffusion area 2 is reset to near the power supply voltage Vdd. In the integration stage, the reset transistor 3 is turned off, and the clamped photodiode 1 begins to accumulate photogenerated charge. In the transfer stage, the transfer transistor 4 is turned on, and the charge accumulated by the clamped photodiode 1 is transferred to the floating diffusion area 2. In the reading stage, the selection transistor 6 is turned on, and the source follower transistor 5 amplifies the voltage change of the floating diffusion area 2 and outputs it to the column line. The voltage change on the column line is collected by the readout circuit as the output voltage Vout and is finally converted into an image signal.

[0060] However, as the application scenarios of CMOS image sensors using a four-element active pixel structure continue to expand, researchers have discovered that in actual use, the images output by CMOS image sensors often contain abnormal bright spots that do not match the actual lighting conditions, resulting in a decrease in image clarity and accuracy. Analysis of the causes of this problem shows that in CMOS image sensors, some pixels may be converted into "white pixels" due to defects such as leakage. "White pixels" often exhibit abnormally high brightness, which appears as abnormal bright spots in the output image.

[0061] The researchers further explored the causes of "white pixels".

[0062] See also Figure 2 In the transmission portion 100 of the existing four-transistor active pixel structure, a P-type well region 102 for dividing the active area and a shallow trench isolation (STI) structure for isolating different pixel areas are formed within a P-type doped silicon substrate 101. An oxide layer 114 is formed on the surface of the P-type doped silicon substrate 101. The gate 113 of the transmission transistor is formed on the side of the oxide layer 114 away from the P-type doped silicon substrate 101. Specifically, within the active area divided by the P-type well region 102, a photodiode doped region 104, a floating diffusion doped region 103, a pinning layer 106 for achieving a pinning between the photodiode doped region 104 and the oxide layer 114, and a lightly doped region 107 for mitigating short channel effects are formed. The doping type of the photodiode doped region 104, the floating diffusion doped region 103, and the lightly doped region 107 can all be N-type, and the doping concentration of the lightly doped region 107 is lower than that of the floating diffusion doped region 103. The doping type of the pinning layer 106 may be P-type. A first spacer 111 and a second spacer 112 are sequentially formed on the side of the gate 113 of the transfer transistor. The first spacer 111 and the second spacer 112 are made of different materials.

[0063] During the experiment, the researchers found that when the transfer transistor is in the off or waiting state, there is a high voltage difference between the gate 113 of the transfer transistor and the floating diffusion doping region 103, that is, the gate-drain voltage V GD The high voltage leads to a strong electric field near the intersection of the transfer transistor's gate 113 and the floating diffusion doped region 103. This causes band-to-band tunneling (BTBT) between the valence band and the conduction band of electrons in the silicon between the projection of the transfer transistor's gate 113 on the P-type doped silicon substrate 101 and the floating diffusion doped region 103. This generates a current from the floating diffusion doped region 103 to the bulk region, triggering gate-induced drain leakage (GIDL). GIDL can increase the static power consumption of the transfer transistor and reduce its energy efficiency. It can also reduce the reliability of the transfer transistor, leading to the appearance of "white pixels."

[0064] In order to improve the gate-induced drain leakage problem of the transfer transistor, researchers have improved the structure of the transfer portion 100 of the existing four-transistor active pixel structure.

[0065] See also Figure 3 Taking the direction perpendicular to the normal direction of the P-type doped silicon substrate 101 as the width direction, the researchers increased the width of the second sidewall 112 along the width direction to increase the distance between the projection of the gate 113 of the transfer transistor on the P-type doped silicon substrate 101 and the floating diffusion doped region 103. That is, the width of the lightly doped region 107 along the width direction is increased, thereby reducing the voltage difference between the gate 113 of the transfer transistor and the floating diffusion doped region 103. Figure 2 and Figure 3 It can be seen that the width D2 of the lightly doped region 107 along the width direction in the transmission portion 100 a of the improved four-transistor active pixel structure is greater than the width D1 of the lightly doped region 107 along the width direction in the transmission portion 100 of the conventional four-transistor active pixel structure.

[0066] However, to meet the trend of thinner and lighter devices and smaller components, the size of CMOS image sensors is constantly shrinking. Forming a pixel array based on the improved four-pixel active pixel would increase the area occupied by the CMOS image sensor, making it difficult to meet the current size requirements of CMOS image sensors.

[0067] To improve the gate-induced drain leakage of the transfer transistor without increasing the size of the CMOS image sensor, researchers conducted the following analysis on the lightly doped region 107 in the transfer section 100 of the existing four-transistor active pixel structure.

[0068] Please also refer to Figure 4 and Figure 5 In the transmission portion 100 of the existing four-tube active pixel structure, the lightly doped region 107 is formed by the following process: first, using the first sidewall 111 as a mask, an ion implantation is performed into the P-type doped silicon substrate 101 to form an N-type ion implantation region 107a, and then annealing is performed to diffuse the N-type ion implantation region 107a to form a lightly doped region 107 with a shape approximately similar to an ellipse. Since the doping type of the lightly doped region 107 is N-type, which is different from the doping type of the P-type well region 102, a PN junction with an interface shape approximately similar to a spherical surface will be formed at the junction of the lightly doped region 107 and the P-type well region 102. At this time, the interface curvature of the PN junction is large, and the charge distribution is uneven. Accordingly, the electric field may be concentrated in the area with a larger curvature, resulting in a stronger local electric field in the area with a larger curvature.

[0069] See also Figure 6 . In addition, when the transfer transistor is in the off or waiting state, the voltage between the photodiode doping region and the floating diffusion doping region will form an electric field near the lightly doped region 107. Driven by the electric field force, the electrons and holes in the lightly doped region 107 move in different directions to form a depletion region with a width of W1. The boundary of the depletion region covers the interface plane P1 between the P-type doped silicon substrate 101 and the oxide layer 114. However, due to the limitations of the process quality of the oxide layer 114, there may be lattice defects such as vacancies and dislocations at the P1 plane. These lattice defects introduce defect energy levels in the band gap to form interface states. Analysis of the electric field distribution near the lightly doped region 107 shows that the electric field intensity near the P1 plane is greater than the electric field intensity near the internal plane P2 of the P-type doped silicon substrate 101. Therefore, under the action of a strong electric field, electrons and holes may undergo a band-to-band tunneling effect, move to the defect energy levels at the inner P1 plane, be captured and recombine, and cause leakage.

[0070] In summary, in the transmission part of the existing four-element active pixel structure, the shape of the lightly doped region and the electric field distribution near the lightly doped region may aggravate the gate-induced drain leakage problem.

[0071] Therefore, it is necessary to provide a semiconductor structure that can improve the gate-induced drain leakage of the transfer transistor without increasing the size of the CMOS image sensor.

[0072] See also Figure 7 One embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure may include steps S110, S120, and S130.

[0073] S110: providing a substrate.

[0074] See also Figure 8In this embodiment, the substrate may include a substrate 201, a doped well region 202 formed in the substrate 201, a photodiode 203, an isolation structure 204, and a heavily doped region 205. Detailed descriptions of various parts of the substrate are as follows.

[0075] In this embodiment, substrate 201 can serve as the foundation for the semiconductor structure. Specifically, substrate 201 can be made of semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, substrate 201 can be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), and silicon carbide (SiC). Substrate 201 can have a single-layer structure or a multi-layer structure. In this embodiment, a silicon wafer doped with P-type ions is used as substrate 201 to reduce the resistance of substrate 201, taking into account factors such as dielectric loss requirements, manufacturing process, and manufacturing cost.

[0076] In this embodiment, the doped well region 202 and isolation structure 204 can be used to define the range of the active area and achieve isolation between different pixels. Specifically, the locations of multiple isolation structures 204 can be first defined in the substrate 201, and the substrate material at these locations can be etched away. The grooves where the substrate material was removed are then filled with isolation material to form multiple isolation structures 204 spaced apart from each other. Subsequently, ion implantation can be performed in the spacing regions between adjacent isolation structures 204 to form doped well regions 202. The doping type of the doped well region 202 can be P-type, and the isolation material can be an oxide.

[0077] In this embodiment, the photodiode 203 can be used to achieve photoelectric conversion, and the heavily doped region 205 can be used to fix the potential on the surface of the photodiode 203 and to isolate the photodiode 203 from the structure on the substrate surface. Specifically, the doping type of the photodiode 203 and the doping type of the heavily doped region 205 can be different, and the doping concentration of the heavily doped region 205 can be greater than the doping concentration of the photodiode 203. For example, the doping type of the photodiode 203 can be N-type, and the doping type of the heavily doped region 205 can be P-type.

[0078] S120: forming a transmission gate on the surface of the substrate.

[0079] In this embodiment, the transfer gate can be used to control charge transfer between the photodiode and the floating diffusion region. Specifically, when a certain voltage is applied to the transfer gate, an electron transfer channel is formed between the photodiode and the floating diffusion region. When no voltage is applied to the transfer gate, the transfer gate can isolate the photodiode and the floating diffusion region, thereby reducing charge leakage or interference between the two.

[0080] During experiments and testing, researchers discovered that the coupling electric field strength between the transfer gate and the floating diffusion is affected not only by the distance between the transfer gate's projection on the substrate and the floating diffusion, but also by the resistance at the transfer gate's edge. Therefore, to reduce the coupling electric field strength between the transfer gate and the floating diffusion, the doping profile within the transfer gate can be altered during fabrication by adding an inversion-doped region or applying a gradient doping pattern. This increases the resistance at the transfer gate's edge and improves gate-induced drain leakage.

[0081] See also Figure 9 In this embodiment, the step of forming a transmission gate on the surface of the substrate may include sub-steps S1211, S1221 and S1231.

[0082] S1211: forming a first transition gate on the surface of the substrate.

[0083] See also Figure 10 To achieve electrical insulation between the transmission gate and the substrate, a gate oxide layer 211 can be formed on the substrate surface before forming the transmission gate. Subsequently, a gate material layer is formed on the side of the gate oxide layer 211 facing away from the substrate. Photolithography and etching processes are used to remove a portion of the gate material layer based on a gate etch mask 221 to form a first transition gate 212. Specifically, the gate oxide layer 211 can be made of silicon oxide (SiO2). The width of the gate etch mask 221 can be equal to the critical dimension (CD) of the transmission gate, perpendicular to the normal direction of the substrate. Therefore, the width of the formed first transition gate 212 can be equal to the CD of the transmission gate, and the projection of the first transition gate 212 on the substrate can partially overlap with the heavily doped region 205. To fully utilize the barrier effect of the gate etch mask 221, in this embodiment, after the first transition gate 212 is formed, the gate etch mask 221 on the side of the first transition gate 212 facing away from the substrate can be retained.

[0084] S1221: Performing a first gate ion implantation into the first transition gate to form a first gate doping region.

[0085] Please also refer to Figure 11 and Figure 12In order to reduce process costs and shorten processing time, the first gate ion implantation can be performed on the first transition gate 212 based on the retained gate etching mask 221, and by controlling the direction of the ion implantation, the first ion implantation of the substrate can be achieved in the same process step, thereby forming a first gate doping region 2131 at the side edge of the first transition gate 212 and forming a first ion implantation region 2061 in the substrate. Specifically, the implantation ion type of the first gate ion implantation and the first ion implantation can be P-type. For example, the implantation ions of the first gate ion implantation and the first ion implantation can be boron fluoride (BF2) ions, the ion implantation energy can be 10KeV, and the ion implantation dose can be 1.0×10 13 ions / cm², the rotation angle of ion implantation can be 30°, the tilt angle can be 0°, and the number of implantations can be 4.

[0086] S1231: Perform a second gate ion implantation on the first transition gate to form a second gate doping region to obtain a transmission gate.

[0087] Please continue reading Figure 12 . In order to enhance the conductivity of the transmission gate and reduce the overall resistance of the transmission gate, after the first gate doping region 2131 is formed, the second gate ion implantation can be performed on the first transition gate 212 as a whole, thereby forming the second gate doping region 2132 in the first transition gate 212 except for the side edge portion, and obtaining the first transmission gate 213. Specifically, the ion implantation dose of the second gate ion implantation can be greater than the ion implantation dose of the first gate ion implantation, and the implantation ion type of the second gate ion implantation is different from the implantation ion type of the first gate ion implantation. Therefore, the doping type of the second gate doping region 2132 is different from the doping type of the first gate doping region 2131. For example, when the implantation ion type of the first gate ion implantation is P-type, the implantation ion type of the second gate ion implantation can be N-type. The other process parameters used for the second gate ion implantation are the transmission gate ion implantation process parameters commonly used in the related art, which will not be repeated here.

[0088] Since the types of implanted ions in the two gate ion implantations are different and the ion implantation dose of the second gate ion implantation is greater than the ion implantation dose of the first gate ion implantation, during the second gate ion implantation process, part of the ions implanted into the side edge portion of the first transition gate 212 combines with part of the ions in the first gate doping region 2131 formed previously, so that the doping concentration of the formed second gate doping region 2132 is greater than the doping concentration of the first gate doping region 2131, that is, along the width direction, the doping concentration of the first transfer gate 213 gradually decreases from the center to the edge.

[0089] See also Figure 13In some embodiments, the step of forming a transfer gate on the substrate surface may include sub-steps S1212 , S1222 , S1232 , and S1242 .

[0090] S1212: forming a gate material layer on the surface of the substrate.

[0091] S1222: performing a third gate ion implantation into the gate material layer based on the gate ion implantation mask.

[0092] Please also refer to Figure 14 and Figure 15 . In this embodiment, the process of forming the gate oxide layer 211 and the gate material layer 214 is basically the same as the process of forming the gate oxide layer 211 and the gate material layer 214 in the above embodiment, and will not be repeated here. A third gate ion implantation can be performed on the gate material layer based on the gate ion implantation mask 222 to form a gate implantation region 2133 in the gate material layer 214. Specifically, taking the direction perpendicular to the normal direction of the substrate as the width direction, along the width direction, the injection opening size of the gate ion implantation mask 222 can be smaller than the critical size of the transfer gate, so that the width of the formed gate implantation region 2133 along the width direction is smaller than the critical size of the transfer gate, providing a basis for the subsequent formation of the second transfer gate gradient doping. The implanted ion type of the third gate ion implantation can be N-type. For example, the implanted ions of the third gate ion implantation can be phosphorus (P) ions, the ion implantation energy can be 10KeV, and the ion implantation dose can be 1.0×10 14 ions / cm², the rotation angle of ion implantation can be 0°, the tilt angle can be 0°, and the number of implantations can be 4.

[0093] S1232: etching away a portion of the gate material layer based on the gate etching mask to form a second transition gate.

[0094] See also Figure 16 . After the gate injection region 2133 is formed, part of the gate material layer 214 and the gate oxide layer 211 can be etched away based on the gate etching mask 221 to form a second transition gate. Specifically, along the width direction, since the injection opening size of the gate ion injection mask 222 is smaller than the critical size of the transmission gate, the etching barrier size of the gate etching mask 221 can be larger than the injection opening size of the gate ion injection mask 222, thereby forming a doping distribution in the second transition gate with a higher doping concentration in the center and a doping concentration close to zero in the side edge. The process parameters used to etch and remove part of the gate material layer 214 are the transmission gate etching process parameters commonly used in related technologies and will not be repeated here.

[0095] S1242: Annealing the second transition gate to form a transmission gate.

[0096] See also Figure 17 . In order to enhance the conductivity of the transmission gate and reduce the overall resistance of the transmission gate while maintaining a high resistance at the side edge of the transmission gate, the second transition gate can be annealed so that the doping ions in the gate injection region diffuse to the undoped side edge of the second transition gate, and then the gate etching mask on the surface of the second transition gate is removed to obtain the second transmission gate. Specifically, the second transmission gate may include a third gate doping region 215, that is, an ion doping region within the second transmission gate. In the third gate doping region 215, the doping concentration gradually decreases from the center to the edge along the width direction.

[0097] S130: performing ion implantation on the substrate to form a floating diffusion region and a transition doping region in the substrate to obtain a semiconductor structure.

[0098] In this embodiment, the floating diffusion region can be used to receive and temporarily store charges transmitted from the photodiode, and convert the received charges into a voltage signal.

[0099] In this embodiment, the transition doped region can be used to reduce the electric field strength near the floating diffusion region and suppress the short channel effect. Specifically, the transition doped region can be located between the projection of the transfer gate on the substrate and the floating diffusion region. The transition doped region can include a first doped region and a second doped region formed by an ion implantation process.

[0100] In this embodiment, the first doped region can be used to optimize the electric field distribution within the substrate when the transfer transistor is in an off or standby state. Specifically, the doping type of the first doped region can be different from the doping type of the floating diffusion region. For example, if the floating diffusion region is doped with N-type, the first doped region can be doped with P-type.

[0101] In this embodiment, the second doping region can be used to reduce the curvature of the PN junction interface near the floating diffusion region and improve the local electric field concentration at the PN junction interface. Specifically, the interface between the second doping region and the doped well region can be approximately plane. The doping type of the second doping region can be the same as the doping type of the floating diffusion region, and correspondingly, the doping type of the second doping region is different from the doping type of the first doping region. Moreover, along the normal direction of the substrate, the ion implantation depth of the second doping region is greater than the ion implantation depth of the first doping region, so that to a certain extent, the first doping region can be used to isolate the second doping region and the gate oxide layer on the surface of the substrate, and the depletion region near the floating diffusion region can be pushed away from the interface plane between the substrate and the gate oxide layer on the surface of the substrate, thereby reducing the occurrence of the band-to-band tunneling effect.

[0102] See also Figure 18In this embodiment, the step of performing ion implantation on the substrate to form a floating diffusion region and a transition doping region in the substrate may include sub-steps S131 , S132 , S133 , S134 , S135 and S136 .

[0103] S131: performing a first ion implantation into the substrate.

[0104] After performing the first ion implantation into the substrate, a first ion implantation region for forming a first doped region may be formed on a side of the projection of the transfer gate on the substrate away from the heavily doped region, wherein the projection of the transfer gate on the substrate may partially overlap with the first ion implantation region.

[0105] Please continue reading Figure 12 In this embodiment, in the process of preparing the floating diffusion region and the transition doping region based on the substrate on which the first transfer gate 213 has been formed, the first ion implantation and the first gate ion implantation can be implemented in the same process step. Therefore, the process parameters of the first ion implantation are the same as those of the first gate ion implantation, and are not further described here.

[0106] See also Figure 19 In some embodiments, in the process of preparing the floating diffusion region and the transition doping region based on the substrate on which the second transfer gate has been formed, the implanted ions of the first ion implantation may be P-type. For example, when the first ion implantation is performed on the substrate on which the second transfer gate has been formed, the process parameters of the first ion implantation may include: the implanted ions are boron fluoride (BF2) ions, the ion implantation energy is 10 KeV, and the ion implantation dose is 1.0×10 13 ions / cm², the rotation angle of ion implantation was 30°, the tilt angle was 0°, and the number of implantations was 4.

[0107] S132: forming a first gate spacer on a surface of the transmission gate and a surface of the substrate.

[0108] To reduce damage to the first ion implantation region caused by subsequent high-concentration ion implantation steps for forming floating diffusion regions and transition doping regions, a first gate sidewall covering the surface of the transmission gate and the surface of the substrate may be formed.

[0109] Please also refer to Figure 20 and Figure 21In this embodiment, the first gate spacer 216 can be formed using a thin film growth process such as vapor deposition or molecular beam epitaxy. The first gate spacer 216 is made of a different material than the substrate 201. Specifically, the process for forming the first gate spacer 216 based on the first transfer gate 213 and the process for forming the first gate spacer 216 based on the second transfer gate are substantially the same. The materials of the first gate spacer 216 can include silicon oxide and silicon nitride (Si3N4). Because the materials are the same, the gate oxide layer 211 can become part of the first gate spacer 216. A silicon oxide layer can be first formed on the substrate surface, and then a silicon nitride layer can be formed on the side of the silicon oxide layer facing away from the substrate. The thickness of the first gate spacer 216 is determined by the growth direction of the first gate spacer 216. The thickness of the silicon oxide layer can be less than the thickness of the silicon nitride layer. The thickness of the silicon oxide layer can be within a range of 25Å to 35Å, and the thickness of the silicon nitride layer can be within a range of 75Å to 85Å. For example, the thickness of the silicon oxide layer may be 25Å, 30Å, or 35Å, and the thickness of the silicon nitride layer may be 75Å, 80Å, or 85Å.

[0110] S133: Perform at least two second ion implantations on the substrate.

[0111] In order to optimize the electric field distribution within the substrate and improve the local electric field concentration at the PN junction interface near the floating diffusion region, after the first gate sidewall is formed, at least two second ion implantations can be performed into the substrate under the blocking effect of the first gate sidewall, thereby forming at least two second ion implantation regions distributed along the normal direction of the substrate on the side of the projection of the transfer gate on the substrate away from the heavily doped region.

[0112] Please also refer to Figure 22 and Figure 23 . In this embodiment, the type of implanted ions of the second ion implantation is different from the type of implanted ions of the first ion implantation, the implantation depth of the second ion implantation may be greater than the implantation depth of the first ion implantation, and the implantation depths of at least two second ion implantations are different. Specifically, the process and process parameters of performing the second ion implantation on the substrate on which the first transfer gate 213 is formed and performing the second ion implantation on the substrate on which the second transfer gate is formed are basically the same. In the case where the implanted ion type of the first ion implantation is P-type, the implanted ion type of the second ion implantation may be N-type. The process parameters such as the implanted ion type, ion implantation dose, and ion implantation angle of at least two second ion implantations may be kept unchanged, and the ion implantation depths of different second ion implantations may be different by changing the ion implantation energy. Taking the execution of two second ion implantations as an example, the implanted ions of the two second ion implantations may both be phosphorus (P) ions, and the ion implantation dose may both be 1.0×10 13ions / cm², the rotation angle of the ion implantation can be 0°, the tilt angle can be 0°, and the number of implantations can be 4. The ion implantation energy of the first and second ion implantations can be 40 KeV, and the ion implantation energy of the second and second ion implantations can be 20 KeV.

[0113] S134: Annealing the substrate.

[0114] To improve the doping distribution in the first ion implantation region and the second ion implantation region and reduce lattice defects in the substrate, the substrate may be annealed after the first ion implantation region and the second ion implantation region are formed in the substrate.

[0115] Please also refer to Figure 24 and Figure 25 In this embodiment, the process and process parameters for annealing the substrate on which the first transfer gate 213 is formed are substantially the same as those for annealing the substrate on which the second transfer gate is formed. Specifically, a rapid thermal processing (RTP) process can be used to anneal the substrate. The annealing temperature can be 1050°C to activate dopants and repair the crystal lattice while reducing excessive diffusion. The annealing time can be 20 seconds to achieve a certain activation and repair effect while reducing the negative effects of prolonged heating.

[0116] S135 : forming a second gate spacer on a side of the first gate spacer away from the transfer gate and the substrate.

[0117] To protect the transfer gate during the subsequent high-energy ion implantation process and provide an alignment reference for the subsequent ion implantation process, a second gate spacer can be formed on the side of the first gate spacer away from the transfer gate and the substrate.

[0118] Please also refer to Figure 26 and Figure 27In this embodiment, the second gate spacer 217 can be formed using a deposition process and an etching process. Specifically, the process and process parameters for forming the second gate spacer 217 based on the first transfer gate 213 and the second transfer gate are substantially the same. For example, a second gate spacer material layer can be first formed on the side of the first gate spacer 216 away from the transfer gate and the substrate using a chemical vapor deposition (CVD) process. An anisotropic etching process is then used to remove a portion of the second gate spacer material layer to form the second gate spacer 217. The second gate spacer 217 can include silicon oxide and silicon nitride. The thickness of the silicon oxide layer can be smaller than that of the silicon nitride layer. The thickness of the silicon oxide layer can fall within the range of 75 Å to 85 Å, and the thickness of the silicon nitride layer can fall within the range of 440 Å to 460 Å. For example, the thickness of the silicon oxide layer can be 75 Å, 80 Å, or 85 Å, and the thickness of the silicon nitride layer can be 440 Å, 450 Å, or 460 Å.

[0119] S136: Perform a third ion implantation into the substrate to form a floating diffusion region on a side where the projection of the second gate sidewall on the substrate is away from the projection of the transfer gate on the substrate, and form a first doped region and a second doped region between the floating diffusion region and the projection of the transfer gate on the substrate to obtain a semiconductor structure.

[0120] In order to increase the distance between the floating diffusion region and the transfer gate, enhance the voltage resistance of the floating diffusion region, and reduce gate-induced drain leakage, a third ion implantation can be performed into the substrate after the second gate sidewall is formed to form a floating diffusion region, and the doping range of the floating diffusion region can be controlled with the help of the third ion implantation mask.

[0121] Please also refer to Figure 28 and Figure 29 . In this embodiment, the implantation ion type of the third ion implantation is the same as the implantation ion type of the second ion implantation, and the implantation dose of the third ion implantation is greater than the implantation dose of the second ion implantation. Specifically, the process and process parameters of performing the third ion implantation on the substrate on which the first transfer gate 213 is formed and performing the third ion implantation on the substrate on which the second transfer gate is formed are basically the same. In order to reduce the size of the floating diffusion region 207 along the width direction, the distance between the projected edge of the third ion implantation mask 224 on the substrate and the heavily doped region 205 can be greater than the distance between the projected edge of the second gate sidewall 217 on the substrate and the heavily doped region 205. In the case where the implantation ion type of the second ion implantation is N-type, the implantation ion type of the third ion implantation can be N-type. For example, the process parameters of the third ion implantation may include: the implanted ions are arsenic (As) ions, the ion implantation energy is 20KeV, and the ion implantation dose is 1.0×10 15ions / cm², the rotation angle of ion implantation is 0°, the tilt angle is 0°, and the number of implantations is 4.

[0122] Please also refer to Figure 30 and Figure 31 To reduce the number of process steps, shorten process time, and save process costs, in this embodiment, after the floating diffusion region 207 is formed by the third ion implantation, the third ion implantation mask 224 can be trimmed to obtain a fourth ion implantation mask 224'. The distance between the projected edge of the substrate and the heavily doped region 205 of the fourth ion implantation mask 224' can be equal to the distance between the projected edge of the second gate spacer 217 and the heavily doped region 205. Subsequently, a fourth ion implantation can be performed on the substrate based on the fourth ion implantation mask 224', such that a second doped region 2082 is present between the projected edge of the second gate spacer 217 and the floating diffusion region 207, thereby reducing the potential PN junction at the interface between the substrate and the first gate spacer 216. Specifically, the process and process parameters for performing the fourth ion implantation on the substrate with the first transfer gate 213 formed thereon and performing the fourth ion implantation on the substrate with the second transfer gate formed thereon are substantially the same. The implantation ion type of the fourth ion implantation may be the same as the implantation ion type of the third ion implantation. In the case where the implantation ion type of the third ion implantation is N-type, the implantation ion type of the third ion implantation may be N-type. The implantation energy of the fourth ion implantation may be less than the implantation energy of the second ion implantation and greater than the implantation energy of the first ion implantation. For example, the process parameters of the fourth ion implantation may include: the implantation ion is arsenic (As) ion, the ion implantation energy is 15 KeV, and the ion implantation dose is 1.0×10 13 ions / cm², the rotation angle of ion implantation is 0°, the tilt angle is 0°, and the number of implantations is 4.

[0123] After completing the fourth ion implantation, a second doping region 2082 having the same doping type as the floating diffusion region 207 can be formed between the projected edge of the substrate and the floating diffusion region 207 on the second gate sidewall 217, and a first doping region 2081 having a different doping type from the floating diffusion region 207 can be formed on the side of the second doping region 2082 away from the floating diffusion region 207. The second doping region 2082 and the first doping region 2081 together constitute a transition doping region 208.

[0124] Please also refer to Figures 32 to 33 After forming the transition doping region 208 , the fourth ion implantation mask may be removed to obtain the first semiconductor structure 200 including the first transfer gate 213 , or the second semiconductor structure 300 including the second transfer gate.

[0125] Please also refer to Figure 34 and Figure 35 . In the semiconductor structure provided in the embodiment of the present application, the transition doping region is formed by the following process: first, using the transmission gate as a mask, an ion implantation is performed into the doped well region 202 of the substrate to form a first ion implantation region 2061. Subsequently, using the first gate sidewall 216 as a mask, at least two ion implantations are performed into the doped well region 202 of the substrate to form at least two second ion implantation regions 2062 distributed along the normal direction of the substrate. Next, annealing is performed so that the at least two second ion implantation regions 2062 are diffused and connected to form a first doped region 2081 and a second doped region 2082 whose shape is approximately the intersection of at least two ellipses. By optimizing process parameters such as ion implantation energy, ion implantation dose, and annealing temperature, the morphology of the second doped region 2082 can be controlled so that a PN junction with an interface shape approximately similar to a plane is formed at the junction of the second doped region 2082 and the doped well region 202. At this time, the interface curvature of the PN junction is small, the charge distribution is more uniform, and accordingly, the local electric field is weak. In addition, since the doping types of the first doping region 2081 and the second doping region 2082 are different, on the basis that the interface between the second ion injection region 2062 and the doped well region 202 is approximately plane, the first doping region 2081 can be used to push the depletion region boundary in the transition doping region 208 away from the substrate surface and move it toward the interior of the substrate.

[0126] See also Figure 36 . Taking the first semiconductor structure 200 as an example, when the transfer transistor is in the off or waiting state, the voltage between the photodiode and the floating diffusion region will form an electric field near the transition doping region 208. The electrons and holes in the transition doping region 208 move in different directions driven by the electric field force to form a depletion region with a width of W2. Although the boundary of the depletion region covers the interface plane P3 between the substrate and the first gate sidewall 216. However, affected by the first doping region 2081, the peak of the electric field strength near the transition doping region 208 appears on the internal plane P4 of the substrate, thereby reducing the electrons and holes that recombine at the P3 plane, reducing the probability of the band-to-band tunneling effect, and improving the gate-induced drain leakage phenomenon.

[0127] Please continue reading Figure 32 and Figure 33 Another embodiment of the present application provides a semiconductor structure. The semiconductor structure may include a substrate, a transfer gate formed on a surface of the substrate, a floating diffusion region 207 and a transition doping region 208 formed in the substrate.

[0128] In this embodiment, the transitional doping region 208 may be located between the projection of the transfer gate on the substrate and the floating diffusion region 207. Specifically, the doping concentration of the transitional doping region 208 may be lower than the doping concentration of the floating diffusion region 207. The transitional doping region 208 may include a first doping region 2081 and a second doping region 2082 formed by an ion implantation process. The doping type of the first doping region 2081 is different from that of the floating diffusion region 207, while the doping type of the second doping region 2082 is the same as that of the floating diffusion region 207. Along the normal direction of the substrate, the ion implantation depth of the second doping region 2082 is greater than that of the first doping region 2081.

[0129] To mitigate damage to the doped regions within the substrate during the high-concentration ion implantation process for forming the floating diffusion region 207 and the transition doped region 208, in this embodiment, the semiconductor structure may further include: a first gate spacer 216 formed on the side of the transfer gate and the surface of the substrate; and a second gate spacer 217 formed on a side of the first gate spacer 216 that is distal from the transfer gate and the substrate. Specifically, the first gate spacer 216 and the substrate are made of different materials. A first doped region 2081 may be located between the projection of the second gate spacer 217 on the substrate and the floating diffusion region 207.

[0130] To increase the edge resistance of the transmission gate, reduce the potential at the edge of the transmission gate, weaken the coupling electric field strength between the transmission gate and the floating diffusion region 207, and improve gate-induced drain leakage, in this embodiment, the transmission gate may include a first gate doping region 2131 and a second gate doping region 2132. Specifically, with the width of the transmission gate perpendicular to the normal direction of the substrate, the first gate doping region 2131 is located between the second gate doping region 2132 and the first gate spacer 216 along the width of the transmission gate. The doping type of the first gate doping region 2131 is different from the doping type of the second gate doping region 2132. For example, the doping type of the first gate doping region 2131 may be P-type, and correspondingly, the doping type of the second gate doping region 2132 may be N-type.

[0131] Alternatively, in some embodiments, the transmission gate may include a third gate doping region 215. Specifically, in the third gate doping region 215, the doping concentration of the region closer to the first gate spacer 216 is lower.

[0132] Regarding other technical effects of the semiconductor structure described in the above embodiment, reference can be made to other embodiments of the present application for comparative explanation, and no further details will be given here.

[0133] In the semiconductor structure provided in an embodiment of the present application, a transition doped region is formed between a projection of the substrate and a floating diffusion region by a transfer gate on the surface of the substrate, wherein the doping concentration of the transition doped region is lower than the doping concentration of the floating diffusion region, and the transition doped region includes a first doped region and a second doped region formed by an ion implantation process, wherein the doping type of the first doped region is different from the doping type of the floating diffusion region, and the doping type of the second doped region is the same as the doping type of the floating diffusion region, and the ion implantation depth of the second doped region along the normal direction of the substrate is greater than the ion implantation depth of the first doped region. This achieves unexpected effects, including: because the interface between the second doped region and the doped well region is approximately planar, and at the same time, in the transition doped region, the ion implantation depth of the first doped region, which has a different doping type from the floating diffusion region, is less than the ion implantation depth of the second doped region, which has the same doping type as the floating diffusion region, thereby improving the interface shape of the PN junction at the interface between the second doped region and the doped well region, optimizing charge distribution, and utilizing the first doped region to push the depletion region from the substrate surface to the interior of the substrate, optimizing the electric field distribution near the transition doped region, thereby reducing the occurrence of gate-induced drain leakage and improving the imaging quality of the CMOS image sensor.

[0134] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0135] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0136] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0137] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art in the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms of "a", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0138] In the several embodiments provided in this application, it should be understood that the disclosed semiconductor structure and image sensor can be implemented in other ways. For example, the embodiments of the semiconductor structure and image sensor described above are merely illustrative.

[0139] The above descriptions are merely specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a transmission gate formed on a surface of the substrate; A floating diffusion region and a transition doping region are formed in the substrate; wherein the transition doping region is located between the projection of the transfer gate on the substrate and the floating diffusion region; the doping concentration of the transition doping region is less than the doping concentration of the floating diffusion region; the transition doping region includes a first doping region and a second doping region formed based on an ion implantation process; the doping type of the first doping region is different from the doping type of the floating diffusion region; the doping type of the second doping region is the same as the doping type of the floating diffusion region; along the normal direction of the substrate, the ion implantation depth of the second doping region is greater than the ion implantation depth of the first doping region.

2. The semiconductor structure according to claim 1, wherein: Also includes: A first gate spacer is formed on the side of the transmission gate and the surface of the substrate; wherein the first gate spacer is made of a different material from that of the substrate; A second gate spacer is formed on a side of the first gate spacer away from the transfer gate and the substrate; the first doped region exists between a projection of the second gate spacer on the substrate and the floating diffusion region.

3. The semiconductor structure according to claim 2, wherein: The transmission gate includes a first gate doping region and a second gate doping region; wherein, with a direction perpendicular to the normal direction of the substrate as the width direction of the transmission gate, along the width direction of the transmission gate, the first gate doping region is located between the second gate doping region and the first gate sidewall; the doping type of the first gate doping region is different from the doping type of the second gate doping region.

4. The semiconductor structure according to claim 2, wherein: The transmission gate includes a third gate doping region; in the third gate doping region, the doping concentration of the region closer to the first gate sidewall is lower.

5. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: providing a substrate; forming a transmission gate on the surface of the substrate; Ion implantation is performed on the substrate to form a floating diffusion region and a transition doping region in the substrate to obtain the semiconductor structure; wherein the transition doping region is located between the projection of the transfer gate on the substrate and the floating diffusion region; the doping concentration of the floating diffusion region is greater than the doping concentration of the transition doping region; the transition doping region includes a first doping region and a second doping region formed based on an ion implantation process; the doping type of the first doping region is different from the doping type of the floating diffusion region; the doping type of the second doping region is the same as the doping type of the floating diffusion region; along the normal direction of the substrate, the ion implantation depth of the second doping region is greater than the ion implantation depth of the first doping region.

6. The method according to claim 5, characterized in that The semiconductor structure further includes a first gate sidewall and a second gate sidewall; and the steps of performing ion implantation on the substrate to form a floating diffusion region and a transition doping region in the substrate to obtain the semiconductor structure include: performing a first ion implantation on the substrate; forming a first gate spacer on a surface of the transmission gate and a surface of the substrate; wherein the first gate spacer is made of a different material from that of the substrate; performing at least two second ion implantations on the substrate; wherein the type of implanted ions in the second ion implantation is different from the type of implanted ions in the first ion implantation; the implantation depth of the second ion implantation is greater than the implantation depth of the first ion implantation; and the implantation depths of the at least two second ion implantations are different; annealing the substrate; forming a second gate spacer on a side of the first gate spacer away from the transfer gate and away from the substrate; A third ion implantation is performed on the substrate to form the floating diffusion region on a side of the second gate sidewall where the projection of the substrate is away from the projection of the transfer gate on the substrate, and a first doped region and a second doped region are formed between the floating diffusion region and the projection of the transfer gate on the substrate, to obtain the semiconductor structure; wherein the implanted ion type of the third ion implantation is the same as the implanted ion type of the second ion implantation; and the implantation dose of the third ion implantation is greater than the implantation dose of the second ion implantation.

7. The method according to claim 6, characterized in that The method further comprises: After the floating diffusion region is formed, a fourth ion implantation is performed on the substrate, so that the second doped region exists between the projection of the second gate sidewall on the substrate and the floating diffusion region; wherein the implanted ion type of the fourth ion implantation is the same as the implanted ion type of the third ion implantation; and the implantation energy of the fourth ion implantation is less than the implantation energy of the second ion implantation and greater than the implantation energy of the first ion implantation.

8. The method according to claim 6, characterized in that The step of forming a transmission gate on the surface of the substrate comprises: forming a first transition gate on the surface of the substrate; Performing a first gate ion implantation on the first transition gate to form a first gate doping region; wherein the performing of the first gate ion implantation on the first transition gate and the performing of the first ion implantation on the substrate are completed in the same process step; A second gate ion implantation is performed on the first transition gate to form a second gate doping region, thereby obtaining the transfer gate; wherein the type of implanted ions of the second gate ion implantation is different from the type of implanted ions of the first gate ion implantation; and a direction perpendicular to the normal direction of the substrate is used as the width direction of the transfer gate. Along the width direction of the transfer gate, the first gate doping region is located between the second gate doping region and the first gate sidewall.

9. The method according to claim 6, characterized in that The step of forming a transmission gate on the surface of the substrate comprises: forming a gate material layer on the surface of the substrate; performing a third gate ion implantation into the gate material layer based on a gate ion implantation mask; Etching away a portion of the gate material layer based on a gate etch mask to form a second transition gate; wherein the etch barrier size of the gate etch mask is larger than the injection opening size of the gate ion implantation mask; Annealing is performed on the second transition gate to form the transmission gate; wherein the transmission gate includes a third gate doping region; in the third gate doping region, the doping concentration of the region closer to the first gate sidewall is lower.

10. An image sensor, characterized in that: The image sensor comprises the semiconductor structure according to any one of claims 1 to 4 or a semiconductor structure manufactured according to the method for manufacturing the semiconductor structure according to any one of claims 5 to 9.

Images