CMOS device based on two-dimensional semiconductor material and preparation method thereof

Abstract

The invention discloses a CMOS device based on a two-dimensional semiconductor material and a preparation method thereof, and the preparation method comprises the steps: preparing the source electrode and the drain electrode of an nMOSFET and a pMOSFET on the surface of a two-dimensional semiconductor, enabling the source electrode and the drain electrode of the nMOSFET to employ a metal with a work function value of 3.5-4.6 eV, enabling the source electrode and the drain electrode of the pMOSFET to employ a metal with a work function value of 5-5.7 eV, and enabling the source electrode and the drain electrode of the pMOSFET to employ a metal with a work function value of 5-5.7 eV; the method comprises the following steps: preparing a two-dimensional semiconductor material, defining a two-dimensional semiconductor channel region, preparing a gate dielectric layer and a gate electrode, preparing the gate electrode of an nMOSFET at least comprising metal with a work function value of 3.5-4.6 eV and the gate electrode of a pMOSFET at least comprising metal with a work function value of 5-5.7 eV, and finally interconnecting the gate electrode of the nMOSFET and the gate electrode of the pMOSFET and interconnecting the drain electrode of the nMOSFET and the drain electrode of the pMOSFET to obtain the CMOS device based on the two-dimensional semiconductor material. The preparation method is low in process complexity, high in practicability and good in stability, the transfer characteristic curve of the obtained CMOS device shows good symmetry, and the logic inverting function and the high voltage gain of the CMOS inverter are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device preparation, in particular to a CMOS device based on two-dimensional semiconductor material and a preparation method thereof. BACKGROUND

[0002] In recent years, two-dimensional semiconductor materials are considered as an important candidate for 1 nm node integrated circuits due to their atomic thickness and good electrical properties. With the gradual improvement of the performance of two-dimensional semiconductor discrete devices in recent years, the research direction is gradually shifting from discrete devices to two-dimensional semiconductor integrated circuits (2D ICs). The foundation of large-scale integrated circuits is CMOS, which is composed of nMOSFET and pMOSFET, has the advantage of low power consumption, and is the basis for realizing large-scale integrated circuits. At present, the p and n channel materials of most reported two-dimensional semiconductor CMOS (2D CMOS) inverters are based on different two-dimensional semiconductor materials, involving a transfer operation of two-dimensional semiconductor materials, which increases the complexity of the process.

[0003] In recent years, most of the research on 2D CMOS involves issues such as incompatibility with silicon-based CMOS processes. Controlling the polarity inversion of two-dimensional semiconductor materials through a process compatible with silicon-based CMOS processes to realize 2D CMOS is a feasible method. However, silicon-based CMOS mainly uses ion implantation for controllable doping, which can easily damage the atomic thickness channel and is incompatible with two-dimensional semiconductor material processes. Therefore, the biggest problem currently faced by research in the field of 2D ICs is the lack of a practical process for two-dimensional semiconductor CMOS (2D CMOS), which restricts the development of 2D ICs.

[0004] Therefore, how to develop a CMOS device preparation method based on two-dimensional semiconductor materials without a transfer operation is a major challenge for two-dimensional semiconductor materials to realize large-scale integrated circuit applications, and is a technical problem that needs to be solved in the field. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a CMOS device based on two-dimensional semiconductor material and a preparation method thereof. In the preparation process, the same top-gate CMOS device is obtained by adjusting the metal type of the source, drain and gate, which does not involve a transfer operation of two-dimensional semiconductor materials, has low process complexity, high practicality, and the transfer characteristic curve of the obtained CMOS device has good symmetry, can realize logic inversion function and high voltage gain.

[0006] To solve the above technical problems, the first aspect of the present application provides a preparation method of a CMOS device based on two-dimensional semiconductor material, comprising: S1, preparing the source and drain of nMOSFET and pMOSFET on the surface of two-dimensional semiconductor, wherein the source and drain of nMOSFET are made of metal with work function value of 3.5-4.6eV, and the source and drain of pMOSFET are made of metal with work function value of 5-5.7eV; S2, etching process to define the channel region of two-dimensional semiconductor; S3, preparing the gate dielectric layer; S4, deposition process to prepare the gate on the surface of gate dielectric layer, wherein the gate of nMOSFET at least includes metal with work function value of 3.5-4.6eV, and the gate of pMOSFET is made of metal with work function value of 5-5.7eV; S5, via etching process to expose the drain of nMOSFET and the drain of pMOSFET, and deposition process to interconnect the gate of nMOSFET and the gate of pMOSFET, and the drain of nMOSFET and the drain of pMOSFET with interconnection metal.

[0007] Preferably, the process for preparing the source and drain in step S1 is metal deposition process.

[0008] Preferably, the material of the source and drain of nMOSFET is selected from one or more of Mg, Al, Y, In, Sb, Ti, and the material of the source and drain of pMOSFET is selected from one or more of Au, Pt and Pd, and the number of layers of two-dimensional semiconductor material is 1-30.

[0009] Preferably, the etching process in step S2 is plasma etching process.

[0010] Preferably, the preparation process of gate dielectric layer in step S3 is atomic layer deposition process.

[0011] Preferably, the material of gate dielectric layer is insulating material with dielectric constant greater than 5, and the thickness of gate dielectric layer is between 1nm and 1μm.

[0012] Preferably, the deposition process in step S4 is metal deposition process. On the gate of nMOSFET with work function value of 3.5-4.6eV, metal with work function value of 5-5.7eV can be selected to be further deposited to be the gate of nMOSFET.

[0013] Preferably, the deposition process in step S5 is metal deposition process, and the material of interconnection metal is metal material with conductivity greater than 3×10 7 S / m.

[0014] To solve the above technical problems, a second aspect of the present application provides a two-dimensional semiconductor CMOS device prepared by the preparation method of the aforementioned two-dimensional semiconductor CMOS device.

[0015] The present application provides a preparation method of a two-dimensional semiconductor CMOS device, by depositing a metal with a work function value of 3.5-4.6 eV as the source and drain of the nMOSFET, while the gate of the nMOSFET at least includes a metal with a work function value of 3.5-4.6 eV, and the source, drain and gate of the pMOSFET are obtained by depositing a metal with a work function value of 5-5.7 eV, the carrier polarity of the transistor is adjusted, thereby obtaining a two-dimensional semiconductor material-based top-gate CMOS device. In the preparation process, no transfer or doping operation of the two-dimensional semiconductor material is involved, the process complexity is low, the practicability is strong, the stability is good, and the transfer characteristic curve of the obtained CMOS device shows good symmetry, and the logic inversion function and high voltage gain of the CMOS inverter are realized. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the present application, the following briefly introduces the drawings needed to be used by the present application. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a preparation process flow chart of the CMOS device of the present application, including a sectional view and a top view; Figure 2 is the transfer characteristic curve of the nMOSFET and the pMOSFET of the CMOS device A; Figure 3 is the voltage transfer characteristic curve of the CMOS device A; Figure 4 is the voltage gain curve of the CMOS device A under different power supply voltage conditions; Figure 5 is the transfer characteristic curve of the nMOSFET and the pMOSFET of the CMOS device B; Figure 6 is the voltage transfer characteristic curve and the voltage gain curve of the CMOS device B; Figure 7 is the transfer characteristic curve of the nMOSFET and the pMOSFET of the CMOS device C; Figure 8 is the voltage transfer characteristic curve and the voltage gain curve of the CMOS device C; 1-substrate; 2-two-dimensional semiconductor material; 3-source electrode of nMOSFET; 4-drain electrode of nMOSFET; 5-drain electrode of pMOSFET; 6-source electrode of pMOSFET; 7-gate dielectric layer; 8-gate electrode of nMOSFET; 9-gate electrode of pMOSFET; 10-interconnection metal. DETAILED DESCRIPTION

[0018] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0019] It should be noted that the shapes and sizes of the regions and layers shown in the drawings are only exemplary and are not drawn to scale. Some details may be exaggerated and some details may be omitted for the sake of clarity. Those skilled in the art can design regions and layers with different shapes, sizes and relative positions according to actual needs.

[0020] Embodiment one: a preparation method of a CMOS device based on a two-dimensional semiconductor material.

[0021] Reference Figure 1 Fig. 1 shows a preparation method of a CMOS device based on a two-dimensional semiconductor material according to the present application, which comprises: S1, preparing source electrodes and drain electrodes of nMOSFET and pMOSFET on a two-dimensional semiconductor surface, wherein the source electrodes and drain electrodes of nMOSFET are made of a metal with a work function value of 3.5-4.6 eV, and the source electrodes and drain electrodes of pMOSFET are made of a metal with a work function value of 5-5.7 eV; S2, etching process to define a two-dimensional semiconductor channel region; S3, preparing a gate dielectric layer; S4, deposition process to prepare gate electrodes on the surface of the gate dielectric layer, wherein the gate electrodes of nMOSFET at least include a metal with a work function value of 3.5-4.6 eV, and the gate electrodes of pMOSFET are made of a metal with a work function value of 5-5.7 eV; S5, via etching process to expose the drain electrodes of nMOSFET and the drain electrodes of pMOSFET, and deposition process to interconnect the gate electrodes of nMOSFET and the gate electrodes of pMOSFET, and the drain electrodes of nMOSFET and the drain electrodes of pMOSFET with an interconnection metal.

[0022] In the present application, the method for preparing a CMOS device of a two-dimensional semiconductor material does not involve transfer, doping and the like of the two-dimensional semiconductor, and has low process complexity. Meanwhile, in the present application, a metal (low work function metal material, such as Mg, Al, Y, In, Sb, Ti and the like) with a work function value of 3.5-4.6 eV is deposited as the source, drain and gate (or part of the gate) of the nMOSFET, and a metal (high work function metal material, such as Au, Pt, Pd and the like) with a work function value of 5-5.7 eV is deposited as the source, drain and gate of the pMOSFET, so as to realize adjustment of the carrier polarity of the transistor, thereby obtaining a homogenous top-gate CMOS device based on a two-dimensional semiconductor material, which is conducive to further development of large-scale integrated circuits. It should be noted that the metal material of the source, drain and low work function metal part of the gate of the nMOSFET can be the same or different, the material of the high work function metal part of the gate of the nMOSFET is, for example, one or more of Au, Pt, Pd and the like, and when there are multiple kinds, they can be deposited separately and stacked, preferably, the source and drain adopt the same metal material; when the gate material of the pMOSFET is multiple, they can also be deposited separately and stacked, and the metal material of the source, drain and gate of the pMOSFET can be the same or different, preferably, the source and drain adopt the same metal material.

[0023] In the present application, the two-dimensional semiconductor material refers to a two-dimensional semiconductor grown on a substrate, for example, the substrate can be Al2O3, SiO2, mica and the like, and the two-dimensional semiconductor material can be MoTe2, WSe2, PdSe2, PtSe2 and the like. The growth of the two-dimensional semiconductor material on the substrate is a relatively mature process, which will not be described here. After the two-dimensional semiconductor material is grown on the surface of the substrate material, it can be directly applied to the present application. The range of the two-dimensional semiconductor material layer is 1-30 layers.

[0024] In a more specific embodiment, the process for preparing the source and drain in step S1 is a metal deposition process. Understandably, the metal deposition process in the present application is mainly to deposit metal by physical vapor deposition, for example, electron beam deposition, thermal evaporation, magnetron sputtering and the like. The thickness of the finally obtained source and drain is 15-30 nm, which can effectively ensure the transmission of the carriers. It should be noted that before the metal deposition process, a photolithography process is required. After the photolithography process defines the area of the source and drain, the metal deposition process is performed to deposit the metal to be deposited at the target position, and finally the photoresist is removed. The photolithography process is, for example, spin coating photoresist, then exposing the selected area, and finally developing and the like. In addition, the present application does not have any restrictive requirements on the preparation sequence of the source and drain of the nMOSFET and the source and drain of the pMOSFET. The photolithography process and the metal deposition process are both conventional processes in the prior art, which will not be described here.

[0025] In a more specific embodiment, the etching process in step S2 is a plasma etching process. In the present application, the two-dimensional semiconductor channel region is defined by a plasma etching process. Specifically, a photoetching process is first used to complete the patterning of the two-dimensional semiconductor channel, and then a plasma etching process is used to remove the two-dimensional semiconductor material other than the channel. The etching time is determined by the number of layers of the two-dimensional semiconductor material. The plasma etching is, for example, a capacitively coupled plasma etching technique, an inductively coupled plasma etching technique, or a reactive ion etching technique. This is also a prior art and will not be described here.

[0026] In a more specific embodiment, the preparation process of the gate dielectric layer in step S3 is an atomic layer deposition process, and the thickness of the gate dielectric layer is between 1 nm and 1 μm. In the present application, the gate dielectric layer is prepared by, for example, an atomic deposition process, and the thickness of the gate dielectric layer can be determined as needed. Preferably, the material of the gate dielectric layer is an insulating material with a dielectric constant greater than 5 (high-K material with a dielectric constant greater than that of silicon dioxide); more preferably, the material of the gate dielectric layer is an insulating material with a dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium dioxide (HfO2), etc.

[0027] In a more specific embodiment, the deposition process in step S4 is a metal deposition process; on the gate of an nMOSFET with a work function value of 3.5-4.6 eV, a metal with a work function value of 5-5.7 eV can be selected to be deposited together as the gate of the nMOSFET. The metal deposition process is synchronized with step S1, and the total thickness of the gate of the nMOSFET is 15-60 nm, and the total thickness of the gate of the pMOSFET is 15-60 nm, preferably the total thickness of the gate of the nMOSFET is equal to the total thickness of the gate of the pMOSFET; it should be noted that the gate of the nMOSFET at least needs to have a metal with a work function value of 3.5-4.6 eV, and can also have a metal with a work function value of 5-5.7 eV, and the two metals form a stack to form the gate of the nMOSFET.

[0028] In a more specific embodiment, the deposition process in step S5 is a metal deposition process, and the material used for the interconnection metal is a metal material with a conductivity greater than 3 x 10 7 S / m. The metal deposition process in this step is synchronized with step S1, and the thickness of the interconnection metal is 15-60 nm; in the present application, the work function of the interconnection metal is not required, but it needs to have a conductivity greater than 3 x 10 7Metallic materials with S / m (20℃) such as Au, Cu and Al, etc. It should be noted that the process sequence in S5 can be, for example, first exposing the drain of the nMOSFET and the drain of the pMOSFET by a via etching process, and then simultaneously interconnecting the gate of the nMOSFET and the gate of the pMOSFET, and interconnecting the drain of the nMOSFET and the drain of the pMOSFET by a metal deposition process. For example, the process sequence can also be, first simultaneously interconnecting the gate of the nMOSFET and the gate of the pMOSFET by a metal deposition process, and then exposing the drain of the nMOSFET and the drain of the pMOSFET by a via etching process, and then interconnecting the drain of the nMOSFET and the drain of the pMOSFET by a metal deposition process.

[0029] Example 2: Homogeneous top-gate CMOS device based on two-dimensional semiconductor material and test results.

[0030] The homogeneous top-gate CMOS device based on two-dimensional semiconductor material in this example is obtained by using the preparation method of Example 1.

[0031] CMOS device A: the substrate is SiO2 with a thickness of 280 nm (grown on a Si substrate); the two-dimensional semiconductor material is 3 layers of MoTe2; the source and drain of the nMOSFET are In with a thickness of 20 nm, and the gate is Mg with a thickness of 20 nm and Au with a thickness of 20 nm; the source and drain of the pMOSFET are Au with a thickness of 20 nm, and the gate is Au with a thickness of 20 nm; the gate dielectric layer is hafnium dioxide (HfO2) with a thickness of 20 nm; and the interconnection metal is Au with a thickness of 30 nm. Figure 2 The transfer characteristic curves of the pull-up tube (pMOSFET) and the pull-down tube (nMOSFET) of CMOS device A are shown, which exhibit good symmetry; Figure 3 The voltage transfer characteristic curves of CMOS device A are shown, which can all achieve the logic inversion function of the CMOS inverter; Figure 4 The voltage gain curves of CMOS device A under different power supply voltage conditions are shown, which exhibit high voltage gain.

[0032] CMOS device B: the substrate is a commercial standard Al2O3 wafer; the two-dimensional semiconductor material is 3 layers of MoTe2; the source and drain of the nMOSFET are In with a thickness of 20 nm, and the gate is an Al and Au stacked structure with a thickness of 5 nm and 20 nm, respectively; the source and drain of the pMOSFET are Pt with a thickness of 20 nm, and the gate is Au with a thickness of 20 nm; the gate dielectric layer is hafnium dioxide (HfO2) with a thickness of 15 nm; and the interconnection metal is Au with a thickness of 30 nm. Figure 5The transfer characteristic curves of the pull-up tube (pMOSFET) and the pull-down tube (nMOSFET) of the CMOS device B are shown, which exhibit good symmetry; Figure 6 The voltage transfer curves and the voltage gain curves of the CMOS device B under different power supply voltages are shown, from which it can be seen that the CMOS inverter realizes the logical inversion function and exhibits high voltage gain.

[0033] The CMOS device C: the substrate is 280nm-thick SiO2 (grown on a Si substrate); the two-dimensional semiconductor material is 3-layer MoTe2; the source and the drain of the nMOSFET are 20nm-thick Sb, and the gate is 10nm-thick Mg and 20nm-thick Au; the source and the drain of the pMOSFET are 20nm-thick Pd, and the gate is 20nm-thick Au; the gate dielectric layer is 20nm-thick hafnium dioxide (HfO2); and the interconnection metal is all 30nm-thick Au. Figure 7 The transfer characteristic curves of the pull-up tube (pMOSFET) and the pull-down tube (nMOSFET) of the CMOS device C are shown, which exhibit good symmetry; Figure 8 The voltage transfer curves and the voltage gain curves of the CMOS device C under different power supply voltages are shown, from which it can be seen that the CMOS inverter realizes the logical inversion function and exhibits high voltage gain.

[0034] The above merely describes the preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a CMOS device based on two-dimensional semiconductor materials, characterized in that: include: S1. preparing the source and drain of nMOSFET and pMOSFET on the two-dimensional semiconductor surface, wherein the source and drain of nMOSFET are made of metal with a work function value of 3.5-4.6 eV, and the source and drain of pMOSFET are made of metal with a work function value of 5-5.7 eV; S2, an etching process defines a two-dimensional semiconductor channel region; S3, preparing a gate dielectric layer; S4, forming a gate on the surface of the gate dielectric layer by a deposition process, wherein the gate of the nMOSFET at least comprises a metal with a work function value of 3.5-4.6 eV, and the gate of the pMOSFET comprises a metal with a work function value of 5-5.7 eV; S5. A through-hole etching process is used to expose the drain of the nMOSFET and the drain of the pMOSFET. A deposition process is used to interconnect the gate of the nMOSFET and the gate of the pMOSFET, as well as the drain of the nMOSFET and the drain of the pMOSFET with interconnecting metal.

2. The method according to claim 1, wherein The process for preparing the source and drain in step S1 is a metal deposition process.

3. The method according to claim 2, wherein The material of the source and drain of nMOSFET is selected from one or more of Mg, Al, Y, In, Sb, and Ti; the material of the source and drain of pMOSFET is selected from one or more of Au, Pt, and Pd; The number of layers of two-dimensional semiconductor materials ranges from 1 to 30.

4. The method according to claim 1, wherein The etching process in step S2 is a plasma etching process.

5. The method according to claim 1, wherein The gate dielectric layer is prepared by atomic layer deposition in step S3.

6. The method according to claim 5, wherein The gate dielectric layer is made of an insulating material with a dielectric constant greater than 5, and the thickness of the gate dielectric layer is between 1 nm and 1 μm.

7. The method according to claim 1, wherein The deposition process in step S4 is a metal deposition process; On the gate of the nMOSFET with a work function value of 3.5-4.6 eV, a metal with a work function value of 5-5.7 eV may be selected to be deposited to serve as the gate of the nMOSFET.

8. The method according to claim 1, wherein The deposition process in step S5 is a metal deposition process, and the material used for the interconnection metal has a conductivity greater than 3×10 7 S / m metal material.

9. A two-dimensional semiconductor CMOS device prepared by the method for preparing a CMOS device based on a two-dimensional semiconductor material according to any one of claims 1 to 8.

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